[LLVMdev] How to partition registers into different RegisterClass?

[Tzu-Chien Chiu]

Hi, everyone.

I' have three set of registers - read-only regs, general purpose regs
(read and write), and write-only regs. How should I partition them
into different RegisterClasses so that I can easy define the
instruction?

All RegisterClasses must be mutally exclusive. That is, a register can
only be in a RegisterClass. Otherwise TableGen will raise an error
message.

  def ReadOnlyRegClass : RegisterClass<...>;
  def GeneralPurposeRegClass : RegisterClass<...>;
  def WriteOnlyRegClass : RegisterClass<...>;

  def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
GeneralPurposeRegClass :$src), "mov $dest, $src">;

There can be only one RegisterClass defined for each instruction
operand, but actually the destition operand could be
'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the source
operand can be 'ReadOnlyRegClass' or 'GeneralPurposeRegClass'.


--
Tzu-Chien Chiu
http://www.csie.nctu.edu.tw/~jwchiu/