[LLVMdev] The live interval of write-only registers

Tzu-Chien Chiu tzuchien.chiu at gmail.com
Mon Dec 12 19:51:50 PST 2005

In my ISA, some registers are write-only. These registers serve as
output ports, writing to these registers will output the values to an
external device. They cannot be read. So their live intervals should
not be joined with any other registers.

The only way I know to do this is defining several instruction
'templates' for an opcode (of course automatically generated by a
script) similar to the x86 code generator in LLVM:

// ORC: output register class
// TRC: temp register class

def ADDoaa : Inst<0x1234, (ops ORC:$dest, TRC:$src0, $TRC:src1), "add
$dest, $src0, $src1)

The letters (oaa) postfixed to the opcode (ADD) is the template. In
this way the output register won't be joined because they are of
different register classes.

However, the problem with the method is that there are too many
register classes in the ISA.

for destinations:
o: outptu register
x: a relatively addressed output register
i: integer register
f: floating-point temporary register

for sources:
a: floating-point temporary register
r: a relatively addressed temporary register
c: a constant register holding an immediate values

I do not list all class, but imagine how many combinations there are
for a three-address operations like MAD (multiply-and-add). It's very
very inconvenient in the code generator to manipulate the opcodes
because TableGen generates an 'opcode' for each of the templates of an

For example, this a code snippet for the file generated by the TableGen tool:

namespace llvm {

namespace Nrw {
  enum {
    PHI, 	// 0
    CMPfaaaa, 	// 16
    CMPfaaar, 	// 17
    CMPfaara, 	// 18
    CMPfaarr, 	// 19
    CMPfaraa, 	// 20
    CMPfarar, 	// 21
    CMPfarra, 	// 22
    CMPfarrr, 	// 23
    CMPfraaa, 	// 24
    CMPfraar, 	// 25
    CMPfrara, 	// 26
    CMPfrarr, 	// 27
    CMPfrraa, 	// 28
    CMPfrrar, 	// 29
    CMPfrrra, 	// 30
    CMPfrrrr, 	// 31

Somewhere in my code, I have to write:

  unsigned opcode = MI->getOpcode(); // MachineInstr*
  if (CMPfaaaa == opcode ||
      CMPfaaar == opcode ||
      CMPfaara == opcode ||

Tzu-Chien Chiu - XGI Technology, Inc.
URL: http://www.csie.nctu.edu.tw/~jwchiu/

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