[LLVMdev] Target.td:Register changes

[Vladimir Prus]

On Tuesday 16 November 2004 20:21, Chris Lattner wrote:
> On Tue, 16 Nov 2004, Vladimir Prus wrote:
> > and I could not find any discussions in the archives.
> >
> > Why the change was necessary? Writing:
> >
> >   def gr0 : Register<"gr0">;
> >   def gr1 : Register<"gr1">;
> >   def gr2 : Register<"gr2">;
> >   def gr3 : Register<"gr3">;
> >   def gr4 : Register<"gr4">;
> >
> > is a bit boring and it's very easy to make a mistake. How the names are
> > used?
>
> To be honest, I don't remember any more. :)  I think it was a combination
> of this:
>
> 1. We would prefer tblgen definitions to be uppercase, but register names
>    are often assemblers want things in lower case (e.g. like the above).
> 2. Some register names have characters that tblgen doesn't like for
>    identifiers, e.g. X86 has "ST(0)".
> 3. Having support for both "has an explicit name" and "does not have an
>    explicit name" means we need to have duplicate tblgen classes, e.g.
>    NamedRegister vs Register.  I think the reason for making this change
>    was because we were introducing RegisterGroup and didn't want to have
>    to introduce NamedRegisterGroup for consistency.

Ok. I wonder if default parameter of some kind would help. OTOH, I've already 
updated my code ;-)

- VOlodya