>From 7e2cc76a0dc5d1c7001a54c50ad887758ee056e1 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 17 Apr 2014 18:58:58 -0400 Subject: [PATCH] XXX: Fix assertion in coalescer. --- lib/CodeGen/RegisterCoalescer.cpp | 7 ++++--- lib/Target/R600/SIInstrInfo.cpp | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index e16b5cb..b4528f0 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -816,12 +816,13 @@ bool RegisterCoalescer::reMaterializeTrivialDef(CoalescerPair &CP, // We need to remember these so we can add intervals once we insert // NewMI into SlotIndexes. SmallVector NewMIImplDefs; + NewMI->dump(); for (unsigned i = NewMI->getDesc().getNumOperands(), e = NewMI->getNumOperands(); i != e; ++i) { + dbgs() << "i is " << i << "\n"; MachineOperand &MO = NewMI->getOperand(i); - if (MO.isReg()) { - assert(MO.isDef() && MO.isImplicit() && MO.isDead() && - TargetRegisterInfo::isPhysicalRegister(MO.getReg())); + if (MO.isReg() && MO.isDef() && MO.isImplicit() && MO.isDead() && + TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { NewMIImplDefs.push_back(MO.getReg()); } } diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index ec405ac..6586e76 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -96,6 +96,7 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, return; } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) { + MI->dump(); assert(AMDGPU::SReg_64RegClass.contains(SrcReg)); BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)); -- 1.8.1.5