[llvm] [CodeLayout] Avoid repeated full scans in ExtTSP merging (PR #214016)

[Satoshi Kawasaki via llvm-commits]

akatsukiwork0320 wrote:

@spupyrev, regarding the layout-equivalence question: AI-assisted differential testing
found non-identical layouts due to near-tie selection, with score changes in
both directions. Of 2,001 synthetic inputs, 15 changed layout: 5 had lower
ExtTSP scores, 9 higher scores, and 1 the same score. Original relative changes
ranged from -4.95% to +7.08%. The inputs deliberately exercise distance-cutoff
boundaries, so these frequencies do not estimate production behavior.

Replacing only the old full-scan chooser with strict score+ID selection
matched the PR on every tested input. In the reduced case below, both first
divergent merge gains are mathematically 4, but one evaluates to
4.0000000000000009. The old EPS rule breaks that tie by chain IDs; the PR
chooses the slightly larger floating value.

This 8-node witness was reduced from walk_788 (-1.46% before reduction):

```cpp
using namespace llvm::codelayout;
const uint64_t Sizes[] = {1, 8, 1, 640, 8, 640, 1, 4};
const uint64_t Counts[] = {8, 8, 1, 7, 7, 9, 3, 8};
const EdgeCount Edges[] = {
    {0, 3, 2},
    {0, 4, 4},
    {0, 5, 2},
    {1, 2, 1},
    {1, 3, 2},
    {1, 4, 2},
    {1, 7, 3},
    {2, 7, 1},
    {3, 1, 4},
    {3, 4, 1},
    {3, 6, 1},
    {3, 7, 1},
    {4, 5, 7},
    {5, 1, 4},
    {5, 3, 1},
    {5, 6, 2},
    {5, 7, 2},
    {6, 3, 2},
    {6, 7, 1}
};
auto Order = computeExtTspLayout(Sizes, Counts, Edges);
```

Parent 8dc4bb7: [0,4,5,6,3,1,7,2], score approximately 23.2792.
Head 3451f2d: [0,6,3,4,5,1,7,2], score approximately 18.3527.
The larger -21.16% change is specific to the reduced witness, not an average.
Its counts come from 8 terminating traces; this is not a miscompilation or
measured generated-binary runtime regression.

For this witness, exhaustive enumeration of all 5,040 entry-first layouts
without padding, using exact rational default ExtTSP weights, finds the
parent's layout uniquely optimal and the PR's layout 49th by objective score.

The parent's EPS is absolute (1e-8). With sizes unchanged, scaling this
witness's node and edge counts by 2^k makes the parent choose the PR layout
for all tested k=25..40; the layouts differ for k=0..24. This is a result for
this witness, not a universal score threshold for rounding effects.

Reproduced with pinned LLVM headers and original SmallVector/MemAlloc sources
in a standalone build with default-option, configuration, debug and error
shims (not a full LLVM build).

Is this near-tie selection change intended? The worklist speedup remains
valuable; this example makes its selection-semantics tradeoff explicit.

AI assistance: harness implementation, execution, reduction and analysis.


https://github.com/llvm/llvm-project/pull/214016