[llvm] [SelectionDAG] Preserve demanded lanes in sign-bit queries (PR #230093)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,223 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs < %s | FileCheck %s
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arsenm wrote:

```suggestion
; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
```

https://github.com/llvm/llvm-project/pull/230093