[llvm] [X86] Allow bf16 masked load/store with AVX512BW (PR #230953)

[Divyansh Yadav via llvm-commits]

schizophrenicmaniac wrote:

@RKSimon You were right. Those patterns never got a chance because v8bf16/v16bf16/v32bf16 only had register classes with BF16/AVXNECONVERT, so on plain BWI the types were illegal and got split up before isel. I've dropped the combines and made the vXbf16 types legal with BWI instead (avx512bf16 implies BWI, so it's just a wider condition).

That needed a few other bits to avoid crashes and regressions: v8bf16/v16bf16 now use the same non-VLX MLOAD/MSTORE widening as f16, a few broadcast/insert/extract/subvec-zero patterns that were gated on HasBF16/HasAVXNECONVERT now only need BWI (or AVX2 for the NoVLX ones), and vector fptrunc to bf16 without native converts now uses expandFP_ROUND. Otherwise the widened v4bf16 fptrunc got unrolled into libcalls, including the undef lanes. I also added a BWI run to bfloat.ll; most of the bf16 vector code there isn't scalarized anymore. Happy to split the fptrunc part out if you'd prefer.

https://github.com/llvm/llvm-project/pull/230953