[llvm] c208df9 - X86/GlobalISel: Mark unused FP compare flag defs dead (#231003)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 11 10:18:37 PDT 2026
Author: Matt Arsenault
Date: 2026-10-11T17:18:32Z
New Revision: c208df95aa58de66aa5e4aa766a51e904bb32eb9
URL: https://github.com/llvm/llvm-project/commit/c208df95aa58de66aa5e4aa766a51e904bb32eb9
DIFF: https://github.com/llvm/llvm-project/commit/c208df95aa58de66aa5e4aa766a51e904bb32eb9.diff
LOG: X86/GlobalISel: Mark unused FP compare flag defs dead (#231003)
Fix not marking FPSW and EFLAGS clobbers as dead in the manual fcmp
selection.
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
Added:
Modified:
llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
llvm/test/CodeGen/X86/GlobalISel/select-fcmp.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index 072fa5f2ef525..f467d85b67f4e 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -1128,6 +1128,8 @@ bool X86InstructionSelector::selectFCmp(MachineInstr &I,
assert((LhsBank == RhsBank) &&
"Both banks assigned to FCMP arguments need to be same!");
+ bool IsX87 = LhsBank->getID() == X86::PSRRegBankID;
+
// Compute the opcode for the CMP instruction.
unsigned OpCmp;
LLT Ty = MRI.getType(LhsReg);
@@ -1135,12 +1137,10 @@ bool X86InstructionSelector::selectFCmp(MachineInstr &I,
default:
return false;
case 32:
- OpCmp = LhsBank->getID() == X86::PSRRegBankID ? X86::UCOM_FpIr32
- : X86::UCOMISSrr;
+ OpCmp = IsX87 ? X86::UCOM_FpIr32 : X86::UCOMISSrr;
break;
case 64:
- OpCmp = LhsBank->getID() == X86::PSRRegBankID ? X86::UCOM_FpIr64
- : X86::UCOMISDrr;
+ OpCmp = IsX87 ? X86::UCOM_FpIr64 : X86::UCOMISDrr;
break;
case 80:
OpCmp = X86::UCOM_FpIr80;
@@ -1156,6 +1156,8 @@ bool X86InstructionSelector::selectFCmp(MachineInstr &I,
*BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
.addReg(LhsReg)
.addReg(RhsReg);
+ if (IsX87)
+ CmpInst.getOperand(3).setIsDead(); // Mark unused FPSW def dead.
Register FlagReg1 = MRI.createVirtualRegister(&X86::GR8RegClass);
Register FlagReg2 = MRI.createVirtualRegister(&X86::GR8RegClass);
@@ -1166,7 +1168,8 @@ bool X86InstructionSelector::selectFCmp(MachineInstr &I,
MachineInstr &Set3 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
TII.get(SETFOpc[2]), ResultReg)
.addReg(FlagReg1)
- .addReg(FlagReg2);
+ .addReg(FlagReg2)
+ .setOperandDead(3);
constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
constrainSelectedInstRegOperands(Set1, TII, TRI, RBI);
constrainSelectedInstRegOperands(Set2, TII, TRI, RBI);
@@ -1189,6 +1192,8 @@ bool X86InstructionSelector::selectFCmp(MachineInstr &I,
*BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
.addReg(LhsReg)
.addReg(RhsReg);
+ if (IsX87)
+ CmpInst.getOperand(3).setIsDead(); // Mark unused FPSW def dead.
MachineInstr &Set =
*BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
diff --git a/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir b/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
index fc9792824a360..de179110ff9ef 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
@@ -19,10 +19,10 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_oeq
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
; GISEL-X86-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
- ; GISEL-X86-NEXT: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
+ ; GISEL-X86-NEXT: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def dead $eflags
; GISEL-X86-NEXT: $al = COPY [[AND8rr]]
; GISEL-X86-NEXT: RET 0, implicit $al
%3:_(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -49,7 +49,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_ogt
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -77,7 +77,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_oge
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -105,7 +105,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_olt
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -133,7 +133,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_ole
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -160,7 +160,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_one
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -188,7 +188,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_ord
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -215,7 +215,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_uno
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -243,7 +243,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_ueq
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -272,7 +272,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_ugt
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -300,7 +300,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_uge
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -329,7 +329,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_ult
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -357,7 +357,7 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_ule
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
; GISEL-X86-NEXT: RET 0, implicit $al
@@ -384,10 +384,10 @@ body: |
; GISEL-X86-LABEL: name: fcmp_double_une
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
- ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
+ ; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def dead $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
; GISEL-X86-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
- ; GISEL-X86-NEXT: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
+ ; GISEL-X86-NEXT: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def dead $eflags
; GISEL-X86-NEXT: $al = COPY [[OR8rr]]
; GISEL-X86-NEXT: RET 0, implicit $al
%3:_(p0) = G_FRAME_INDEX %fixed-stack.0
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fcmp.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fcmp.mir
index 2f0e60d53b9b0..97984d837cf9a 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-fcmp.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-fcmp.mir
@@ -172,7 +172,7 @@ body: |
; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
- ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
+ ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def dead $eflags
; CHECK: $al = COPY [[AND8rr]]
; CHECK: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
@@ -668,7 +668,7 @@ body: |
; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
- ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
+ ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def dead $eflags
; CHECK: $al = COPY [[OR8rr]]
; CHECK: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
@@ -708,7 +708,7 @@ body: |
; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
- ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
+ ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def dead $eflags
; CHECK: $al = COPY [[AND8rr]]
; CHECK: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
@@ -1204,7 +1204,7 @@ body: |
; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
- ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
+ ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def dead $eflags
; CHECK: $al = COPY [[OR8rr]]
; CHECK: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
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