[llvm] Rename TableGen MIPS Registers to R<#> (PR #230696)
Anton Rapetov via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 11 10:06:22 PDT 2026
https://github.com/willir updated https://github.com/llvm/llvm-project/pull/230696
>From 7e65235b5143aaa25782979e18ce9e891fb7535f Mon Sep 17 00:00:00 2001
From: Vince Del Vecchio <vince.delvecchio at mediatek.com>
Date: Wed, 30 Sep 2026 18:37:57 -0400
Subject: [PATCH 1/7] [Mips] Rename ABI-dependent GPRs to R2/R3/R8-R15 and add
ABI aliases
The records for $2-$3 and $8-$15 were named after their O32 roles
(V0-V1, T0-T7), but those names mean different registers in N32/N64
and P32/P64 (e.g. T0 is $8 in O32 but $12 in N32/N64/P32). #224284
left a TODO to move to ABI-independent record names.
Rename them to R2, R3 and R8-R15 (plus _64 forms) and keep per-ABI
aliases in TableGen (defvar) and C++ (constexpr in MipsMCTargetDesc.h):
O32: V0, V1, T0-T7
N32/N64: V0_N, V1_N, A4_N-A7_N, T0_N-T3_N
P32/P64: T4_P, T5_P, A4_P-A7_P, T0_P-T3_P
The NABI/PABI tables and N32/N64 calling conventions use the new
aliases. The interrupt callee-saved lists use R%u sequences, since
`sequence` can't see defvars. Assembly syntax is unchanged. Since the
enum is sorted by record name, this reorders MIR liveins and changes
one register-allocation tie-break (mips64-f128.ll).
Co-Authored-By: Claude Opus <noreply at anthropic.com>
---
.../Target/Mips/MCTargetDesc/MipsABIInfo.cpp | 26 ++--
.../Mips/MCTargetDesc/MipsMCTargetDesc.h | 75 +++++++++++
llvm/lib/Target/Mips/MipsCallingConv.td | 47 ++++---
llvm/lib/Target/Mips/MipsRegisterInfo.td | 118 ++++++++++++++----
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 2 +-
5 files changed, 213 insertions(+), 55 deletions(-)
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 3f7a0c7f2fa10..57b1324af9481 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -29,11 +29,11 @@ namespace {
static constexpr MCPhysReg O32IntRegs[] = {Mips::A0, Mips::A1, Mips::A2,
Mips::A3};
static constexpr MCPhysReg NABIIntRegs[] = {Mips::A0, Mips::A1, Mips::A2,
- Mips::A3, Mips::T0, Mips::T1,
- Mips::T2, Mips::T3};
+ Mips::A3, Mips::A4_N, Mips::A5_N,
+ Mips::A6_N, Mips::A7_N};
static constexpr MCPhysReg Mips64IntRegs[] = {
Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
- Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
+ Mips::A4_N_64, Mips::A5_N_64, Mips::A6_N_64, Mips::A7_N_64};
struct GPR {
MCPhysReg Reg32;
@@ -48,10 +48,10 @@ static constexpr GPR OABITempRegs[] = {
};
static constexpr GPR NABITempRegs[] = {
- {Mips::T4, Mips::T4_64},
- {Mips::T5, Mips::T5_64},
- {Mips::T6, Mips::T6_64},
- {Mips::T7, Mips::T7_64},
+ {Mips::T0_N, Mips::T0_N_64},
+ {Mips::T1_N, Mips::T1_N_64},
+ {Mips::T2_N, Mips::T2_N_64},
+ {Mips::T3_N, Mips::T3_N_64},
{Mips::NoRegister, Mips::NoRegister},
{Mips::NoRegister, Mips::NoRegister},
{Mips::NoRegister, Mips::NoRegister},
@@ -61,12 +61,12 @@ static constexpr GPR NABITempRegs[] = {
};
static constexpr GPR PABITempRegs[] = {
- {Mips::T4, Mips::T4_64},
- {Mips::T5, Mips::T5_64},
- {Mips::T6, Mips::T6_64},
- {Mips::T7, Mips::T7_64},
- {Mips::V0, Mips::V0_64},
- {Mips::V1, Mips::V1_64},
+ {Mips::T0_P, Mips::T0_P_64},
+ {Mips::T1_P, Mips::T1_P_64},
+ {Mips::T2_P, Mips::T2_P_64},
+ {Mips::T3_P, Mips::T3_P_64},
+ {Mips::T4_P, Mips::T4_P_64},
+ {Mips::T5_P, Mips::T5_P_64},
{Mips::NoRegister, Mips::NoRegister},
{Mips::NoRegister, Mips::NoRegister},
{Mips::T8, Mips::T8_64},
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
index db9b4bf233353..44b709f3a0410 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
@@ -13,6 +13,7 @@
#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
+#include "llvm/MC/MCRegister.h"
#include "llvm/Support/DataTypes.h"
#include <memory>
@@ -78,6 +79,80 @@ int getCPURegisterIndex(StringRef Name, const MCRegisterInfo &MRI,
#define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc"
+namespace llvm {
+namespace Mips {
+// R2-R3 and R8-R15 have different names in the O32 (O), N32/N64 (N) and
+// P32/P64 (P) ABIs. These aliases match the ones in MipsRegisterInfo.td; the
+// unsuffixed O names are kept for compatibility.
+
+// O32 names.
+inline constexpr MCPhysReg V0 = R2;
+inline constexpr MCPhysReg V1 = R3;
+inline constexpr MCPhysReg T0 = R8;
+inline constexpr MCPhysReg T1 = R9;
+inline constexpr MCPhysReg T2 = R10;
+inline constexpr MCPhysReg T3 = R11;
+inline constexpr MCPhysReg T4 = R12;
+inline constexpr MCPhysReg T5 = R13;
+inline constexpr MCPhysReg T6 = R14;
+inline constexpr MCPhysReg T7 = R15;
+inline constexpr MCPhysReg V0_64 = R2_64;
+inline constexpr MCPhysReg V1_64 = R3_64;
+inline constexpr MCPhysReg T0_64 = R8_64;
+inline constexpr MCPhysReg T1_64 = R9_64;
+inline constexpr MCPhysReg T2_64 = R10_64;
+inline constexpr MCPhysReg T3_64 = R11_64;
+inline constexpr MCPhysReg T4_64 = R12_64;
+inline constexpr MCPhysReg T5_64 = R13_64;
+inline constexpr MCPhysReg T6_64 = R14_64;
+inline constexpr MCPhysReg T7_64 = R15_64;
+
+// N32/N64 names.
+inline constexpr MCPhysReg V0_N = R2;
+inline constexpr MCPhysReg V1_N = R3;
+inline constexpr MCPhysReg A4_N = R8;
+inline constexpr MCPhysReg A5_N = R9;
+inline constexpr MCPhysReg A6_N = R10;
+inline constexpr MCPhysReg A7_N = R11;
+inline constexpr MCPhysReg T0_N = R12;
+inline constexpr MCPhysReg T1_N = R13;
+inline constexpr MCPhysReg T2_N = R14;
+inline constexpr MCPhysReg T3_N = R15;
+inline constexpr MCPhysReg V0_N_64 = R2_64;
+inline constexpr MCPhysReg V1_N_64 = R3_64;
+inline constexpr MCPhysReg A4_N_64 = R8_64;
+inline constexpr MCPhysReg A5_N_64 = R9_64;
+inline constexpr MCPhysReg A6_N_64 = R10_64;
+inline constexpr MCPhysReg A7_N_64 = R11_64;
+inline constexpr MCPhysReg T0_N_64 = R12_64;
+inline constexpr MCPhysReg T1_N_64 = R13_64;
+inline constexpr MCPhysReg T2_N_64 = R14_64;
+inline constexpr MCPhysReg T3_N_64 = R15_64;
+
+// P32/P64 names.
+inline constexpr MCPhysReg T4_P = R2;
+inline constexpr MCPhysReg T5_P = R3;
+inline constexpr MCPhysReg A4_P = R8;
+inline constexpr MCPhysReg A5_P = R9;
+inline constexpr MCPhysReg A6_P = R10;
+inline constexpr MCPhysReg A7_P = R11;
+inline constexpr MCPhysReg T0_P = R12;
+inline constexpr MCPhysReg T1_P = R13;
+inline constexpr MCPhysReg T2_P = R14;
+inline constexpr MCPhysReg T3_P = R15;
+inline constexpr MCPhysReg T4_P_64 = R2_64;
+inline constexpr MCPhysReg T5_P_64 = R3_64;
+inline constexpr MCPhysReg A4_P_64 = R8_64;
+inline constexpr MCPhysReg A5_P_64 = R9_64;
+inline constexpr MCPhysReg A6_P_64 = R10_64;
+inline constexpr MCPhysReg A7_P_64 = R11_64;
+inline constexpr MCPhysReg T0_P_64 = R12_64;
+inline constexpr MCPhysReg T1_P_64 = R13_64;
+inline constexpr MCPhysReg T2_P_64 = R14_64;
+inline constexpr MCPhysReg T3_P_64 = R15_64;
+} // namespace Mips
+} // namespace llvm
+
// Defines symbolic names for the Mips instructions.
#define GET_INSTRINFO_ENUM
#define GET_INSTRINFO_MC_HELPER_DECLS
diff --git a/llvm/lib/Target/Mips/MipsCallingConv.td b/llvm/lib/Target/Mips/MipsCallingConv.td
index d3e552bc71ca9..e6f14f9234ea6 100644
--- a/llvm/lib/Target/Mips/MipsCallingConv.td
+++ b/llvm/lib/Target/Mips/MipsCallingConv.td
@@ -37,7 +37,7 @@ class CCIfSpecialCallingConv<string CC, CCAction A>
// For soft-float, f128 values are returned in A0_64 rather than V1_64.
def RetCC_F128SoftFloat : CallingConv<[
- CCAssignToReg<[V0_64, A0_64]>
+ CCAssignToReg<[V0_N_64, A0_64]>
]>;
// For hard-float, f128 values are returned as a pair of f64's rather than a
@@ -113,7 +113,7 @@ def CC_MipsO32_FP : CallingConv<[
def CC_MipsN_SoftFloat : CallingConv<[
CCAssignToRegWithShadow<[A0, A1, A2, A3,
- T0, T1, T2, T3],
+ A4_N, A5_N, A6_N, A7_N],
[D12_64, D13_64, D14_64, D15_64,
D16_64, D17_64, D18_64, D19_64]>,
CCAssignToStack<4, 8>
@@ -134,7 +134,8 @@ def CC_MipsN : CallingConv<[
// Integer arguments are passed in integer registers.
CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
- T0_64, T1_64, T2_64, T3_64],
+ A4_N_64, A5_N_64, A6_N_64,
+ A7_N_64],
[D12_64, D13_64, D14_64, D15_64,
D16_64, D17_64, D18_64, D19_64]>>,
@@ -142,13 +143,15 @@ def CC_MipsN : CallingConv<[
CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
F16, F17, F18, F19],
[A0_64, A1_64, A2_64, A3_64,
- T0_64, T1_64, T2_64, T3_64]>>,
+ A4_N_64, A5_N_64, A6_N_64,
+ A7_N_64]>>,
// f64 arguments are passed in double precision FP registers.
CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
D16_64, D17_64, D18_64, D19_64],
[A0_64, A1_64, A2_64, A3_64,
- T0_64, T1_64, T2_64, T3_64]>>,
+ A4_N_64, A5_N_64, A6_N_64,
+ A7_N_64]>>,
// All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
CCIfType<[f32], CCAssignToStack<4, 8>>,
@@ -165,10 +168,10 @@ def CC_MipsN_VarArg : CallingConv<[
// All integers are promoted to 64-bit.
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
- CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
+ CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, A4_N, A5_N, A6_N, A7_N]>>,
CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
- T0_64, T1_64, T2_64, T3_64]>>,
+ A4_N_64, A5_N_64, A6_N_64, A7_N_64]>>,
// All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
CCIfType<[f32], CCAssignToStack<4, 8>>,
@@ -198,8 +201,8 @@ def RetCC_MipsN : CallingConv<[
CCIfType<[i8, i16, i32, i64],
CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
- // i64 are returned in registers V0_64, V1_64
- CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
+ // i64 are returned in registers V0_N_64, V1_N_64
+ CCIfType<[i64], CCAssignToReg<[V0_N_64, V1_N_64]>>,
// f32 are returned in registers F0, F2
CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
@@ -234,9 +237,9 @@ def CC_MipsO32_FastCC : CallingConv<[
def CC_MipsN_FastCC : CallingConv<[
// Integer arguments are passed in integer registers.
- CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
- T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
- T8_64, V1_64]>>,
+ CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, A4_N_64,
+ A5_N_64, A6_N_64, A7_N_64, T0_N_64, T1_N_64,
+ T2_N_64, T3_N_64, T8_64, V1_N_64]>>,
// f64 arguments are passed in double-precision floating pointer registers.
CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
@@ -392,25 +395,29 @@ def CSR_Mips16RetHelper :
def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
(sequence "S%u", 7, 0),
- (sequence "V%u", 1, 0),
- (sequence "T%u", 9, 0),
+ (sequence "R%u", 3, 2),
+ T9, T8,
+ (sequence "R%u", 15, 8),
RA, FP, GP, AT)>;
def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
(sequence "S%u", 7, 0),
- (sequence "V%u", 1, 0),
- (sequence "T%u", 9, 0),
+ (sequence "R%u", 3, 2),
+ T9, T8,
+ (sequence "R%u", 15, 8),
RA, FP, GP, AT, LO0, HI0)>;
def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
- (sequence "V%u_64", 1, 0),
+ (sequence "R%u_64", 3, 2),
(sequence "S%u_64", 7, 0),
- (sequence "T%u_64", 9, 0),
+ T9_64, T8_64,
+ (sequence "R%u_64", 15, 8),
RA_64, FP_64, GP_64, AT_64)>;
def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
(sequence "S%u_64", 7, 0),
- (sequence "T%u_64", 9, 0),
- (sequence "V%u_64", 1, 0),
+ T9_64, T8_64,
+ (sequence "R%u_64", 15, 8),
+ (sequence "R%u_64", 3, 2),
RA_64, FP_64, GP_64, AT_64,
LO0_64, HI0_64)>;
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td
index a1c775060786d..e25ca335cdb0e 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.td
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td
@@ -103,25 +103,27 @@ class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
let Namespace = "Mips" in {
// General Purpose Registers
- // TODO: Use R0-R31/R0_64-R31_64 record names without changing MIR names.
+ // Registers whose ABI names differ between the O, N and P ABIs use
+ // ABI-independent R<n> record names; see the ABI aliases below.
+ // TODO: Use R0-R31/R0_64-R31_64 record names for the remaining registers.
// Use MipsABIInfo accessors for ABI roles.
let isConstant = true in
def ZERO : MipsGPRReg< 0, "zero", "zero">, DwarfRegNum<[0]>;
def AT : MipsGPRReg< 1, "1", "at">, DwarfRegNum<[1]>;
- def V0 : MipsGPRReg< 2, "2", "v0", "v0", "t4">, DwarfRegNum<[2]>;
- def V1 : MipsGPRReg< 3, "3", "v1", "v1", "t5">, DwarfRegNum<[3]>;
+ def R2 : MipsGPRReg< 2, "2", "v0", "v0", "t4">, DwarfRegNum<[2]>;
+ def R3 : MipsGPRReg< 3, "3", "v1", "v1", "t5">, DwarfRegNum<[3]>;
def A0 : MipsGPRReg< 4, "4", "a0">, DwarfRegNum<[4]>;
def A1 : MipsGPRReg< 5, "5", "a1">, DwarfRegNum<[5]>;
def A2 : MipsGPRReg< 6, "6", "a2">, DwarfRegNum<[6]>;
def A3 : MipsGPRReg< 7, "7", "a3">, DwarfRegNum<[7]>;
- def T0 : MipsGPRReg< 8, "8", "t0", "a4">, DwarfRegNum<[8]>;
- def T1 : MipsGPRReg< 9, "9", "t1", "a5">, DwarfRegNum<[9]>;
- def T2 : MipsGPRReg<10, "10", "t2", "a6">, DwarfRegNum<[10]>;
- def T3 : MipsGPRReg<11, "11", "t3", "a7">, DwarfRegNum<[11]>;
- def T4 : MipsGPRReg<12, "12", "t4", "t0">, DwarfRegNum<[12]>;
- def T5 : MipsGPRReg<13, "13", "t5", "t1">, DwarfRegNum<[13]>;
- def T6 : MipsGPRReg<14, "14", "t6", "t2">, DwarfRegNum<[14]>;
- def T7 : MipsGPRReg<15, "15", "t7", "t3">, DwarfRegNum<[15]>;
+ def R8 : MipsGPRReg< 8, "8", "t0", "a4">, DwarfRegNum<[8]>;
+ def R9 : MipsGPRReg< 9, "9", "t1", "a5">, DwarfRegNum<[9]>;
+ def R10 : MipsGPRReg<10, "10", "t2", "a6">, DwarfRegNum<[10]>;
+ def R11 : MipsGPRReg<11, "11", "t3", "a7">, DwarfRegNum<[11]>;
+ def R12 : MipsGPRReg<12, "12", "t4", "t0">, DwarfRegNum<[12]>;
+ def R13 : MipsGPRReg<13, "13", "t5", "t1">, DwarfRegNum<[13]>;
+ def R14 : MipsGPRReg<14, "14", "t6", "t2">, DwarfRegNum<[14]>;
+ def R15 : MipsGPRReg<15, "15", "t7", "t3">, DwarfRegNum<[15]>;
def S0 : MipsGPRReg<16, "16", "s0">, DwarfRegNum<[16]>;
def S1 : MipsGPRReg<17, "17", "s1">, DwarfRegNum<[17]>;
def S2 : MipsGPRReg<18, "18", "s2">, DwarfRegNum<[18]>;
@@ -143,20 +145,20 @@ let Namespace = "Mips" in {
let isConstant = true in
def ZERO_64 : Mips64GPRReg<ZERO>, DwarfRegNum<[0]>;
def AT_64 : Mips64GPRReg<AT>, DwarfRegNum<[1]>;
- def V0_64 : Mips64GPRReg<V0>, DwarfRegNum<[2]>;
- def V1_64 : Mips64GPRReg<V1>, DwarfRegNum<[3]>;
+ def R2_64 : Mips64GPRReg<R2>, DwarfRegNum<[2]>;
+ def R3_64 : Mips64GPRReg<R3>, DwarfRegNum<[3]>;
def A0_64 : Mips64GPRReg<A0>, DwarfRegNum<[4]>;
def A1_64 : Mips64GPRReg<A1>, DwarfRegNum<[5]>;
def A2_64 : Mips64GPRReg<A2>, DwarfRegNum<[6]>;
def A3_64 : Mips64GPRReg<A3>, DwarfRegNum<[7]>;
- def T0_64 : Mips64GPRReg<T0>, DwarfRegNum<[8]>;
- def T1_64 : Mips64GPRReg<T1>, DwarfRegNum<[9]>;
- def T2_64 : Mips64GPRReg<T2>, DwarfRegNum<[10]>;
- def T3_64 : Mips64GPRReg<T3>, DwarfRegNum<[11]>;
- def T4_64 : Mips64GPRReg<T4>, DwarfRegNum<[12]>;
- def T5_64 : Mips64GPRReg<T5>, DwarfRegNum<[13]>;
- def T6_64 : Mips64GPRReg<T6>, DwarfRegNum<[14]>;
- def T7_64 : Mips64GPRReg<T7>, DwarfRegNum<[15]>;
+ def R8_64 : Mips64GPRReg<R8>, DwarfRegNum<[8]>;
+ def R9_64 : Mips64GPRReg<R9>, DwarfRegNum<[9]>;
+ def R10_64 : Mips64GPRReg<R10>, DwarfRegNum<[10]>;
+ def R11_64 : Mips64GPRReg<R11>, DwarfRegNum<[11]>;
+ def R12_64 : Mips64GPRReg<R12>, DwarfRegNum<[12]>;
+ def R13_64 : Mips64GPRReg<R13>, DwarfRegNum<[13]>;
+ def R14_64 : Mips64GPRReg<R14>, DwarfRegNum<[14]>;
+ def R15_64 : Mips64GPRReg<R15>, DwarfRegNum<[15]>;
def S0_64 : Mips64GPRReg<S0>, DwarfRegNum<[16]>;
def S1_64 : Mips64GPRReg<S1>, DwarfRegNum<[17]>;
def S2_64 : Mips64GPRReg<S2>, DwarfRegNum<[18]>;
@@ -299,6 +301,80 @@ let Namespace = "Mips" in {
}
+//===----------------------------------------------------------------------===//
+// ABI register aliases
+//===----------------------------------------------------------------------===//
+
+// R2-R3 and R8-R15 have different names in the O32 (O), N32/N64 (N) and
+// P32/P64 (P) ABIs. Provide aliases for each ABI; the unsuffixed O names are
+// kept for compatibility. MipsMCTargetDesc.h has the matching C++ aliases.
+
+// O32 names.
+defvar V0 = R2;
+defvar V1 = R3;
+defvar T0 = R8;
+defvar T1 = R9;
+defvar T2 = R10;
+defvar T3 = R11;
+defvar T4 = R12;
+defvar T5 = R13;
+defvar T6 = R14;
+defvar T7 = R15;
+defvar V0_64 = R2_64;
+defvar V1_64 = R3_64;
+defvar T0_64 = R8_64;
+defvar T1_64 = R9_64;
+defvar T2_64 = R10_64;
+defvar T3_64 = R11_64;
+defvar T4_64 = R12_64;
+defvar T5_64 = R13_64;
+defvar T6_64 = R14_64;
+defvar T7_64 = R15_64;
+
+// N32/N64 names.
+defvar V0_N = R2;
+defvar V1_N = R3;
+defvar A4_N = R8;
+defvar A5_N = R9;
+defvar A6_N = R10;
+defvar A7_N = R11;
+defvar T0_N = R12;
+defvar T1_N = R13;
+defvar T2_N = R14;
+defvar T3_N = R15;
+defvar V0_N_64 = R2_64;
+defvar V1_N_64 = R3_64;
+defvar A4_N_64 = R8_64;
+defvar A5_N_64 = R9_64;
+defvar A6_N_64 = R10_64;
+defvar A7_N_64 = R11_64;
+defvar T0_N_64 = R12_64;
+defvar T1_N_64 = R13_64;
+defvar T2_N_64 = R14_64;
+defvar T3_N_64 = R15_64;
+
+// P32/P64 names.
+defvar T4_P = R2;
+defvar T5_P = R3;
+defvar A4_P = R8;
+defvar A5_P = R9;
+defvar A6_P = R10;
+defvar A7_P = R11;
+defvar T0_P = R12;
+defvar T1_P = R13;
+defvar T2_P = R14;
+defvar T3_P = R15;
+defvar T4_P_64 = R2_64;
+defvar T5_P_64 = R3_64;
+defvar A4_P_64 = R8_64;
+defvar A5_P_64 = R9_64;
+defvar A6_P_64 = R10_64;
+defvar A7_P_64 = R11_64;
+defvar T0_P_64 = R12_64;
+defvar T1_P_64 = R13_64;
+defvar T2_P_64 = R14_64;
+defvar T3_P_64 = R15_64;
+
//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index 54a2260b8311c..392b9b4f9059a 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -1034,7 +1034,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
DestReg = Mips::V1;
} else {
RdhwrOpc = Mips::RDHWR64;
- DestReg = Mips::V1_64;
+ DestReg = Mips::V1_N_64;
}
SDNode *Rdhwr =
>From 4e0866c66a04c2b2008d9baacd22eee47f69b05e Mon Sep 17 00:00:00 2001
From: Vince Del Vecchio <vince.delvecchio at mediatek.com>
Date: Wed, 30 Sep 2026 18:38:28 -0400
Subject: [PATCH 2/7] [Mips][test] Rename V0-V1/T0-T7 in MIR test inputs
Follow-up to the rename of the V0-V1 and T0-T7 register records to
R2-R3 and R8-R15. The MIR parser only accepts record names, so update
the register spellings in the input sections of the Mips MIR tests:
$v0/$v1 become $r2/$r3 and $t0-$t7 become $r8-$r15 (the _64 forms too).
This is a mechanical change. It only affects non-comment lines of .mir
files, including liveins, callee-saved and fixed-stack entries in the
YAML header. The CHECK lines were updated with the rename itself. The
change is kept separate so it can be replaced with MIR parser support
for the old spellings.
Co-Authored-By: Claude Opus <noreply at anthropic.com>
---
...lobal-value-or-symbol-after-call-entry.mir | 18 +-
.../test/CodeGen/MIR/Mips/memory-operands.mir | 42 +-
.../mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir | 8 +-
.../CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll | 4 +-
.../GlobalISel/instruction-select/add.mir | 32 +-
.../GlobalISel/instruction-select/bitwise.mir | 120 +++---
.../GlobalISel/instruction-select/branch.mir | 24 +-
.../instruction-select/brindirect.mir | 16 +-
.../GlobalISel/instruction-select/bswap.mir | 8 +-
.../instruction-select/constants.mir | 32 +-
.../GlobalISel/instruction-select/ctlz.mir | 8 +-
.../GlobalISel/instruction-select/fcmp.mir | 384 +++++++++---------
.../GlobalISel/instruction-select/fence.mir | 8 +-
.../instruction-select/fptosi_and_fptoui.mir | 24 +-
.../instruction-select/gloal_address.mir | 14 +-
.../instruction-select/gloal_address_pic.mir | 84 ++--
.../GlobalISel/instruction-select/icmp.mir | 88 ++--
.../inttoptr_and_ptrtoint.mir | 16 +-
.../jump_table_and_brjt.mir | 112 ++---
.../GlobalISel/instruction-select/load.mir | 12 +-
.../instruction-select/load_4_unaligned.mir | 8 +-
.../load_4_unaligned_r6.mir | 8 +-
.../instruction-select/load_store_fold.mir | 24 +-
.../GlobalISel/instruction-select/mul.mir | 8 +-
.../GlobalISel/instruction-select/phi.mir | 30 +-
.../instruction-select/pointers.mir | 24 +-
.../instruction-select/rem_and_div.mir | 32 +-
.../GlobalISel/instruction-select/select.mir | 24 +-
.../instruction-select/stack_args.mir | 16 +-
.../GlobalISel/instruction-select/sub.mir | 8 +-
.../GlobalISel/instruction-select/var_arg.mir | 4 +-
.../zextLoad_and_sextLoad.mir | 32 +-
.../Mips/GlobalISel/irtranslator/add.ll | 4 +-
.../GlobalISel/irtranslator/big-endian.ll | 16 +-
.../Mips/GlobalISel/irtranslator/bitwise.ll | 24 +-
.../Mips/GlobalISel/irtranslator/call.ll | 68 ++--
.../GlobalISel/irtranslator/extend_args.ll | 72 ++--
.../GlobalISel/irtranslator/global_address.ll | 8 +-
.../irtranslator/global_address_pic.ll | 28 +-
.../Mips/GlobalISel/irtranslator/pointers.ll | 12 +-
.../GlobalISel/irtranslator/split_args.ll | 30 +-
.../GlobalISel/irtranslator/stack_args.ll | 8 +-
.../Mips/GlobalISel/irtranslator/var_arg.ll | 4 +-
.../CodeGen/Mips/GlobalISel/legalizer/add.mir | 80 ++--
.../Mips/GlobalISel/legalizer/bitreverse.mir | 30 +-
.../Mips/GlobalISel/legalizer/bitwise.mir | 248 +++++------
.../Mips/GlobalISel/legalizer/branch.mir | 24 +-
.../Mips/GlobalISel/legalizer/brindirect.mir | 16 +-
.../Mips/GlobalISel/legalizer/bswap.mir | 30 +-
.../Mips/GlobalISel/legalizer/constants.mir | 68 ++--
.../Mips/GlobalISel/legalizer/ctlz.mir | 20 +-
.../Mips/GlobalISel/legalizer/ctpop.mir | 20 +-
.../Mips/GlobalISel/legalizer/cttz.mir | 40 +-
.../GlobalISel/legalizer/dyn_stackalloc.mir | 4 +-
.../Mips/GlobalISel/legalizer/fcmp.mir | 24 +-
.../Mips/GlobalISel/legalizer/fence.mir | 8 +-
.../legalizer/fptosi_and_fptoui.mir | 264 ++++++------
.../GlobalISel/legalizer/global_address.mir | 16 +-
.../Mips/GlobalISel/legalizer/icmp.mir | 112 ++---
.../legalizer/inttoptr_and_ptrtoint.mir | 16 +-
.../legalizer/jump_table_and_brjt.mir | 72 ++--
.../Mips/GlobalISel/legalizer/load.mir | 20 +-
.../GlobalISel/legalizer/load_4_unaligned.mir | 48 +--
.../CodeGen/Mips/GlobalISel/legalizer/mul.mir | 92 ++---
.../CodeGen/Mips/GlobalISel/legalizer/phi.mir | 44 +-
.../Mips/GlobalISel/legalizer/pointers.mir | 24 +-
.../Mips/GlobalISel/legalizer/rem_and_div.mir | 168 ++++----
.../Mips/GlobalISel/legalizer/select.mir | 52 +--
.../Mips/GlobalISel/legalizer/stack_args.mir | 16 +-
.../CodeGen/Mips/GlobalISel/legalizer/sub.mir | 80 ++--
.../Mips/GlobalISel/legalizer/trunc.mir | 8 +-
.../legalizer/truncStore_and_aExtLoad.mir | 16 +-
.../Mips/GlobalISel/legalizer/var_arg.mir | 4 +-
.../legalizer/zextLoad_and_sextLoad.mir | 88 ++--
.../GlobalISel/legalizer/zext_and_sext.mir | 24 +-
.../GlobalISel/llvm-ir/big-endian-memory.ll | 12 +-
.../GlobalISel/llvm-ir/load_4_unaligned.ll | 4 +-
.../load_split_because_of_memsize_or_align.ll | 24 +-
.../truncStore_and_aExtLoad.mir | 16 +-
.../mips-prelegalizer-combiner/tryCombine.mir | 12 +-
.../zextLoad_and_sextLoad.mir | 88 ++--
.../Mips/GlobalISel/regbankselect/add.mir | 8 +-
.../Mips/GlobalISel/regbankselect/bitwise.mir | 72 ++--
.../Mips/GlobalISel/regbankselect/branch.mir | 24 +-
.../GlobalISel/regbankselect/brindirect.mir | 16 +-
.../Mips/GlobalISel/regbankselect/bswap.mir | 8 +-
.../Mips/GlobalISel/regbankselect/ctlz.mir | 8 +-
.../Mips/GlobalISel/regbankselect/fcmp.mir | 24 +-
.../Mips/GlobalISel/regbankselect/fence.mir | 8 +-
.../regbankselect/fptosi_and_fptoui.mir | 24 +-
.../regbankselect/global_address.mir | 16 +-
.../regbankselect/global_address_pic.mir | 24 +-
.../Mips/GlobalISel/regbankselect/icmp.mir | 16 +-
.../regbankselect/inttoptr_and_ptrtoint.mir | 16 +-
.../regbankselect/jump_table_and_brjt.mir | 72 ++--
.../Mips/GlobalISel/regbankselect/load.mir | 20 +-
.../regbankselect/load_4_unaligned.mir | 12 +-
.../Mips/GlobalISel/regbankselect/mul.mir | 8 +-
.../Mips/GlobalISel/regbankselect/phi.mir | 20 +-
.../GlobalISel/regbankselect/pointers.mir | 24 +-
.../GlobalISel/regbankselect/rem_and_div.mir | 32 +-
.../Mips/GlobalISel/regbankselect/select.mir | 28 +-
.../GlobalISel/regbankselect/stack_args.mir | 16 +-
.../Mips/GlobalISel/regbankselect/sub.mir | 8 +-
.../regbankselect/test_TypeInfoforMF.mir | 32 +-
.../Mips/GlobalISel/regbankselect/var_arg.mir | 4 +-
.../regbankselect/zextLoad_and_sextLoad.mir | 56 +--
.../regbankselect/zext_and_sext.mir | 24 +-
llvm/test/CodeGen/Mips/avoid-zero-copy.mir | 8 +-
.../CodeGen/Mips/cconv/illegal-vectors.ll | 6 +-
.../compact-branch-implicit-def.mir | 12 +-
.../Mips/compactbranches/empty-block.mir | 4 +-
llvm/test/CodeGen/Mips/copy-fp64.ll | 4 +-
...elay-slot-filler-bundled-insts-def-use.mir | 26 +-
.../Mips/delay-slot-filler-bundled-insts.mir | 14 +-
llvm/test/CodeGen/Mips/fmuladd-soft-float.ll | 8 +-
.../test/CodeGen/Mips/instverify/dext-pos.mir | 4 +-
.../CodeGen/Mips/instverify/dext-size.mir | 4 +-
.../Mips/instverify/dextm-pos-size.mir | 4 +-
.../CodeGen/Mips/instverify/dextm-pos.mir | 4 +-
.../CodeGen/Mips/instverify/dextm-size.mir | 4 +-
.../Mips/instverify/dextu-pos-size.mir | 4 +-
.../CodeGen/Mips/instverify/dextu-pos.mir | 4 +-
.../Mips/instverify/dextu-size-valid.mir | 4 +-
.../CodeGen/Mips/instverify/dextu-size.mir | 4 +-
.../CodeGen/Mips/instverify/dins-pos-size.mir | 4 +-
.../test/CodeGen/Mips/instverify/dins-pos.mir | 4 +-
.../CodeGen/Mips/instverify/dins-size.mir | 4 +-
.../Mips/instverify/dinsm-pos-size.mir | 4 +-
.../CodeGen/Mips/instverify/dinsm-pos.mir | 4 +-
.../CodeGen/Mips/instverify/dinsm-size.mir | 4 +-
.../Mips/instverify/dinsu-pos-size.mir | 4 +-
.../CodeGen/Mips/instverify/dinsu-pos.mir | 4 +-
.../CodeGen/Mips/instverify/dinsu-size.mir | 4 +-
.../CodeGen/Mips/instverify/ext-pos-size.mir | 4 +-
llvm/test/CodeGen/Mips/instverify/ext-pos.mir | 4 +-
.../test/CodeGen/Mips/instverify/ext-size.mir | 4 +-
.../CodeGen/Mips/instverify/ins-pos-size.mir | 4 +-
llvm/test/CodeGen/Mips/instverify/ins-pos.mir | 4 +-
.../test/CodeGen/Mips/instverify/ins-size.mir | 4 +-
llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll | 40 +-
llvm/test/CodeGen/Mips/llvm-ir/load.ll | 182 ++++-----
llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll | 12 +-
llvm/test/CodeGen/Mips/llvm-ir/store.ll | 12 +-
.../longbranch/branch-limits-fp-micromips.mir | 48 +--
.../branch-limits-fp-micromipsr6.mir | 48 +--
.../Mips/longbranch/branch-limits-fp-mips.mir | 48 +--
.../longbranch/branch-limits-fp-mipsr6.mir | 48 +--
.../branch-limits-int-microMIPS.mir | 24 +-
.../longbranch/branch-limits-int-mips64.mir | 144 +++----
.../longbranch/branch-limits-int-mips64r6.mir | 288 ++++++-------
.../Mips/longbranch/branch-limits-msa.mir | 240 +++++------
llvm/test/CodeGen/Mips/micromips-eva.mir | 4 +-
.../Mips/micromips-pseudo-mtlohi-expand.ll | 24 +-
.../Mips/micromips-short-delay-slot.mir | 4 +-
.../micromips-lwp-swp.mir | 24 +-
.../micromips-movep.mir | 36 +-
.../micromips-no-lwp-swp.mir | 24 +-
llvm/test/CodeGen/Mips/mips64-f128.ll | 4 +-
.../mirparser/target-flags-pic-mxgot-tls.mir | 32 +-
.../Mips/mirparser/target-flags-pic-o32.mir | 14 +-
.../Mips/mirparser/target-flags-pic.mir | 8 +-
.../mirparser/target-flags-static-tls.mir | 28 +-
.../test/CodeGen/Mips/msa/emergency-spill.mir | 56 +--
llvm/test/CodeGen/Mips/msa/ldr_str.ll | 4 +-
.../CodeGen/Mips/optimize-pic-call-dead-gp.ll | 28 +-
llvm/test/CodeGen/Mips/setcc-se.ll | 132 +++---
.../Mips/sll-micromips-r6-encoding.mir | 2 +-
...all-site-info-update-delay-slot-filler.mir | 4 +-
.../MIR/Mips/dbg-call-site-copy-sub-reg.mir | 6 +-
...l-site-delay-slot-interpretation-64bit.mir | 4 +-
...bg-call-site-delay-slot-interpretation.mir | 4 +-
.../Mips/dbg-call-site-param-addiu-64bit.mir | 14 +-
.../MIR/Mips/dbg-call-site-param-addiu.mir | 12 +-
.../MIR/Mips/live-debug-values-reg-copy.mir | 8 +-
.../Mips/livedebugvars-stop-trimming-loc.mir | 8 +-
.../Mips/livedebugvariables-reorder.mir | 10 +-
177 files changed, 2952 insertions(+), 2952 deletions(-)
diff --git a/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir b/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
index da0af94b98268..0ce54eb41d761 100644
--- a/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
+++ b/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
@@ -27,15 +27,15 @@ body: |
liveins: $a0, $ra
Save16 $ra, 24, implicit-def $sp, implicit $sp
- $v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp
- $v0 = SllX16 killed $v0, 16
- $v0 = AdduRxRyRz16 killed $v1, killed $v0
+ $r2, $r3 = GotPrologue16 &_gp_disp, &_gp_disp
+ $r2 = SllX16 killed $r2, 16
+ $r2 = AdduRxRyRz16 killed $r3, killed $r2
; CHECK: [[@LINE+1]]:71: expected a global value or an external symbol after 'call-entry'
- $v1 = LwRxRyOffMemX16 $v0, @foo, 0 :: (load (s32) from call-entry foo)
- $t9 = COPY $v1
- $gp = COPY killed $v0
- JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $v0
- $v0 = LiRxImmX16 0
+ $r3 = LwRxRyOffMemX16 $r2, @foo, 0 :: (load (s32) from call-entry foo)
+ $t9 = COPY $r3
+ $gp = COPY killed $r2
+ JumpLinkReg16 killed $r3, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $r2
+ $r2 = LiRxImmX16 0
$ra = Restore16 24, implicit-def $sp, implicit $sp
- RetRA16 implicit $v0
+ RetRA16 implicit $r2
...
diff --git a/llvm/test/CodeGen/MIR/Mips/memory-operands.mir b/llvm/test/CodeGen/MIR/Mips/memory-operands.mir
index f7da11372fa65..22ed276a2dcf4 100644
--- a/llvm/test/CodeGen/MIR/Mips/memory-operands.mir
+++ b/llvm/test/CodeGen/MIR/Mips/memory-operands.mir
@@ -46,18 +46,18 @@ body: |
Save16 $ra, 24, implicit-def $sp, implicit $sp
CFI_INSTRUCTION def_cfa_offset 24
CFI_INSTRUCTION offset $ra_64, -4
- $v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp
- $v0 = SllX16 killed $v0, 16
- $v0 = AdduRxRyRz16 killed $v1, killed $v0
+ $r2, $r3 = GotPrologue16 &_gp_disp, &_gp_disp
+ $r2 = SllX16 killed $r2, 16
+ $r2 = AdduRxRyRz16 killed $r3, killed $r2
; CHECK-LABEL: name: test
- ; CHECK: $v1 = LwRxRyOffMemX16 $v0, @foo :: (load (s32) from call-entry @foo)
- $v1 = LwRxRyOffMemX16 $v0, @foo :: (load (s32) from call-entry @foo)
- $t9 = COPY $v1
- $gp = COPY killed $v0
- JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $v0
- $v0 = LiRxImmX16 0
+ ; CHECK: $r3 = LwRxRyOffMemX16 $r2, @foo :: (load (s32) from call-entry @foo)
+ $r3 = LwRxRyOffMemX16 $r2, @foo :: (load (s32) from call-entry @foo)
+ $t9 = COPY $r3
+ $gp = COPY killed $r2
+ JumpLinkReg16 killed $r3, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $r2
+ $r2 = LiRxImmX16 0
$ra = Restore16 24, implicit-def $sp, implicit $sp
- RetRA16 implicit $v0
+ RetRA16 implicit $r2
...
---
name: test2
@@ -84,19 +84,19 @@ body: |
CFI_INSTRUCTION offset $ra_64, -4
CFI_INSTRUCTION offset $s2_64, -8
CFI_INSTRUCTION offset $s0_64, -12
- $v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp
- $v0 = SllX16 killed $v0, 16
- $s0 = AdduRxRyRz16 killed $v1, killed $v0
- $v0 = LwRxRyOffMemX16 $s0, @g :: (load (s32) from call-entry @g)
+ $r2, $r3 = GotPrologue16 &_gp_disp, &_gp_disp
+ $r2 = SllX16 killed $r2, 16
+ $s0 = AdduRxRyRz16 killed $r3, killed $r2
+ $r2 = LwRxRyOffMemX16 $s0, @g :: (load (s32) from call-entry @g)
; CHECK-LABEL: test2
- ; CHECK: $v1 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load (s32) from call-entry &__mips16_call_stub_sf_0)
- $v1 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load (s32) from call-entry &__mips16_call_stub_sf_0)
+ ; CHECK: $r3 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load (s32) from call-entry &__mips16_call_stub_sf_0)
+ $r3 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load (s32) from call-entry &__mips16_call_stub_sf_0)
$gp = COPY $s0
- JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit $v0, implicit killed $gp, implicit-def $sp, implicit-def $v0
- $v1 = LwRxRyOffMemX16 $s0, @__mips16_ret_sf :: (load (s32) from call-entry @__mips16_ret_sf)
- $t9 = COPY $v1
+ JumpLinkReg16 killed $r3, csr_o32, implicit-def $ra, implicit $r2, implicit killed $gp, implicit-def $sp, implicit-def $r2
+ $r3 = LwRxRyOffMemX16 $s0, @__mips16_ret_sf :: (load (s32) from call-entry @__mips16_ret_sf)
+ $t9 = COPY $r3
$gp = COPY killed $s0
- JumpLinkReg16 killed $v1, csr_mips16rethelper, implicit-def $ra, implicit killed $t9, implicit $v0, implicit killed $gp, implicit-def $sp
+ JumpLinkReg16 killed $r3, csr_mips16rethelper, implicit-def $ra, implicit killed $t9, implicit $r2, implicit killed $gp, implicit-def $sp
$s0, $ra, $s2 = RestoreX16 32, implicit-def $sp, implicit $sp
- RetRA16 implicit $v0
+ RetRA16 implicit $r2
...
diff --git a/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir b/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir
index 305ff096f949d..cf2210adb1637 100644
--- a/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir
+++ b/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir
@@ -18,12 +18,12 @@ body: |
BEQ %3:gpr32, $zero, %bb.2, implicit-def dead $at
bb.1:
- $v0 = ADDiu %4:gpr32, 1
- RetRA implicit $v0
+ $r2 = ADDiu %4:gpr32, 1
+ RetRA implicit $r2
bb.2:
%5:gpr32 = COPY renamable %1:fgr64cc
; CHECK: mfc1
- $v0 = ADDiu %5:gpr32, 2
- RetRA implicit $v0
+ $r2 = ADDiu %5:gpr32, 2
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll b/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
index c237731b1c76e..bf4a1a65c9acd 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
@@ -11,8 +11,8 @@ define i32 @mul(i32 %a, i32 %b) {
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY]]
; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY2]], [[COPY3]], implicit-def dead $hi0, implicit-def dead $lo0
- ; CHECK-NEXT: $v0 = COPY [[MUL]]
- ; CHECK-NEXT: RetRA implicit $v0
+ ; CHECK-NEXT: $r2 = COPY [[MUL]]
+ ; CHECK-NEXT: RetRA implicit $r2
entry:
%0 = mul i32 %a, %b
ret i32 %0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
index a622c581f2151..80fa5ee8fab41 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
@@ -23,13 +23,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[ADDu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADDu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_ADD %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -46,13 +46,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[COPY]], 3
- ; MIPS32: $v0 = COPY [[ADDiu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADDiu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 3
%2:gprb(s32) = G_ADD %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -69,13 +69,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[COPY]], -3
- ; MIPS32: $v0 = COPY [[ADDiu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADDiu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 -3
%2:gprb(s32) = G_ADD %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -93,12 +93,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 65535
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY]], [[ORi]]
- ; MIPS32: $v0 = COPY [[ADDu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADDu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 65535
%2:gprb(s32) = G_ADD %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir
index 32090c3ccf619..18ed022619f2b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir
@@ -34,13 +34,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[AND]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[AND]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_AND %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -57,13 +57,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 255
- ; MIPS32: $v0 = COPY [[ANDi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ANDi]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 255
%2:gprb(s32) = G_AND %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -81,13 +81,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65280
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ADDiu]]
- ; MIPS32: $v0 = COPY [[AND]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[AND]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 -256
%2:gprb(s32) = G_AND %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -105,13 +105,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[OR]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[OR]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_OR %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -128,13 +128,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[COPY]], 65535
- ; MIPS32: $v0 = COPY [[ORi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ORi]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 65535
%2:gprb(s32) = G_OR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -152,13 +152,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 1
; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY]], [[LUi]]
- ; MIPS32: $v0 = COPY [[OR]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[OR]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 65536
%2:gprb(s32) = G_OR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -176,13 +176,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[XOR]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[XOR]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_XOR %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -199,13 +199,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[COPY]], 1
- ; MIPS32: $v0 = COPY [[XORi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[XORi]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 1
%2:gprb(s32) = G_XOR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -222,13 +222,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[NOR:%[0-9]+]]:gpr32 = NOR [[COPY]], $zero
- ; MIPS32: $v0 = COPY [[NOR]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[NOR]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 -1
%2:gprb(s32) = G_XOR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -245,13 +245,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[SLL:%[0-9]+]]:gpr32 = SLL [[COPY]], 1
- ; MIPS32: $v0 = COPY [[SLL]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SLL]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 1
%2:gprb(s32) = G_SHL %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -268,13 +268,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[SRA:%[0-9]+]]:gpr32 = SRA [[COPY]], 1
- ; MIPS32: $v0 = COPY [[SRA]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SRA]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 1
%2:gprb(s32) = G_ASHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -291,13 +291,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[SRL:%[0-9]+]]:gpr32 = SRL [[COPY]], 1
- ; MIPS32: $v0 = COPY [[SRL]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SRL]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 1
%2:gprb(s32) = G_LSHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -315,13 +315,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLLV:%[0-9]+]]:gpr32 = SLLV [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[SLLV]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SLLV]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_SHL %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -339,13 +339,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SRAV:%[0-9]+]]:gpr32 = SRAV [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[SRAV]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SRAV]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_ASHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -363,12 +363,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SRLV:%[0-9]+]]:gpr32 = SRLV [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[SRLV]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SRLV]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_LSHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
index 13116329fe1aa..c97de3f7d4d15 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
@@ -40,8 +40,8 @@ body: |
; MIPS32-NEXT: J %bb.2, implicit-def dead $at
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.1.end:
- ; MIPS32-NEXT: $v0 = COPY [[COPY]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[COPY]]
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.2.block:
; MIPS32-NEXT: successors: %bb.1(0x80000000)
@@ -54,8 +54,8 @@ body: |
G_BR %bb.3
bb.2.end:
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
bb.3.block:
G_BR %bb.2
@@ -81,12 +81,12 @@ body: |
; MIPS32-NEXT: J %bb.2, implicit-def dead $at
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.1.if.then:
- ; MIPS32-NEXT: $v0 = COPY [[COPY1]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[COPY1]]
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.2.if.else:
- ; MIPS32-NEXT: $v0 = COPY [[COPY2]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[COPY2]]
+ ; MIPS32-NEXT: RetRA implicit $r2
bb.1 (%ir-block.0):
liveins: $a0, $a1, $a2
@@ -100,11 +100,11 @@ body: |
G_BR %bb.3
bb.2.if.then:
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
bb.3.if.else:
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir
index bca4283ccfc7c..1041d8a50656a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir
@@ -30,11 +30,11 @@ body: |
; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 0
; MIPS32: PseudoIndirectBranch [[COPY]]
; MIPS32: bb.1.L1:
- ; MIPS32: $v0 = COPY [[ORi1]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ORi1]]
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.2.L2:
- ; MIPS32: $v0 = COPY [[ORi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ORi]]
+ ; MIPS32: RetRA implicit $r2
bb.1.entry:
successors: %bb.2, %bb.3
liveins: $a0
@@ -45,12 +45,12 @@ body: |
G_BRINDIRECT %0(p0)
bb.2.L1:
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
bb.3.L2:
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir
index 2cec5eba3ba52..0c2fc16f3cb4a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir
@@ -20,11 +20,11 @@ body: |
; MIPS32R2: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32R2: [[WSBH:%[0-9]+]]:gpr32 = WSBH [[COPY]]
; MIPS32R2: [[ROTR:%[0-9]+]]:gpr32 = ROTR [[WSBH]], 16
- ; MIPS32R2: $v0 = COPY [[ROTR]]
- ; MIPS32R2: RetRA implicit $v0
+ ; MIPS32R2: $r2 = COPY [[ROTR]]
+ ; MIPS32R2: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_BSWAP %0
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir
index 8a65fc8e558a8..7408789aa5ea0 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir
@@ -18,11 +18,11 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: _0xABCD0000
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 43981
- ; MIPS32: $v0 = COPY [[LUi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LUi]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = G_CONSTANT i32 -1412628480
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
---
@@ -35,11 +35,11 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: _0x00008000
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 32768
- ; MIPS32: $v0 = COPY [[ORi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ORi]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = G_CONSTANT i32 32768
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
---
@@ -52,11 +52,11 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: _0xFFFFFFF6
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65526
- ; MIPS32: $v0 = COPY [[ADDiu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADDiu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = G_CONSTANT i32 -10
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
---
@@ -70,11 +70,11 @@ body: |
; MIPS32-LABEL: name: _0x0A0B0C0D
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 2571
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 3085
- ; MIPS32: $v0 = COPY [[ORi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ORi]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = G_CONSTANT i32 168496141
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ctlz.mir
index 165e5bd348d96..1ea90ab4cd2b5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ctlz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ctlz.mir
@@ -14,11 +14,11 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[CLZ:%[0-9]+]]:gpr32 = CLZ [[COPY]]
- ; MIPS32: $v0 = COPY [[CLZ]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[CLZ]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = G_CTLZ %0(s32)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir
index 03fa8c8789d6e..32eabec16962d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir
@@ -51,17 +51,17 @@ body: |
; FP32-LABEL: name: false_s
; FP32: liveins: $f12, $f14
; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; FP32: $v0 = COPY [[ORi]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[ORi]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: false_s
; FP64: liveins: $f12, $f14
; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; FP64: $v0 = COPY [[ORi]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[ORi]]
+ ; FP64: RetRA implicit $r2
%5:gprb(s32) = G_CONSTANT i32 0
%4:gprb(s32) = COPY %5(s32)
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -77,17 +77,17 @@ body: |
; FP32-LABEL: name: true_s
; FP32: liveins: $f12, $f14
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
- ; FP32: $v0 = COPY [[ADDiu]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[ADDiu]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: true_s
; FP64: liveins: $f12, $f14
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
- ; FP64: $v0 = COPY [[ADDiu]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[ADDiu]]
+ ; FP64: RetRA implicit $r2
%5:gprb(s32) = G_CONSTANT i32 -1
%4:gprb(s32) = COPY %5(s32)
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -107,8 +107,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: uno_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -116,14 +116,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(uno), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -143,8 +143,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ord_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -152,14 +152,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(ord), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -179,8 +179,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: oeq_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -188,14 +188,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(oeq), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -215,8 +215,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: une_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -224,14 +224,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(une), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -251,8 +251,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ueq_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -260,14 +260,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(ueq), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -287,8 +287,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: one_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -296,14 +296,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(one), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -323,8 +323,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: olt_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -332,14 +332,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(olt), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -359,8 +359,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: uge_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -368,14 +368,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(uge), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -395,8 +395,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ult_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -404,14 +404,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(ult), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -431,8 +431,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: oge_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -440,14 +440,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(oge), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -467,8 +467,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ole_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -476,14 +476,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(ole), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -503,8 +503,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ugt_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -512,14 +512,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(ugt), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -539,8 +539,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ule_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -548,14 +548,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(ule), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -575,8 +575,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ogt_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
@@ -584,14 +584,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
%4:gprb(s32) = G_FCMP floatpred(ogt), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -607,17 +607,17 @@ body: |
; FP32-LABEL: name: false_d
; FP32: liveins: $d6, $d7
; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; FP32: $v0 = COPY [[ORi]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[ORi]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: false_d
; FP64: liveins: $d6, $d7
; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; FP64: $v0 = COPY [[ORi]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[ORi]]
+ ; FP64: RetRA implicit $r2
%5:gprb(s32) = G_CONSTANT i32 0
%4:gprb(s32) = COPY %5(s32)
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -633,17 +633,17 @@ body: |
; FP32-LABEL: name: true_d
; FP32: liveins: $d6, $d7
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
- ; FP32: $v0 = COPY [[ADDiu]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[ADDiu]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: true_d
; FP64: liveins: $d6, $d7
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
- ; FP64: $v0 = COPY [[ADDiu]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[ADDiu]]
+ ; FP64: RetRA implicit $r2
%5:gprb(s32) = G_CONSTANT i32 -1
%4:gprb(s32) = COPY %5(s32)
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -663,8 +663,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: uno_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -672,14 +672,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(uno), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -699,8 +699,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ord_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -708,14 +708,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(ord), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -735,8 +735,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: oeq_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -744,14 +744,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(oeq), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -771,8 +771,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: une_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -780,14 +780,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(une), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -807,8 +807,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ueq_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -816,14 +816,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(ueq), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -843,8 +843,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: one_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -852,14 +852,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(one), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -879,8 +879,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: olt_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -888,14 +888,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(olt), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -915,8 +915,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: uge_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -924,14 +924,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(uge), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -951,8 +951,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ult_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -960,14 +960,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(ult), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -987,8 +987,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: oge_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -996,14 +996,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(oge), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -1023,8 +1023,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ole_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -1032,14 +1032,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(ole), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -1059,8 +1059,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ugt_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -1068,14 +1068,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(ugt), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -1095,8 +1095,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVF_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVF_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ule_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -1104,14 +1104,14 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVF_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVF_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(ule), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -1131,8 +1131,8 @@ body: |
; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP32: $v0 = COPY [[MOVT_I]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MOVT_I]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: ogt_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
@@ -1140,13 +1140,13 @@ body: |
; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
- ; FP64: $v0 = COPY [[MOVT_I]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MOVT_I]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
%4:gprb(s32) = G_FCMP floatpred(ogt), %0(s64), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
index c3903fafc3a55..25ca5279f5478 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
@@ -20,12 +20,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load monotonic (s32) from %ir.ptr)
; MIPS32: SYNC 0
- ; MIPS32: $v0 = COPY [[LW]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LW]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%1:gprb(s32) = G_LOAD %0(p0) :: (load monotonic (s32) from %ir.ptr)
G_FENCE 4, 1
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fptosi_and_fptoui.mir
index 32eab52adbdf6..fdf89d77d0ac2 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fptosi_and_fptoui.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fptosi_and_fptoui.mir
@@ -22,19 +22,19 @@ body: |
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[TRUNC_W_S:%[0-9]+]]:fgr32 = TRUNC_W_S [[COPY]]
; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
- ; FP32: $v0 = COPY [[MFC1_]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MFC1_]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: f32toi32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[TRUNC_W_S:%[0-9]+]]:fgr32 = TRUNC_W_S [[COPY]]
; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
- ; FP64: $v0 = COPY [[MFC1_]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MFC1_]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
%1:gprb(s32) = G_FPTOSI %0(s32)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -52,18 +52,18 @@ body: |
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[TRUNC_W_D32_:%[0-9]+]]:fgr32 = TRUNC_W_D32 [[COPY]]
; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_D32_]]
- ; FP32: $v0 = COPY [[MFC1_]]
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[MFC1_]]
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: f64toi32
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[TRUNC_W_D64_:%[0-9]+]]:fgr32 = TRUNC_W_D64 [[COPY]]
; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_D64_]]
- ; FP64: $v0 = COPY [[MFC1_]]
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[MFC1_]]
+ ; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
%1:gprb(s32) = G_FPTOSI %0(s64)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
index b627f9743cd91..f24d2dcb33b9e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
@@ -25,10 +25,10 @@ body: |
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[ADDiu]]
; MIPS32: $a1 = COPY [[ORi]]
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[ORi1]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ORi1]]
+ ; MIPS32: RetRA implicit $r2
%2:gprb(p0) = G_GLOBAL_VALUE @.str
%1:gprb(p0) = COPY %2(p0)
%3:gprb(s32) = G_CONSTANT i32 1234567890
@@ -36,10 +36,10 @@ body: |
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %1(p0)
$a1 = COPY %3(s32)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- %0:gprb(s32) = COPY $v0
+ JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ %0:gprb(s32) = COPY $r2
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir
index 83ddb9e4ff224..482f630ffacec 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir
@@ -28,13 +28,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[ADDu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADDu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_ADD %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -45,12 +45,12 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $t9, $v0
+ liveins: $a0, $a1, $t9, $r2
; MIPS32-LABEL: name: call_global
- ; MIPS32: liveins: $a0, $a1, $t9, $v0, $t9, $v0
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
- ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32: liveins: $a0, $a1, $t9, $r2, $t9, $r2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
+ ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
@@ -58,12 +58,12 @@ body: |
; MIPS32: $a0 = COPY [[COPY]]
; MIPS32: $a1 = COPY [[COPY1]]
; MIPS32: $gp = COPY [[ADDu1]]
- ; MIPS32: JALRPseudo [[LW]], csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $v0
- ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $v0
+ ; MIPS32: JALRPseudo [[LW]], csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY2]]
- ; MIPS32: RetRA implicit $v0
- %4:gpr32 = ADDu $v0, $t9
+ ; MIPS32: $r2 = COPY [[COPY2]]
+ ; MIPS32: RetRA implicit $r2
+ %4:gpr32 = ADDu $r2, $t9
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
@@ -71,11 +71,11 @@ body: |
$a0 = COPY %0(s32)
$a1 = COPY %1(s32)
$gp = COPY %4
- JALRPseudo %3(p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $v0
- %2:gprb(s32) = COPY $v0
+ JALRPseudo %3(p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ %2:gprb(s32) = COPY $r2
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -86,12 +86,12 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $t9, $v0
+ liveins: $a0, $a1, $t9, $r2
; MIPS32-LABEL: name: call_global_with_local_linkage
- ; MIPS32: liveins: $a0, $a1, $t9, $v0, $t9, $v0
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
- ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32: liveins: $a0, $a1, $t9, $r2, $t9, $r2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
+ ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
@@ -100,12 +100,12 @@ body: |
; MIPS32: $a0 = COPY [[COPY]]
; MIPS32: $a1 = COPY [[COPY1]]
; MIPS32: $gp = COPY [[ADDu1]]
- ; MIPS32: JALRPseudo [[ADDiu]], csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $v0
- ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $v0
+ ; MIPS32: JALRPseudo [[ADDiu]], csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY2]]
- ; MIPS32: RetRA implicit $v0
- %4:gpr32 = ADDu $v0, $t9
+ ; MIPS32: $r2 = COPY [[COPY2]]
+ ; MIPS32: RetRA implicit $r2
+ %4:gpr32 = ADDu $r2, $t9
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
@@ -113,11 +113,11 @@ body: |
$a0 = COPY %0(s32)
$a1 = COPY %1(s32)
$gp = COPY %4
- JALRPseudo %3(p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $v0
- %2:gprb(s32) = COPY $v0
+ JALRPseudo %3(p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ %2:gprb(s32) = COPY $r2
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -129,16 +129,16 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: ret_global_int
- ; MIPS32: liveins: $t9, $v0
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32: liveins: $t9, $r2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) @val :: (load (s32) from got)
; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[LW]], 0 :: (load (s32) from @val)
- ; MIPS32: $v0 = COPY [[LW1]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LW1]]
+ ; MIPS32: RetRA implicit $r2
%1:gprb(p0) = G_GLOBAL_VALUE @val
%0:gprb(s32) = G_LOAD %1(p0) :: (load (s32) from @val)
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
---
@@ -150,16 +150,16 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: ret_global_int_with_local_linkage
- ; MIPS32: liveins: $t9, $v0
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32: liveins: $t9, $r2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) @val_with_local_linkage :: (load (s32) from got)
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LW]], target-flags(mips-abs-lo) @val_with_local_linkage
; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from @val_with_local_linkage)
- ; MIPS32: $v0 = COPY [[LW1]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LW1]]
+ ; MIPS32: RetRA implicit $r2
%1:gprb(p0) = G_GLOBAL_VALUE @val_with_local_linkage
%0:gprb(s32) = G_LOAD %1(p0) :: (load (s32) from @val_with_local_linkage)
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
index 833adb8721c33..5a870264bba7f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
@@ -32,14 +32,14 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
- ; MIPS32: $v0 = COPY [[SLTiu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SLTiu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(eq), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -58,14 +58,14 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
- ; MIPS32: $v0 = COPY [[SLTu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SLTu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(ne), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -83,14 +83,14 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[SLT]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SLT]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(sgt), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -109,14 +109,14 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
- ; MIPS32: $v0 = COPY [[XORi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[XORi]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(sge), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -134,14 +134,14 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[SLT]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SLT]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(slt), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -160,14 +160,14 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
- ; MIPS32: $v0 = COPY [[XORi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[XORi]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(sle), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -185,14 +185,14 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[SLTu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SLTu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(ugt), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -211,14 +211,14 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
- ; MIPS32: $v0 = COPY [[XORi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[XORi]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(uge), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -236,14 +236,14 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[SLTu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SLTu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(ult), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -262,14 +262,14 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
- ; MIPS32: $v0 = COPY [[XORi]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[XORi]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(ule), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -288,13 +288,13 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
- ; MIPS32: $v0 = COPY [[SLTiu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SLTiu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%1:gprb(p0) = COPY $a1
%4:gprb(s32) = G_ICMP intpred(eq), %0(p0), %1
%3:gprb(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir
index e56b48ba5602f..606dd2b813e17 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir
@@ -19,12 +19,12 @@ body: |
; MIPS32-LABEL: name: inttoptr
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: $v0 = COPY [[COPY]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(p0) = G_INTTOPTR %0(s32)
- $v0 = COPY %1(p0)
- RetRA implicit $v0
+ $r2 = COPY %1(p0)
+ RetRA implicit $r2
...
---
@@ -40,12 +40,12 @@ body: |
; MIPS32-LABEL: name: ptrtoint
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: $v0 = COPY [[COPY]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%1:gprb(s32) = G_PTRTOINT %0(p0)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
index 6022e7ac4828f..2f8a8b9a6c3cf 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
@@ -99,20 +99,20 @@ body: |
; MIPS32-NEXT: PseudoIndirectBranch [[LW]]
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.2.sw.bb:
- ; MIPS32-NEXT: $v0 = COPY [[ORi4]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ORi4]]
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.3.sw.bb1:
- ; MIPS32-NEXT: $v0 = COPY [[ORi3]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ORi3]]
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.4.sw.bb2:
- ; MIPS32-NEXT: $v0 = COPY [[ORi2]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ORi2]]
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.5.sw.bb3:
- ; MIPS32-NEXT: $v0 = COPY [[ORi1]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ORi1]]
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.6.sw.default:
; MIPS32-NEXT: successors: %bb.7(0x80000000)
@@ -136,31 +136,31 @@ body: |
; MIPS32-NEXT: PseudoIndirectBranch [[LW1]]
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.9.sw.bb4:
- ; MIPS32-NEXT: $v0 = COPY [[ORi4]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ORi4]]
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.10.sw.bb5:
- ; MIPS32-NEXT: $v0 = COPY [[ORi3]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ORi3]]
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.11.sw.bb6:
- ; MIPS32-NEXT: $v0 = COPY [[ORi2]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ORi2]]
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.12.sw.bb7:
- ; MIPS32-NEXT: $v0 = COPY [[ORi1]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ORi1]]
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.13.sw.default8:
- ; MIPS32-NEXT: $v0 = COPY [[ADDiu]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ADDiu]]
+ ; MIPS32-NEXT: RetRA implicit $r2
;
; MIPS32_PIC-LABEL: name: mod4_0_to_11
; MIPS32_PIC: bb.0.entry:
; MIPS32_PIC-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)
- ; MIPS32_PIC-NEXT: liveins: $a0, $t9, $v0
+ ; MIPS32_PIC-NEXT: liveins: $a0, $t9, $r2
; MIPS32_PIC-NEXT: {{ $}}
- ; MIPS32_PIC-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32_PIC-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32_PIC-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32_PIC-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
; MIPS32_PIC-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
@@ -185,20 +185,20 @@ body: |
; MIPS32_PIC-NEXT: PseudoIndirectBranch [[ADDu2]]
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.2.sw.bb:
- ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi4]]
- ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: $r2 = COPY [[ORi4]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $r2
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.3.sw.bb1:
- ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi3]]
- ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: $r2 = COPY [[ORi3]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $r2
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.4.sw.bb2:
- ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi2]]
- ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: $r2 = COPY [[ORi2]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $r2
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.5.sw.bb3:
- ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi1]]
- ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: $r2 = COPY [[ORi1]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $r2
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.6.sw.default:
; MIPS32_PIC-NEXT: successors: %bb.7(0x80000000)
@@ -223,24 +223,24 @@ body: |
; MIPS32_PIC-NEXT: PseudoIndirectBranch [[ADDu4]]
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.9.sw.bb4:
- ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi4]]
- ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: $r2 = COPY [[ORi4]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $r2
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.10.sw.bb5:
- ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi3]]
- ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: $r2 = COPY [[ORi3]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $r2
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.11.sw.bb6:
- ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi2]]
- ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: $r2 = COPY [[ORi2]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $r2
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.12.sw.bb7:
- ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi1]]
- ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: $r2 = COPY [[ORi1]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $r2
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.13.sw.default8:
- ; MIPS32_PIC-NEXT: $v0 = COPY [[ADDiu]]
- ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: $r2 = COPY [[ADDiu]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $r2
bb.1.entry:
liveins: $a0
@@ -267,20 +267,20 @@ body: |
G_BRJT %7(p0), %jump-table.0, %3(s32)
bb.2.sw.bb:
- $v0 = COPY %11(s32)
- RetRA implicit $v0
+ $r2 = COPY %11(s32)
+ RetRA implicit $r2
bb.3.sw.bb1:
- $v0 = COPY %10(s32)
- RetRA implicit $v0
+ $r2 = COPY %10(s32)
+ RetRA implicit $r2
bb.4.sw.bb2:
- $v0 = COPY %9(s32)
- RetRA implicit $v0
+ $r2 = COPY %9(s32)
+ RetRA implicit $r2
bb.5.sw.bb3:
- $v0 = COPY %8(s32)
- RetRA implicit $v0
+ $r2 = COPY %8(s32)
+ RetRA implicit $r2
bb.6.sw.default:
@@ -302,23 +302,23 @@ body: |
G_BRJT %17(p0), %jump-table.1, %14(s32)
bb.8.sw.bb4:
- $v0 = COPY %11(s32)
- RetRA implicit $v0
+ $r2 = COPY %11(s32)
+ RetRA implicit $r2
bb.9.sw.bb5:
- $v0 = COPY %10(s32)
- RetRA implicit $v0
+ $r2 = COPY %10(s32)
+ RetRA implicit $r2
bb.10.sw.bb6:
- $v0 = COPY %9(s32)
- RetRA implicit $v0
+ $r2 = COPY %9(s32)
+ RetRA implicit $r2
bb.11.sw.bb7:
- $v0 = COPY %8(s32)
- RetRA implicit $v0
+ $r2 = COPY %8(s32)
+ RetRA implicit $r2
bb.12.sw.default8:
- $v0 = COPY %18(s32)
- RetRA implicit $v0
+ $r2 = COPY %18(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir
index e5af2cc5acde1..4e2c5ea1bf58d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir
@@ -22,18 +22,18 @@ body: |
; MIPS32FP32: liveins: $a0
; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load (s32) from %ir.ptr)
- ; MIPS32FP32: $v0 = COPY [[LW]]
- ; MIPS32FP32: RetRA implicit $v0
+ ; MIPS32FP32: $r2 = COPY [[LW]]
+ ; MIPS32FP32: RetRA implicit $r2
; MIPS32FP64-LABEL: name: load_i32
; MIPS32FP64: liveins: $a0
; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load (s32) from %ir.ptr)
- ; MIPS32FP64: $v0 = COPY [[LW]]
- ; MIPS32FP64: RetRA implicit $v0
+ ; MIPS32FP64: $r2 = COPY [[LW]]
+ ; MIPS32FP64: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%1:gprb(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned.mir
index e053a0934b844..aa9cd4563fca6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned.mir
@@ -79,11 +79,11 @@ body: |
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load (s32) from @i32_align8, align 8)
- ; MIPS32: $v0 = COPY [[LW]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LW]]
+ ; MIPS32: RetRA implicit $r2
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align8
%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align8, align 8)
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned_r6.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned_r6.mir
index 26d397410ff9e..f4764acbc5e1f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned_r6.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned_r6.mir
@@ -80,11 +80,11 @@ body: |
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
; MIPS32R6: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load (s32) from @i32_align2, align 2)
- ; MIPS32R6: $v0 = COPY [[LW]]
- ; MIPS32R6: RetRA implicit $v0
+ ; MIPS32R6: $r2 = COPY [[LW]]
+ ; MIPS32R6: RetRA implicit $r2
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align2
%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align2, align 2)
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
index 43ddd4c429baa..0dbe4cb4d8788 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
@@ -26,14 +26,14 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY]], 32767 :: (load (s8))
- ; MIPS32: $v0 = COPY [[LBu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LBu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 32767
%2:gprb(p0) = G_PTR_ADD %0, %1(s32)
%4:gprb(s32) = G_ZEXTLOAD %2(p0) :: (load (s8))
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -105,14 +105,14 @@ body: |
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 32767
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY]], [[ORi]]
; MIPS32: [[LB:%[0-9]+]]:gpr32 = LB [[ADDu]], 0 :: (load (s8))
- ; MIPS32: $v0 = COPY [[LB]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LB]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 -32769
%2:gprb(p0) = G_PTR_ADD %0, %1(s32)
%4:gprb(s32) = G_SEXTLOAD %2(p0) :: (load (s8))
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -177,14 +177,14 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY]], -20 :: (load (s16))
- ; MIPS32: $v0 = COPY [[LHu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LHu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 -20
%2:gprb(p0) = G_PTR_ADD %0, %1(s32)
%4:gprb(s32) = G_LOAD %2(p0) :: (load (s16))
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
index 6044f73b1c805..4b5b0d3d6aadc 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
@@ -21,13 +21,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
- ; MIPS32: $v0 = COPY [[MUL]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[MUL]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_MUL %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
index 44d31d99efcac..74ca62367aa83 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
@@ -93,8 +93,8 @@ body: |
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.3.cond.end:
; MIPS32FP32-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
- ; MIPS32FP32-NEXT: $v0 = COPY [[PHI]]
- ; MIPS32FP32-NEXT: RetRA implicit $v0
+ ; MIPS32FP32-NEXT: $r2 = COPY [[PHI]]
+ ; MIPS32FP32-NEXT: RetRA implicit $r2
;
; MIPS32FP64-LABEL: name: phi_i32
; MIPS32FP64: bb.0.entry:
@@ -118,8 +118,8 @@ body: |
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.3.cond.end:
; MIPS32FP64-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
- ; MIPS32FP64-NEXT: $v0 = COPY [[PHI]]
- ; MIPS32FP64-NEXT: RetRA implicit $v0
+ ; MIPS32FP64-NEXT: $r2 = COPY [[PHI]]
+ ; MIPS32FP64-NEXT: RetRA implicit $r2
bb.1.entry:
liveins: $a0, $a1, $a2
@@ -139,8 +139,8 @@ body: |
bb.4.cond.end:
%4:gprb(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -180,9 +180,9 @@ body: |
; MIPS32FP32-NEXT: bb.3.cond.end:
; MIPS32FP32-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
; MIPS32FP32-NEXT: [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
- ; MIPS32FP32-NEXT: $v0 = COPY [[PHI]]
- ; MIPS32FP32-NEXT: $v1 = COPY [[PHI1]]
- ; MIPS32FP32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32FP32-NEXT: $r2 = COPY [[PHI]]
+ ; MIPS32FP32-NEXT: $r3 = COPY [[PHI1]]
+ ; MIPS32FP32-NEXT: RetRA implicit $r2, implicit $r3
;
; MIPS32FP64-LABEL: name: phi_i64
; MIPS32FP64: bb.0.entry:
@@ -211,9 +211,9 @@ body: |
; MIPS32FP64-NEXT: bb.3.cond.end:
; MIPS32FP64-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
; MIPS32FP64-NEXT: [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
- ; MIPS32FP64-NEXT: $v0 = COPY [[PHI]]
- ; MIPS32FP64-NEXT: $v1 = COPY [[PHI1]]
- ; MIPS32FP64-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32FP64-NEXT: $r2 = COPY [[PHI]]
+ ; MIPS32FP64-NEXT: $r3 = COPY [[PHI1]]
+ ; MIPS32FP64-NEXT: RetRA implicit $r2, implicit $r3
bb.1.entry:
liveins: $a0, $a2, $a3
@@ -238,9 +238,9 @@ body: |
bb.4.cond.end:
%20:gprb(s32) = G_PHI %4(s32), %bb.2, %6(s32), %bb.3
%21:gprb(s32) = G_PHI %5(s32), %bb.2, %7(s32), %bb.3
- $v0 = COPY %20(s32)
- $v1 = COPY %21(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %20(s32)
+ $r3 = COPY %21(s32)
+ RetRA implicit $r2, implicit $r3
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
index 0ae5c1871a24a..0cb6245b8ad8d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
@@ -21,12 +21,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load (s32) from %ir.p)
- ; MIPS32: $v0 = COPY [[LW]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LW]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%1:gprb(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.p)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -46,8 +46,8 @@ body: |
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[LW]], 0 :: (load (s32) from %ir.p)
- ; MIPS32: $v0 = COPY [[LW1]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LW1]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = COPY $a2
@@ -55,8 +55,8 @@ body: |
%5:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
%4:gprb(p0) = G_LOAD %5(p0) :: (load (p0) from %fixed-stack.0, align 8)
%6:gprb(s32) = G_LOAD %4(p0) :: (load (s32) from %ir.p)
- $v0 = COPY %6(s32)
- RetRA implicit $v0
+ $r2 = COPY %6(s32)
+ RetRA implicit $r2
...
---
@@ -72,10 +72,10 @@ body: |
; MIPS32-LABEL: name: ret_ptr
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: $v0 = COPY [[COPY]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
- $v0 = COPY %0(p0)
- RetRA implicit $v0
+ $r2 = COPY %0(p0)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir
index 67e80d0c364b8..f01defd8c2c21 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir
@@ -24,13 +24,13 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[PseudoSDIV:%[0-9]+]]:acc64 = PseudoSDIV [[COPY1]], [[COPY]]
; MIPS32: [[PseudoMFLO:%[0-9]+]]:gpr32 = PseudoMFLO [[PseudoSDIV]]
- ; MIPS32: $v0 = COPY [[PseudoMFLO]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PseudoMFLO]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_SDIV %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -49,13 +49,13 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[PseudoSDIV:%[0-9]+]]:acc64 = PseudoSDIV [[COPY1]], [[COPY]]
; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoSDIV]]
- ; MIPS32: $v0 = COPY [[PseudoMFHI]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PseudoMFHI]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_SREM %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -74,13 +74,13 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[PseudoUDIV:%[0-9]+]]:acc64 = PseudoUDIV [[COPY1]], [[COPY]]
; MIPS32: [[PseudoMFLO:%[0-9]+]]:gpr32 = PseudoMFLO [[PseudoUDIV]]
- ; MIPS32: $v0 = COPY [[PseudoMFLO]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PseudoMFLO]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_UDIV %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -99,12 +99,12 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[PseudoUDIV:%[0-9]+]]:acc64 = PseudoUDIV [[COPY1]], [[COPY]]
; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoUDIV]]
- ; MIPS32: $v0 = COPY [[PseudoMFHI]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PseudoMFHI]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_UREM %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
index db558df87c762..74a8d61959787 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
@@ -26,8 +26,8 @@ body: |
; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
- ; MIPS32FP32: $v0 = COPY [[MOVN_I_I]]
- ; MIPS32FP32: RetRA implicit $v0
+ ; MIPS32FP32: $r2 = COPY [[MOVN_I_I]]
+ ; MIPS32FP32: RetRA implicit $r2
; MIPS32FP64-LABEL: name: select_i32
; MIPS32FP64: liveins: $a0, $a1, $a2
; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
@@ -35,8 +35,8 @@ body: |
; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
- ; MIPS32FP64: $v0 = COPY [[MOVN_I_I]]
- ; MIPS32FP64: RetRA implicit $v0
+ ; MIPS32FP64: $r2 = COPY [[MOVN_I_I]]
+ ; MIPS32FP64: RetRA implicit $r2
%3:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = COPY $a2
@@ -44,8 +44,8 @@ body: |
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
%4:gprb(s32) = G_SELECT %5(s32), %1, %2
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -65,8 +65,8 @@ body: |
; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
- ; MIPS32FP32: $v0 = COPY [[MOVN_I_I]]
- ; MIPS32FP32: RetRA implicit $v0
+ ; MIPS32FP32: $r2 = COPY [[MOVN_I_I]]
+ ; MIPS32FP32: RetRA implicit $r2
; MIPS32FP64-LABEL: name: select_ptr
; MIPS32FP64: liveins: $a0, $a1, $a2
; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
@@ -74,8 +74,8 @@ body: |
; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
- ; MIPS32FP64: $v0 = COPY [[MOVN_I_I]]
- ; MIPS32FP64: RetRA implicit $v0
+ ; MIPS32FP64: $r2 = COPY [[MOVN_I_I]]
+ ; MIPS32FP64: RetRA implicit $r2
%3:gprb(s32) = COPY $a0
%1:gprb(p0) = COPY $a1
%2:gprb(p0) = COPY $a2
@@ -83,8 +83,8 @@ body: |
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
%4:gprb(p0) = G_SELECT %5(s32), %1, %2
- $v0 = COPY %4(p0)
- RetRA implicit $v0
+ $r2 = COPY %4(p0)
+ RetRA implicit $r2
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
index 1b59c4ed1e375..e057deb2335f1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
@@ -33,11 +33,11 @@ body: |
; MIPS32: $a3 = COPY [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:gpr32 = COPY $sp
; MIPS32: SW [[LW]], [[COPY4]], 16 :: (store (s32) into stack + 16)
- ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- ; MIPS32: [[COPY5:%[0-9]+]]:gpr32 = COPY $v0
+ ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32: [[COPY5:%[0-9]+]]:gpr32 = COPY $r2
; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY5]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY5]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = COPY $a2
@@ -53,10 +53,10 @@ body: |
%8:gprb(s32) = G_CONSTANT i32 16
%9:gprb(p0) = G_PTR_ADD %7, %8(s32)
G_STORE %4(s32), %9(p0) :: (store (s32) into stack + 16, align 4)
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- %6:gprb(s32) = COPY $v0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ %6:gprb(s32) = COPY $r2
ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
- $v0 = COPY %6(s32)
- RetRA implicit $v0
+ $r2 = COPY %6(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir
index 9e0fd5129e558..3be681afaafe1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir
@@ -20,12 +20,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[SUBu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SUBu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_SUB %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
index 0201d6853a4e1..b653746e2ba16 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
@@ -87,7 +87,7 @@ body: |
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[ADDiu3]]
; MIPS32: $a1 = COPY [[LW3]]
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:gprb(p0) = COPY $a0
@@ -120,7 +120,7 @@ body: |
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %17(p0)
$a1 = COPY %15(p0)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
+ JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir
index 1efa32ddd72b7..a442a9853ef85 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir
@@ -22,12 +22,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY]], 0 :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[LBu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LBu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%2:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -44,12 +44,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY]], 0 :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[LHu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LHu]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%2:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -66,12 +66,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LB:%[0-9]+]]:gpr32 = LB [[COPY]], 0 :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[LB]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LB]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%2:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -88,11 +88,11 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LH:%[0-9]+]]:gpr32 = LH [[COPY]], 0 :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[LH]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LH]]
+ ; MIPS32: RetRA implicit $r2
%0:gprb(p0) = COPY $a0
%2:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
index 5339e55259220..2f0739e428509 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
@@ -8,8 +8,8 @@ define i32 @add_i32(i32 %x, i32 %y) {
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[ADD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $r2
entry:
%z = add i32 %x, %y
ret i32 %z
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll
index eb4165d6a3016..6344c78ba0817 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll
@@ -14,10 +14,10 @@ define i64 @integer_regs(i64 %x) {
; LE-NEXT: [[HI:%[0-9]+]]:_(s32) = COPY $a1
; CHECK-NEXT: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LO]](s32), [[HI]](s32)
; CHECK-NEXT: [[RLO:%[0-9]+]]:_(s32), [[RHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64)
-; BE-NEXT: $v1 = COPY [[RLO]](s32)
-; BE-NEXT: $v0 = COPY [[RHI]](s32)
-; LE-NEXT: $v0 = COPY [[RLO]](s32)
-; LE-NEXT: $v1 = COPY [[RHI]](s32)
+; BE-NEXT: $r3 = COPY [[RLO]](s32)
+; BE-NEXT: $r2 = COPY [[RHI]](s32)
+; LE-NEXT: $r2 = COPY [[RLO]](s32)
+; LE-NEXT: $r3 = COPY [[RHI]](s32)
ret i64 %x
}
@@ -33,10 +33,10 @@ define i64 @integer_call(i64 %x) {
; LE-NEXT: $a2 = COPY [[LO]](s32)
; LE-NEXT: $a3 = COPY [[HI]](s32)
; CHECK-NEXT: JAL @callee_integer,
-; BE-NEXT: [[RLO:%[0-9]+]]:_(s32) = COPY $v1
-; BE-NEXT: [[RHI:%[0-9]+]]:_(s32) = COPY $v0
-; LE-NEXT: [[RLO:%[0-9]+]]:_(s32) = COPY $v0
-; LE-NEXT: [[RHI:%[0-9]+]]:_(s32) = COPY $v1
+; BE-NEXT: [[RLO:%[0-9]+]]:_(s32) = COPY $r3
+; BE-NEXT: [[RHI:%[0-9]+]]:_(s32) = COPY $r2
+; LE-NEXT: [[RLO:%[0-9]+]]:_(s32) = COPY $r2
+; LE-NEXT: [[RHI:%[0-9]+]]:_(s32) = COPY $r3
; CHECK-NEXT: {{%[0-9]+}}:_(s64) = G_MERGE_VALUES [[RLO]](s32), [[RHI]](s32)
%r = call i64 @callee_integer(i32 1, i64 %x)
ret i64 %r
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll
index 8f1f678e3c17e..6409b58fc32df 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll
@@ -8,8 +8,8 @@ define i32 @shl(i32 %a) {
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]]
- ; MIPS32: $v0 = COPY [[SHL]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SHL]](s32)
+ ; MIPS32: RetRA implicit $r2
entry:
%shl = shl i32 %a, 1
ret i32 %shl
@@ -22,8 +22,8 @@ define i32 @ashr(i32 %a) {
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]]
- ; MIPS32: $v0 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2
entry:
%shr = ashr i32 %a, 1
ret i32 %shr
@@ -36,8 +36,8 @@ define i32 @lshr(i32 %a) {
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]]
- ; MIPS32: $v0 = COPY [[LSHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LSHR]](s32)
+ ; MIPS32: RetRA implicit $r2
entry:
%shr = lshr i32 %a, 1
ret i32 %shr
@@ -50,8 +50,8 @@ define i32 @shlv(i32 %a, i32 %b) {
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[SHL]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SHL]](s32)
+ ; MIPS32: RetRA implicit $r2
entry:
%shl = shl i32 %a, %b
ret i32 %shl
@@ -64,8 +64,8 @@ define i32 @ashrv(i32 %a, i32 %b) {
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2
entry:
%shr = ashr i32 %a, %b
ret i32 %shr
@@ -78,8 +78,8 @@ define i32 @lshrv(i32 %a, i32 %b) {
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[LSHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LSHR]](s32)
+ ; MIPS32: RetRA implicit $r2
entry:
%shr = lshr i32 %a, %b
ret i32 %shr
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
index c4797198f11b4..b9fcdd0b57d29 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
@@ -15,16 +15,16 @@ define i32 @call_global(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY2]](s32)
; MIPS32: $a1 = COPY [[COPY3]](s32)
- ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
- ; MIPS32: $v0 = COPY [[ADD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32_PIC-LABEL: name: call_global
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1, $a2, $a3, $t9, $v0
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32_PIC: liveins: $a0, $a1, $a2, $a3, $r2, $t9
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
@@ -34,12 +34,12 @@ define i32 @call_global(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32_PIC: $a0 = COPY [[COPY2]](s32)
; MIPS32_PIC: $a1 = COPY [[COPY3]](s32)
; MIPS32_PIC: $gp = COPY [[ADDu]]
- ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $v0
- ; MIPS32_PIC: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $r2
+ ; MIPS32_PIC: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32_PIC: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
- ; MIPS32_PIC: $v0 = COPY [[ADD]](s32)
- ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: $r2 = COPY [[ADD]](s32)
+ ; MIPS32_PIC: RetRA implicit $r2
entry:
%z = call i32 @f(i32 %x, i32 %y)
%doublez = add i32 %z, %z
@@ -53,16 +53,16 @@ define internal i32 @f_with_local_linkage(i32 %x, i32 %y) {
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[ADD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32_PIC-LABEL: name: f_with_local_linkage
; MIPS32_PIC: bb.1.entry:
; MIPS32_PIC: liveins: $a0, $a1
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32_PIC: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32_PIC: $v0 = COPY [[ADD]](s32)
- ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: $r2 = COPY [[ADD]](s32)
+ ; MIPS32_PIC: RetRA implicit $r2
entry:
%add = add i32 %y, %x
ret i32 %add
@@ -79,16 +79,16 @@ define i32 @call_global_with_local_linkage(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY2]](s32)
; MIPS32: $a1 = COPY [[COPY3]](s32)
- ; MIPS32: JAL @f_with_local_linkage, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32: JAL @f_with_local_linkage, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
- ; MIPS32: $v0 = COPY [[ADD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32_PIC-LABEL: name: call_global_with_local_linkage
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1, $a2, $a3, $t9, $v0
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32_PIC: liveins: $a0, $a1, $a2, $a3, $r2, $t9
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
@@ -98,12 +98,12 @@ define i32 @call_global_with_local_linkage(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32_PIC: $a0 = COPY [[COPY2]](s32)
; MIPS32_PIC: $a1 = COPY [[COPY3]](s32)
; MIPS32_PIC: $gp = COPY [[ADDu]]
- ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $v0
- ; MIPS32_PIC: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $r2
+ ; MIPS32_PIC: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32_PIC: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
- ; MIPS32_PIC: $v0 = COPY [[ADD]](s32)
- ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: $r2 = COPY [[ADD]](s32)
+ ; MIPS32_PIC: RetRA implicit $r2
entry:
%z = call i32 @f_with_local_linkage(i32 %x, i32 %y)
%doublez = add i32 %z, %z
@@ -120,11 +120,11 @@ define i32 @call_reg(ptr %f_ptr, i32 %x, i32 %y) {
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY1]](s32)
; MIPS32: $a1 = COPY [[COPY2]](s32)
- ; MIPS32: JALRPseudo [[COPY]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32: JALRPseudo [[COPY]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY3]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY3]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32_PIC-LABEL: name: call_reg
; MIPS32_PIC: bb.1.entry:
; MIPS32_PIC: liveins: $a0, $a1, $a2
@@ -134,11 +134,11 @@ define i32 @call_reg(ptr %f_ptr, i32 %x, i32 %y) {
; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32_PIC: $a0 = COPY [[COPY1]](s32)
; MIPS32_PIC: $a1 = COPY [[COPY2]](s32)
- ; MIPS32_PIC: JALRPseudo [[COPY]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- ; MIPS32_PIC: [[COPY3:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32_PIC: JALRPseudo [[COPY]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32_PIC: [[COPY3:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32_PIC: $v0 = COPY [[COPY3]](s32)
- ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: $r2 = COPY [[COPY3]](s32)
+ ; MIPS32_PIC: RetRA implicit $r2
entry:
%call = call i32 %f_ptr(i32 %x, i32 %y)
ret i32 %call
@@ -179,8 +179,8 @@ define void @call_f_with_void_ret() {
; MIPS32: RetRA
; MIPS32_PIC-LABEL: name: call_f_with_void_ret
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $t9, $v0
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32_PIC: liveins: $r2, $t9
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32_PIC: [[GV:%[0-9]+]]:gpr32(p0) = G_GLOBAL_VALUE target-flags(mips-got-call) @f_with_void_ret
; MIPS32_PIC: $gp = COPY [[ADDu]]
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
index 5e8743659b463..90cb341d20af5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
@@ -12,8 +12,8 @@ define signext i8 @sext_arg_i8(i8 signext %a) {
; MIPS32-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
; MIPS32-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s8)
- ; MIPS32-NEXT: $v0 = COPY [[SEXT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SEXT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
ret i8 %a
}
@@ -27,8 +27,8 @@ define zeroext i8 @zext_arg_i8(i8 zeroext %a) {
; MIPS32-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32)
; MIPS32-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
- ; MIPS32-NEXT: $v0 = COPY [[ZEXT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ZEXT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
ret i8 %a
}
@@ -41,8 +41,8 @@ define i8 @aext_arg_i8(i8 %a) {
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; MIPS32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; MIPS32-NEXT: $v0 = COPY [[ANYEXT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ANYEXT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
ret i8 %a
}
@@ -74,14 +74,14 @@ define signext i8 @call_sext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8
; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @sext_stack_arg_i8, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32-NEXT: JAL @sext_stack_arg_i8, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY5]], 8
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT1]](s32)
; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
; MIPS32-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC1]](s8)
- ; MIPS32-NEXT: $v0 = COPY [[SEXT1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SEXT1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
%call = call signext i8 @sext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 signext %a)
ret i8 %call
@@ -110,14 +110,14 @@ define zeroext i8 @call_zext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8
; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @zext_stack_arg_i8, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32-NEXT: JAL @zext_stack_arg_i8, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY5]], 8
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT1]](s32)
; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
; MIPS32-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s8)
- ; MIPS32-NEXT: $v0 = COPY [[ZEXT1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ZEXT1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
%call = call zeroext i8 @zext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 zeroext %a)
ret i8 %call
@@ -145,13 +145,13 @@ define i8 @call_aext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 %a) {
; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @aext_stack_arg_i8, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32-NEXT: JAL @aext_stack_arg_i8, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY5]](s32)
; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
; MIPS32-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8)
- ; MIPS32-NEXT: $v0 = COPY [[ANYEXT1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ANYEXT1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
%call = call i8 @aext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 %a)
ret i8 %call
@@ -167,8 +167,8 @@ define signext i16 @sext_arg_i16(i16 signext %a) {
; MIPS32-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
; MIPS32-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
- ; MIPS32-NEXT: $v0 = COPY [[SEXT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SEXT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
ret i16 %a
}
@@ -182,8 +182,8 @@ define zeroext i16 @zext_arg_i16(i16 zeroext %a) {
; MIPS32-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
; MIPS32-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; MIPS32-NEXT: $v0 = COPY [[ZEXT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ZEXT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
ret i16 %a
}
@@ -196,8 +196,8 @@ define i16 @aext_arg_i16(i16 %a) {
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; MIPS32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
- ; MIPS32-NEXT: $v0 = COPY [[ANYEXT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ANYEXT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
ret i16 %a
}
@@ -229,14 +229,14 @@ define signext i16 @call_sext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4,
; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @sext_stack_arg_i16, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32-NEXT: JAL @sext_stack_arg_i16, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY5]], 16
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT1]](s32)
; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
; MIPS32-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC1]](s16)
- ; MIPS32-NEXT: $v0 = COPY [[SEXT1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SEXT1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
%call = call signext i16 @sext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 signext %a)
ret i16 %call
@@ -265,14 +265,14 @@ define zeroext i16 @call_zext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4,
; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @zext_stack_arg_i16, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32-NEXT: JAL @zext_stack_arg_i16, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY5]], 16
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT1]](s32)
; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
; MIPS32-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16)
- ; MIPS32-NEXT: $v0 = COPY [[ZEXT1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ZEXT1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
%call = call zeroext i16 @zext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 zeroext %a)
ret i16 %call
@@ -300,13 +300,13 @@ define i16 @call_aext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 %a)
; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @aext_stack_arg_i16, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32-NEXT: JAL @aext_stack_arg_i16, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32)
; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
; MIPS32-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
- ; MIPS32-NEXT: $v0 = COPY [[ANYEXT1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ANYEXT1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
%call = call i16 @aext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 %a)
ret i16 %call
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
index 5274729977782..eaa279cfe17c0 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
@@ -12,11 +12,11 @@ define i32 @main() {
; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32-NEXT: $a0 = COPY [[GV]](p0)
; MIPS32-NEXT: $a1 = COPY [[C]](s32)
- ; MIPS32-NEXT: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32-NEXT: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32-NEXT: $v0 = COPY [[C1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
%call = call i32 (ptr, ...) @printf(ptr @.str, i32 signext 1234567890)
ret i32 0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
index f13aa38eec4fd..97c7fafbc4758 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
@@ -10,8 +10,8 @@ define internal i32 @f_with_local_linkage(i32 %x, i32 %y) {
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32_PIC: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32_PIC: $v0 = COPY [[ADD]](s32)
- ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: $r2 = COPY [[ADD]](s32)
+ ; MIPS32_PIC: RetRA implicit $r2
entry:
%add = add i32 %y, %x
ret i32 %add
@@ -20,8 +20,8 @@ entry:
define i32 @call_global(i32 %a, i32 %b) {
; MIPS32_PIC-LABEL: name: call_global
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1, $t9, $v0
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32_PIC: liveins: $a0, $a1, $r2, $t9
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
@@ -29,11 +29,11 @@ define i32 @call_global(i32 %a, i32 %b) {
; MIPS32_PIC: $a0 = COPY [[COPY]](s32)
; MIPS32_PIC: $a1 = COPY [[COPY1]](s32)
; MIPS32_PIC: $gp = COPY [[ADDu]]
- ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $v0
- ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $r2
+ ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32_PIC: $v0 = COPY [[COPY2]](s32)
- ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: $r2 = COPY [[COPY2]](s32)
+ ; MIPS32_PIC: RetRA implicit $r2
entry:
%call = call i32 @f(i32 %a, i32 %b)
ret i32 %call
@@ -42,8 +42,8 @@ entry:
define i32 @call_global_with_local_linkage(i32 %a, i32 %b) {
; MIPS32_PIC-LABEL: name: call_global_with_local_linkage
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1, $t9, $v0
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32_PIC: liveins: $a0, $a1, $r2, $t9
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
@@ -51,11 +51,11 @@ define i32 @call_global_with_local_linkage(i32 %a, i32 %b) {
; MIPS32_PIC: $a0 = COPY [[COPY]](s32)
; MIPS32_PIC: $a1 = COPY [[COPY1]](s32)
; MIPS32_PIC: $gp = COPY [[ADDu]]
- ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $v0
- ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $r2
+ ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32_PIC: $v0 = COPY [[COPY2]](s32)
- ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: $r2 = COPY [[COPY2]](s32)
+ ; MIPS32_PIC: RetRA implicit $r2
entry:
%call = call i32 @f_with_local_linkage(i32 %a, i32 %b)
ret i32 %call
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
index a9d44c946f6d4..646d3a3409e95 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
@@ -8,8 +8,8 @@ define i32 @ptr_arg_in_regs(ptr %p) {
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.p)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
entry:
%0 = load i32, ptr %p
ret i32 %0
@@ -26,8 +26,8 @@ define i32 @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, ptr %p) {
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.p)
- ; MIPS32: $v0 = COPY [[LOAD1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD1]](s32)
+ ; MIPS32: RetRA implicit $r2
entry:
%0 = load i32, ptr %p
ret i32 %0
@@ -38,8 +38,8 @@ define ptr @ret_ptr(ptr %p) {
; MIPS32: bb.1.entry:
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: $v0 = COPY [[COPY]](p0)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY]](p0)
+ ; MIPS32: RetRA implicit $r2
entry:
ret ptr %p
}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll
index d85c63774d064..768ea7b970b01 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll
@@ -8,9 +8,9 @@ define i64 @i64_reg(i64 %a) {
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
- ; MIPS32: $v0 = COPY [[UV]](s32)
- ; MIPS32: $v1 = COPY [[UV1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[UV]](s32)
+ ; MIPS32: $r3 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
entry:
ret i64 %a
}
@@ -32,9 +32,9 @@ define i64 @i64_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i64 %a) {
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.[[STACK0]])
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
- ; MIPS32: $v0 = COPY [[UV]](s32)
- ; MIPS32: $v1 = COPY [[UV1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[UV]](s32)
+ ; MIPS32: $r3 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
entry:
ret i64 %a
}
@@ -48,9 +48,9 @@ define i64 @i64_reg_allign(i32 %a0, i64 %a) {
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
- ; MIPS32: $v0 = COPY [[UV]](s32)
- ; MIPS32: $v1 = COPY [[UV1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[UV]](s32)
+ ; MIPS32: $r3 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
entry:
ret i64 %a
}
@@ -75,9 +75,9 @@ define i64 @i64_stack_allign(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %s16, i64 %
; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.[[STACK0]])
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[LOAD2]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
- ; MIPS32: $v0 = COPY [[UV]](s32)
- ; MIPS32: $v1 = COPY [[UV1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[UV]](s32)
+ ; MIPS32: $r3 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
entry:
ret i64 %a
}
@@ -98,9 +98,9 @@ define i64 @i64_reg_stack(i32 %a0, i32 %a1, i32 %a2, i64 %a) {
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.[[STACK0]])
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
- ; MIPS32: $v0 = COPY [[UV]](s32)
- ; MIPS32: $v1 = COPY [[UV1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[UV]](s32)
+ ; MIPS32: $r3 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
entry:
ret i64 %a
}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
index d549afab2126e..8420e44996789 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
@@ -23,11 +23,11 @@ define i32 @g(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5){
; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32-NEXT: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
- ; MIPS32-NEXT: $v0 = COPY [[COPY5]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[COPY5]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
entry:
%call = call i32 @f(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5)
ret i32 %call
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
index d27e0a96ef2d9..96797c95fafe6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
@@ -39,8 +39,8 @@ define void @testVaCopyArg(ptr %fmt, ...) {
; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32-NEXT: $a0 = COPY [[GV]](p0)
; MIPS32-NEXT: $a1 = COPY [[LOAD2]](p0)
- ; MIPS32-NEXT: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32-NEXT: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32-NEXT: RetRA
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
index e471e1047caa2..fb205853e6ab8 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
@@ -28,13 +28,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[ADD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ADD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_ADD %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -54,16 +54,16 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_ADD %1, %0
%5:_(s32) = G_SEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -82,16 +82,16 @@ body: |
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_ADD %1, %0
%5:_(s32) = G_ZEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -108,16 +108,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[ADD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ADD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_ADD %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -137,16 +137,16 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_ADD %1, %0
%5:_(s32) = G_SEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -165,16 +165,16 @@ body: |
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_ADD %1, %0
%5:_(s32) = G_ZEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -191,16 +191,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[ADD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ADD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_ADD %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -224,9 +224,9 @@ body: |
; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[COPY5]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[COPY4]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[COPY5]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[COPY4]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32)
@@ -235,9 +235,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %5(s32), %4(s32)
%6:_(s64) = G_ADD %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %8(s32)
- $v1 = COPY %7(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %8(s32)
+ $r3 = COPY %7(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -292,11 +292,11 @@ body: |
; MIPS32-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C1]]
; MIPS32-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND3]]
; MIPS32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD6]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[COPY4]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[COPY5]](s32)
+ ; MIPS32-NEXT: $r2 = COPY [[COPY4]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[COPY5]](s32)
; MIPS32-NEXT: $a0 = COPY [[COPY6]](s32)
; MIPS32-NEXT: $a1 = COPY [[COPY7]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%4:_(s32) = COPY $a2
@@ -313,11 +313,11 @@ body: |
%1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
%14:_(s128) = G_ADD %1, %0
%15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
- $v0 = COPY %15(s32)
- $v1 = COPY %16(s32)
+ $r2 = COPY %15(s32)
+ $r3 = COPY %16(s32)
$a0 = COPY %17(s32)
$a1 = COPY %18(s32)
- RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
index 61fa792d9a8e1..84fe5971904de 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
@@ -51,8 +51,8 @@ body: |
; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]]
; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND7]]
- ; MIPS32: $v0 = COPY [[OR5]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[OR5]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32R2-LABEL: name: bitreverse_i32
; MIPS32R2: liveins: $a0
; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
@@ -78,12 +78,12 @@ body: |
; MIPS32R2: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32)
; MIPS32R2: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND5]]
- ; MIPS32R2: $v0 = COPY [[OR2]](s32)
- ; MIPS32R2: RetRA implicit $v0
+ ; MIPS32R2: $r2 = COPY [[OR2]](s32)
+ ; MIPS32R2: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_BITREVERSE %0
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -155,9 +155,9 @@ body: |
; MIPS32: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[OR10]], [[C7]](s32)
; MIPS32: [[AND15:%[0-9]+]]:_(s32) = G_AND [[SHL9]], [[C8]]
; MIPS32: [[OR11:%[0-9]+]]:_(s32) = G_OR [[LSHR9]], [[AND15]]
- ; MIPS32: $v0 = COPY [[OR5]](s32)
- ; MIPS32: $v1 = COPY [[OR11]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[OR5]](s32)
+ ; MIPS32: $r3 = COPY [[OR11]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
; MIPS32R2-LABEL: name: bitreverse_i64
; MIPS32R2: liveins: $a0, $a1
; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
@@ -200,16 +200,16 @@ body: |
; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
; MIPS32R2: [[AND11:%[0-9]+]]:_(s32) = G_AND [[SHL5]], [[C5]]
; MIPS32R2: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[AND11]]
- ; MIPS32R2: $v0 = COPY [[OR2]](s32)
- ; MIPS32R2: $v1 = COPY [[OR5]](s32)
- ; MIPS32R2: RetRA implicit $v0, implicit $v1
+ ; MIPS32R2: $r2 = COPY [[OR2]](s32)
+ ; MIPS32R2: $r3 = COPY [[OR5]](s32)
+ ; MIPS32R2: RetRA implicit $r2, implicit $r3
%1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_BITREVERSE %0
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
- $v0 = COPY %4(s32)
- $v1 = COPY %5(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %4(s32)
+ $r3 = COPY %5(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
index ec88831baa724..e948758409fab 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
@@ -46,16 +46,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s1) = G_TRUNC %3(s32)
%4:_(s1) = G_AND %1, %0
%5:_(s32) = G_ANYEXT %4(s1)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -72,16 +72,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_AND %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -98,16 +98,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_AND %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -124,13 +124,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_AND %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -150,9 +150,9 @@ body: |
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[AND1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[AND1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -161,9 +161,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_AND %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -180,16 +180,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[OR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[OR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s1) = G_TRUNC %3(s32)
%4:_(s1) = G_OR %1, %0
%5:_(s32) = G_ANYEXT %4(s1)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -206,16 +206,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[OR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[OR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_OR %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -232,16 +232,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[OR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[OR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_OR %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -258,13 +258,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[OR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[OR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_OR %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -284,9 +284,9 @@ body: |
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[OR]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[OR1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[OR]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[OR1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -295,9 +295,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_OR %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -314,16 +314,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[XOR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[XOR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s1) = G_TRUNC %3(s32)
%4:_(s1) = G_XOR %1, %0
%5:_(s32) = G_ANYEXT %4(s1)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -340,16 +340,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[XOR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[XOR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_XOR %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -366,16 +366,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[XOR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[XOR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_XOR %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -392,13 +392,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[XOR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[XOR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_XOR %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -418,9 +418,9 @@ body: |
; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[XOR]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[XOR1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[XOR]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[XOR1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -429,9 +429,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_XOR %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -448,13 +448,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[SHL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SHL]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_SHL %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -471,13 +471,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_ASHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -494,13 +494,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[LSHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[LSHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_LSHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -517,13 +517,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[LSHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[LSHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s32) = G_LSHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -540,13 +540,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[SHL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SHL]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_SHL %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -563,13 +563,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_ASHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -586,13 +586,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[LSHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[LSHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_LSHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -609,15 +609,15 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[SHL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SHL]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%1:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CONSTANT i16 2
%3:_(s16) = G_SHL %0, %2(s16)
%4:_(s32) = G_ANYEXT %3(s16)
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -637,15 +637,15 @@ body: |
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ASHR1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%1:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s8) = G_CONSTANT i8 2
%3:_(s8) = G_ASHR %0, %2(s8)
%4:_(s32) = G_ANYEXT %3(s8)
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -664,15 +664,15 @@ body: |
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[LSHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[LSHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%1:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CONSTANT i16 2
%3:_(s16) = G_LSHR %0, %2(s16)
%4:_(s32) = G_ANYEXT %3(s16)
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -703,9 +703,9 @@ body: |
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C1]]
; MIPS32-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]]
; MIPS32-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY1]], [[SELECT1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[SELECT2]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[SELECT2]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -714,9 +714,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_SHL %0, %1(s64)
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -749,9 +749,9 @@ body: |
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[ASHR2]]
; MIPS32-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY]], [[SELECT]]
; MIPS32-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ASHR]], [[ASHR1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT1]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[SELECT2]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT1]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[SELECT2]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -760,9 +760,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_ASHR %0, %1(s64)
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -793,9 +793,9 @@ body: |
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR2]]
; MIPS32-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY]], [[SELECT]]
; MIPS32-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[LSHR]], [[C1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT1]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[SELECT2]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT1]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[SELECT2]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -804,8 +804,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_LSHR %0, %1(s64)
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
index 621f1c478ebde..49330e61d0305 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
@@ -36,8 +36,8 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.end:
- ; MIPS32: $v0 = COPY [[COPY]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.2.block:
; MIPS32: successors: %bb.1(0x80000000)
; MIPS32: G_BR %bb.1
@@ -48,8 +48,8 @@ body: |
G_BR %bb.3
bb.2.end:
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
bb.3.block:
G_BR %bb.2
@@ -72,11 +72,11 @@ body: |
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.if.then:
- ; MIPS32: $v0 = COPY [[COPY1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY1]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.2.if.else:
- ; MIPS32: $v0 = COPY [[COPY2]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY2]](s32)
+ ; MIPS32: RetRA implicit $r2
bb.1 (%ir-block.0):
liveins: $a0, $a1, $a2
@@ -88,12 +88,12 @@ body: |
G_BR %bb.3
bb.2.if.then:
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
bb.3.if.else:
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir
index 6431fb0da8e94..d5f183974e4bd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir
@@ -28,11 +28,11 @@ body: |
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: G_BRINDIRECT [[COPY]](p0)
; MIPS32: bb.1.L1:
- ; MIPS32: $v0 = COPY [[C1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.2.L2:
- ; MIPS32: $v0 = COPY [[C]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $r2
bb.1.entry:
successors: %bb.2, %bb.3
liveins: $a0
@@ -43,11 +43,11 @@ body: |
G_BRINDIRECT %0(p0)
bb.2.L1:
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
bb.3.L2:
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir
index 62a95b8c10a06..4708706ec6c3e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir
@@ -30,18 +30,18 @@ body: |
; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
- ; MIPS32: $v0 = COPY [[OR2]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[OR2]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32R2-LABEL: name: bswap_i32
; MIPS32R2: liveins: $a0
; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
- ; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
- ; MIPS32R2: RetRA implicit $v0
+ ; MIPS32R2: $r2 = COPY [[BSWAP]](s32)
+ ; MIPS32R2: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_BSWAP %0
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -77,25 +77,25 @@ body: |
; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[AND3]]
- ; MIPS32: $v0 = COPY [[OR2]](s32)
- ; MIPS32: $v1 = COPY [[OR5]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[OR2]](s32)
+ ; MIPS32: $r3 = COPY [[OR5]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
; MIPS32R2-LABEL: name: bswap_i64
; MIPS32R2: liveins: $a0, $a1
; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
; MIPS32R2: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
- ; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
- ; MIPS32R2: $v1 = COPY [[BSWAP1]](s32)
- ; MIPS32R2: RetRA implicit $v0, implicit $v1
+ ; MIPS32R2: $r2 = COPY [[BSWAP]](s32)
+ ; MIPS32R2: $r3 = COPY [[BSWAP1]](s32)
+ ; MIPS32R2: RetRA implicit $r2, implicit $r3
%1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_BSWAP %0
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
- $v0 = COPY %4(s32)
- $v1 = COPY %5(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %4(s32)
+ $r3 = COPY %5(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
index 65a7e78044997..307358f8e7035 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
@@ -21,14 +21,14 @@ body: |
; MIPS32-LABEL: name: any_i64
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; MIPS32-NEXT: $v0 = COPY [[C1]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[C1]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%0:_(s64) = G_CONSTANT i64 -9223372036854775808
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %1(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %1(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -39,11 +39,11 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: any_i32
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = G_CONSTANT i32 -2147483648
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
---
@@ -54,12 +54,12 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: signed_i16
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s16) = G_CONSTANT i16 -32768
%1:_(s32) = G_SEXT %0(s16)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -70,12 +70,12 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: signed_i8
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s8) = G_CONSTANT i8 -128
%1:_(s32) = G_SEXT %0(s8)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -86,12 +86,12 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: unsigned_i16
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s16) = G_CONSTANT i16 -32768
%1:_(s32) = G_ZEXT %0(s16)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -102,12 +102,12 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: unsigned_i8
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s8) = G_CONSTANT i8 -128
%1:_(s32) = G_ZEXT %0(s8)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -118,12 +118,12 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: i1_true
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s1) = G_CONSTANT i1 true
%1:_(s32) = G_ZEXT %0(s1)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -134,11 +134,11 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: i1_false
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s1) = G_CONSTANT i1 false
%1:_(s32) = G_ZEXT %0(s1)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
index 73ea9338426c2..6e382cc3801f5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
@@ -13,12 +13,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[CTLZ]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[CTLZ]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_CTLZ %0(s32)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -41,16 +41,16 @@ body: |
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]]
; MIPS32-NEXT: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32)
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTLZ1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_CTLZ %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
- $v0 = COPY %4(s32)
- $v1 = COPY %5(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %4(s32)
+ $r3 = COPY %5(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctpop.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctpop.mir
index f518e9ec9e589..04ae7c91f9f72 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctpop.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctpop.mir
@@ -32,12 +32,12 @@ body: |
; MIPS32-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]
; MIPS32-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[LSHR3]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[LSHR3]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_CTPOP %0(s32)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -87,16 +87,16 @@ body: |
; MIPS32-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C7]](s32)
; MIPS32-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[LSHR3]]
; MIPS32-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: $v0 = COPY [[ADD4]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[C8]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[ADD4]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[C8]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_CTPOP %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
- $v0 = COPY %4(s32)
- $v1 = COPY %5(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %4(s32)
+ $r3 = COPY %5(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
index 64cb476d961e2..87cbe47367c0f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
@@ -19,12 +19,12 @@ body: |
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; MIPS32-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[CTLZ]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SUB]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_CTTZ %0(s32)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -56,17 +56,17 @@ body: |
; MIPS32-NEXT: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ1]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD1]], [[SUB1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_CTTZ %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
- $v0 = COPY %4(s32)
- $v1 = COPY %5(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %4(s32)
+ $r3 = COPY %5(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -93,8 +93,8 @@ body: |
; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = nuw nsw G_ADD [[SUB]], [[C]]
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C1]], [[ADD1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%2:_(s32) = G_CONSTANT i32 1
%4:_(s32) = G_CONSTANT i32 0
@@ -102,8 +102,8 @@ body: |
%3:_(s32) = nuw nsw G_ADD %1, %2
%5:_(s1) = G_ICMP intpred(eq), %0(s32), %4
%6:_(s32) = G_SELECT %5(s1), %4, %3
- $v0 = COPY %6(s32)
- RetRA implicit $v0
+ $r2 = COPY %6(s32)
+ RetRA implicit $r2
...
---
@@ -150,9 +150,9 @@ body: |
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C1]]
; MIPS32-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s32), [[MV]], [[MV1]]
; MIPS32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64)
- ; MIPS32-NEXT: $v0 = COPY [[UV]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[UV1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[UV]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[UV1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
@@ -163,8 +163,8 @@ body: |
%7:_(s1) = G_ICMP intpred(eq), %0(s64), %6
%8:_(s64) = G_SELECT %7(s1), %6, %5
%9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(s64)
- $v0 = COPY %9(s32)
- $v1 = COPY %10(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %9(s32)
+ $r3 = COPY %10(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
index 4e600b586bb6e..89ae5cbad7f05 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
@@ -56,7 +56,7 @@ body: |
; MIPS32: G_STORE [[C1]](s32), [[COPY4]](p0) :: (store (s8) into %ir.arrayidx)
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY3]](p0)
- ; MIPS32: JAL @puts, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $v0
+ ; MIPS32: JAL @puts, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%2:_(s32) = COPY $a0
@@ -77,7 +77,7 @@ body: |
G_STORE %13(s8), %12(p0) :: (store (s8) into %ir.arrayidx)
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %10(p0)
- JAL @puts, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $v0
+ JAL @puts, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $r2
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir
index 141113b6efa26..74c2b27e03706 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir
@@ -20,21 +20,21 @@ body: |
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
- ; FP32: $v0 = COPY [[FCMP]](s32)
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[FCMP]](s32)
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: oeq_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
- ; FP64: $v0 = COPY [[FCMP]](s32)
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[FCMP]](s32)
+ ; FP64: RetRA implicit $r2
%0:_(s32) = COPY $f12
%1:_(s32) = COPY $f14
%2:_(s1) = G_FCMP floatpred(oeq), %0(s32), %1
%3:_(s32) = G_ANYEXT %2(s1)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -50,20 +50,20 @@ body: |
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
- ; FP32: $v0 = COPY [[FCMP]](s32)
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[FCMP]](s32)
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: oeq_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
- ; FP64: $v0 = COPY [[FCMP]](s32)
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[FCMP]](s32)
+ ; FP64: RetRA implicit $r2
%0:_(s64) = COPY $d6
%1:_(s64) = COPY $d7
%2:_(s1) = G_FCMP floatpred(oeq), %0(s64), %1
%3:_(s32) = G_ANYEXT %2(s1)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
index d2074542cb5bd..5e38867ad0e33 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
@@ -18,12 +18,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic (s32) from %ir.ptr)
; MIPS32: G_FENCE 4, 1
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load monotonic (s32) from %ir.ptr)
G_FENCE 4, 1
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
index 970e1f0351264..627f58bc304f7 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
@@ -35,13 +35,13 @@ body: |
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP32-NEXT: JAL &__fixsfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP32-NEXT: JAL &__fixsfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $r2, implicit-def $r3
+ ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
+ ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP32-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP32-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP32-NEXT: $r2 = COPY [[COPY1]](s32)
+ ; FP32-NEXT: $r3 = COPY [[COPY2]](s32)
+ ; FP32-NEXT: RetRA implicit $r2, implicit $r3
;
; FP64-LABEL: name: f32toi64
; FP64: liveins: $f12
@@ -49,19 +49,19 @@ body: |
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP64-NEXT: JAL &__fixsfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP64-NEXT: JAL &__fixsfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $r2, implicit-def $r3
+ ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
+ ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP64-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP64-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP64-NEXT: $r2 = COPY [[COPY1]](s32)
+ ; FP64-NEXT: $r3 = COPY [[COPY2]](s32)
+ ; FP64-NEXT: RetRA implicit $r2, implicit $r3
%0:_(s32) = COPY $f12
%1:_(s64) = G_FPTOSI %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %3(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %3(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -77,20 +77,20 @@ body: |
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32-NEXT: $v0 = COPY [[FPTOSI]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[FPTOSI]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f32toi32
; FP64: liveins: $f12
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64-NEXT: $v0 = COPY [[FPTOSI]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[FPTOSI]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $f12
%1:_(s32) = G_FPTOSI %0(s32)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -109,8 +109,8 @@ body: |
; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f32toi16
; FP64: liveins: $f12
@@ -120,13 +120,13 @@ body: |
; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP64-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP64-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP64-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $f12
%1:_(s16) = G_FPTOSI %0(s32)
%2:_(s32) = G_SEXT %1(s16)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -145,8 +145,8 @@ body: |
; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f32toi8
; FP64: liveins: $f12
@@ -156,13 +156,13 @@ body: |
; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP64-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP64-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP64-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $f12
%1:_(s8) = G_FPTOSI %0(s32)
%2:_(s32) = G_SEXT %1(s8)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -179,13 +179,13 @@ body: |
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32-NEXT: $d6 = COPY [[COPY]](s64)
- ; FP32-NEXT: JAL &__fixdfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP32-NEXT: JAL &__fixdfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit-def $r2, implicit-def $r3
+ ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
+ ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP32-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP32-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP32-NEXT: $r2 = COPY [[COPY1]](s32)
+ ; FP32-NEXT: $r3 = COPY [[COPY2]](s32)
+ ; FP32-NEXT: RetRA implicit $r2, implicit $r3
;
; FP64-LABEL: name: f64toi64
; FP64: liveins: $d6
@@ -193,19 +193,19 @@ body: |
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64-NEXT: $d12_64 = COPY [[COPY]](s64)
- ; FP64-NEXT: JAL &__fixdfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP64-NEXT: JAL &__fixdfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $d12_64, implicit-def $r2, implicit-def $r3
+ ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
+ ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP64-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP64-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP64-NEXT: $r2 = COPY [[COPY1]](s32)
+ ; FP64-NEXT: $r3 = COPY [[COPY2]](s32)
+ ; FP64-NEXT: RetRA implicit $r2, implicit $r3
%0:_(s64) = COPY $d6
%1:_(s64) = G_FPTOSI %0(s64)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %3(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %3(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -221,20 +221,20 @@ body: |
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32-NEXT: $v0 = COPY [[FPTOSI]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[FPTOSI]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f64toi32
; FP64: liveins: $d6
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64-NEXT: $v0 = COPY [[FPTOSI]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[FPTOSI]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s64) = COPY $d6
%1:_(s32) = G_FPTOSI %0(s64)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -253,8 +253,8 @@ body: |
; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f64toi16
; FP64: liveins: $d6
@@ -264,13 +264,13 @@ body: |
; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP64-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP64-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP64-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s64) = COPY $d6
%1:_(s16) = G_FPTOSI %0(s64)
%2:_(s32) = G_SEXT %1(s16)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -289,8 +289,8 @@ body: |
; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f64toi8
; FP64: liveins: $d6
@@ -300,13 +300,13 @@ body: |
; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP64-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP64-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP64-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s64) = COPY $d6
%1:_(s8) = G_FPTOSI %0(s64)
%2:_(s32) = G_SEXT %1(s8)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -323,13 +323,13 @@ body: |
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP32-NEXT: JAL &__fixunssfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP32-NEXT: JAL &__fixunssfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $r2, implicit-def $r3
+ ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
+ ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP32-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP32-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP32-NEXT: $r2 = COPY [[COPY1]](s32)
+ ; FP32-NEXT: $r3 = COPY [[COPY2]](s32)
+ ; FP32-NEXT: RetRA implicit $r2, implicit $r3
;
; FP64-LABEL: name: f32tou64
; FP64: liveins: $f12
@@ -337,19 +337,19 @@ body: |
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP64-NEXT: JAL &__fixunssfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP64-NEXT: JAL &__fixunssfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $r2, implicit-def $r3
+ ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
+ ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP64-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP64-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP64-NEXT: $r2 = COPY [[COPY1]](s32)
+ ; FP64-NEXT: $r3 = COPY [[COPY2]](s32)
+ ; FP64-NEXT: RetRA implicit $r2, implicit $r3
%0:_(s32) = COPY $f12
%1:_(s64) = G_FPTOUI %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %3(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %3(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -372,8 +372,8 @@ body: |
; FP32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f32tou32
; FP64: liveins: $f12
@@ -387,12 +387,12 @@ body: |
; FP64-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP64-NEXT: $v0 = COPY [[SELECT]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $f12
%1:_(s32) = G_FPTOUI %0(s32)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -417,8 +417,8 @@ body: |
; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP32-NEXT: $v0 = COPY [[AND]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[AND]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f32tou16
; FP64: liveins: $f12
@@ -434,13 +434,13 @@ body: |
; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP64-NEXT: $v0 = COPY [[AND]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[AND]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $f12
%1:_(s16) = G_FPTOUI %0(s32)
%2:_(s32) = G_ZEXT %1(s16)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -465,8 +465,8 @@ body: |
; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP32-NEXT: $v0 = COPY [[AND]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[AND]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f32tou8
; FP64: liveins: $f12
@@ -482,13 +482,13 @@ body: |
; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP64-NEXT: $v0 = COPY [[AND]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[AND]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $f12
%1:_(s8) = G_FPTOUI %0(s32)
%2:_(s32) = G_ZEXT %1(s8)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -505,13 +505,13 @@ body: |
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32-NEXT: $d6 = COPY [[COPY]](s64)
- ; FP32-NEXT: JAL &__fixunsdfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP32-NEXT: JAL &__fixunsdfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit-def $r2, implicit-def $r3
+ ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
+ ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP32-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP32-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP32-NEXT: $r2 = COPY [[COPY1]](s32)
+ ; FP32-NEXT: $r3 = COPY [[COPY2]](s32)
+ ; FP32-NEXT: RetRA implicit $r2, implicit $r3
;
; FP64-LABEL: name: f64tou64
; FP64: liveins: $d6
@@ -519,19 +519,19 @@ body: |
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64-NEXT: $d12_64 = COPY [[COPY]](s64)
- ; FP64-NEXT: JAL &__fixunsdfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP64-NEXT: JAL &__fixunsdfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $d12_64, implicit-def $r2, implicit-def $r3
+ ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
+ ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP64-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP64-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP64-NEXT: $r2 = COPY [[COPY1]](s32)
+ ; FP64-NEXT: $r3 = COPY [[COPY2]](s32)
+ ; FP64-NEXT: RetRA implicit $r2, implicit $r3
%0:_(s64) = COPY $d6
%1:_(s64) = G_FPTOUI %0(s64)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %3(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %3(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -554,8 +554,8 @@ body: |
; FP32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f64tou32
; FP64: liveins: $d6
@@ -569,12 +569,12 @@ body: |
; FP64-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP64-NEXT: $v0 = COPY [[SELECT]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s64) = COPY $d6
%1:_(s32) = G_FPTOUI %0(s64)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -599,8 +599,8 @@ body: |
; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP32-NEXT: $v0 = COPY [[AND]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[AND]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f64tou16
; FP64: liveins: $d6
@@ -616,13 +616,13 @@ body: |
; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP64-NEXT: $v0 = COPY [[AND]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[AND]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s64) = COPY $d6
%1:_(s16) = G_FPTOUI %0(s64)
%2:_(s32) = G_ZEXT %1(s16)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -647,8 +647,8 @@ body: |
; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP32-NEXT: $v0 = COPY [[AND]](s32)
- ; FP32-NEXT: RetRA implicit $v0
+ ; FP32-NEXT: $r2 = COPY [[AND]](s32)
+ ; FP32-NEXT: RetRA implicit $r2
;
; FP64-LABEL: name: f64tou8
; FP64: liveins: $d6
@@ -664,12 +664,12 @@ body: |
; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP64-NEXT: $v0 = COPY [[AND]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64-NEXT: $r2 = COPY [[AND]](s32)
+ ; FP64-NEXT: RetRA implicit $r2
%0:_(s64) = COPY $d6
%1:_(s8) = G_FPTOUI %0(s64)
%2:_(s32) = G_ZEXT %1(s8)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir
index 73db7436f0cef..cf95cc19badf5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir
@@ -22,11 +22,11 @@ body: |
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY]](p0)
; MIPS32: $a1 = COPY [[C]](s32)
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[C1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $r2
%2:_(p0) = G_GLOBAL_VALUE @.str
%1:_(p0) = COPY %2(p0)
%3:_(s32) = G_CONSTANT i32 1234567890
@@ -34,10 +34,10 @@ body: |
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %1(p0)
$a1 = COPY %3(s32)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- %0:_(s32) = COPY $v0
+ JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ %0:_(s32) = COPY $r2
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
index c3ccc820fc02b..abe5cceef848c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
@@ -32,14 +32,14 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s1) = G_ICMP intpred(ne), %0(s32), %1
%3:_(s32) = G_ANYEXT %2(s1)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -56,14 +56,14 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(s1) = G_ICMP intpred(eq), %0(p0), %1
%3:_(s32) = G_ANYEXT %2(s1)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -83,16 +83,16 @@ body: |
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s1) = G_ICMP intpred(ult), %0(s8), %1
%5:_(s32) = G_ANYEXT %4(s1)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -114,16 +114,16 @@ body: |
; MIPS32-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s1) = G_ICMP intpred(slt), %0(s16), %1
%5:_(s32) = G_ANYEXT %4(s1)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -146,8 +146,8 @@ body: |
; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -156,8 +156,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(eq), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -180,8 +180,8 @@ body: |
; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -190,8 +190,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(ne), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -213,8 +213,8 @@ body: |
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -223,8 +223,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -246,8 +246,8 @@ body: |
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -256,8 +256,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(sge), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -279,8 +279,8 @@ body: |
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -289,8 +289,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(slt), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -312,8 +312,8 @@ body: |
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -322,8 +322,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(sle), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -345,8 +345,8 @@ body: |
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -355,8 +355,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(ugt), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -378,8 +378,8 @@ body: |
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -388,8 +388,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(uge), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -411,8 +411,8 @@ body: |
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -421,8 +421,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(ult), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -444,8 +444,8 @@ body: |
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -454,7 +454,7 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(ule), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir
index 4d34f21d25853..d0c12814d6c4f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir
@@ -18,12 +18,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s32)
- ; MIPS32: $v0 = COPY [[INTTOPTR]](p0)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[INTTOPTR]](p0)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(p0) = G_INTTOPTR %0(s32)
- $v0 = COPY %1(p0)
- RetRA implicit $v0
+ $r2 = COPY %1(p0)
+ RetRA implicit $r2
...
---
@@ -38,11 +38,11 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
- ; MIPS32: $v0 = COPY [[PTRTOINT]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PTRTOINT]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s32) = G_PTRTOINT %0(p0)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
index fe32504be62db..8285b2408644a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
@@ -94,20 +94,20 @@ body: |
; MIPS32-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[COPY1]](s32)
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.2.sw.bb:
- ; MIPS32-NEXT: $v0 = COPY [[C4]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C4]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.3.sw.bb1:
- ; MIPS32-NEXT: $v0 = COPY [[C3]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C3]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.4.sw.bb2:
- ; MIPS32-NEXT: $v0 = COPY [[C2]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C2]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.5.sw.bb3:
- ; MIPS32-NEXT: $v0 = COPY [[C1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.6.sw.default:
; MIPS32-NEXT: successors: %bb.7(0x80000000)
@@ -129,24 +129,24 @@ body: |
; MIPS32-NEXT: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY3]](s32)
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.9.sw.bb4:
- ; MIPS32-NEXT: $v0 = COPY [[C4]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C4]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.10.sw.bb5:
- ; MIPS32-NEXT: $v0 = COPY [[C3]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C3]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.11.sw.bb6:
- ; MIPS32-NEXT: $v0 = COPY [[C2]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C2]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.12.sw.bb7:
- ; MIPS32-NEXT: $v0 = COPY [[C1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.13.sw.default8:
- ; MIPS32-NEXT: $v0 = COPY [[C5]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[C5]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
bb.1.entry:
liveins: $a0
@@ -171,20 +171,20 @@ body: |
G_BRJT %7(p0), %jump-table.0, %3(s32)
bb.2.sw.bb:
- $v0 = COPY %11(s32)
- RetRA implicit $v0
+ $r2 = COPY %11(s32)
+ RetRA implicit $r2
bb.3.sw.bb1:
- $v0 = COPY %10(s32)
- RetRA implicit $v0
+ $r2 = COPY %10(s32)
+ RetRA implicit $r2
bb.4.sw.bb2:
- $v0 = COPY %9(s32)
- RetRA implicit $v0
+ $r2 = COPY %9(s32)
+ RetRA implicit $r2
bb.5.sw.bb3:
- $v0 = COPY %8(s32)
- RetRA implicit $v0
+ $r2 = COPY %8(s32)
+ RetRA implicit $r2
bb.6.sw.default:
@@ -203,23 +203,23 @@ body: |
G_BRJT %17(p0), %jump-table.1, %14(s32)
bb.8.sw.bb4:
- $v0 = COPY %11(s32)
- RetRA implicit $v0
+ $r2 = COPY %11(s32)
+ RetRA implicit $r2
bb.9.sw.bb5:
- $v0 = COPY %10(s32)
- RetRA implicit $v0
+ $r2 = COPY %10(s32)
+ RetRA implicit $r2
bb.10.sw.bb6:
- $v0 = COPY %9(s32)
- RetRA implicit $v0
+ $r2 = COPY %9(s32)
+ RetRA implicit $r2
bb.11.sw.bb7:
- $v0 = COPY %8(s32)
- RetRA implicit $v0
+ $r2 = COPY %8(s32)
+ RetRA implicit $r2
bb.12.sw.default8:
- $v0 = COPY %18(s32)
- RetRA implicit $v0
+ $r2 = COPY %18(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
index c58b8541d1ee1..c9dfb19e0e07e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
@@ -13,12 +13,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
- ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load (s32))
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -35,15 +35,15 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
; MIPS32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
- ; MIPS32-NEXT: $v0 = COPY [[UV]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[UV1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[UV]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[UV1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%0:_(p0) = COPY $a0
%1:_(s64) = G_LOAD %0(p0) :: (load (s64))
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %3(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %3(s32)
+ RetRA implicit $r2, implicit $r3
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir
index 8de7b2da18591..0c611d4dae454 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir
@@ -158,17 +158,17 @@ body: |
; MIPS32-LABEL: name: load_i32_align1
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @i32_align1, align 1)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32R6-LABEL: name: load_i32_align1
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @i32_align1, align 1)
- ; MIPS32R6: $v0 = COPY [[LOAD]](s32)
- ; MIPS32R6: RetRA implicit $v0
+ ; MIPS32R6: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32R6: RetRA implicit $r2
%1:_(p0) = G_GLOBAL_VALUE @i32_align1
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align1, align 1)
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
---
@@ -180,17 +180,17 @@ body: |
; MIPS32-LABEL: name: load_i32_align2
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @i32_align2, align 2)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32R6-LABEL: name: load_i32_align2
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @i32_align2, align 2)
- ; MIPS32R6: $v0 = COPY [[LOAD]](s32)
- ; MIPS32R6: RetRA implicit $v0
+ ; MIPS32R6: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32R6: RetRA implicit $r2
%1:_(p0) = G_GLOBAL_VALUE @i32_align2
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align2, align 2)
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
---
@@ -202,17 +202,17 @@ body: |
; MIPS32-LABEL: name: load_i32_align4
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @i32_align4)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32R6-LABEL: name: load_i32_align4
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @i32_align4)
- ; MIPS32R6: $v0 = COPY [[LOAD]](s32)
- ; MIPS32R6: RetRA implicit $v0
+ ; MIPS32R6: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32R6: RetRA implicit $r2
%1:_(p0) = G_GLOBAL_VALUE @i32_align4
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align4)
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
---
@@ -224,16 +224,16 @@ body: |
; MIPS32-LABEL: name: load_i32_align8
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @i32_align8, align 8)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32R6-LABEL: name: load_i32_align8
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @i32_align8, align 8)
- ; MIPS32R6: $v0 = COPY [[LOAD]](s32)
- ; MIPS32R6: RetRA implicit $v0
+ ; MIPS32R6: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32R6: RetRA implicit $r2
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align8, align 8)
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
index 74d5e8c32a5d5..79709c734145b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
@@ -29,13 +29,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[MUL]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_MUL %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -55,16 +55,16 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_MUL %1, %0
%5:_(s32) = G_SEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -83,16 +83,16 @@ body: |
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_MUL %1, %0
%5:_(s32) = G_ZEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -109,16 +109,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[MUL]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_MUL %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -138,16 +138,16 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_MUL %1, %0
%5:_(s32) = G_SEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -166,16 +166,16 @@ body: |
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_MUL %1, %0
%5:_(s32) = G_ZEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -192,16 +192,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[MUL]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_MUL %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -225,9 +225,9 @@ body: |
; MIPS32-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY]]
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UMULH]], [[MUL1]]
; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL2]]
- ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[ADD1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[MUL]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[ADD1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -236,9 +236,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_MUL %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -318,11 +318,11 @@ body: |
; MIPS32-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[ADD15]], [[MUL8]]
; MIPS32-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[MUL9]]
; MIPS32-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[ADD11]]
- ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[COPY5]](s32)
+ ; MIPS32-NEXT: $r2 = COPY [[MUL]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[COPY5]](s32)
; MIPS32-NEXT: $a0 = COPY [[COPY10]](s32)
; MIPS32-NEXT: $a1 = COPY [[ADD18]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%4:_(s32) = COPY $a2
@@ -339,11 +339,11 @@ body: |
%1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
%14:_(s128) = G_MUL %1, %0
%15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
- $v0 = COPY %15(s32)
- $v1 = COPY %16(s32)
+ $r2 = COPY %15(s32)
+ $r3 = COPY %16(s32)
$a0 = COPY %17(s32)
$a1 = COPY %18(s32)
- RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
...
---
@@ -387,9 +387,9 @@ body: |
; MIPS32-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[ICMP4]]
; MIPS32-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY1]]
; MIPS32-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD7]]
- ; MIPS32-NEXT: $v0 = COPY [[COPY8]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[ADD8]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[COPY8]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[ADD8]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -398,9 +398,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_UMULH %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
index 261bcd63c28a6..82f740dce7897 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
@@ -167,8 +167,8 @@ body: |
; MIPS32: successors: %bb.3(0x80000000)
; MIPS32: bb.3.cond.end:
; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
- ; MIPS32: $v0 = COPY [[PHI]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PHI]](s32)
+ ; MIPS32: RetRA implicit $r2
bb.1.entry:
liveins: $a0, $a1, $a2
@@ -189,8 +189,8 @@ body: |
bb.4.cond.end:
%6:_(s1) = G_PHI %1(s1), %bb.2, %2(s1), %bb.3
%7:_(s32) = G_ANYEXT %6(s1)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -216,8 +216,8 @@ body: |
; MIPS32: successors: %bb.3(0x80000000)
; MIPS32: bb.3.cond.end:
; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
- ; MIPS32: $v0 = COPY [[PHI]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PHI]](s32)
+ ; MIPS32: RetRA implicit $r2
bb.1.entry:
liveins: $a0, $a1, $a2
@@ -238,8 +238,8 @@ body: |
bb.4.cond.end:
%6:_(s8) = G_PHI %1(s8), %bb.2, %2(s8), %bb.3
%7:_(s32) = G_ANYEXT %6(s8)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -265,8 +265,8 @@ body: |
; MIPS32: successors: %bb.3(0x80000000)
; MIPS32: bb.3.cond.end:
; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
- ; MIPS32: $v0 = COPY [[PHI]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PHI]](s32)
+ ; MIPS32: RetRA implicit $r2
bb.1.entry:
liveins: $a0, $a1, $a2
@@ -287,8 +287,8 @@ body: |
bb.4.cond.end:
%6:_(s16) = G_PHI %1(s16), %bb.2, %2(s16), %bb.3
%7:_(s32) = G_ANYEXT %6(s16)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -314,8 +314,8 @@ body: |
; MIPS32: successors: %bb.3(0x80000000)
; MIPS32: bb.3.cond.end:
; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
- ; MIPS32: $v0 = COPY [[PHI]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PHI]](s32)
+ ; MIPS32: RetRA implicit $r2
bb.1.entry:
liveins: $a0, $a1, $a2
@@ -333,8 +333,8 @@ body: |
bb.4.cond.end:
%4:_(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -370,9 +370,9 @@ body: |
; MIPS32: bb.3.cond.end:
; MIPS32: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[MV]](s64), %bb.1, [[MV1]](s64), %bb.2
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PHI]](s64)
- ; MIPS32: $v0 = COPY [[UV]](s32)
- ; MIPS32: $v1 = COPY [[UV1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[UV]](s32)
+ ; MIPS32: $r3 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
bb.1.entry:
liveins: $a0, $a2, $a3
@@ -397,9 +397,9 @@ body: |
bb.4.cond.end:
%10:_(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3
%11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %10(s64)
- $v0 = COPY %11(s32)
- $v1 = COPY %12(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %11(s32)
+ $r3 = COPY %12(s32)
+ RetRA implicit $r2, implicit $r3
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
index 2e455a130e702..d4f2f76df7d3f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
@@ -19,12 +19,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.p)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.p)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -46,8 +46,8 @@ body: |
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.p)
- ; MIPS32: $v0 = COPY [[LOAD1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD1]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
@@ -55,8 +55,8 @@ body: |
%5:_(p0) = G_FRAME_INDEX %fixed-stack.0
%4:_(p0) = G_LOAD %5(p0) :: (load (p0) from %fixed-stack.0, align 4)
%6:_(s32) = G_LOAD %4(p0) :: (load (s32) from %ir.p)
- $v0 = COPY %6(s32)
- RetRA implicit $v0
+ $r2 = COPY %6(s32)
+ RetRA implicit $r2
...
---
@@ -70,10 +70,10 @@ body: |
; MIPS32-LABEL: name: ret_ptr
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: $v0 = COPY [[COPY]](p0)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY]](p0)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
- $v0 = COPY %0(p0)
- RetRA implicit $v0
+ $r2 = COPY %0(p0)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
index 8de113eae3e5c..36014a04a534b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
@@ -40,16 +40,16 @@ body: |
; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SDIV]], [[C]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
- ; MIPS32: $v0 = COPY [[ASHR2]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ASHR2]](s32)
+ ; MIPS32: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SDIV %1, %0
%5:_(s32) = G_SEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -72,16 +72,16 @@ body: |
; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SDIV]], [[C]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
- ; MIPS32: $v0 = COPY [[ASHR2]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ASHR2]](s32)
+ ; MIPS32: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SDIV %1, %0
%5:_(s32) = G_SEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -97,13 +97,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[SDIV]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SDIV]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_SDIV %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -125,13 +125,13 @@ body: |
; MIPS32: $a1 = COPY [[COPY3]](s32)
; MIPS32: $a2 = COPY [[COPY]](s32)
; MIPS32: $a3 = COPY [[COPY1]](s32)
- ; MIPS32: JAL &__divdi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
+ ; MIPS32: JAL &__divdi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2, implicit-def $r3
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
+ ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $r3
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
- ; MIPS32: $v1 = COPY [[COPY5]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[COPY4]](s32)
+ ; MIPS32: $r3 = COPY [[COPY5]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -140,9 +140,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_SDIV %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -163,16 +163,16 @@ body: |
; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
- ; MIPS32: $v0 = COPY [[SREM]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SREM]](s32)
+ ; MIPS32: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SREM %1, %0
%5:_(s32) = G_SEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -193,16 +193,16 @@ body: |
; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
- ; MIPS32: $v0 = COPY [[SREM]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SREM]](s32)
+ ; MIPS32: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SREM %1, %0
%5:_(s32) = G_SEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -218,13 +218,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[SREM]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SREM]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_SREM %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -246,13 +246,13 @@ body: |
; MIPS32: $a1 = COPY [[COPY3]](s32)
; MIPS32: $a2 = COPY [[COPY]](s32)
; MIPS32: $a3 = COPY [[COPY1]](s32)
- ; MIPS32: JAL &__moddi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
+ ; MIPS32: JAL &__moddi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2, implicit-def $r3
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
+ ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $r3
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
- ; MIPS32: $v1 = COPY [[COPY5]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[COPY4]](s32)
+ ; MIPS32: $r3 = COPY [[COPY5]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -261,9 +261,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_SREM %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -285,16 +285,16 @@ body: |
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UDIV]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; MIPS32: $v0 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_UDIV %1, %0
%5:_(s32) = G_SEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -316,16 +316,16 @@ body: |
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UDIV]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; MIPS32: $v0 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_UDIV %1, %0
%5:_(s32) = G_SEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -341,13 +341,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[UDIV]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[UDIV]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_UDIV %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -369,13 +369,13 @@ body: |
; MIPS32: $a1 = COPY [[COPY3]](s32)
; MIPS32: $a2 = COPY [[COPY]](s32)
; MIPS32: $a3 = COPY [[COPY1]](s32)
- ; MIPS32: JAL &__udivdi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
+ ; MIPS32: JAL &__udivdi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2, implicit-def $r3
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
+ ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $r3
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
- ; MIPS32: $v1 = COPY [[COPY5]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[COPY4]](s32)
+ ; MIPS32: $r3 = COPY [[COPY5]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -384,9 +384,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_UDIV %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -408,16 +408,16 @@ body: |
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UREM]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; MIPS32: $v0 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_UREM %1, %0
%5:_(s32) = G_SEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -439,16 +439,16 @@ body: |
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UREM]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; MIPS32: $v0 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_UREM %1, %0
%5:_(s32) = G_SEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -464,13 +464,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[UREM]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[UREM]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_UREM %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -492,13 +492,13 @@ body: |
; MIPS32: $a1 = COPY [[COPY3]](s32)
; MIPS32: $a2 = COPY [[COPY]](s32)
; MIPS32: $a3 = COPY [[COPY1]](s32)
- ; MIPS32: JAL &__umoddi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
+ ; MIPS32: JAL &__umoddi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2, implicit-def $r3
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
+ ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $r3
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
- ; MIPS32: $v1 = COPY [[COPY5]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[COPY4]](s32)
+ ; MIPS32: $r3 = COPY [[COPY5]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -507,8 +507,8 @@ body: |
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_UREM %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %7(s32)
- $v1 = COPY %8(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %7(s32)
+ $r3 = COPY %8(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
index a0bf22dbffd4b..28b12f586b214 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
@@ -29,8 +29,8 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%4:_(s32) = COPY $a1
@@ -39,8 +39,8 @@ body: |
%2:_(s8) = G_TRUNC %5(s32)
%6:_(s8) = G_SELECT %0(s1), %1, %2
%7:_(s32) = G_ANYEXT %6(s8)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -60,8 +60,8 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%4:_(s32) = COPY $a1
@@ -70,8 +70,8 @@ body: |
%2:_(s16) = G_TRUNC %5(s32)
%6:_(s16) = G_SELECT %0(s1), %1, %2
%7:_(s32) = G_ANYEXT %6(s16)
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -91,15 +91,15 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
%4:_(s32) = G_SELECT %0(s1), %1, %2
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -119,15 +119,15 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](p0)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](p0)
+ ; MIPS32-NEXT: RetRA implicit $r2
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%4:_(p0) = G_SELECT %0(s1), %1, %2
- $v0 = COPY %4(p0)
- RetRA implicit $v0
+ $r2 = COPY %4(p0)
+ RetRA implicit $r2
...
---
@@ -149,8 +149,8 @@ body: |
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[COPY2]], [[COPY3]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
@@ -159,8 +159,8 @@ body: |
%4:_(s1) = G_ICMP intpred(slt), %0(s32), %1
%6:_(s1) = G_XOR %4, %5
%7:_(s32) = G_SELECT %6(s1), %2, %3
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
@@ -190,9 +190,9 @@ body: |
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[MV]], [[MV1]]
; MIPS32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
- ; MIPS32-NEXT: $v0 = COPY [[UV]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[UV1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[UV]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[UV1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%4:_(s32) = COPY $a2
@@ -205,9 +205,9 @@ body: |
%2:_(s64) = G_MERGE_VALUES %6(s32), %7(s32)
%10:_(s64) = G_SELECT %0(s1), %1, %2
%11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %10(s64)
- $v0 = COPY %11(s32)
- $v1 = COPY %12(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %11(s32)
+ $r3 = COPY %12(s32)
+ RetRA implicit $r2, implicit $r3
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
index f292b0b8fd8eb..89d77c3aa29cf 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
@@ -33,11 +33,11 @@ body: |
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store (s32) into stack + 16)
- ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
+ ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY5]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY5]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
@@ -53,10 +53,10 @@ body: |
%8:_(s32) = G_CONSTANT i32 16
%9:_(p0) = G_PTR_ADD %7, %8(s32)
G_STORE %4(s32), %9(p0) :: (store (s32) into stack + 16, align 4)
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- %6:_(s32) = COPY $v0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ %6:_(s32) = COPY $r2
ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
- $v0 = COPY %6(s32)
- RetRA implicit $v0
+ $r2 = COPY %6(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
index db62b72be87d8..d78a49ec46791 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
@@ -27,13 +27,13 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SUB]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_SUB %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -53,16 +53,16 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SUB %1, %0
%5:_(s32) = G_SEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -81,16 +81,16 @@ body: |
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SUB %1, %0
%5:_(s32) = G_ZEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -107,16 +107,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SUB]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SUB %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -136,16 +136,16 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SUB %1, %0
%5:_(s32) = G_SEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -164,16 +164,16 @@ body: |
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SUB %1, %0
%5:_(s32) = G_ZEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -190,16 +190,16 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SUB]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SUB %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -221,9 +221,9 @@ body: |
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY3]](s32), [[COPY1]]
; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB2]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[SUB2]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[SUB]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32)
@@ -232,9 +232,9 @@ body: |
%1:_(s64) = G_MERGE_VALUES %5(s32), %4(s32)
%6:_(s64) = G_SUB %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
- $v0 = COPY %8(s32)
- $v1 = COPY %7(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %8(s32)
+ $r3 = COPY %7(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -285,11 +285,11 @@ body: |
; MIPS32-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]]
; MIPS32-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C1]]
; MIPS32-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND3]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[SUB2]](s32)
+ ; MIPS32-NEXT: $r2 = COPY [[SUB]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[SUB2]](s32)
; MIPS32-NEXT: $a0 = COPY [[SUB4]](s32)
; MIPS32-NEXT: $a1 = COPY [[SUB6]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%4:_(s32) = COPY $a2
@@ -306,10 +306,10 @@ body: |
%1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
%14:_(s128) = G_SUB %1, %0
%15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
- $v0 = COPY %15(s32)
- $v1 = COPY %16(s32)
+ $r2 = COPY %15(s32)
+ $r3 = COPY %16(s32)
$a0 = COPY %17(s32)
$a1 = COPY %18(s32)
- RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir
index 8fe300b60f7a5..3f539775312d2 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir
@@ -16,13 +16,13 @@ body: |
; MIPS32-LABEL: name: trunc
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: $v0 = COPY [[COPY]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY]](s32)
+ ; MIPS32: RetRA implicit $r2
%1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s32) = G_TRUNC %0(s64)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
index e22a44524e222..d298395ac4368 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
@@ -13,12 +13,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
- ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s32) = G_LOAD %0(p0) :: (load (s8))
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -34,12 +34,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
- ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s32) = G_LOAD %0(p0) :: (load (s16))
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
index e1c0fa24cf9af..721b10a14e347 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
@@ -84,7 +84,7 @@ body: |
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY4]](p0)
; MIPS32: $a1 = COPY [[LOAD3]](p0)
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:_(p0) = COPY $a0
@@ -116,7 +116,7 @@ body: |
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %17(p0)
$a1 = COPY %15(p0)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
+ JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
index b2d6acbc7267f..cfbdb58707ab4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
@@ -27,12 +27,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -48,12 +48,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -69,13 +69,13 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
%3:_(s32) = G_ANYEXT %2(s16)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -91,12 +91,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -113,15 +113,15 @@ body: |
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%0:_(p0) = COPY $a0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32) from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
- $v0 = COPY %3(s32)
- $v1 = COPY %4(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %3(s32)
+ $r3 = COPY %4(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -137,12 +137,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -158,12 +158,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -179,13 +179,13 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
%3:_(s32) = G_ANYEXT %2(s16)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -201,12 +201,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -224,14 +224,14 @@ body: |
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%0:_(p0) = COPY $a0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32) from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
- $v0 = COPY %3(s32)
- $v1 = COPY %4(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %3(s32)
+ $r3 = COPY %4(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
index 125205d341800..b067cfd72152b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
@@ -18,15 +18,15 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32: $v0 = COPY [[COPY]](s32)
- ; MIPS32: $v1 = COPY [[C]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[COPY]](s32)
+ ; MIPS32: $r3 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%0:_(s32) = COPY $a0
%1:_(s64) = G_ZEXT %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %3(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %3(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -42,14 +42,14 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
- ; MIPS32: $v0 = COPY [[COPY]](s32)
- ; MIPS32: $v1 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[COPY]](s32)
+ ; MIPS32: $r3 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%0:_(s32) = COPY $a0
%1:_(s64) = G_SEXT %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %3(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %3(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/big-endian-memory.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/big-endian-memory.ll
index ffc95be49a148..c121531ca8bdc 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/big-endian-memory.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/big-endian-memory.ll
@@ -81,7 +81,7 @@ define i32 @load_i24(ptr %p) {
define i64 @load_i40(ptr %p) {
; BE-LABEL: load_i40:
; BE: # %bb.0:
-; BE-NEXT: # implicit-def: $v0
+; BE-NEXT: # implicit-def: $r2
; BE-NEXT: lwl $2, 1($4)
; BE-NEXT: lwr $2, 4($4)
; BE-NEXT: lbu $1, 0($4)
@@ -93,7 +93,7 @@ define i64 @load_i40(ptr %p) {
;
; LE-LABEL: load_i40:
; LE: # %bb.0:
-; LE-NEXT: # implicit-def: $v0
+; LE-NEXT: # implicit-def: $r2
; LE-NEXT: lwl $2, 3($4)
; LE-NEXT: lwr $2, 0($4)
; LE-NEXT: lbu $1, 4($4)
@@ -128,10 +128,10 @@ define i64 @load_i40(ptr %p) {
define i64 @load_i64(ptr %p) {
; BE-LABEL: load_i64:
; BE: # %bb.0:
-; BE-NEXT: # implicit-def: $v1
+; BE-NEXT: # implicit-def: $r3
; BE-NEXT: lwl $3, 4($4)
; BE-NEXT: lwr $3, 7($4)
-; BE-NEXT: # implicit-def: $v0
+; BE-NEXT: # implicit-def: $r2
; BE-NEXT: lwl $2, 0($4)
; BE-NEXT: lwr $2, 3($4)
; BE-NEXT: jr $ra
@@ -139,10 +139,10 @@ define i64 @load_i64(ptr %p) {
;
; LE-LABEL: load_i64:
; LE: # %bb.0:
-; LE-NEXT: # implicit-def: $v0
+; LE-NEXT: # implicit-def: $r2
; LE-NEXT: lwl $2, 3($4)
; LE-NEXT: lwr $2, 0($4)
-; LE-NEXT: # implicit-def: $v1
+; LE-NEXT: # implicit-def: $r3
; LE-NEXT: lwl $3, 7($4)
; LE-NEXT: lwr $3, 4($4)
; LE-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
index 037964d0f7699..c1418284b570b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
@@ -102,7 +102,7 @@ define i32 @load_i32_align1() {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i32_align1)
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align1)
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: jr $ra
@@ -124,7 +124,7 @@ define i32 @load_i32_align2() {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i32_align2)
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align2)
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
index 6d7a8306c3992..60b7bb16131e1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
@@ -127,7 +127,7 @@ entry:
define i64 @load5align1(ptr %S) {
; MIPS32-LABEL: load5align1:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: lbu $1, 4($4)
@@ -154,7 +154,7 @@ entry:
define i64 @load5align2(ptr %S) {
; MIPS32-LABEL: load5align2:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: lbu $1, 4($4)
@@ -231,7 +231,7 @@ entry:
define i64 @load6align1(ptr %S) {
; MIPS32-LABEL: load6align1:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: # implicit-def: $at
@@ -260,7 +260,7 @@ entry:
define i64 @load6align2(ptr %S) {
; MIPS32-LABEL: load6align2:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: lhu $1, 4($4)
@@ -337,7 +337,7 @@ entry:
define i64 @load7align1(ptr %S) {
; MIPS32-LABEL: load7align1:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: # implicit-def: $at
@@ -370,7 +370,7 @@ entry:
define i64 @load7align2(ptr %S) {
; MIPS32-LABEL: load7align2:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: # implicit-def: $at
@@ -466,7 +466,7 @@ define double @load_double_align1() {
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($3)
; MIPS32-NEXT: lwr $1, 0($3)
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 7($3)
; MIPS32-NEXT: lwr $2, 4($3)
; MIPS32-NEXT: mtc1 $1, $f0
@@ -493,7 +493,7 @@ define double @load_double_align2() {
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($3)
; MIPS32-NEXT: lwr $1, 0($3)
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 7($3)
; MIPS32-NEXT: lwr $2, 4($3)
; MIPS32-NEXT: mtc1 $1, $f0
@@ -560,10 +560,10 @@ define i64 @load_i64_align1() {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i64_align1)
; MIPS32-NEXT: addiu $1, $1, %lo(i64_align1)
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
-; MIPS32-NEXT: # implicit-def: $v1
+; MIPS32-NEXT: # implicit-def: $r3
; MIPS32-NEXT: lwl $3, 7($1)
; MIPS32-NEXT: lwr $3, 4($1)
; MIPS32-NEXT: jr $ra
@@ -586,10 +586,10 @@ define i64 @load_i64_align2() {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i64_align2)
; MIPS32-NEXT: addiu $1, $1, %lo(i64_align2)
-; MIPS32-NEXT: # implicit-def: $v0
+; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
-; MIPS32-NEXT: # implicit-def: $v1
+; MIPS32-NEXT: # implicit-def: $r3
; MIPS32-NEXT: lwl $3, 7($1)
; MIPS32-NEXT: lwr $3, 4($1)
; MIPS32-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
index b68179aa0bda9..b5304cf89e873 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
@@ -18,13 +18,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s32) = G_ANYEXT %1(s8)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -39,12 +39,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s16) = G_LOAD %0(p0) :: (load (s16) from %ir.px)
%2:_(s32) = G_ANYEXT %1(s16)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir
index ace678c240032..570ce07ee20f6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir
@@ -13,8 +13,8 @@
# MIPS32: Try combining %0:_(s32) = COPY $a0
# MIPS32: Try combining %1:_(s32) = COPY $a1
# MIPS32: Try combining %2:_(s32) = G_ADD %1:_, %0:_
-# MIPS32: Try combining $v0 = COPY %2:_(s32)
-# MIPS32: Try combining RetRA implicit $v0
+# MIPS32: Try combining $r2 = COPY %2:_(s32)
+# MIPS32: Try combining RetRA implicit $r2
name: f
alignment: 4
tracksRegLiveness: true
@@ -27,12 +27,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[ADD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_ADD %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
index cea581c614844..f9cb66b46aacf 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
@@ -26,13 +26,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s32) = G_ZEXT %1(s8)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -47,13 +47,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s16) = G_LOAD %0(p0) :: (load (s16) from %ir.px)
%2:_(s32) = G_ZEXT %1(s16)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -69,14 +69,14 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s16) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXTLOAD]](s16)
- ; MIPS32: $v0 = COPY [[ANYEXT]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ANYEXT]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s16) = G_ZEXT %1(s8)
%3:_(s32) = G_ANYEXT %2(s16)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -91,14 +91,14 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s16) = G_ZEXT %1(s8)
%3:_(s32) = G_ZEXT %2(s16)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -114,16 +114,16 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXTLOAD]](s64)
- ; MIPS32: $v0 = COPY [[UV]](s32)
- ; MIPS32: $v1 = COPY [[UV1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[UV]](s32)
+ ; MIPS32: $r3 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
%2:_(s64) = G_ZEXT %1(s32)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
- $v0 = COPY %3(s32)
- $v1 = COPY %4(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %3(s32)
+ $r3 = COPY %4(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -138,13 +138,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s32) = G_SEXT %1(s8)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -159,13 +159,13 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s16) = G_LOAD %0(p0) :: (load (s16) from %ir.px)
%2:_(s32) = G_SEXT %1(s16)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -181,14 +181,14 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)
- ; MIPS32: $v0 = COPY [[ANYEXT]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ANYEXT]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s16) = G_SEXT %1(s8)
%3:_(s32) = G_ANYEXT %2(s16)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -203,14 +203,14 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s16) = G_SEXT %1(s8)
%3:_(s32) = G_SEXT %2(s16)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -226,15 +226,15 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXTLOAD]](s64)
- ; MIPS32: $v0 = COPY [[UV]](s32)
- ; MIPS32: $v1 = COPY [[UV1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[UV]](s32)
+ ; MIPS32: $r3 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
%2:_(s64) = G_SEXT %1(s32)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
- $v0 = COPY %3(s32)
- $v1 = COPY %4(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %3(s32)
+ $r3 = COPY %4(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
index 0160440a47181..b097d791ae809 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
@@ -19,12 +19,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[ADD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_ADD %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
index 78145c8eff966..f4fd7e8c9a4b4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
@@ -28,13 +28,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[AND]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_AND %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -51,13 +51,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[OR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[OR]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_OR %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -74,13 +74,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[XOR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[XOR]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_XOR %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -97,13 +97,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[C]]
- ; MIPS32: $v0 = COPY [[SHL]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SHL]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_SHL %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -120,13 +120,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[C]]
- ; MIPS32: $v0 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_ASHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -143,13 +143,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[C]]
- ; MIPS32: $v0 = COPY [[LSHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LSHR]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_LSHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -166,13 +166,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[SHL]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SHL]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_SHL %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -189,13 +189,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_ASHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -212,12 +212,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[LSHR]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LSHR]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_LSHR %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
index 6c9a2410a0e4a..d36b4813e31ef 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
@@ -37,8 +37,8 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.end:
- ; MIPS32: $v0 = COPY [[COPY]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.2.block:
; MIPS32: successors: %bb.1(0x80000000)
; MIPS32: G_BR %bb.1
@@ -49,8 +49,8 @@ body: |
G_BR %bb.3
bb.2.end:
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
bb.3.block:
G_BR %bb.2
@@ -75,11 +75,11 @@ body: |
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.if.then:
- ; MIPS32: $v0 = COPY [[COPY1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY1]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.2.if.else:
- ; MIPS32: $v0 = COPY [[COPY2]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY2]](s32)
+ ; MIPS32: RetRA implicit $r2
bb.1 (%ir-block.0):
liveins: $a0, $a1, $a2
@@ -93,11 +93,11 @@ body: |
G_BR %bb.3
bb.2.if.then:
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
bb.3.if.else:
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
index d42da94c798ac..2226dc0312f65 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
@@ -29,11 +29,11 @@ body: |
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: G_BRINDIRECT [[COPY]](p0)
; MIPS32: bb.1.L1:
- ; MIPS32: $v0 = COPY [[C1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.2.L2:
- ; MIPS32: $v0 = COPY [[C]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $r2
bb.1.entry:
successors: %bb.2, %bb.3
liveins: $a0
@@ -44,11 +44,11 @@ body: |
G_BRINDIRECT %0(p0)
bb.2.L1:
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
bb.3.L2:
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
index 902537a4c4534..3d6699277afa5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
@@ -18,11 +18,11 @@ body: |
; MIPS32R2: liveins: $a0
; MIPS32R2: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32R2: [[BSWAP:%[0-9]+]]:gprb(s32) = G_BSWAP [[COPY]]
- ; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
- ; MIPS32R2: RetRA implicit $v0
+ ; MIPS32R2: $r2 = COPY [[BSWAP]](s32)
+ ; MIPS32R2: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_BSWAP %0
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
index 6a9853c6bc6fb..a25bc2fe327b3 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
@@ -13,11 +13,11 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[CTLZ:%[0-9]+]]:gprb(s32) = G_CTLZ [[COPY]](s32)
- ; MIPS32: $v0 = COPY [[CTLZ]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[CTLZ]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = G_CTLZ %0(s32)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir
index 96192b7e55a78..729fac9d637cb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir
@@ -22,22 +22,22 @@ body: |
; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
- ; FP32: $v0 = COPY [[COPY2]](s32)
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[COPY2]](s32)
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: oeq_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
- ; FP64: $v0 = COPY [[COPY2]](s32)
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[COPY2]](s32)
+ ; FP64: RetRA implicit $r2
%0:_(s32) = COPY $f12
%1:_(s32) = COPY $f14
%4:_(s32) = G_FCMP floatpred(oeq), %0(s32), %1
%3:_(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -55,21 +55,21 @@ body: |
; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
- ; FP32: $v0 = COPY [[COPY2]](s32)
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[COPY2]](s32)
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: oeq_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
- ; FP64: $v0 = COPY [[COPY2]](s32)
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[COPY2]](s32)
+ ; FP64: RetRA implicit $r2
%0:_(s64) = COPY $d6
%1:_(s64) = COPY $d7
%4:_(s32) = G_FCMP floatpred(oeq), %0(s64), %1
%3:_(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
index dbd9b315c201b..af862720be6da 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
@@ -19,12 +19,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load monotonic (s32) from %ir.ptr)
; MIPS32: G_FENCE 4, 1
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load monotonic (s32) from %ir.ptr)
G_FENCE 4, 1
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir
index e5c6dfd3b26bb..a175a8d0e04cd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir
@@ -20,18 +20,18 @@ body: |
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32: $v0 = COPY [[FPTOSI]](s32)
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[FPTOSI]](s32)
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: f32toi32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64: $v0 = COPY [[FPTOSI]](s32)
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[FPTOSI]](s32)
+ ; FP64: RetRA implicit $r2
%0:_(s32) = COPY $f12
%1:_(s32) = G_FPTOSI %0(s32)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -47,17 +47,17 @@ body: |
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32: $v0 = COPY [[FPTOSI]](s32)
- ; FP32: RetRA implicit $v0
+ ; FP32: $r2 = COPY [[FPTOSI]](s32)
+ ; FP32: RetRA implicit $r2
; FP64-LABEL: name: f64toi32
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64: $v0 = COPY [[FPTOSI]](s32)
- ; FP64: RetRA implicit $v0
+ ; FP64: $r2 = COPY [[FPTOSI]](s32)
+ ; FP64: RetRA implicit $r2
%0:_(s64) = COPY $d6
%1:_(s32) = G_FPTOSI %0(s64)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
index c991b2fc07901..53f09fb3f08ff 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
@@ -23,11 +23,11 @@ body: |
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY]](p0)
; MIPS32: $a1 = COPY [[C]](s32)
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $v0
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[C1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $r2
%2:_(p0) = G_GLOBAL_VALUE @.str
%1:_(p0) = COPY %2(p0)
%3:_(s32) = G_CONSTANT i32 1234567890
@@ -35,10 +35,10 @@ body: |
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %1(p0)
$a1 = COPY %3(s32)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
- %0:_(s32) = COPY $v0
+ JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ %0:_(s32) = COPY $r2
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
index 9cec9949f7f1e..77b8d044a4f5d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
@@ -13,11 +13,11 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $t9, $v0
+ liveins: $a0, $a1, $t9, $r2
; MIPS32-LABEL: name: call_global
- ; MIPS32: liveins: $a0, $a1, $t9, $v0
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32: liveins: $a0, $a1, $t9, $r2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
@@ -25,12 +25,12 @@ body: |
; MIPS32: $a0 = COPY [[COPY]](s32)
; MIPS32: $a1 = COPY [[COPY1]](s32)
; MIPS32: $gp = COPY [[ADDu]]
- ; MIPS32: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $v0
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $v0
+ ; MIPS32: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY2]](s32)
- ; MIPS32: RetRA implicit $v0
- %4:gpr32 = ADDu $v0, $t9
+ ; MIPS32: $r2 = COPY [[COPY2]](s32)
+ ; MIPS32: RetRA implicit $r2
+ %4:gpr32 = ADDu $r2, $t9
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
@@ -38,11 +38,11 @@ body: |
$a0 = COPY %0(s32)
$a1 = COPY %1(s32)
$gp = COPY %4
- JALRPseudo %3(p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $v0
- %2:_(s32) = COPY $v0
+ JALRPseudo %3(p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ %2:_(s32) = COPY $r2
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
index a40d89eaf72bb..96408a12c636e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
@@ -21,14 +21,14 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
- ; MIPS32: $v0 = COPY [[COPY2]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY2]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%4:_(s32) = G_ICMP intpred(ne), %0(s32), %1
%3:_(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
---
@@ -46,13 +46,13 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
- ; MIPS32: $v0 = COPY [[COPY2]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY2]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%4:_(s32) = G_ICMP intpred(eq), %0(p0), %1
%3:_(s32) = COPY %4(s32)
- $v0 = COPY %3(s32)
- RetRA implicit $v0
+ $r2 = COPY %3(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
index a289c2e8f4d76..2a1d94fa08baf 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
@@ -19,12 +19,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[INTTOPTR:%[0-9]+]]:gprb(p0) = G_INTTOPTR [[COPY]](s32)
- ; MIPS32: $v0 = COPY [[INTTOPTR]](p0)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[INTTOPTR]](p0)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(p0) = G_INTTOPTR %0(s32)
- $v0 = COPY %1(p0)
- RetRA implicit $v0
+ $r2 = COPY %1(p0)
+ RetRA implicit $r2
...
---
@@ -40,11 +40,11 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[PTRTOINT:%[0-9]+]]:gprb(s32) = G_PTRTOINT [[COPY]](p0)
- ; MIPS32: $v0 = COPY [[PTRTOINT]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PTRTOINT]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s32) = G_PTRTOINT %0(p0)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
index b1e63839aba2f..7972126fefb4d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
@@ -93,17 +93,17 @@ body: |
; MIPS32: [[JUMP_TABLE:%[0-9]+]]:gprb(p0) = G_JUMP_TABLE %jump-table.0
; MIPS32: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[COPY1]](s32)
; MIPS32: bb.2.sw.bb:
- ; MIPS32: $v0 = COPY [[C4]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C4]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.3.sw.bb1:
- ; MIPS32: $v0 = COPY [[C3]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C3]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.4.sw.bb2:
- ; MIPS32: $v0 = COPY [[C2]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C2]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.5.sw.bb3:
- ; MIPS32: $v0 = COPY [[C1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.6.sw.default:
; MIPS32: successors: %bb.7(0x80000000)
; MIPS32: bb.7.sw.epilog:
@@ -122,20 +122,20 @@ body: |
; MIPS32: [[JUMP_TABLE1:%[0-9]+]]:gprb(p0) = G_JUMP_TABLE %jump-table.1
; MIPS32: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY4]](s32)
; MIPS32: bb.9.sw.bb4:
- ; MIPS32: $v0 = COPY [[C4]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C4]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.10.sw.bb5:
- ; MIPS32: $v0 = COPY [[C3]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C3]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.11.sw.bb6:
- ; MIPS32: $v0 = COPY [[C2]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C2]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.12.sw.bb7:
- ; MIPS32: $v0 = COPY [[C1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32: bb.13.sw.default8:
- ; MIPS32: $v0 = COPY [[C5]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[C5]](s32)
+ ; MIPS32: RetRA implicit $r2
bb.1.entry:
liveins: $a0
@@ -162,20 +162,20 @@ body: |
G_BRJT %7(p0), %jump-table.0, %3(s32)
bb.2.sw.bb:
- $v0 = COPY %11(s32)
- RetRA implicit $v0
+ $r2 = COPY %11(s32)
+ RetRA implicit $r2
bb.3.sw.bb1:
- $v0 = COPY %10(s32)
- RetRA implicit $v0
+ $r2 = COPY %10(s32)
+ RetRA implicit $r2
bb.4.sw.bb2:
- $v0 = COPY %9(s32)
- RetRA implicit $v0
+ $r2 = COPY %9(s32)
+ RetRA implicit $r2
bb.5.sw.bb3:
- $v0 = COPY %8(s32)
- RetRA implicit $v0
+ $r2 = COPY %8(s32)
+ RetRA implicit $r2
bb.6.sw.default:
@@ -197,23 +197,23 @@ body: |
G_BRJT %17(p0), %jump-table.1, %14(s32)
bb.8.sw.bb4:
- $v0 = COPY %11(s32)
- RetRA implicit $v0
+ $r2 = COPY %11(s32)
+ RetRA implicit $r2
bb.9.sw.bb5:
- $v0 = COPY %10(s32)
- RetRA implicit $v0
+ $r2 = COPY %10(s32)
+ RetRA implicit $r2
bb.10.sw.bb6:
- $v0 = COPY %9(s32)
- RetRA implicit $v0
+ $r2 = COPY %9(s32)
+ RetRA implicit $r2
bb.11.sw.bb7:
- $v0 = COPY %8(s32)
- RetRA implicit $v0
+ $r2 = COPY %8(s32)
+ RetRA implicit $r2
bb.12.sw.default8:
- $v0 = COPY %18(s32)
- RetRA implicit $v0
+ $r2 = COPY %18(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
index 25a4d2a107acc..3dd38467e81df 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
@@ -24,12 +24,12 @@ body: |
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.ptr)
- ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -49,15 +49,15 @@ body: |
; MIPS32-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32-NEXT: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from %ir.ptr + 4, basealign 8)
- ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[LOAD1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: $r3 = COPY [[LOAD1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
%0:_(p0) = COPY $a0
%1:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %3(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %3(s32)
+ RetRA implicit $r2, implicit $r3
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
index 5da84fc790d72..68280e5ea93e3 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
@@ -82,16 +82,16 @@ body: |
; MIPS32-LABEL: name: load_i32_align8
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @i32_align8, align 8)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
; MIPS32R6-LABEL: name: load_i32_align8
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32R6: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @i32_align8, align 8)
- ; MIPS32R6: $v0 = COPY [[LOAD]](s32)
- ; MIPS32R6: RetRA implicit $v0
+ ; MIPS32R6: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32R6: RetRA implicit $r2
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align8, align 8)
- $v0 = COPY %0(s32)
- RetRA implicit $v0
+ $r2 = COPY %0(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
index 6decdd9cb32e3..637e4998a2542 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
@@ -20,13 +20,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[MUL]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[MUL]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_MUL %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
index 5b7ba0922c72e..9c442b064b4ae 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
@@ -124,8 +124,8 @@ body: |
; MIPS32: successors: %bb.3(0x80000000)
; MIPS32: bb.3.cond.end:
; MIPS32: [[PHI:%[0-9]+]]:gprb(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
- ; MIPS32: $v0 = COPY [[PHI]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[PHI]](s32)
+ ; MIPS32: RetRA implicit $r2
bb.1.entry:
liveins: $a0, $a1, $a2
@@ -145,8 +145,8 @@ body: |
bb.4.cond.end:
%4:_(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -182,9 +182,9 @@ body: |
; MIPS32: bb.3.cond.end:
; MIPS32: [[PHI:%[0-9]+]]:gprb(s32) = G_PHI [[COPY1]](s32), %bb.1, [[LOAD]](s32), %bb.2
; MIPS32: [[PHI1:%[0-9]+]]:gprb(s32) = G_PHI [[COPY2]](s32), %bb.1, [[LOAD1]](s32), %bb.2
- ; MIPS32: $v0 = COPY [[PHI]](s32)
- ; MIPS32: $v1 = COPY [[PHI1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[PHI]](s32)
+ ; MIPS32: $r3 = COPY [[PHI1]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
bb.1.entry:
liveins: $a0, $a2, $a3
@@ -211,9 +211,9 @@ body: |
bb.4.cond.end:
%10:_(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3
%11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %10(s64)
- $v0 = COPY %11(s32)
- $v1 = COPY %12(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %11(s32)
+ $r3 = COPY %12(s32)
+ RetRA implicit $r2, implicit $r3
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
index 1080d4364399a..3111779e28c2a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
@@ -20,12 +20,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.p)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.p)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -48,8 +48,8 @@ body: |
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.p)
- ; MIPS32: $v0 = COPY [[LOAD1]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD1]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
@@ -57,8 +57,8 @@ body: |
%5:_(p0) = G_FRAME_INDEX %fixed-stack.0
%4:_(p0) = G_LOAD %5(p0) :: (load (p0) from %fixed-stack.0, align 8)
%6:_(s32) = G_LOAD %4(p0) :: (load (s32) from %ir.p)
- $v0 = COPY %6(s32)
- RetRA implicit $v0
+ $r2 = COPY %6(s32)
+ RetRA implicit $r2
...
---
@@ -73,10 +73,10 @@ body: |
; MIPS32-LABEL: name: ret_ptr
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32: $v0 = COPY [[COPY]](p0)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY]](p0)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
- $v0 = COPY %0(p0)
- RetRA implicit $v0
+ $r2 = COPY %0(p0)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
index 238a2843627ae..5171c8d5f94af 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
@@ -22,13 +22,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[SDIV:%[0-9]+]]:gprb(s32) = G_SDIV [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[SDIV]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SDIV]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_SDIV %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -45,13 +45,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[SREM:%[0-9]+]]:gprb(s32) = G_SREM [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[SREM]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SREM]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_SREM %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -68,13 +68,13 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[UDIV:%[0-9]+]]:gprb(s32) = G_UDIV [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[UDIV]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[UDIV]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_UDIV %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -91,12 +91,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[UREM:%[0-9]+]]:gprb(s32) = G_UREM [[COPY1]], [[COPY]]
- ; MIPS32: $v0 = COPY [[UREM]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[UREM]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_UREM %1, %0
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
index 1bdebc897ae86..477910bd7dd5b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
@@ -29,8 +29,8 @@ body: |
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32: $v0 = COPY [[SELECT]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $r2
%3:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
@@ -38,8 +38,8 @@ body: |
%7:_(s32) = COPY %3(s32)
%5:_(s32) = G_AND %7, %6
%4:_(s32) = G_SELECT %5(s32), %1, %2
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -60,8 +60,8 @@ body: |
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32: $v0 = COPY [[SELECT]](p0)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SELECT]](p0)
+ ; MIPS32: RetRA implicit $r2
%3:_(s32) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
@@ -69,8 +69,8 @@ body: |
%7:_(s32) = COPY %3(s32)
%5:_(s32) = G_AND %7, %6
%4:_(p0) = G_SELECT %5(s32), %1, %2
- $v0 = COPY %4(p0)
- RetRA implicit $v0
+ $r2 = COPY %4(p0)
+ RetRA implicit $r2
...
---
@@ -99,9 +99,9 @@ body: |
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[LOAD]]
; MIPS32: [[SELECT1:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY2]], [[LOAD1]]
- ; MIPS32: $v0 = COPY [[SELECT]](s32)
- ; MIPS32: $v1 = COPY [[SELECT1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32: $r3 = COPY [[SELECT1]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%3:_(s32) = COPY $a0
%4:_(s32) = COPY $a2
%5:_(s32) = COPY $a3
@@ -116,9 +116,9 @@ body: |
%13:_(s32) = G_AND %15, %14
%10:_(s64) = G_SELECT %13(s32), %1, %2
%11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %10(s64)
- $v0 = COPY %11(s32)
- $v1 = COPY %12(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %11(s32)
+ $r3 = COPY %12(s32)
+ RetRA implicit $r2, implicit $r3
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
index 52b21a274d7bf..d82ada7ccfc65 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
@@ -34,11 +34,11 @@ body: |
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 16
; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store (s32) into stack + 16)
- ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- ; MIPS32: [[COPY5:%[0-9]+]]:gprb(s32) = COPY $v0
+ ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32: [[COPY5:%[0-9]+]]:gprb(s32) = COPY $r2
; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $v0 = COPY [[COPY5]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[COPY5]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
@@ -54,10 +54,10 @@ body: |
%8:_(s32) = G_CONSTANT i32 16
%9:_(p0) = G_PTR_ADD %7, %8(s32)
G_STORE %4(s32), %9(p0) :: (store (s32) into stack + 16, align 4)
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
- %6:_(s32) = COPY $v0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ %6:_(s32) = COPY $r2
ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
- $v0 = COPY %6(s32)
- RetRA implicit $v0
+ $r2 = COPY %6(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
index d3350cffc385f..a21b33cd4a99f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
@@ -19,12 +19,12 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[COPY1]]
- ; MIPS32: $v0 = COPY [[SUB]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SUB]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_SUB %0, %1
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
index a73026f9af44b..87855bc6a1977 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
@@ -25,12 +25,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.i32_ptr)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.i32_ptr)
- $v0 = COPY %1(s32)
- RetRA implicit $v0
+ $r2 = COPY %1(s32)
+ RetRA implicit $r2
...
---
@@ -70,15 +70,15 @@ body: |
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.i32_ptr1)
; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.i32_ptr2)
; MIPS32: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[LOAD1]], [[LOAD]]
- ; MIPS32: $v0 = COPY [[ADD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.i32_ptr1)
%3:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.i32_ptr2)
%4:_(s32) = G_ADD %3, %2
- $v0 = COPY %4(s32)
- RetRA implicit $v0
+ $r2 = COPY %4(s32)
+ RetRA implicit $r2
...
---
@@ -127,8 +127,8 @@ body: |
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[LOAD]], [[COPY]]
- ; MIPS32: $v0 = COPY [[SELECT]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%2:_(p0) = COPY $a2
@@ -137,8 +137,8 @@ body: |
%8:_(s32) = COPY %3(s32)
%6:_(s32) = G_AND %8, %7
%5:_(s32) = G_SELECT %6(s32), %4, %0
- $v0 = COPY %5(s32)
- RetRA implicit $v0
+ $r2 = COPY %5(s32)
+ RetRA implicit $r2
...
---
@@ -195,8 +195,8 @@ body: |
; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[COPY3]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[LOAD]], [[ADD]]
- ; MIPS32: $v0 = COPY [[SELECT]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(p0) = COPY $a2
@@ -207,8 +207,8 @@ body: |
%10:_(s32) = COPY %4(s32)
%8:_(s32) = G_AND %10, %9
%7:_(s32) = G_SELECT %8(s32), %5, %6
- $v0 = COPY %7(s32)
- RetRA implicit $v0
+ $r2 = COPY %7(s32)
+ RetRA implicit $r2
...
---
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
index 9cf86f01644ce..6d739b9125e99 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
@@ -85,7 +85,7 @@ body: |
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY4]](p0)
; MIPS32: $a1 = COPY [[LOAD2]](p0)
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:_(p0) = COPY $a0
@@ -118,7 +118,7 @@ body: |
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %17(p0)
$a1 = COPY %15(p0)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
+ JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
index 0078fca55d88c..59cc1bb0fca59 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
@@ -23,12 +23,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -44,12 +44,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -66,17 +66,17 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: $v1 = COPY [[C]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: $r3 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%0:_(p0) = COPY $a0
%5:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
%6:_(s32) = G_CONSTANT i32 0
%2:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
- $v0 = COPY %3(s32)
- $v1 = COPY %4(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %3(s32)
+ $r3 = COPY %4(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -92,12 +92,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -113,12 +113,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32: $r2 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $r2
%0:_(p0) = COPY $a0
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
- $v0 = COPY %2(s32)
- RetRA implicit $v0
+ $r2 = COPY %2(s32)
+ RetRA implicit $r2
...
---
@@ -138,9 +138,9 @@ body: |
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: $v1 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[LOAD]](s32)
+ ; MIPS32: $r3 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%0:_(p0) = COPY $a0
%5:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
%9:_(s32) = G_CONSTANT i32 31
@@ -149,9 +149,9 @@ body: |
%7:_(s32) = G_ASHR %5, %8(s32)
%2:_(s64) = G_MERGE_VALUES %5(s32), %7(s32)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
- $v0 = COPY %3(s32)
- $v1 = COPY %4(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %3(s32)
+ $r3 = COPY %4(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
index 6074a9d6fda9b..efc2caf14921f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
@@ -19,16 +19,16 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
- ; MIPS32: $v0 = COPY [[COPY]](s32)
- ; MIPS32: $v1 = COPY [[C]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[COPY]](s32)
+ ; MIPS32: $r3 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%0:_(s32) = COPY $a0
%4:_(s32) = G_CONSTANT i32 0
%1:_(s64) = G_MERGE_VALUES %0(s32), %4(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %3(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %3(s32)
+ RetRA implicit $r2, implicit $r3
...
---
@@ -47,9 +47,9 @@ body: |
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
- ; MIPS32: $v0 = COPY [[COPY]](s32)
- ; MIPS32: $v1 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32: $r2 = COPY [[COPY]](s32)
+ ; MIPS32: $r3 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $r2, implicit $r3
%0:_(s32) = COPY $a0
%7:_(s32) = G_CONSTANT i32 31
%8:_(s32) = G_CONSTANT i32 0
@@ -57,8 +57,8 @@ body: |
%5:_(s32) = G_ASHR %0, %6(s32)
%1:_(s64) = G_MERGE_VALUES %0(s32), %5(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
- $v0 = COPY %2(s32)
- $v1 = COPY %3(s32)
- RetRA implicit $v0, implicit $v1
+ $r2 = COPY %2(s32)
+ $r3 = COPY %3(s32)
+ RetRA implicit $r2, implicit $r3
...
diff --git a/llvm/test/CodeGen/Mips/avoid-zero-copy.mir b/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
index e3990bdf9bc3f..73e2b66cfddfc 100644
--- a/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
+++ b/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
@@ -29,15 +29,15 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: $a0_64 = COPY $zero_64
- ; CHECK-NEXT: JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ ; CHECK-NEXT: JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: $a0_64 = COPY $zero_64
- ; CHECK-NEXT: PseudoReturn64 undef $ra_64, implicit $v0_64, implicit killed $a0_64
+ ; CHECK-NEXT: PseudoReturn64 undef $ra_64, implicit $r2_64, implicit killed $a0_64
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
renamable $s0_64 = COPY $zero_64
$a0_64 = COPY renamable $s0_64
- JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
$a0_64 = COPY killed renamable $s0_64
- PseudoReturn64 undef $ra_64, implicit $v0_64, implicit killed $a0_64
+ PseudoReturn64 undef $ra_64, implicit $r2_64, implicit killed $a0_64
...
diff --git a/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll b/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
index 5cf418e4d9bc2..46446eed4f6ca 100644
--- a/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
+++ b/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
@@ -328,7 +328,7 @@ define void @call_v3i32(ptr %p) nounwind {
; MIPS64-NEXT: dsrl $4, $5, 32
; MIPS64-NEXT: jal ret_v3i32
; MIPS64-NEXT: nop
-; MIPS64-NEXT: # kill: def $v0 killed $v0 def $v0_64
+; MIPS64-NEXT: # kill: def $r2 killed $r2 def $r2_64
; MIPS64-NEXT: sw $4, 8($16)
; MIPS64-NEXT: dsll $1, $2, 32
; MIPS64-NEXT: dsll $2, $3, 32
@@ -1277,8 +1277,8 @@ define void @call_v4i18(ptr %p) nounwind {
; MIPS64-NEXT: dsll $19, $1, 56
; MIPS64-NEXT: jal ret_v4i18
; MIPS64-NEXT: ori $17, $17, 65280
-; MIPS64-NEXT: # kill: def $v0 killed $v0 def $v0_64
-; MIPS64-NEXT: # kill: def $v1 killed $v1 def $v1_64
+; MIPS64-NEXT: # kill: def $r2 killed $r2 def $r2_64
+; MIPS64-NEXT: # kill: def $r3 killed $r3 def $r3_64
; MIPS64-NEXT: # kill: def $a0 killed $a0 def $a0_64
; MIPS64-NEXT: # kill: def $a1 killed $a1 def $a1_64
; MIPS64-NEXT: dsll $1, $2, 54
diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
index dfaad3a01bb75..a502e0b4f5b59 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
+++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
@@ -108,7 +108,7 @@ body: |
CFI_INSTRUCTION offset $gp_64, -24
CFI_INSTRUCTION def_cfa_register $fp_64
$at_64 = LUi64 @f
- $v0_64 = DADDu killed $at_64, $t9_64
+ $r2_64 = DADDu killed $at_64, $t9_64
SW $a0, $sp_64, 0 :: (store (s32) into %ir.a.addr)
BGTZC $a0, %bb.5.if.else, implicit-def $at
@@ -139,16 +139,16 @@ body: |
bb.5.if.else:
successors: %bb.6.return(0x80000000)
- liveins: $v0_64
+ liveins: $r2_64
- $gp_64 = DADDiu killed $v0_64, @f
+ $gp_64 = DADDiu killed $r2_64, @f
$a0_64 = LW64 $sp_64, 0 :: (dereferenceable load (s32) from %ir.a.addr)
$t9_64 = LD $gp_64, @g :: (load (s64) from call-entry @g)
- JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
- SW killed $v0, $sp_64, 4 :: (store (s32) into %ir.retval)
+ JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
+ SW killed $r2, $sp_64, 4 :: (store (s32) into %ir.retval)
bb.6.return:
- $v0 = LW $sp_64, 4 :: (dereferenceable load (s32) from %ir.retval)
+ $r2 = LW $sp_64, 4 :: (dereferenceable load (s32) from %ir.retval)
$gp_64 = LD $sp_64, 8 :: (load (s64) from %stack.4)
$fp_64 = LD $sp_64, 16 :: (load (s64) from %stack.3)
$ra_64 = LD $sp_64, 24 :: (load (s64) from %stack.2)
diff --git a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
index 41f59f535a4c9..3a2da93e6ecec 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
+++ b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
@@ -68,8 +68,8 @@ body: |
CFI_INSTRUCTION def_cfa_offset 24
SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
CFI_INSTRUCTION offset $ra_64, -4
- JAL @k, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit-def $v0
- BLEZ $v0, %bb.4.if.end, implicit-def $at
+ JAL @k, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit-def $r2
+ BLEZ $r2, %bb.4.if.end, implicit-def $at
bb.1.if.then:
successors: %bb.2.if.then(0x80000000)
diff --git a/llvm/test/CodeGen/Mips/copy-fp64.ll b/llvm/test/CodeGen/Mips/copy-fp64.ll
index 9a136799bb47c..8a6e2460690fb 100644
--- a/llvm/test/CodeGen/Mips/copy-fp64.ll
+++ b/llvm/test/CodeGen/Mips/copy-fp64.ll
@@ -9,8 +9,8 @@ define double @foo(double %self) {
; CHECK-LABEL: name: foo
; CHECK: bb.0.start:
; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $d12_64, $t9, $v0
- ; CHECK: renamable $at = ADDu killed $v0, killed $t9
+ ; CHECK: liveins: $d12_64, $t9, $r2
+ ; CHECK: renamable $at = ADDu killed $r2, killed $t9
; CHECK: renamable $d6_64 = COPY killed $d12_64
; CHECK: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; CHECK: renamable $t9 = LW killed renamable $at, target-flags(mips-got) @bar
diff --git a/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir b/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
index e04a84855ed40..e010aff459bef 100644
--- a/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
+++ b/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
@@ -65,17 +65,17 @@ body: |
; CHECK: successors: %bb.2(0x00000001), %bb.1(0x7fffffff)
; CHECK: renamable $at = SLL renamable $a0, 0, implicit killed $a0_64
; CHECK: renamable $at = ANDi killed renamable $at, 1
- ; CHECK: $v0_64 = DADDiu $zero_64, 1
- ; CHECK: $v0_64 = DADDiu $v0_64, 1
- ; CHECK: BUNDLE implicit-def $v0_64 {
- ; CHECK: $v0_64 = DADDiu $zero_64, 1
- ; CHECK: $v0_64 = DADDiu $v0_64, 1
+ ; CHECK: $r2_64 = DADDiu $zero_64, 1
+ ; CHECK: $r2_64 = DADDiu $r2_64, 1
+ ; CHECK: BUNDLE implicit-def $r2_64 {
+ ; CHECK: $r2_64 = DADDiu $zero_64, 1
+ ; CHECK: $r2_64 = DADDiu $r2_64, 1
; CHECK: }
; CHECK: BNE killed renamable $at, $zero, %bb.2, implicit-def $at {
; CHECK: $zero = SLL $zero, 0
; CHECK: }
; CHECK: bb.1.return:
- ; CHECK: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
+ ; CHECK: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
; CHECK: $zero = SLL $zero, 0
; CHECK: }
; CHECK: bb.2.err:
@@ -87,17 +87,17 @@ body: |
renamable $at = ANDi killed renamable $at, 1
; Check that none of these instructions are hoisted after the BUNDLE to avoid
; incorrect values from being
- $v0_64 = DADDiu $zero_64, 1
- $v0_64 = DADDiu $v0_64, 1
- BUNDLE implicit-def $v0_64 {
- $v0_64 = DADDiu $zero_64, 1
- $v0_64 = DADDiu $v0_64, 1
+ $r2_64 = DADDiu $zero_64, 1
+ $r2_64 = DADDiu $r2_64, 1
+ BUNDLE implicit-def $r2_64 {
+ $r2_64 = DADDiu $zero_64, 1
+ $r2_64 = DADDiu $r2_64, 1
}
BNE killed renamable $at, $zero, %bb.1, implicit-def $at
bb.2.return:
- liveins: $v0_64
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ liveins: $r2_64
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.1.err:
diff --git a/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir b/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
index 3e300371e8115..792026c7c90ea 100644
--- a/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
+++ b/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
@@ -99,7 +99,7 @@ body: |
; CHECK: }
; CHECK: bb.1.if.then:
; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: JAL @func_a, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0_64 {
+ ; CHECK: JAL @func_a, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2_64 {
; CHECK: $zero = SLL $zero, 0
; CHECK: }
; CHECK: J %bb.3, implicit-def dead $at {
@@ -107,12 +107,12 @@ body: |
; CHECK: }
; CHECK: bb.2.if.else:
; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: JAL @func_b, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0_64 {
+ ; CHECK: JAL @func_b, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2_64 {
; CHECK: $a0_64 = DADDiu $zero_64, 0
; CHECK: }
; CHECK: bb.3.return:
; CHECK: $ra_64 = LD $sp_64, 8 :: (load (s64) from %stack.0)
- ; CHECK: PseudoReturn64 undef $ra_64, implicit $v0_64 {
+ ; CHECK: PseudoReturn64 undef $ra_64, implicit $r2_64 {
; CHECK: $sp_64 = DADDiu $sp_64, 16
; CHECK: }
bb.0.entry:
@@ -134,20 +134,20 @@ body: |
successors: %bb.3(0x80000000)
liveins: $a0_64
- JAL @func_a, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0_64
+ JAL @func_a, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2_64
J %bb.3, implicit-def dead $at
bb.2.if.else:
successors: %bb.3(0x80000000)
$a0_64 = DADDiu $zero_64, 0
- JAL @func_b, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0_64
+ JAL @func_b, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2_64
bb.3.return:
- liveins: $v0_64
+ liveins: $r2_64
$ra_64 = LD $sp_64, 8 :: (load (s64) from %stack.0)
$sp_64 = DADDiu $sp_64, 16
- PseudoReturn64 undef $ra_64, implicit $v0_64
+ PseudoReturn64 undef $ra_64, implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/fmuladd-soft-float.ll b/llvm/test/CodeGen/Mips/fmuladd-soft-float.ll
index 409b1a1f818ab..4fa1085274457 100644
--- a/llvm/test/CodeGen/Mips/fmuladd-soft-float.ll
+++ b/llvm/test/CodeGen/Mips/fmuladd-soft-float.ll
@@ -483,7 +483,7 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-64-NEXT: sll $5, $2, 0
; SOFT-FLOAT-64-NEXT: jal __addsf3
; SOFT-FLOAT-64-NEXT: dsrl $19, $1, 32
-; SOFT-FLOAT-64-NEXT: # kill: def $v0 killed $v0 def $v0_64
+; SOFT-FLOAT-64-NEXT: # kill: def $r2 killed $r2 def $r2_64
; SOFT-FLOAT-64-NEXT: dsll $1, $2, 32
; SOFT-FLOAT-64-NEXT: sll $5, $16, 0
; SOFT-FLOAT-64-NEXT: or $19, $19, $1
@@ -501,7 +501,7 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-64-NEXT: dsrl $1, $16, 32
; SOFT-FLOAT-64-NEXT: jal __addsf3
; SOFT-FLOAT-64-NEXT: sll $5, $1, 0
-; SOFT-FLOAT-64-NEXT: # kill: def $v0 killed $v0 def $v0_64
+; SOFT-FLOAT-64-NEXT: # kill: def $r2 killed $r2 def $r2_64
; SOFT-FLOAT-64-NEXT: dsll $1, $2, 32
; SOFT-FLOAT-64-NEXT: or $3, $17, $1
; SOFT-FLOAT-64-NEXT: move $2, $19
@@ -566,7 +566,7 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-64R2-NEXT: sll $5, $1, 0
; SOFT-FLOAT-64R2-NEXT: jal __addsf3
; SOFT-FLOAT-64R2-NEXT: dext $19, $22, 0, 32
-; SOFT-FLOAT-64R2-NEXT: # kill: def $v0 killed $v0 def $v0_64
+; SOFT-FLOAT-64R2-NEXT: # kill: def $r2 killed $r2 def $r2_64
; SOFT-FLOAT-64R2-NEXT: dsll $1, $2, 32
; SOFT-FLOAT-64R2-NEXT: sll $5, $16, 0
; SOFT-FLOAT-64R2-NEXT: or $19, $19, $1
@@ -583,7 +583,7 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-64R2-NEXT: dsrl $1, $16, 32
; SOFT-FLOAT-64R2-NEXT: jal __addsf3
; SOFT-FLOAT-64R2-NEXT: sll $5, $1, 0
-; SOFT-FLOAT-64R2-NEXT: # kill: def $v0 killed $v0 def $v0_64
+; SOFT-FLOAT-64R2-NEXT: # kill: def $r2 killed $r2 def $r2_64
; SOFT-FLOAT-64R2-NEXT: dsll $1, $2, 32
; SOFT-FLOAT-64R2-NEXT: or $3, $17, $1
; SOFT-FLOAT-64R2-NEXT: move $2, $19
diff --git a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
index 3f00162604a03..f8a57ce5078cc 100644
--- a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DEXT %0, 55, 10
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dext-size.mir b/llvm/test/CodeGen/Mips/instverify/dext-size.mir
index ca8d03270bec7..a870679fa878a 100644
--- a/llvm/test/CodeGen/Mips/instverify/dext-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dext-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DEXT %0, 5, 50
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
index a26ca38ca087e..b9c6cf18e5834 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DEXTM %0, 3, 62
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
index 5f780c45c384b..35ab1a2d97096 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DEXTM %0, 65, 5
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
index 2e155f4ca7a4f..ef6da5cbd1222 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DEXTM %0, 31, 67
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
index 2e5da9d57a20a..0dd646d28c1f8 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DEXTU %0, 43, 30
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
index c91c6f6d194c4..1da64f1432249 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DEXTU %0, 64, 5
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
index 7ca5b9c7b64fc..6ff76b327b594 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DEXTU %0, 63, 1
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
index a030cf3206144..9ab835e708378 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DEXTU %0, 33, 67
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
index 510b5521ddc65..e13d1f86946e2 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DINS %0, 17, 17
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
index 9f47daeab3ed9..eda7c0e778d96 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DINS %0, 55, 10
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-size.mir
index 8c6c0cbd9a241..08ae7d6053f79 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DINS %0, 5, 50
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
index 42f1ca0ab3078..a33f16fabf0fa 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DINSM %0, 20, 50
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
index 9109377093e0d..7d5f81ddf2ed7 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DINSM %0, 65, 5
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
index 69839d4ef013a..458549e8053ba 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DINSM %0, 31, 67
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
index 71957d98e4fdd..30d3108f2d7bb 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DINSU %0, 50, 20
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
index 0a2428a09e30a..f78a33888b347 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DINSU %0, 65, 5
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
index f6ce04370a409..d086e5c3bfd54 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0_64
%1 = DINSU %0, 33, 67
- $v0_64 = COPY %1
- RetRA implicit $v0_64
+ $r2_64 = COPY %1
+ RetRA implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
index bbac1b0efa924..90835c138eb3d 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0
%1 = EXT %0, 17, 17
- $v0 = COPY %1
- RetRA implicit $v0
+ $r2 = COPY %1
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
index f67a4a5eead5a..47df1b150e43b 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0
%1 = EXT %0, 44, 21
- $v0 = COPY %1
- RetRA implicit $v0
+ $r2 = COPY %1
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-size.mir
index 1089b495779e6..135486ecc76f4 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-size.mir
@@ -43,7 +43,7 @@ body: |
%0 = COPY $a0
%1 = EXT %0, 0, 33
- $v0 = COPY %1
- RetRA implicit $v0
+ $r2 = COPY %1
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
index 526df82688637..f4f6c71a32df8 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
@@ -48,7 +48,7 @@ body: |
%0 = COPY $a0
%2 = ANDi %1, 15
%3 = INS killed %2, 17, 17, %0
- $v0 = COPY %3
- RetRA implicit $v0
+ $r2 = COPY %3
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
index 03f524975ce02..822f464c89995 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
@@ -48,7 +48,7 @@ body: |
%0 = COPY $a0
%2 = ANDi %1, 15
%3 = INS killed %2, 32, 4, %0
- $v0 = COPY %3
- RetRA implicit $v0
+ $r2 = COPY %3
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-size.mir
index 4375e01023849..29e45d60fce06 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-size.mir
@@ -48,7 +48,7 @@ body: |
%0 = COPY $a0
%2 = ANDi %1, 15
%3 = INS killed %2, 0, 40, %0
- $v0 = COPY %3
- RetRA implicit $v0
+ $r2 = COPY %3
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
index e379619663078..097fb322c8df5 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
@@ -44,7 +44,7 @@ define i32 @test1(float %t) {
; M32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
; M32-NEXT: # <MCOperand Reg:RA>>
; M32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M32-NEXT: # <MCOperand Reg:V0>
+; M32-NEXT: # <MCOperand Reg:R2>
; M32-NEXT: # <MCOperand Reg:F0>>
;
; M32R2-FP64-LABEL: test1:
@@ -55,7 +55,7 @@ define i32 @test1(float %t) {
; M32R2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
; M32R2-FP64-NEXT: # <MCOperand Reg:RA>>
; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M32R2-FP64-NEXT: # <MCOperand Reg:V0>
+; M32R2-FP64-NEXT: # <MCOperand Reg:R2>
; M32R2-FP64-NEXT: # <MCOperand Reg:F0>>
;
; M32R2-SF-LABEL: test1:
@@ -97,7 +97,7 @@ define i32 @test1(float %t) {
; M32R3R5-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
; M32R3R5-NEXT: # <MCOperand Reg:RA>>
; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M32R3R5-NEXT: # <MCOperand Reg:V0>
+; M32R3R5-NEXT: # <MCOperand Reg:R2>
; M32R3R5-NEXT: # <MCOperand Reg:F0>>
;
; M32R6-LABEL: test1:
@@ -109,7 +109,7 @@ define i32 @test1(float %t) {
; M32R6-NEXT: # <MCOperand Reg:ZERO>
; M32R6-NEXT: # <MCOperand Reg:RA>>
; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M32R6-NEXT: # <MCOperand Reg:V0>
+; M32R6-NEXT: # <MCOperand Reg:R2>
; M32R6-NEXT: # <MCOperand Reg:F0>>
;
; M3-LABEL: test1:
@@ -118,7 +118,7 @@ define i32 @test1(float %t) {
; M3-NEXT: # <MCOperand Reg:F0>
; M3-NEXT: # <MCOperand Reg:F12>>
; M3-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M3-NEXT: # <MCOperand Reg:V0>
+; M3-NEXT: # <MCOperand Reg:R2>
; M3-NEXT: # <MCOperand Reg:F0>>
; M3-NEXT: nop # <MCInst #[[#MCINST7:]] SLL
; M3-NEXT: # <MCOperand Reg:ZERO>
@@ -139,7 +139,7 @@ define i32 @test1(float %t) {
; M64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
; M64-NEXT: # <MCOperand Reg:RA_64>>
; M64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M64-NEXT: # <MCOperand Reg:V0>
+; M64-NEXT: # <MCOperand Reg:R2>
; M64-NEXT: # <MCOperand Reg:F0>>
;
; M64R6-LABEL: test1:
@@ -151,7 +151,7 @@ define i32 @test1(float %t) {
; M64R6-NEXT: # <MCOperand Reg:ZERO_64>
; M64R6-NEXT: # <MCOperand Reg:RA_64>>
; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M64R6-NEXT: # <MCOperand Reg:V0>
+; M64R6-NEXT: # <MCOperand Reg:R2>
; M64R6-NEXT: # <MCOperand Reg:F0>>
;
; MMR2-FP32-LABEL: test1:
@@ -162,7 +162,7 @@ define i32 @test1(float %t) {
; MMR2-FP32-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM
; MMR2-FP32-NEXT: # <MCOperand Reg:RA>>
; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
-; MMR2-FP32-NEXT: # <MCOperand Reg:V0>
+; MMR2-FP32-NEXT: # <MCOperand Reg:R2>
; MMR2-FP32-NEXT: # <MCOperand Reg:F0>>
;
; MMR2-FP64-LABEL: test1:
@@ -173,7 +173,7 @@ define i32 @test1(float %t) {
; MMR2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM
; MMR2-FP64-NEXT: # <MCOperand Reg:RA>>
; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
-; MMR2-FP64-NEXT: # <MCOperand Reg:V0>
+; MMR2-FP64-NEXT: # <MCOperand Reg:R2>
; MMR2-FP64-NEXT: # <MCOperand Reg:F0>>
;
; MMR2-SF-LABEL: test1:
@@ -209,7 +209,7 @@ define i32 @test1(float %t) {
; MMR6-NEXT: # <MCOperand Reg:F0>
; MMR6-NEXT: # <MCOperand Reg:F12>>
; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:F0>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:RA>>
@@ -254,7 +254,7 @@ define i32 @test2(double %t) {
; M32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; M32-NEXT: # <MCOperand Reg:RA>>
; M32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M32-NEXT: # <MCOperand Reg:V0>
+; M32-NEXT: # <MCOperand Reg:R2>
; M32-NEXT: # <MCOperand Reg:F0>>
;
; M32R2-FP64-LABEL: test2:
@@ -265,7 +265,7 @@ define i32 @test2(double %t) {
; M32R2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; M32R2-FP64-NEXT: # <MCOperand Reg:RA>>
; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M32R2-FP64-NEXT: # <MCOperand Reg:V0>
+; M32R2-FP64-NEXT: # <MCOperand Reg:R2>
; M32R2-FP64-NEXT: # <MCOperand Reg:F0>>
;
; M32R2-SF-LABEL: test2:
@@ -307,7 +307,7 @@ define i32 @test2(double %t) {
; M32R3R5-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; M32R3R5-NEXT: # <MCOperand Reg:RA>>
; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M32R3R5-NEXT: # <MCOperand Reg:V0>
+; M32R3R5-NEXT: # <MCOperand Reg:R2>
; M32R3R5-NEXT: # <MCOperand Reg:F0>>
;
; M32R6-LABEL: test2:
@@ -319,7 +319,7 @@ define i32 @test2(double %t) {
; M32R6-NEXT: # <MCOperand Reg:ZERO>
; M32R6-NEXT: # <MCOperand Reg:RA>>
; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M32R6-NEXT: # <MCOperand Reg:V0>
+; M32R6-NEXT: # <MCOperand Reg:R2>
; M32R6-NEXT: # <MCOperand Reg:F0>>
;
; M3-LABEL: test2:
@@ -328,7 +328,7 @@ define i32 @test2(double %t) {
; M3-NEXT: # <MCOperand Reg:F0>
; M3-NEXT: # <MCOperand Reg:D12_64>>
; M3-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M3-NEXT: # <MCOperand Reg:V0>
+; M3-NEXT: # <MCOperand Reg:R2>
; M3-NEXT: # <MCOperand Reg:F0>>
; M3-NEXT: nop # <MCInst #[[#MCINST7]] SLL
; M3-NEXT: # <MCOperand Reg:ZERO>
@@ -349,7 +349,7 @@ define i32 @test2(double %t) {
; M64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; M64-NEXT: # <MCOperand Reg:RA_64>>
; M64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M64-NEXT: # <MCOperand Reg:V0>
+; M64-NEXT: # <MCOperand Reg:R2>
; M64-NEXT: # <MCOperand Reg:F0>>
;
; M64R6-LABEL: test2:
@@ -361,7 +361,7 @@ define i32 @test2(double %t) {
; M64R6-NEXT: # <MCOperand Reg:ZERO_64>
; M64R6-NEXT: # <MCOperand Reg:RA_64>>
; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M64R6-NEXT: # <MCOperand Reg:V0>
+; M64R6-NEXT: # <MCOperand Reg:R2>
; M64R6-NEXT: # <MCOperand Reg:F0>>
;
; MMR2-FP32-LABEL: test2:
@@ -372,7 +372,7 @@ define i32 @test2(double %t) {
; MMR2-FP32-NEXT: jr $ra # <MCInst #[[#MCINST12]] JR_MM
; MMR2-FP32-NEXT: # <MCOperand Reg:RA>>
; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
-; MMR2-FP32-NEXT: # <MCOperand Reg:V0>
+; MMR2-FP32-NEXT: # <MCOperand Reg:R2>
; MMR2-FP32-NEXT: # <MCOperand Reg:F0>>
;
; MMR2-FP64-LABEL: test2:
@@ -383,7 +383,7 @@ define i32 @test2(double %t) {
; MMR2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST12]] JR_MM
; MMR2-FP64-NEXT: # <MCOperand Reg:RA>>
; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
-; MMR2-FP64-NEXT: # <MCOperand Reg:V0>
+; MMR2-FP64-NEXT: # <MCOperand Reg:R2>
; MMR2-FP64-NEXT: # <MCOperand Reg:F0>>
;
; MMR2-SF-LABEL: test2:
@@ -419,7 +419,7 @@ define i32 @test2(double %t) {
; MMR6-NEXT: # <MCOperand Reg:F0>
; MMR6-NEXT: # <MCOperand Reg:D12_64>>
; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:F0>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:RA>>
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/load.ll b/llvm/test/CodeGen/Mips/llvm-ir/load.ll
index 204decb37c638..d97016bf43321 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/load.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/load.ll
@@ -32,7 +32,7 @@ define i8 @f1() {
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
; MIPS32-NEXT: # <MCOperand Reg:RA>>
; MIPS32-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
-; MIPS32-NEXT: # <MCOperand Reg:V0>
+; MIPS32-NEXT: # <MCOperand Reg:R2>
; MIPS32-NEXT: # <MCOperand Reg:AT>
; MIPS32-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -44,7 +44,7 @@ define i8 @f1() {
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
; MMR3-NEXT: # <MCOperand Reg:RA>>
; MMR3-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM
-; MMR3-NEXT: # <MCOperand Reg:V0>
+; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -57,7 +57,7 @@ define i8 @f1() {
; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
; MIPS32R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
-; MIPS32R6-NEXT: # <MCOperand Reg:V0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R2>
; MIPS32R6-NEXT: # <MCOperand Reg:AT>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -67,7 +67,7 @@ define i8 @f1() {
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%lo(a)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
@@ -97,7 +97,7 @@ define i8 @f1() {
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
; MIPS3-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
-; MIPS3-NEXT: # <MCOperand Reg:V0>
+; MIPS3-NEXT: # <MCOperand Reg:R2>
; MIPS3-NEXT: # <MCOperand Reg:AT_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -125,7 +125,7 @@ define i8 @f1() {
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
-; MIPS64-NEXT: # <MCOperand Reg:V0>
+; MIPS64-NEXT: # <MCOperand Reg:R2>
; MIPS64-NEXT: # <MCOperand Reg:AT_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -154,7 +154,7 @@ define i8 @f1() {
; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
-; MIPS64R6-NEXT: # <MCOperand Reg:V0>
+; MIPS64R6-NEXT: # <MCOperand Reg:R2>
; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -166,7 +166,7 @@ define i8 @f1() {
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
; MMR5FP64-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:V0>
+; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -178,7 +178,7 @@ define i8 @f1() {
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
; MIPS32R5FP643-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:V0>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -188,7 +188,7 @@ define i8 @f1() {
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS1-PSX-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
-; MIPS1-PSX-NEXT: # <MCOperand Reg:V0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(a)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
@@ -211,7 +211,7 @@ define i32 @f2() {
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32-NEXT: # <MCOperand Reg:RA>>
; MIPS32-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
-; MIPS32-NEXT: # <MCOperand Reg:V0>
+; MIPS32-NEXT: # <MCOperand Reg:R2>
; MIPS32-NEXT: # <MCOperand Reg:AT>
; MIPS32-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -223,7 +223,7 @@ define i32 @f2() {
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR3-NEXT: # <MCOperand Reg:RA>>
; MMR3-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST15:]] LB_MM
-; MMR3-NEXT: # <MCOperand Reg:V0>
+; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -236,7 +236,7 @@ define i32 @f2() {
; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
; MIPS32R6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
-; MIPS32R6-NEXT: # <MCOperand Reg:V0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R2>
; MIPS32R6-NEXT: # <MCOperand Reg:AT>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -246,7 +246,7 @@ define i32 @f2() {
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST15:]] LB_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%lo(a)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
@@ -276,7 +276,7 @@ define i32 @f2() {
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
; MIPS3-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
-; MIPS3-NEXT: # <MCOperand Reg:V0>
+; MIPS3-NEXT: # <MCOperand Reg:R2>
; MIPS3-NEXT: # <MCOperand Reg:AT_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -304,7 +304,7 @@ define i32 @f2() {
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
-; MIPS64-NEXT: # <MCOperand Reg:V0>
+; MIPS64-NEXT: # <MCOperand Reg:R2>
; MIPS64-NEXT: # <MCOperand Reg:AT_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -333,7 +333,7 @@ define i32 @f2() {
; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64R6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
-; MIPS64R6-NEXT: # <MCOperand Reg:V0>
+; MIPS64R6-NEXT: # <MCOperand Reg:R2>
; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -345,7 +345,7 @@ define i32 @f2() {
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
; MMR5FP64-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST15:]] LB_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:V0>
+; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -357,7 +357,7 @@ define i32 @f2() {
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
; MIPS32R5FP643-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:V0>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(a)>>
;
@@ -367,7 +367,7 @@ define i32 @f2() {
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS1-PSX-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
-; MIPS1-PSX-NEXT: # <MCOperand Reg:V0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(a)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
@@ -391,7 +391,7 @@ define i16 @f3() {
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32-NEXT: # <MCOperand Reg:RA>>
; MIPS32-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
-; MIPS32-NEXT: # <MCOperand Reg:V0>
+; MIPS32-NEXT: # <MCOperand Reg:R2>
; MIPS32-NEXT: # <MCOperand Reg:AT>
; MIPS32-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -403,7 +403,7 @@ define i16 @f3() {
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR3-NEXT: # <MCOperand Reg:RA>>
; MMR3-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LHu_MM
-; MMR3-NEXT: # <MCOperand Reg:V0>
+; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -416,7 +416,7 @@ define i16 @f3() {
; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
; MIPS32R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
-; MIPS32R6-NEXT: # <MCOperand Reg:V0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R2>
; MIPS32R6-NEXT: # <MCOperand Reg:AT>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -426,7 +426,7 @@ define i16 @f3() {
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LHu_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%lo(b)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
@@ -456,7 +456,7 @@ define i16 @f3() {
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
; MIPS3-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
-; MIPS3-NEXT: # <MCOperand Reg:V0>
+; MIPS3-NEXT: # <MCOperand Reg:R2>
; MIPS3-NEXT: # <MCOperand Reg:AT_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -484,7 +484,7 @@ define i16 @f3() {
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
-; MIPS64-NEXT: # <MCOperand Reg:V0>
+; MIPS64-NEXT: # <MCOperand Reg:R2>
; MIPS64-NEXT: # <MCOperand Reg:AT_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -513,7 +513,7 @@ define i16 @f3() {
; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
-; MIPS64R6-NEXT: # <MCOperand Reg:V0>
+; MIPS64R6-NEXT: # <MCOperand Reg:R2>
; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -525,7 +525,7 @@ define i16 @f3() {
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
; MMR5FP64-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LHu_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:V0>
+; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -537,7 +537,7 @@ define i16 @f3() {
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
; MIPS32R5FP643-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:V0>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -547,7 +547,7 @@ define i16 @f3() {
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS1-PSX-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
-; MIPS1-PSX-NEXT: # <MCOperand Reg:V0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(b)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
@@ -570,7 +570,7 @@ define i32 @f4() {
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32-NEXT: # <MCOperand Reg:RA>>
; MIPS32-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
-; MIPS32-NEXT: # <MCOperand Reg:V0>
+; MIPS32-NEXT: # <MCOperand Reg:R2>
; MIPS32-NEXT: # <MCOperand Reg:AT>
; MIPS32-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -582,7 +582,7 @@ define i32 @f4() {
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR3-NEXT: # <MCOperand Reg:RA>>
; MMR3-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST19:]] LH_MM
-; MMR3-NEXT: # <MCOperand Reg:V0>
+; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -595,7 +595,7 @@ define i32 @f4() {
; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
; MIPS32R6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
-; MIPS32R6-NEXT: # <MCOperand Reg:V0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R2>
; MIPS32R6-NEXT: # <MCOperand Reg:AT>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -605,7 +605,7 @@ define i32 @f4() {
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST19:]] LH_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%lo(b)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
@@ -635,7 +635,7 @@ define i32 @f4() {
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
; MIPS3-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
-; MIPS3-NEXT: # <MCOperand Reg:V0>
+; MIPS3-NEXT: # <MCOperand Reg:R2>
; MIPS3-NEXT: # <MCOperand Reg:AT_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -663,7 +663,7 @@ define i32 @f4() {
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
-; MIPS64-NEXT: # <MCOperand Reg:V0>
+; MIPS64-NEXT: # <MCOperand Reg:R2>
; MIPS64-NEXT: # <MCOperand Reg:AT_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -692,7 +692,7 @@ define i32 @f4() {
; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64R6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
-; MIPS64R6-NEXT: # <MCOperand Reg:V0>
+; MIPS64R6-NEXT: # <MCOperand Reg:R2>
; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -704,7 +704,7 @@ define i32 @f4() {
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
; MMR5FP64-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST19:]] LH_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:V0>
+; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -716,7 +716,7 @@ define i32 @f4() {
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
; MIPS32R5FP643-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:V0>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(b)>>
;
@@ -726,7 +726,7 @@ define i32 @f4() {
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS1-PSX-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
-; MIPS1-PSX-NEXT: # <MCOperand Reg:V0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(b)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
@@ -750,7 +750,7 @@ define i32 @f5() {
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32-NEXT: # <MCOperand Reg:RA>>
; MIPS32-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
-; MIPS32-NEXT: # <MCOperand Reg:V0>
+; MIPS32-NEXT: # <MCOperand Reg:R2>
; MIPS32-NEXT: # <MCOperand Reg:AT>
; MIPS32-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -762,7 +762,7 @@ define i32 @f5() {
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR3-NEXT: # <MCOperand Reg:RA>>
; MMR3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST21:]] LW_MM
-; MMR3-NEXT: # <MCOperand Reg:V0>
+; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -775,7 +775,7 @@ define i32 @f5() {
; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
; MIPS32R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
-; MIPS32R6-NEXT: # <MCOperand Reg:V0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R2>
; MIPS32R6-NEXT: # <MCOperand Reg:AT>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -785,7 +785,7 @@ define i32 @f5() {
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST21:]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
@@ -815,7 +815,7 @@ define i32 @f5() {
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
-; MIPS3-NEXT: # <MCOperand Reg:V0>
+; MIPS3-NEXT: # <MCOperand Reg:R2>
; MIPS3-NEXT: # <MCOperand Reg:AT_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -843,7 +843,7 @@ define i32 @f5() {
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
-; MIPS64-NEXT: # <MCOperand Reg:V0>
+; MIPS64-NEXT: # <MCOperand Reg:R2>
; MIPS64-NEXT: # <MCOperand Reg:AT_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -872,7 +872,7 @@ define i32 @f5() {
; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
-; MIPS64R6-NEXT: # <MCOperand Reg:V0>
+; MIPS64R6-NEXT: # <MCOperand Reg:R2>
; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -884,7 +884,7 @@ define i32 @f5() {
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
; MMR5FP64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST21:]] LW_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:V0>
+; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -896,7 +896,7 @@ define i32 @f5() {
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
; MIPS32R5FP643-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:V0>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -906,7 +906,7 @@ define i32 @f5() {
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS1-PSX-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
-; MIPS1-PSX-NEXT: # <MCOperand Reg:V0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
@@ -927,13 +927,13 @@ define i64 @f6() {
; MIPS32-NEXT: # <MCOperand Reg:AT>
; MIPS32-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
-; MIPS32-NEXT: # <MCOperand Reg:V1>
+; MIPS32-NEXT: # <MCOperand Reg:R3>
; MIPS32-NEXT: # <MCOperand Reg:AT>
; MIPS32-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32-NEXT: # <MCOperand Reg:RA>>
; MIPS32-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST22:]] ADDiu
-; MIPS32-NEXT: # <MCOperand Reg:V0>
+; MIPS32-NEXT: # <MCOperand Reg:R2>
; MIPS32-NEXT: # <MCOperand Reg:ZERO>
; MIPS32-NEXT: # <MCOperand Imm:0>>
;
@@ -943,12 +943,12 @@ define i64 @f6() {
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR3-NEXT: li16 $2, 0 # <MCInst #[[#MCINST23:]] LI16_MM
-; MMR3-NEXT: # <MCOperand Reg:V0>
+; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Imm:0>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR3-NEXT: # <MCOperand Reg:RA>>
; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
-; MMR3-NEXT: # <MCOperand Reg:V1>
+; MMR3-NEXT: # <MCOperand Reg:R3>
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -958,14 +958,14 @@ define i64 @f6() {
; MIPS32R6-NEXT: # <MCOperand Reg:AT>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
-; MIPS32R6-NEXT: # <MCOperand Reg:V1>
+; MIPS32R6-NEXT: # <MCOperand Reg:R3>
; MIPS32R6-NEXT: # <MCOperand Reg:AT>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
; MIPS32R6-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST22:]] ADDiu
-; MIPS32R6-NEXT: # <MCOperand Reg:V0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R2>
; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
; MIPS32R6-NEXT: # <MCOperand Imm:0>>
;
@@ -975,11 +975,11 @@ define i64 @f6() {
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V1>
+; MMR6-NEXT: # <MCOperand Reg:R3>
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR6-NEXT: li16 $2, 0 # <MCInst #[[#MCINST23:]] LI16_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:RA>>
@@ -1008,7 +1008,7 @@ define i64 @f6() {
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
; MIPS3-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST24:]] LWu
-; MIPS3-NEXT: # <MCOperand Reg:V0_64>
+; MIPS3-NEXT: # <MCOperand Reg:R2_64>
; MIPS3-NEXT: # <MCOperand Reg:AT_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -1036,7 +1036,7 @@ define i64 @f6() {
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST24:]] LWu
-; MIPS64-NEXT: # <MCOperand Reg:V0_64>
+; MIPS64-NEXT: # <MCOperand Reg:R2_64>
; MIPS64-NEXT: # <MCOperand Reg:AT_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -1065,7 +1065,7 @@ define i64 @f6() {
; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64R6-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST24:]] LWu
-; MIPS64R6-NEXT: # <MCOperand Reg:V0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R2_64>
; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -1075,12 +1075,12 @@ define i64 @f6() {
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR5FP64-NEXT: li16 $2, 0 # <MCInst #[[#MCINST23:]] LI16_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:V0>
+; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Imm:0>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:V1>
+; MMR5FP64-NEXT: # <MCOperand Reg:R3>
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -1090,13 +1090,13 @@ define i64 @f6() {
; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:V1>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R3>
; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
; MIPS32R5FP643-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST22:]] ADDiu
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:V0>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
; MIPS32R5FP643-NEXT: # <MCOperand Reg:ZERO>
; MIPS32R5FP643-NEXT: # <MCOperand Imm:0>>
;
@@ -1106,13 +1106,13 @@ define i64 @f6() {
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS1-PSX-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
-; MIPS1-PSX-NEXT: # <MCOperand Reg:V0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
; MIPS1-PSX-NEXT: addiu $3, $zero, 0 # <MCInst #[[#MCINST22:]] ADDiu
-; MIPS1-PSX-NEXT: # <MCOperand Reg:V1>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R3>
; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
; MIPS1-PSX-NEXT: # <MCOperand Imm:0>>
entry:
@@ -1128,14 +1128,14 @@ define i64 @f7() {
; MIPS32-NEXT: # <MCOperand Reg:AT>
; MIPS32-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
-; MIPS32-NEXT: # <MCOperand Reg:V1>
+; MIPS32-NEXT: # <MCOperand Reg:R3>
; MIPS32-NEXT: # <MCOperand Reg:AT>
; MIPS32-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32-NEXT: # <MCOperand Reg:RA>>
; MIPS32-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA
-; MIPS32-NEXT: # <MCOperand Reg:V0>
-; MIPS32-NEXT: # <MCOperand Reg:V1>
+; MIPS32-NEXT: # <MCOperand Reg:R2>
+; MIPS32-NEXT: # <MCOperand Reg:R3>
; MIPS32-NEXT: # <MCOperand Imm:31>>
;
; MMR3-LABEL: f7:
@@ -1144,14 +1144,14 @@ define i64 @f7() {
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
-; MMR3-NEXT: # <MCOperand Reg:V1>
+; MMR3-NEXT: # <MCOperand Reg:R3>
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR3-NEXT: # <MCOperand Reg:RA>>
; MMR3-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST26:]] SRA_MM
-; MMR3-NEXT: # <MCOperand Reg:V0>
-; MMR3-NEXT: # <MCOperand Reg:V1>
+; MMR3-NEXT: # <MCOperand Reg:R2>
+; MMR3-NEXT: # <MCOperand Reg:R3>
; MMR3-NEXT: # <MCOperand Imm:31>>
;
; MIPS32R6-LABEL: f7:
@@ -1160,15 +1160,15 @@ define i64 @f7() {
; MIPS32R6-NEXT: # <MCOperand Reg:AT>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
-; MIPS32R6-NEXT: # <MCOperand Reg:V1>
+; MIPS32R6-NEXT: # <MCOperand Reg:R3>
; MIPS32R6-NEXT: # <MCOperand Reg:AT>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
; MIPS32R6-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA
-; MIPS32R6-NEXT: # <MCOperand Reg:V0>
-; MIPS32R6-NEXT: # <MCOperand Reg:V1>
+; MIPS32R6-NEXT: # <MCOperand Reg:R2>
+; MIPS32R6-NEXT: # <MCOperand Reg:R3>
; MIPS32R6-NEXT: # <MCOperand Imm:31>>
;
; MMR6-LABEL: f7:
@@ -1177,12 +1177,12 @@ define i64 @f7() {
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V1>
+; MMR6-NEXT: # <MCOperand Reg:R3>
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR6-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST26:]] SRA_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V1>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R3>
; MMR6-NEXT: # <MCOperand Imm:31>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:RA>>
@@ -1211,7 +1211,7 @@ define i64 @f7() {
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST27:]] LW64
-; MIPS3-NEXT: # <MCOperand Reg:V0_64>
+; MIPS3-NEXT: # <MCOperand Reg:R2_64>
; MIPS3-NEXT: # <MCOperand Reg:AT_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -1239,7 +1239,7 @@ define i64 @f7() {
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST27:]] LW64
-; MIPS64-NEXT: # <MCOperand Reg:V0_64>
+; MIPS64-NEXT: # <MCOperand Reg:R2_64>
; MIPS64-NEXT: # <MCOperand Reg:AT_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -1268,7 +1268,7 @@ define i64 @f7() {
; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST27:]] LW64
-; MIPS64R6-NEXT: # <MCOperand Reg:V0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R2_64>
; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(c)>>
;
@@ -1278,14 +1278,14 @@ define i64 @f7() {
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:V1>
+; MMR5FP64-NEXT: # <MCOperand Reg:R3>
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
; MMR5FP64-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST26:]] SRA_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:V0>
-; MMR5FP64-NEXT: # <MCOperand Reg:V1>
+; MMR5FP64-NEXT: # <MCOperand Reg:R2>
+; MMR5FP64-NEXT: # <MCOperand Reg:R3>
; MMR5FP64-NEXT: # <MCOperand Imm:31>>
;
; MIPS32R5FP643-LABEL: f7:
@@ -1294,14 +1294,14 @@ define i64 @f7() {
; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:V1>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R3>
; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
; MIPS32R5FP643-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:V0>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:V1>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R3>
; MIPS32R5FP643-NEXT: # <MCOperand Imm:31>>
;
; MIPS1-PSX-LABEL: f7:
@@ -1310,14 +1310,14 @@ define i64 @f7() {
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS1-PSX-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
-; MIPS1-PSX-NEXT: # <MCOperand Reg:V0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
; MIPS1-PSX-NEXT: sra $3, $2, 31 # <MCInst #[[#MCINST25:]] SRA
-; MIPS1-PSX-NEXT: # <MCOperand Reg:V1>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:V0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R3>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
; MIPS1-PSX-NEXT: # <MCOperand Imm:31>>
entry:
%0 = load i32, ptr @c
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
index 4f56ed2932a0d..345180995c948 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
@@ -111,7 +111,7 @@ define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
; MM32R3-NEXT: # <MCOperand Reg:D1>
; MM32R3-NEXT: # <MCOperand Reg:A2>>
; MM32R3-NEXT: andi16 $2, $4, 1 # <MCInst #[[#MCINST3:]] ANDI16_MM
-; MM32R3-NEXT: # <MCOperand Reg:V0>
+; MM32R3-NEXT: # <MCOperand Reg:R2>
; MM32R3-NEXT: # <MCOperand Reg:A0>
; MM32R3-NEXT: # <MCOperand Imm:1>>
; MM32R3-NEXT: ldc1 $f0, 16($sp) # <MCInst #[[#MCINST4:]] LDC1_MM_D32
@@ -123,7 +123,7 @@ define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
; MM32R3-NEXT: movn.d $f0, $f2, $2 # <MCInst #[[#MCINST6:]] MOVN_I_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D1>
-; MM32R3-NEXT: # <MCOperand Reg:V0>
+; MM32R3-NEXT: # <MCOperand Reg:R2>
; MM32R3-NEXT: # <MCOperand Reg:D0>>
;
; MM32R6-LABEL: tst_select_i1_double:
@@ -222,19 +222,19 @@ define double @tst_select_i1_double_reordered(double %x, double %y,
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D7>>
; MM32R3-NEXT: lw $2, 16($sp) # <MCInst #[[#MCINST8:]] LWSP_MM
-; MM32R3-NEXT: # <MCOperand Reg:V0>
+; MM32R3-NEXT: # <MCOperand Reg:R2>
; MM32R3-NEXT: # <MCOperand Reg:SP>
; MM32R3-NEXT: # <MCOperand Imm:16>>
; MM32R3-NEXT: andi16 $2, $2, 1 # <MCInst #[[#MCINST3]] ANDI16_MM
-; MM32R3-NEXT: # <MCOperand Reg:V0>
-; MM32R3-NEXT: # <MCOperand Reg:V0>
+; MM32R3-NEXT: # <MCOperand Reg:R2>
+; MM32R3-NEXT: # <MCOperand Reg:R2>
; MM32R3-NEXT: # <MCOperand Imm:1>>
; MM32R3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
; MM32R3-NEXT: # <MCOperand Reg:RA>>
; MM32R3-NEXT: movn.d $f0, $f12, $2 # <MCInst #[[#MCINST6]] MOVN_I_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D6>
-; MM32R3-NEXT: # <MCOperand Reg:V0>
+; MM32R3-NEXT: # <MCOperand Reg:R2>
; MM32R3-NEXT: # <MCOperand Reg:D0>>
;
; MM32R6-LABEL: tst_select_i1_double_reordered:
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/store.ll b/llvm/test/CodeGen/Mips/llvm-ir/store.ll
index bd3bb5099c733..b5a930569da71 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/store.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/store.ll
@@ -454,12 +454,12 @@ define void @f4(i64 %a) {
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR3-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM
-; MMR3-NEXT: # <MCOperand Reg:V0>
+; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Reg:AT>
; MMR3-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR3-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM
; MMR3-NEXT: # <MCOperand Reg:A1>
-; MMR3-NEXT: # <MCOperand Reg:V0>
+; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Imm:4>>
; MMR3-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
; MMR3-NEXT: # <MCOperand Reg:RA>>
@@ -495,12 +495,12 @@ define void @f4(i64 %a) {
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR6-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:AT>
; MMR6-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR6-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM
; MMR6-NEXT: # <MCOperand Reg:A1>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:4>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:RA>>
@@ -572,12 +572,12 @@ define void @f4(i64 %a) {
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR5FP64-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:V0>
+; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Reg:AT>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR5FP64-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM
; MMR5FP64-NEXT: # <MCOperand Reg:A1>
-; MMR5FP64-NEXT: # <MCOperand Reg:V0>
+; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Imm:4>>
; MMR5FP64-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
index 7f0c59672d3d4..6eaa4d16614c5 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
@@ -82,11 +82,11 @@ body: |
; MM: }
; MM: bb.2.if.then:
; MM: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MM: $v0 = LI16_MM 0
- ; MM: JRC16_MM undef $ra, implicit killed $v0
+ ; MM: $r2 = LI16_MM 0
+ ; MM: JRC16_MM undef $ra, implicit killed $r2
; MM: bb.3.return:
- ; MM: $v0 = LI16_MM 1
- ; MM: JRC16_MM undef $ra, implicit killed $v0
+ ; MM: $r2 = LI16_MM 1
+ ; MM: JRC16_MM undef $ra, implicit killed $r2
; PIC-LABEL: name: a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
@@ -111,11 +111,11 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: $v0 = LI16_MM 0
- ; PIC: JRC16_MM undef $ra, implicit killed $v0
+ ; PIC: $r2 = LI16_MM 0
+ ; PIC: JRC16_MM undef $ra, implicit killed $r2
; PIC: bb.4.return:
- ; PIC: $v0 = LI16_MM 1
- ; PIC: JRC16_MM undef $ra, implicit killed $v0
+ ; PIC: $r2 = LI16_MM 1
+ ; PIC: JRC16_MM undef $ra, implicit killed $r2
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d6, $d7
@@ -125,12 +125,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
- $v0 = LI16_MM 0
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = LI16_MM 0
+ PseudoReturn undef $ra, implicit killed $r2
bb.2.return:
- $v0 = LI16_MM 1
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = LI16_MM 1
+ PseudoReturn undef $ra, implicit killed $r2
...
---
@@ -176,12 +176,12 @@ body: |
; MM: $zero = SLL_MM $zero, 0
; MM: }
; MM: bb.1.return:
- ; MM: $v0 = LI16_MM 1
- ; MM: JRC16_MM undef $ra, implicit killed $v0
+ ; MM: $r2 = LI16_MM 1
+ ; MM: JRC16_MM undef $ra, implicit killed $r2
; MM: bb.2.if.then:
; MM: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MM: $v0 = LI16_MM 0
- ; MM: JRC16_MM undef $ra, implicit killed $v0
+ ; MM: $r2 = LI16_MM 0
+ ; MM: JRC16_MM undef $ra, implicit killed $r2
; PIC-LABEL: name: b
; PIC: bb.0.entry:
; PIC: successors: %bb.2(0x30000000), %bb.1(0x50000000)
@@ -190,12 +190,12 @@ body: |
; PIC: $zero = SLL_MM $zero, 0
; PIC: }
; PIC: bb.1.return:
- ; PIC: $v0 = LI16_MM 1
- ; PIC: JRC16_MM undef $ra, implicit killed $v0
+ ; PIC: $r2 = LI16_MM 1
+ ; PIC: JRC16_MM undef $ra, implicit killed $r2
; PIC: bb.2.if.then:
; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: $v0 = LI16_MM 0
- ; PIC: JRC16_MM undef $ra, implicit killed $v0
+ ; PIC: $r2 = LI16_MM 0
+ ; PIC: JRC16_MM undef $ra, implicit killed $r2
bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $d6, $d7
@@ -204,12 +204,12 @@ body: |
BC1F_MM killed $fcc0, %bb.2, implicit-def dead $at
bb.2.return:
- $v0 = LI16_MM 1
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = LI16_MM 1
+ PseudoReturn undef $ra, implicit killed $r2
bb.1.if.then:
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
- $v0 = LI16_MM 0
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = LI16_MM 0
+ PseudoReturn undef $ra, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
index 21afed21d029e..fe4258cf1fedf 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
@@ -78,11 +78,11 @@ body: |
; MM: BC_MMR6 %bb.3
; MM: bb.2.if.then:
; MM: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MM: $v0 = LI16_MM 0
- ; MM: JRC16_MM undef $ra, implicit $v0
+ ; MM: $r2 = LI16_MM 0
+ ; MM: JRC16_MM undef $ra, implicit $r2
; MM: bb.3.return:
- ; MM: $v0 = LI16_MM 1
- ; MM: JRC16_MM undef $ra, implicit $v0
+ ; MM: $r2 = LI16_MM 1
+ ; MM: JRC16_MM undef $ra, implicit $r2
; PIC-LABEL: name: a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
@@ -103,11 +103,11 @@ body: |
; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: $v0 = LI16_MM 0
- ; PIC: JRC16_MM undef $ra, implicit $v0
+ ; PIC: $r2 = LI16_MM 0
+ ; PIC: JRC16_MM undef $ra, implicit $r2
; PIC: bb.4.return:
- ; PIC: $v0 = LI16_MM 1
- ; PIC: JRC16_MM undef $ra, implicit $v0
+ ; PIC: $r2 = LI16_MM 1
+ ; PIC: JRC16_MM undef $ra, implicit $r2
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d12_64, $d14_64
@@ -117,12 +117,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- $v0 = LI16_MM 0
- PseudoReturn undef $ra, implicit $v0
+ $r2 = LI16_MM 0
+ PseudoReturn undef $ra, implicit $r2
bb.2.return:
- $v0 = LI16_MM 1
- PseudoReturn undef $ra, implicit $v0
+ $r2 = LI16_MM 1
+ PseudoReturn undef $ra, implicit $r2
...
---
@@ -170,11 +170,11 @@ body: |
; MM: BC_MMR6 %bb.3
; MM: bb.2.if.then:
; MM: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MM: $v0 = LI16_MM 0
- ; MM: JRC16_MM undef $ra, implicit $v0
+ ; MM: $r2 = LI16_MM 0
+ ; MM: JRC16_MM undef $ra, implicit $r2
; MM: bb.3.return:
- ; MM: $v0 = LI16_MM 1
- ; MM: JRC16_MM undef $ra, implicit $v0
+ ; MM: $r2 = LI16_MM 1
+ ; MM: JRC16_MM undef $ra, implicit $r2
; PIC-LABEL: name: b
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x30000000), %bb.1(0x50000000)
@@ -195,11 +195,11 @@ body: |
; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: $v0 = LI16_MM 0
- ; PIC: JRC16_MM undef $ra, implicit $v0
+ ; PIC: $r2 = LI16_MM 0
+ ; PIC: JRC16_MM undef $ra, implicit $r2
; PIC: bb.4.return:
- ; PIC: $v0 = LI16_MM 1
- ; PIC: JRC16_MM undef $ra, implicit $v0
+ ; PIC: $r2 = LI16_MM 1
+ ; PIC: JRC16_MM undef $ra, implicit $r2
bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $d12_64, $d14_64
@@ -209,11 +209,11 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- $v0 = LI16_MM 0
- PseudoReturn undef $ra, implicit $v0
+ $r2 = LI16_MM 0
+ PseudoReturn undef $ra, implicit $r2
bb.2.return:
- $v0 = LI16_MM 1
- PseudoReturn undef $ra, implicit $v0
+ $r2 = LI16_MM 1
+ PseudoReturn undef $ra, implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
index ef539c6c7f01a..0ca457ae56350 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
@@ -81,12 +81,12 @@ body: |
; MIPS: }
; MIPS: bb.2.if.then:
; MIPS: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
- ; MIPS: $v0 = ADDiu $zero, 0
+ ; MIPS: PseudoReturn undef $ra, implicit killed $r2 {
+ ; MIPS: $r2 = ADDiu $zero, 0
; MIPS: }
; MIPS: bb.3.return:
- ; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
- ; MIPS: $v0 = ADDiu $zero, 1
+ ; MIPS: PseudoReturn undef $ra, implicit killed $r2 {
+ ; MIPS: $r2 = ADDiu $zero, 1
; MIPS: }
; PIC-LABEL: name: a
; PIC: bb.0.entry:
@@ -112,12 +112,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
- ; PIC: $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $zero, 0
; PIC: }
; PIC: bb.4.return:
- ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
- ; PIC: $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $zero, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
@@ -128,12 +128,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
- $v0 = ADDiu $zero, 0
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = ADDiu $zero, 0
+ PseudoReturn undef $ra, implicit killed $r2
bb.2.return:
- $v0 = ADDiu $zero, 1
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = ADDiu $zero, 1
+ PseudoReturn undef $ra, implicit killed $r2
...
---
@@ -185,12 +185,12 @@ body: |
; MIPS: }
; MIPS: bb.2.if.then:
; MIPS: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
- ; MIPS: $v0 = ADDiu $zero, 0
+ ; MIPS: PseudoReturn undef $ra, implicit killed $r2 {
+ ; MIPS: $r2 = ADDiu $zero, 0
; MIPS: }
; MIPS: bb.3.return:
- ; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
- ; MIPS: $v0 = ADDiu $zero, 1
+ ; MIPS: PseudoReturn undef $ra, implicit killed $r2 {
+ ; MIPS: $r2 = ADDiu $zero, 1
; MIPS: }
; PIC-LABEL: name: b
; PIC: bb.0.entry:
@@ -216,12 +216,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
- ; PIC: $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $zero, 0
; PIC: }
; PIC: bb.4.return:
- ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
- ; PIC: $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $zero, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
@@ -232,11 +232,11 @@ body: |
bb.1.if.then:
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
- $v0 = ADDiu $zero, 0
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = ADDiu $zero, 0
+ PseudoReturn undef $ra, implicit killed $r2
bb.2.return:
- $v0 = ADDiu $zero, 1
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = ADDiu $zero, 1
+ PseudoReturn undef $ra, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
index 9ee5f20597fd4..a6250ba6f50b1 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
@@ -81,12 +81,12 @@ body: |
; R6: BC %bb.3
; R6: bb.2.if.then:
; R6: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; R6: PseudoReturn undef $ra, implicit killed $v0 {
- ; R6: $v0 = ADDiu $zero, 0
+ ; R6: PseudoReturn undef $ra, implicit killed $r2 {
+ ; R6: $r2 = ADDiu $zero, 0
; R6: }
; R6: bb.3.return:
- ; R6: PseudoReturn undef $ra, implicit killed $v0 {
- ; R6: $v0 = ADDiu $zero, 1
+ ; R6: PseudoReturn undef $ra, implicit killed $r2 {
+ ; R6: $r2 = ADDiu $zero, 1
; R6: }
; PIC-LABEL: name: a
; PIC: bb.0.entry:
@@ -110,12 +110,12 @@ body: |
; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
- ; PIC: $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $zero, 0
; PIC: }
; PIC: bb.4.return:
- ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
- ; PIC: $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $zero, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
@@ -126,12 +126,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
- $v0 = ADDiu $zero, 0
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = ADDiu $zero, 0
+ PseudoReturn undef $ra, implicit killed $r2
bb.2.return:
- $v0 = ADDiu $zero, 1
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = ADDiu $zero, 1
+ PseudoReturn undef $ra, implicit killed $r2
...
---
@@ -181,12 +181,12 @@ body: |
; R6: BC %bb.3
; R6: bb.2.if.then:
; R6: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; R6: PseudoReturn undef $ra, implicit killed $v0 {
- ; R6: $v0 = ADDiu $zero, 0
+ ; R6: PseudoReturn undef $ra, implicit killed $r2 {
+ ; R6: $r2 = ADDiu $zero, 0
; R6: }
; R6: bb.3.return:
- ; R6: PseudoReturn undef $ra, implicit killed $v0 {
- ; R6: $v0 = ADDiu $zero, 1
+ ; R6: PseudoReturn undef $ra, implicit killed $r2 {
+ ; R6: $r2 = ADDiu $zero, 1
; R6: }
; PIC-LABEL: name: b
; PIC: bb.0.entry:
@@ -210,12 +210,12 @@ body: |
; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
- ; PIC: $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $zero, 0
; PIC: }
; PIC: bb.4.return:
- ; PIC: PseudoReturn undef $ra, implicit killed $v0 {
- ; PIC: $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $zero, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
@@ -226,11 +226,11 @@ body: |
bb.1.if.then:
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
- $v0 = ADDiu $zero, 0
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = ADDiu $zero, 0
+ PseudoReturn undef $ra, implicit killed $r2
bb.2.return:
- $v0 = ADDiu $zero, 1
- PseudoReturn undef $ra, implicit killed $v0
+ $r2 = ADDiu $zero, 1
+ PseudoReturn undef $ra, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
index bb37d9feb3fa9..bebb66dfe29bd 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
@@ -694,8 +694,8 @@ body: |
; MM-LABEL: name: expand_BEQZ16_MM
; MM: bb.0 (%ir-block.0):
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MM: renamable $v0 = ANDi killed renamable $a0, 1
- ; MM: BNEZ16_MM $v0, %bb.2, implicit-def $at {
+ ; MM: renamable $r2 = ANDi killed renamable $a0, 1
+ ; MM: BNEZ16_MM $r2, %bb.2, implicit-def $at {
; MM: $zero = SLL_MM $zero, 0
; MM: }
; MM: bb.1 (%ir-block.0):
@@ -711,8 +711,8 @@ body: |
; PIC-LABEL: name: expand_BEQZ16_MM
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $v0 = ANDi killed renamable $a0, 1
- ; PIC: BNEZ16_MM $v0, %bb.3, implicit-def $at {
+ ; PIC: renamable $r2 = ANDi killed renamable $a0, 1
+ ; PIC: BNEZ16_MM $r2, %bb.3, implicit-def $at {
; PIC: $zero = SLL_MM $zero, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
@@ -739,8 +739,8 @@ body: |
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0
- renamable $v0 = ANDi killed renamable $a0, 1
- BEQZ16_MM killed renamable $v0, %bb.2, implicit-def $at
+ renamable $r2 = ANDi killed renamable $a0, 1
+ BEQZ16_MM killed renamable $r2, %bb.2, implicit-def $at
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -789,8 +789,8 @@ body: |
; MM-LABEL: name: expand_BNEZ16_MM
; MM: bb.0 (%ir-block.0):
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MM: renamable $v0 = ANDi killed renamable $a0, 1
- ; MM: BEQZ16_MM $v0, %bb.2, implicit-def $at {
+ ; MM: renamable $r2 = ANDi killed renamable $a0, 1
+ ; MM: BEQZ16_MM $r2, %bb.2, implicit-def $at {
; MM: $zero = SLL_MM $zero, 0
; MM: }
; MM: bb.1 (%ir-block.0):
@@ -806,8 +806,8 @@ body: |
; PIC-LABEL: name: expand_BNEZ16_MM
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $v0 = ANDi killed renamable $a0, 1
- ; PIC: BEQZ16_MM $v0, %bb.3, implicit-def $at {
+ ; PIC: renamable $r2 = ANDi killed renamable $a0, 1
+ ; PIC: BEQZ16_MM $r2, %bb.3, implicit-def $at {
; PIC: $zero = SLL_MM $zero, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
@@ -834,8 +834,8 @@ body: |
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0
- renamable $v0 = ANDi killed renamable $a0, 1
- BNEZ16_MM killed renamable $v0, %bb.2, implicit-def $at
+ renamable $r2 = ANDi killed renamable $a0, 1
+ BNEZ16_MM killed renamable $r2, %bb.2, implicit-def $at
bb.1.iftrue:
successors: %bb.2(0x80000000)
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
index 6a19a5b6db717..94c97f5c0d05d 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
@@ -126,12 +126,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BEQ64
; PIC: bb.0 (%ir-block.0):
@@ -157,12 +157,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -172,12 +172,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -228,12 +228,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BNE64
; PIC: bb.0 (%ir-block.0):
@@ -259,12 +259,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -274,12 +274,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -330,12 +330,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEZ64
; PIC: bb.0 (%ir-block.0):
@@ -361,12 +361,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -376,12 +376,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -432,12 +432,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGTZ64
; PIC: bb.0 (%ir-block.0):
@@ -463,12 +463,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -478,12 +478,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -534,12 +534,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLEZ64
; PIC: bb.0 (%ir-block.0):
@@ -565,12 +565,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -580,12 +580,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -636,12 +636,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTZ64
; PIC: bb.0 (%ir-block.0):
@@ -667,12 +667,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -682,11 +682,11 @@ body: |
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
index 9634eebb8e79e..67ad61d45636a 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
@@ -191,12 +191,12 @@ body: |
; MIPS64: BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
; MIPS64: bb.1.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.2.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BNEZC64
; PIC: bb.0 (%ir-block.0):
@@ -204,12 +204,12 @@ body: |
; PIC: BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
; PIC: bb.1.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.2.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -219,12 +219,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -268,12 +268,12 @@ body: |
; MIPS64: BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
; MIPS64: bb.1.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.2.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BEQZC64
; PIC: bb.0 (%ir-block.0):
@@ -281,12 +281,12 @@ body: |
; PIC: BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
; PIC: bb.1.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.2.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -296,12 +296,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -350,12 +350,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BNEC64
; PIC: bb.0 (%ir-block.0):
@@ -379,12 +379,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -394,12 +394,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -448,12 +448,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BEQC64
; PIC: bb.0 (%ir-block.0):
@@ -477,12 +477,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -492,12 +492,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -546,12 +546,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTC64
; PIC: bb.0 (%ir-block.0):
@@ -575,12 +575,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -590,12 +590,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -644,12 +644,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTUC64
; PIC: bb.0 (%ir-block.0):
@@ -673,12 +673,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -688,12 +688,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -742,12 +742,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEC64
; PIC: bb.0 (%ir-block.0):
@@ -771,12 +771,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -786,12 +786,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -840,12 +840,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEUC64
; PIC: bb.0 (%ir-block.0):
@@ -869,12 +869,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -884,12 +884,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -938,12 +938,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLEZC64
; PIC: bb.0 (%ir-block.0):
@@ -967,12 +967,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -982,12 +982,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -1036,12 +1036,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTZC64
; PIC: bb.0 (%ir-block.0):
@@ -1065,12 +1065,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1080,12 +1080,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -1134,12 +1134,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEZC64
; PIC: bb.0 (%ir-block.0):
@@ -1163,12 +1163,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1178,12 +1178,12 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
---
@@ -1232,12 +1232,12 @@ body: |
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; MIPS64: $v0_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGTZC64
; PIC: bb.0 (%ir-block.0):
@@ -1261,12 +1261,12 @@ body: |
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
- ; PIC: $v0_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1276,11 +1276,11 @@ body: |
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $v0_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
bb.2.tail:
- $v0_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0_64
+ $r2_64 = DADDiu $zero_64, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
index 2e01a99033a38..2b010d7d89e91 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
@@ -272,12 +272,12 @@ body: |
; MSA: }
; MSA: bb.2.if.then:
; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 0
; MSA: }
; PIC-LABEL: name: _Z4bz_8Dv16_a
; PIC: bb.0.entry:
@@ -308,12 +308,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -328,12 +328,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $v0 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2
bb.2:
- renamable $v0 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2
...
---
@@ -388,12 +388,12 @@ body: |
; MSA: }
; MSA: bb.2.if.then:
; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 0
; MSA: }
; PIC-LABEL: name: _Z5bz_16Dv8_s
; PIC: bb.0.entry:
@@ -423,12 +423,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -442,12 +442,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $v0 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2
bb.2:
- renamable $v0 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2
...
---
@@ -502,12 +502,12 @@ body: |
; MSA: }
; MSA: bb.2.if.then:
; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 0
; MSA: }
; PIC-LABEL: name: _Z5bz_32Dv4_i
; PIC: bb.0.entry:
@@ -537,12 +537,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -556,12 +556,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $v0 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2
bb.2:
- renamable $v0 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2
...
---
@@ -615,12 +615,12 @@ body: |
; MSA: }
; MSA: bb.2.if.then:
; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 0
; MSA: }
; PIC-LABEL: name: _Z5bz_64Dv2_x
; PIC: bb.0.entry:
@@ -649,12 +649,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -667,12 +667,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $v0 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2
bb.2:
- renamable $v0 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2
...
---
@@ -726,12 +726,12 @@ body: |
; MSA: }
; MSA: bb.2.if.then:
; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 0
; MSA: }
; PIC-LABEL: name: _Z5bz_64_vDv2_x
; PIC: bb.0.entry:
@@ -760,12 +760,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -778,12 +778,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $v0 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2
bb.2:
- renamable $v0 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2
...
---
@@ -839,12 +839,12 @@ body: |
; MSA: }
; MSA: bb.2.if.then:
; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 0
; MSA: }
; PIC-LABEL: name: _Z5bnz_8Dv16_a
; PIC: bb.0.entry:
@@ -875,12 +875,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -895,12 +895,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $v0 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2
bb.2:
- renamable $v0 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2
...
---
@@ -955,12 +955,12 @@ body: |
; MSA: }
; MSA: bb.2.if.then:
; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 0
; MSA: }
; PIC-LABEL: name: _Z6bnz_16Dv8_s
; PIC: bb.0.entry:
@@ -990,12 +990,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1009,12 +1009,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $v0 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2
bb.2:
- renamable $v0 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2
...
---
@@ -1069,12 +1069,12 @@ body: |
; MSA: }
; MSA: bb.2.if.then:
; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 0
; MSA: }
; PIC-LABEL: name: _Z6bnz_32Dv4_i
; PIC: bb.0.entry:
@@ -1104,12 +1104,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1123,12 +1123,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $v0 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2
bb.2:
- renamable $v0 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2
...
---
@@ -1182,12 +1182,12 @@ body: |
; MSA: }
; MSA: bb.2.if.then:
; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 0
; MSA: }
; PIC-LABEL: name: _Z6bnz_64Dv2_x
; PIC: bb.0.entry:
@@ -1216,12 +1216,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1234,12 +1234,12 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $v0 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2
bb.2:
- renamable $v0 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2
...
---
@@ -1293,12 +1293,12 @@ body: |
; MSA: }
; MSA: bb.2.if.then:
; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 1
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; MSA: renamable $v0 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $zero, 0
; MSA: }
; PIC-LABEL: name: _Z6bnz_64_vDv2_x
; PIC: bb.0.entry:
@@ -1327,12 +1327,12 @@ body: |
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 1
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
- ; PIC: renamable $v0 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $zero, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1345,11 +1345,11 @@ body: |
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $v0 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 1
+ PseudoReturn64 undef $ra_64, implicit killed $r2
bb.2:
- renamable $v0 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $v0
+ renamable $r2 = ADDiu $zero, 0
+ PseudoReturn64 undef $ra_64, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/micromips-eva.mir b/llvm/test/CodeGen/Mips/micromips-eva.mir
index 90bcefa431f6e..f3a58ef94c3c0 100644
--- a/llvm/test/CodeGen/Mips/micromips-eva.mir
+++ b/llvm/test/CodeGen/Mips/micromips-eva.mir
@@ -189,10 +189,10 @@ body: |
bb.2.entry:
SYNC 0
%5:gpr32 = ADDiu killed %4, 42
- $v0 = COPY %5
+ $r2 = COPY %5
CACHEE %1, 5, 2
PREFE %1, 5, 2
- RetRA implicit $v0
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll b/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
index 3519f019dd554..85262983c0a27 100644
--- a/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
+++ b/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
@@ -8,51 +8,51 @@ define i64 @test(i32 signext %a, i32 signext %b) {
; MMR2-LABEL: test:
; MMR2: # %bb.0: # %entry
; MMR2-NEXT: li16 $2, 0 # <MCInst #[[#MCINST1:]] LI16_MM
-; MMR2-NEXT: # <MCOperand Reg:V0>
+; MMR2-NEXT: # <MCOperand Reg:R2>
; MMR2-NEXT: # <MCOperand Imm:0>>
; MMR2-NEXT: li16 $3, 1 # <MCInst #[[#MCINST1]] LI16_MM
-; MMR2-NEXT: # <MCOperand Reg:V1>
+; MMR2-NEXT: # <MCOperand Reg:R3>
; MMR2-NEXT: # <MCOperand Imm:1>>
; MMR2-NEXT: mtlo $3 # <MCInst #[[#MCINST2:]] MTLO_MM
-; MMR2-NEXT: # <MCOperand Reg:V1>>
+; MMR2-NEXT: # <MCOperand Reg:R3>>
; MMR2-NEXT: mthi $2 # <MCInst #[[#MCINST3:]] MTHI_MM
-; MMR2-NEXT: # <MCOperand Reg:V0>>
+; MMR2-NEXT: # <MCOperand Reg:R2>>
; MMR2-NEXT: madd $4, $5 # <MCInst #[[#MCINST4:]] MADD
; MMR2-NEXT: # <MCOperand Reg:A0>
; MMR2-NEXT: # <MCOperand Reg:A1>>
; MMR2-NEXT: mflo16 $2 # <MCInst #[[#MCINST5:]] MFLO16_MM
-; MMR2-NEXT: # <MCOperand Reg:V0>>
+; MMR2-NEXT: # <MCOperand Reg:R2>>
; MMR2-NEXT: mfhi16 $3 # <MCInst #[[#MCINST6:]] MFHI16_MM
-; MMR2-NEXT: # <MCOperand Reg:V1>>
+; MMR2-NEXT: # <MCOperand Reg:R3>>
; MMR2-NEXT: jrc $ra # <MCInst #[[#MCINST7:]] JRC16_MM
; MMR2-NEXT: # <MCOperand Reg:RA>>
;
; MMR2-DSP-LABEL: test:
; MMR2-DSP: # %bb.0: # %entry
; MMR2-DSP-NEXT: li16 $2, 0 # <MCInst #[[#MCINST1:]] LI16_MM
-; MMR2-DSP-NEXT: # <MCOperand Reg:V0>
+; MMR2-DSP-NEXT: # <MCOperand Reg:R2>
; MMR2-DSP-NEXT: # <MCOperand Imm:0>>
; MMR2-DSP-NEXT: li16 $3, 1 # <MCInst #[[#MCINST1]] LI16_MM
-; MMR2-DSP-NEXT: # <MCOperand Reg:V1>
+; MMR2-DSP-NEXT: # <MCOperand Reg:R3>
; MMR2-DSP-NEXT: # <MCOperand Imm:1>>
; MMR2-DSP-NEXT: mtlo $3, $ac0 # <MCInst #[[#MCINST8:]] MTLO_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:LO0>
-; MMR2-DSP-NEXT: # <MCOperand Reg:V1>>
+; MMR2-DSP-NEXT: # <MCOperand Reg:R3>>
; MMR2-DSP-NEXT: mthi $2, $ac0 # <MCInst #[[#MCINST9:]] MTHI_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:HI0>
-; MMR2-DSP-NEXT: # <MCOperand Reg:V0>>
+; MMR2-DSP-NEXT: # <MCOperand Reg:R2>>
; MMR2-DSP-NEXT: madd $ac0, $4, $5 # <MCInst #[[#MCINST10:]] MADD_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:AC0>
; MMR2-DSP-NEXT: # <MCOperand Reg:A0>
; MMR2-DSP-NEXT: # <MCOperand Reg:A1>
; MMR2-DSP-NEXT: # <MCOperand Reg:AC0>>
; MMR2-DSP-NEXT: mflo $2, $ac0 # <MCInst #[[#MCINST11:]] MFLO_DSP
-; MMR2-DSP-NEXT: # <MCOperand Reg:V0>
+; MMR2-DSP-NEXT: # <MCOperand Reg:R2>
; MMR2-DSP-NEXT: # <MCOperand Reg:AC0>>
; MMR2-DSP-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM
; MMR2-DSP-NEXT: # <MCOperand Reg:RA>>
; MMR2-DSP-NEXT: mfhi $3, $ac0 # <MCInst #[[#MCINST13:]] MFHI_DSP
-; MMR2-DSP-NEXT: # <MCOperand Reg:V1>
+; MMR2-DSP-NEXT: # <MCOperand Reg:R3>
; MMR2-DSP-NEXT: # <MCOperand Reg:AC0>>
entry:
%conv = sext i32 %a to i64
diff --git a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
index 4d1ba43f06ead..37a20acf7f991 100644
--- a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
+++ b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
@@ -62,10 +62,10 @@ body: |
CFI_INSTRUCTION offset $ra_64, -4
$a0 = LI16_MM 1
$a1 = LI16_MM 2
- JAL_MM @callee13, csr_o32, implicit-def dead $ra, implicit killed $a0, implicit killed $a1, implicit-def $sp, implicit-def $v0
+ JAL_MM @callee13, csr_o32, implicit-def dead $ra, implicit killed $a0, implicit killed $a1, implicit-def $sp, implicit-def $r2
$ra = LW $sp, 20 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit $v0
+ PseudoReturn undef $ra, implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
index 5a14ccbb96b31..b2b057259d584 100644
--- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
@@ -72,14 +72,14 @@ body: |
CFI_INSTRUCTION offset $s0_64, -12
$s1 = MOVE16_MM $a1
$s0 = MOVE16_MM $a0
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store (s32) into %ir.adr)
- $v0 = LI16_MM 0
+ $r2 = LI16_MM 0
$s0 = LW $sp, 20 :: (load (s32) from %stack.2)
$s1 = LW $sp, 24 :: (load (s32) from %stack.1)
$ra = LW $sp, 28 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 32
- PseudoReturn undef $ra, implicit killed $v0
+ PseudoReturn undef $ra, implicit killed $r2
...
---
@@ -140,14 +140,14 @@ body: |
CFI_INSTRUCTION offset $s0_64, -12
$s1 = MOVE16_MM $a1
$s0 = MOVE16_MM $a0
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store (s32) into %ir.adr)
- $v0 = LI16_MM 0
+ $r2 = LI16_MM 0
$s0 = LW_MM $sp, 20 :: (load (s32) from %stack.2)
$s1 = LW_MM $sp, 24 :: (load (s32) from %stack.1)
$ra = LW $sp, 28 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 32
- PseudoReturn undef $ra, implicit killed $v0
+ PseudoReturn undef $ra, implicit killed $r2
...
---
@@ -208,14 +208,14 @@ body: |
CFI_INSTRUCTION offset $s0_64, -12
$s1 = MOVE16_MM $a1
$s0 = MOVE16_MM $a0
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store (s32) into %ir.adr)
- $v0 = LI16_MM 0
+ $r2 = LI16_MM 0
$s0 = LW_MM $sp, 20 :: (load (s32) from %stack.2)
$s1 = LW $sp, 24 :: (load (s32) from %stack.1)
$ra = LW $sp, 28 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 32
- PseudoReturn undef $ra, implicit killed $v0
+ PseudoReturn undef $ra, implicit killed $r2
...
---
@@ -276,14 +276,14 @@ body: |
CFI_INSTRUCTION offset $s0_64, -12
$s1 = MOVE16_MM $a1
$s0 = MOVE16_MM $a0
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store (s32) into %ir.adr)
- $v0 = LI16_MM 0
+ $r2 = LI16_MM 0
$s0 = LW $sp, 20 :: (load (s32) from %stack.2)
$s1 = LW_MM $sp, 24 :: (load (s32) from %stack.1)
$ra = LW $sp, 28 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 32
- PseudoReturn undef $ra, implicit killed $v0
+ PseudoReturn undef $ra, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-movep.mir b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-movep.mir
index 37bf0a798157d..e46352c169ee9 100644
--- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-movep.mir
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-movep.mir
@@ -27,23 +27,23 @@ body: |
; CHECK: CFI_INSTRUCTION def_cfa_offset 24
; CHECK: SWSP_MM killed $ra, $sp, 20 :: (store (s32) into %stack.0)
; CHECK: CFI_INSTRUCTION offset $ra_64, -4
- ; CHECK: JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $v0, implicit-def $v1
- ; CHECK: $a0, $a1 = MOVEP_MM $v0, $v1
- ; CHECK: JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $v0, implicit-def $v1
+ ; CHECK: JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $r2, implicit-def $r3
+ ; CHECK: $a0, $a1 = MOVEP_MM $r2, $r3
+ ; CHECK: JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $r2, implicit-def $r3
; CHECK: $ra = LWSP_MM $sp, 20 :: (load (s32) from %stack.0)
; CHECK: ADDIUSP_MM 24
- ; CHECK: PseudoReturn undef $ra, implicit $v0, implicit $v1
+ ; CHECK: PseudoReturn undef $ra, implicit $r2, implicit $r3
$sp = ADDiu $sp, -24
CFI_INSTRUCTION def_cfa_offset 24
SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
CFI_INSTRUCTION offset $ra_64, -4
- JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $v0, implicit-def $v1
- $a0 = MOVE16_MM $v0
- $a1 = MOVE16_MM $v1
- JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $v0, implicit-def $v1
+ JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $r2, implicit-def $r3
+ $a0 = MOVE16_MM $r2
+ $a1 = MOVE16_MM $r3
+ JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $r2, implicit-def $r3
$ra = LW $sp, 20 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit $v0, implicit $v1
+ PseudoReturn undef $ra, implicit $r2, implicit $r3
...
---
@@ -62,23 +62,23 @@ body: |
; CHECK: CFI_INSTRUCTION def_cfa_offset 24
; CHECK: SWSP_MM killed $ra, $sp, 20 :: (store (s32) into %stack.0)
; CHECK: CFI_INSTRUCTION offset $ra_64, -4
- ; CHECK: JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $v0, implicit-def $v1
- ; CHECK: $a0, $a1 = MOVEP_MM $v0, $v1
- ; CHECK: JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $v0, implicit-def $v1
+ ; CHECK: JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $r2, implicit-def $r3
+ ; CHECK: $a0, $a1 = MOVEP_MM $r2, $r3
+ ; CHECK: JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $r2, implicit-def $r3
; CHECK: $ra = LWSP_MM $sp, 20 :: (load (s32) from %stack.0)
; CHECK: ADDIUSP_MM 24
- ; CHECK: PseudoReturn undef $ra, implicit $v0, implicit $v1
+ ; CHECK: PseudoReturn undef $ra, implicit $r2, implicit $r3
$sp = ADDiu $sp, -24
CFI_INSTRUCTION def_cfa_offset 24
SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
CFI_INSTRUCTION offset $ra_64, -4
- JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $v0, implicit-def $v1
- $a1 = MOVE16_MM $v1
- $a0 = MOVE16_MM $v0
- JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $v0, implicit-def $v1
+ JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $r2, implicit-def $r3
+ $a1 = MOVE16_MM $r3
+ $a0 = MOVE16_MM $r2
+ JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $r2, implicit-def $r3
$ra = LW $sp, 20 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit $v0, implicit $v1
+ PseudoReturn undef $ra, implicit $r2, implicit $r3
...
---
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
index 18eb341de3681..70d7fdcd2690c 100644
--- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
@@ -64,12 +64,12 @@ body: |
CFI_INSTRUCTION offset $ra_64, -4
CFI_INSTRUCTION offset $s0_64, -8
$s0 = MOVE16_MM $a1
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
- $v0 = MOVE16_MM killed $s0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
+ $r2 = MOVE16_MM killed $s0
$s0 = LW $sp, 16 :: (load (s32) from %stack.1)
$ra = LW $sp, 20 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit killed $v0
+ PseudoReturn undef $ra, implicit killed $r2
...
---
@@ -123,12 +123,12 @@ body: |
CFI_INSTRUCTION offset $ra_64, -4
CFI_INSTRUCTION offset $s0_64, -8
$s0 = MOVE16_MM $a1
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
- $v0 = MOVE16_MM killed $s0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
+ $r2 = MOVE16_MM killed $s0
$s0 = LW_MM $sp, 16 :: (load (s32) from %stack.1)
$ra = LW_MM $sp, 20 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit killed $v0
+ PseudoReturn undef $ra, implicit killed $r2
...
---
@@ -182,12 +182,12 @@ body: |
CFI_INSTRUCTION offset $ra_64, -4
CFI_INSTRUCTION offset $s0_64, -8
$s0 = MOVE16_MM $a1
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
- $v0 = MOVE16_MM killed $s0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
+ $r2 = MOVE16_MM killed $s0
$s0 = LW_MM $sp, 16 :: (load (s32) from %stack.1)
$ra = LW $sp, 20 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit killed $v0
+ PseudoReturn undef $ra, implicit killed $r2
...
---
@@ -241,12 +241,12 @@ body: |
CFI_INSTRUCTION offset $ra_64, -4
CFI_INSTRUCTION offset $s0_64, -8
$s0 = MOVE16_MM $a1
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
- $v0 = MOVE16_MM killed $s0
+ JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
+ $r2 = MOVE16_MM killed $s0
$s0 = LW $sp, 16 :: (load (s32) from %stack.1)
$ra = LW_MM $sp, 20 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit killed $v0
+ PseudoReturn undef $ra, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll
index fb150094d5678..0cf6e7198c5e2 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128.ll
@@ -2780,9 +2780,9 @@ entry:
define fp128 @select_LD(i32 signext %a, i64, fp128 %b, fp128 %c) {
; C_CC_FMT-LABEL: select_LD:
; C_CC_FMT: # %bb.0: # %entry
-; C_CC_FMT-NEXT: movn $8, $6, $4
-; C_CC_FMT-NEXT: movn $9, $7, $4
; C_CC_FMT-NEXT: move $2, $8
+; C_CC_FMT-NEXT: movn $2, $6, $4
+; C_CC_FMT-NEXT: movn $9, $7, $4
; C_CC_FMT-NEXT: move $4, $9
; C_CC_FMT-NEXT: jr $ra
; C_CC_FMT-NEXT: nop
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
index 3b1fc43e5dc72..2a1e5abb15d6a 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
@@ -156,9 +156,9 @@ body: |
%9 = LD killed %8, target-flags(mips-call-lo16) @_Z1gi :: (load (s64) from call-entry @_Z1gi)
$a0_64 = COPY %5
$gp_64 = COPY %6
- JALR64Pseudo killed %9, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ JALR64Pseudo killed %9, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- %10 = COPY $v0
+ %10 = COPY $r2
%11 = COPY %5.sub_32
%12 = ADDu %10, killed %11
%13 = LUi64 target-flags(mips-got-hi16) @v
@@ -173,9 +173,9 @@ body: |
%20 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
$a0_64 = COPY %20
$gp_64 = COPY %6
- JALR64Pseudo killed %19, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ JALR64Pseudo killed %19, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- %21 = COPY $v0_64
+ %21 = COPY $r2_64
%22 = DADDiu %21, target-flags(mips-dtprel-hi) @__tls_guard
%23 = LBu killed %22, target-flags(mips-dtprel-lo) @__tls_guard :: (dereferenceable load (s8) from @__tls_guard)
BEQ killed %23, $zero, %bb.2.init.i.i, implicit-def dead $at
@@ -191,9 +191,9 @@ body: |
%42 = DADDiu %6, target-flags(mips-tlsgd) @k
$a0_64 = COPY %42
$gp_64 = COPY %6
- JALR64Pseudo killed %41, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ JALR64Pseudo killed %41, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- %43 = COPY $v0_64
+ %43 = COPY $r2_64
%1 = LW %43, 0 :: (dereferenceable load (s32) from @k)
B %bb.3._ZTW1k.exit, implicit-def dead $at
@@ -207,9 +207,9 @@ body: |
%27 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
$a0_64 = COPY %27
$gp_64 = COPY %6
- JALR64Pseudo killed %26, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ JALR64Pseudo killed %26, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- %28 = COPY $v0_64
+ %28 = COPY $r2_64
%29 = DADDiu %28, target-flags(mips-dtprel-hi) @__tls_guard
%30 = ADDiu $zero, 1
SB killed %30, killed %29, target-flags(mips-dtprel-lo) @__tls_guard :: (store (s8) into @__tls_guard)
@@ -220,17 +220,17 @@ body: |
%34 = LD killed %32, target-flags(mips-call-lo16) @_Z1gi :: (load (s64) from call-entry @_Z1gi)
$a0_64 = COPY %33
$gp_64 = COPY %6
- JALR64Pseudo killed %34, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ JALR64Pseudo killed %34, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- %35 = COPY $v0
+ %35 = COPY $r2
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%36 = LD %25, target-flags(mips-call-lo16) &__tls_get_addr :: (load (s64) from call-entry &__tls_get_addr)
%37 = DADDiu %6, target-flags(mips-tlsgd) @k
$a0_64 = COPY %37
$gp_64 = COPY %6
- JALR64Pseudo killed %36, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ JALR64Pseudo killed %36, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- %38 = COPY $v0_64
+ %38 = COPY $r2_64
SW %35, %38, 0 :: (store (s32) into @k)
%2 = COPY %35
@@ -264,13 +264,13 @@ body: |
%53 = DADDiu %6, target-flags(mips-tlsgd) @j
$a0_64 = COPY %53
$gp_64 = COPY %6
- JALR64Pseudo killed %52, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ JALR64Pseudo killed %52, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- %54 = COPY $v0_64
+ %54 = COPY $r2_64
%55 = LW %54, 0 :: (dereferenceable load (s32) from @j)
%56 = ADDu %4, killed %55
- $v0 = COPY %56
- RetRA implicit $v0
+ $r2 = COPY %56
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
index 972899b13810b..c2b158dd7fb19 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
@@ -47,7 +47,7 @@ registers:
liveins:
- { reg: '$a0', virtual-reg: '%0' }
- { reg: '$t9', virtual-reg: '' }
- - { reg: '$v0', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -70,17 +70,17 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0, $t9, $v0
+ liveins: $a0, $t9, $r2
- %1 = ADDu $v0, $t9
+ %1 = ADDu $r2, $t9
%0 = COPY $a0
ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp
%2 = LW %1, target-flags(mips-got-call) @_Z1gi :: (load (s32) from call-entry @_Z1gi)
$a0 = COPY %0
$gp = COPY %1
- JALRPseudo killed %2, csr_o32_fpxx, implicit-def dead $ra, implicit $a0, implicit $gp, implicit-def $sp, implicit-def $v0
+ JALRPseudo killed %2, csr_o32_fpxx, implicit-def dead $ra, implicit $a0, implicit $gp, implicit-def $sp, implicit-def $r2
ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp
- %3 = COPY $v0
+ %3 = COPY $r2
%4 = ADDu %3, %0
%5 = LW %1, target-flags(mips-got) @v :: (load (s32) from got)
%6 = LW killed %5, 0 :: (dereferenceable load (s32) from @v)
@@ -88,8 +88,8 @@ body: |
%8 = LW %1, target-flags(mips-got) @j :: (load (s32) from got)
%9 = LW killed %8, 0 :: (dereferenceable load (s32) from @j)
%10 = ADDu killed %7, killed %9
- $v0 = COPY %10
- RetRA implicit $v0
+ $r2 = COPY %10
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
index 7c6b856414563..0b312c5b2da73 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
@@ -80,9 +80,9 @@ body: |
%2 = LD %1, target-flags(mips-got-call) @_Z1gi :: (load (s64) from call-entry @_Z1gi)
$a0_64 = COPY %0
$gp_64 = COPY %1
- JALR64Pseudo killed %2, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ JALR64Pseudo killed %2, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- %3 = COPY $v0
+ %3 = COPY $r2
%4 = COPY %0.sub_32
%5 = ADDu %3, killed %4
%6 = LD %1, target-flags(mips-got-disp) @v :: (load (s64) from got)
@@ -91,8 +91,8 @@ body: |
%9 = LD %1, target-flags(mips-got-disp) @j :: (load (s64) from got)
%10 = LW killed %9, 0 :: (dereferenceable load (s32) from @j)
%11 = ADDu killed %8, killed %10
- $v0 = COPY %11
- RetRA implicit $v0
+ $r2 = COPY %11
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
index b0ea8ea2bb8cc..45598990e4c19 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
@@ -145,9 +145,9 @@ body: |
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%6 = COPY %5.sub_32
$a0_64 = COPY %5
- JAL @_Z1gi, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0
+ JAL @_Z1gi, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- %7 = COPY $v0
+ %7 = COPY $r2
%8 = ADDu %7, killed %6
%9 = LUi64 target-flags(mips-highest) @v
%10 = DADDiu killed %9, target-flags(mips-higher) @v
@@ -159,8 +159,8 @@ body: |
%15 = LUi64 target-flags(mips-tprel-hi) @__tls_guard
%16 = DADDiu killed %15, target-flags(mips-tprel-lo) @__tls_guard
%17 = RDHWR64 $hwr29, 0
- $v1_64 = COPY %17
- %18 = COPY $v1_64
+ $r3_64 = COPY %17
+ %18 = COPY $r3_64
%19 = DADDu %18, killed %16
%20 = LBu killed %19, 0 :: (dereferenceable load (s8) from @__tls_guard)
BEQ killed %20, $zero, %bb.2.init.i.i, implicit-def dead $at
@@ -172,8 +172,8 @@ body: |
%32 = LUi64 target-flags(mips-tprel-hi) @k
%33 = DADDiu killed %32, target-flags(mips-tprel-lo) @k
%34 = RDHWR64 $hwr29, 0
- $v1_64 = COPY %34
- %35 = COPY $v1_64
+ $r3_64 = COPY %34
+ %35 = COPY $r3_64
%36 = DADDu %35, killed %33
%1 = LW killed %36, 0 :: (dereferenceable load (s32) from @k)
J %bb.3._ZTW1k.exit, implicit-def dead $at
@@ -184,8 +184,8 @@ body: |
%21 = LUi64 target-flags(mips-tprel-hi) @__tls_guard
%22 = DADDiu killed %21, target-flags(mips-tprel-lo) @__tls_guard
%23 = RDHWR64 $hwr29, 0
- $v1_64 = COPY %23
- %24 = COPY $v1_64
+ $r3_64 = COPY %23
+ %24 = COPY $r3_64
%25 = DADDu %24, killed %22
%26 = ADDiu $zero, 1
SB killed %26, killed %25, 0 :: (store (s8) into @__tls_guard)
@@ -195,9 +195,9 @@ body: |
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%30 = DADDiu $zero_64, 3
$a0_64 = COPY %30
- JAL @_Z1gi, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0
+ JAL @_Z1gi, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- %31 = COPY $v0
+ %31 = COPY $r2
SW %31, killed %29, 0 :: (store (s32) into @k)
%2 = COPY %31
@@ -224,14 +224,14 @@ body: |
bb.5._ZTW1j.exit:
%44 = RDHWR64 $hwr29, 0
- $v1_64 = COPY %44
+ $r3_64 = COPY %44
%45 = LD %43, target-flags(mips-gottprel) @j :: (load (s64))
- %46 = COPY $v1_64
+ %46 = COPY $r3_64
%47 = DADDu %46, killed %45
%48 = LW killed %47, 0 :: (dereferenceable load (s32) from @j)
%49 = ADDu %4, killed %48
- $v0 = COPY %49
- RetRA implicit $v0
+ $r2 = COPY %49
+ RetRA implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
index 0111758018413..63bb2d2eef4ed 100644
--- a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
+++ b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
@@ -81,7 +81,7 @@ liveins:
- { reg: '$a1_64', virtual-reg: '' }
- { reg: '$a2_64', virtual-reg: '' }
- { reg: '$a3_64', virtual-reg: '' }
- - { reg: '$t0_64', virtual-reg: '' }
+ - { reg: '$r8_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -131,7 +131,7 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64, $a1_64, $a2_64, $a3_64, $t0_64
+ liveins: $a0_64, $a1_64, $a2_64, $a3_64, $r8_64
SD killed $a0_64, %stack.1.a, 0 :: (store (s64) into %ir.1, align 16)
SD killed $a1_64, %stack.1.a, 8 :: (store (s64) into %ir.2)
@@ -141,7 +141,7 @@ body: |
$w1 = LD_B %stack.2.b, 0 :: (dereferenceable load (s128) from %ir.b)
ST_B killed $w0, %stack.3.a.addr, 0 :: (store (s128) into %ir.a.addr)
ST_B killed $w1, %stack.4.b.addr, 0 :: (store (s128) into %ir.b.addr)
- SW $t0, %stack.5.c.addr, 0, implicit killed $t0_64 :: (store (s32) into %ir.c.addr)
+ SW $r8, %stack.5.c.addr, 0, implicit killed $r8_64 :: (store (s32) into %ir.c.addr)
$at_64 = LEA_ADDiu64 %stack.8, 0
SD killed $at_64, %stack.6.g, 0 :: (store (s64) into %ir.g)
$a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
@@ -150,20 +150,20 @@ body: |
JAL @h, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1_64, implicit-def $sp
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
$at_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $v0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $v1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$a0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$a2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$a3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $t0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $t1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $t2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $t3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $t4_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $t5_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $t6_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $t7_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r8_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r9_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r10_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r11_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r12_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r13_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r14_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r15_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$s0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$s1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$s2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
@@ -177,20 +177,20 @@ body: |
$ra_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load (s128) from %ir.a.addr)
SD $at_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $v0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $v1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $a0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $a1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $a2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $a3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $t0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $t1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $t2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $t3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $t4_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $t5_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $t6_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $t7_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r8_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r9_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r10_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r11_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r12_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r13_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r14_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r15_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $s0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $s1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $s2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
@@ -203,8 +203,8 @@ body: |
SD $t9_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $ra_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
$at_64 = LD %stack.7.d, 0 :: (dereferenceable load (s64) from %ir.d)
- $v0 = LB $at_64, 0 :: (load (s8) from %ir.arrayidx)
- $w1 = FILL_B killed $v0
+ $r2 = LB $at_64, 0 :: (load (s8) from %ir.arrayidx)
+ $w1 = FILL_B killed $r2
$w0 = ADDV_B killed $w0, killed $w1
$at = LB killed $at_64, 1 :: (load (s8) from %ir.arrayidx3)
$w1 = FILL_B killed $at
@@ -214,8 +214,8 @@ body: |
ST_B killed $w0, %stack.4.b.addr, 0 :: (store (s128) into %ir.b.addr)
$w0 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load (s128) from %ir.b.addr)
ST_B killed $w0, %stack.0.retval, 0 :: (store (s128) into %ir.retval)
- $v0_64 = LD %stack.0.retval, 0 :: (dereferenceable load (s64) from %ir.20, basealign 16)
- $v1_64 = LD %stack.0.retval, 8 :: (dereferenceable load (s64) from %ir.20 + 8, basealign 16)
- RetRA implicit $v0_64, implicit $v1_64
+ $r2_64 = LD %stack.0.retval, 0 :: (dereferenceable load (s64) from %ir.20, basealign 16)
+ $r3_64 = LD %stack.0.retval, 8 :: (dereferenceable load (s64) from %ir.20 + 8, basealign 16)
+ RetRA implicit $r2_64, implicit $r3_64
...
diff --git a/llvm/test/CodeGen/Mips/msa/ldr_str.ll b/llvm/test/CodeGen/Mips/msa/ldr_str.ll
index ff766491834e5..a029b39b06d27 100644
--- a/llvm/test/CodeGen/Mips/msa/ldr_str.ll
+++ b/llvm/test/CodeGen/Mips/msa/ldr_str.ll
@@ -11,7 +11,7 @@
define void @llvm_mips_ldr_d_test(ptr %val, ptr %ptr) nounwind {
; MIPS32R5-EB-LABEL: llvm_mips_ldr_d_test:
; MIPS32R5-EB: # %bb.0: # %entry
-; MIPS32R5-EB-NEXT: # implicit-def: $v0
+; MIPS32R5-EB-NEXT: # implicit-def: $r2
; MIPS32R5-EB-NEXT: lwr $2, 23($5)
; MIPS32R5-EB-NEXT: lwl $2, 20($5)
; MIPS32R5-EB-NEXT: # implicit-def: $at
@@ -25,7 +25,7 @@ define void @llvm_mips_ldr_d_test(ptr %val, ptr %ptr) nounwind {
;
; MIPS32R5-EL-LABEL: llvm_mips_ldr_d_test:
; MIPS32R5-EL: # %bb.0: # %entry
-; MIPS32R5-EL-NEXT: # implicit-def: $v0
+; MIPS32R5-EL-NEXT: # implicit-def: $r2
; MIPS32R5-EL-NEXT: lwr $2, 16($5)
; MIPS32R5-EL-NEXT: lwl $2, 19($5)
; MIPS32R5-EL-NEXT: # implicit-def: $at
diff --git a/llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll b/llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll
index 3db0693fd2dcc..027e1ee1cfe6a 100644
--- a/llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll
+++ b/llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll
@@ -10,18 +10,18 @@
define i32 @two_tls_calls() {
; MIPS32-LABEL: name: two_tls_calls
; MIPS32: bb.0 (%ir-block.0):
- ; MIPS32-NEXT: liveins: $t9, $v0
+ ; MIPS32-NEXT: liveins: $t9, $r2
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp
; MIPS32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[ADDu]], target-flags(mips-tlsgd) @tls_gd
; MIPS32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got-call) &__tls_get_addr :: (load (s32) from call-entry &__tls_get_addr)
; MIPS32-NEXT: $a0 = COPY [[ADDiu]]
; MIPS32-NEXT: $gp = COPY [[ADDu]]
; MIPS32-NEXT: $t9 = COPY [[LW]]
- ; MIPS32-NEXT: JALRPseudo $t9, csr_o32, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0, implicit $gp, implicit-def $sp, implicit-def $v0
+ ; MIPS32-NEXT: JALRPseudo $t9, csr_o32, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0, implicit $gp, implicit-def $sp, implicit-def $r2
; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $v0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r2
; MIPS32-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (dereferenceable load (s32) from @tls_gd)
; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp
; MIPS32-NEXT: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu [[ADDu]], target-flags(mips-tlsldm) @tls_ld
@@ -29,15 +29,15 @@ define i32 @two_tls_calls() {
; MIPS32-NEXT: $a0 = COPY [[ADDiu1]]
; MIPS32-NEXT: dead $gp = COPY [[ADDu]]
; MIPS32-NEXT: $t9 = COPY [[LW2]]
- ; MIPS32-NEXT: JALRPseudo $t9, csr_o32, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0, implicit-def $sp, implicit-def $v0
+ ; MIPS32-NEXT: JALRPseudo $t9, csr_o32, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0, implicit-def $sp, implicit-def $r2
; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $v0
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $r2
; MIPS32-NEXT: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-dtprel-hi) @tls_ld
; MIPS32-NEXT: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[COPY1]]
; MIPS32-NEXT: [[LW3:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-dtprel-lo) @tls_ld :: (dereferenceable load (s32) from @tls_ld)
; MIPS32-NEXT: [[ADDu2:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[LW3]]
- ; MIPS32-NEXT: $v0 = COPY [[ADDu2]]
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: $r2 = COPY [[ADDu2]]
+ ; MIPS32-NEXT: RetRA implicit $r2
;
; MIPS64-LABEL: name: two_tls_calls
; MIPS64: bb.0 (%ir-block.0):
@@ -52,9 +52,9 @@ define i32 @two_tls_calls() {
; MIPS64-NEXT: $a0_64 = COPY [[DADDiu1]]
; MIPS64-NEXT: $gp_64 = COPY [[DADDiu]]
; MIPS64-NEXT: $t9_64 = COPY [[LD]]
- ; MIPS64-NEXT: JALR64Pseudo $t9_64, csr_n64, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ; MIPS64-NEXT: JALR64Pseudo $t9_64, csr_n64, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
; MIPS64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; MIPS64-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $v0_64
+ ; MIPS64-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $r2_64
; MIPS64-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (dereferenceable load (s32) from @tls_gd)
; MIPS64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; MIPS64-NEXT: [[DADDiu2:%[0-9]+]]:gpr64 = DADDiu [[DADDiu]], target-flags(mips-tlsldm) @tls_ld
@@ -62,15 +62,15 @@ define i32 @two_tls_calls() {
; MIPS64-NEXT: $a0_64 = COPY [[DADDiu2]]
; MIPS64-NEXT: dead $gp_64 = COPY [[DADDiu]]
; MIPS64-NEXT: $t9_64 = COPY [[LD1]]
- ; MIPS64-NEXT: JALR64Pseudo $t9_64, csr_n64, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0_64
+ ; MIPS64-NEXT: JALR64Pseudo $t9_64, csr_n64, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2_64
; MIPS64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; MIPS64-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $v0_64
+ ; MIPS64-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $r2_64
; MIPS64-NEXT: [[LUi64_1:%[0-9]+]]:gpr64 = LUi64 target-flags(mips-dtprel-hi) @tls_ld
; MIPS64-NEXT: [[DADDu1:%[0-9]+]]:gpr64 = DADDu [[LUi64_1]], [[COPY1]]
; MIPS64-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[DADDu1]], target-flags(mips-dtprel-lo) @tls_ld :: (dereferenceable load (s32) from @tls_ld)
; MIPS64-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LW]], [[LW1]]
- ; MIPS64-NEXT: $v0 = COPY [[ADDu]]
- ; MIPS64-NEXT: RetRA implicit $v0
+ ; MIPS64-NEXT: $r2 = COPY [[ADDu]]
+ ; MIPS64-NEXT: RetRA implicit $r2
%a = load i32, ptr @tls_gd
%b = load i32, ptr @tls_ld
%c = add i32 %a, %b
diff --git a/llvm/test/CodeGen/Mips/setcc-se.ll b/llvm/test/CodeGen/Mips/setcc-se.ll
index 00358135c42be..2ddce7855ecc2 100644
--- a/llvm/test/CodeGen/Mips/setcc-se.ll
+++ b/llvm/test/CodeGen/Mips/setcc-se.ll
@@ -13,7 +13,7 @@ define i32 @seteq0(i32 %a) {
; MMR6-LABEL: seteq0:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: sltiu $2, $4, 1 # <MCInst #[[#MCINST1:]] SLTiu_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:A0>
; MMR6-NEXT: # <MCOperand Imm:1>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2:]] JRC16_MM
@@ -33,7 +33,7 @@ define i32 @setne0(i32 %a) {
; MMR6-LABEL: setne0:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: sltu $2, $zero, $4 # <MCInst #[[#MCINST3:]] SLTu_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:ZERO>
; MMR6-NEXT: # <MCOperand Reg:A0>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
@@ -60,15 +60,15 @@ define void @slti_beq0(i32 %a) {
; MMR6-LABEL: slti_beq0:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4:]] LUi
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%hi(_gp_disp)>>
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5:]] ADDiu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%lo(_gp_disp)>>
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6:]] ADDu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:T9>>
; MMR6-NEXT: slti $1, $4, -32768 # <MCInst #[[#MCINST7:]] SLTi_MM
; MMR6-NEXT: # <MCOperand Reg:AT>
@@ -79,12 +79,12 @@ define void @slti_beq0(i32 %a) {
; MMR6-NEXT: # <MCOperand Expr:$BB2_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9:]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10:]] SW16_MM
; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB2_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
@@ -119,15 +119,15 @@ define void @slti_beq1(i32 %a) {
; MMR6-LABEL: slti_beq1:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%hi(_gp_disp)>>
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%lo(_gp_disp)>>
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:T9>>
; MMR6-NEXT: lui $1, 65535 # <MCInst #[[#MCINST11:]] LUi_MM
; MMR6-NEXT: # <MCOperand Reg:AT>
@@ -145,12 +145,12 @@ define void @slti_beq1(i32 %a) {
; MMR6-NEXT: # <MCOperand Expr:$BB3_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB3_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
@@ -183,15 +183,15 @@ define void @slti_beq2(i32 %a) {
; MMR6-LABEL: slti_beq2:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%hi(_gp_disp)>>
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%lo(_gp_disp)>>
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:T9>>
; MMR6-NEXT: slti $1, $4, 32767 # <MCInst #[[#MCINST7]] SLTi_MM
; MMR6-NEXT: # <MCOperand Reg:AT>
@@ -202,12 +202,12 @@ define void @slti_beq2(i32 %a) {
; MMR6-NEXT: # <MCOperand Expr:$BB4_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB4_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
@@ -241,15 +241,15 @@ define void @slti_beq3(i32 %a) {
; MMR6-LABEL: slti_beq3:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%hi(_gp_disp)>>
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%lo(_gp_disp)>>
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:T9>>
; MMR6-NEXT: addiu $1, $zero, 32767 # <MCInst #[[#MCINST15:]] ADDiu_MM
; MMR6-NEXT: # <MCOperand Reg:AT>
@@ -264,12 +264,12 @@ define void @slti_beq3(i32 %a) {
; MMR6-NEXT: # <MCOperand Expr:$BB5_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB5_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
@@ -302,15 +302,15 @@ define void @sltiu_beq0(i32 %a) {
; MMR6-LABEL: sltiu_beq0:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%hi(_gp_disp)>>
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%lo(_gp_disp)>>
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:T9>>
; MMR6-NEXT: sltiu $1, $4, 32767 # <MCInst #[[#MCINST1]] SLTiu_MM
; MMR6-NEXT: # <MCOperand Reg:AT>
@@ -321,12 +321,12 @@ define void @sltiu_beq0(i32 %a) {
; MMR6-NEXT: # <MCOperand Expr:$BB6_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB6_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
@@ -360,15 +360,15 @@ define void @sltiu_beq1(i32 %a) {
; MMR6-LABEL: sltiu_beq1:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%hi(_gp_disp)>>
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%lo(_gp_disp)>>
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:T9>>
; MMR6-NEXT: addiu $1, $zero, 32767 # <MCInst #[[#MCINST15]] ADDiu_MM
; MMR6-NEXT: # <MCOperand Reg:AT>
@@ -383,12 +383,12 @@ define void @sltiu_beq1(i32 %a) {
; MMR6-NEXT: # <MCOperand Expr:$BB7_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB7_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
@@ -421,15 +421,15 @@ define void @sltiu_beq2(i32 %a) {
; MMR6-LABEL: sltiu_beq2:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%hi(_gp_disp)>>
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%lo(_gp_disp)>>
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:T9>>
; MMR6-NEXT: sltiu $1, $4, -32768 # <MCInst #[[#MCINST1]] SLTiu_MM
; MMR6-NEXT: # <MCOperand Reg:AT>
@@ -440,12 +440,12 @@ define void @sltiu_beq2(i32 %a) {
; MMR6-NEXT: # <MCOperand Expr:$BB8_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB8_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
@@ -480,15 +480,15 @@ define void @sltiu_beq3(i32 %a) {
; MMR6-LABEL: sltiu_beq3:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $2, %hi(_gp_disp) # <MCInst #[[#MCINST4]] LUi
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%hi(_gp_disp)>>
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # <MCInst #[[#MCINST5]] ADDiu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%lo(_gp_disp)>>
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:T9>>
; MMR6-NEXT: lui $1, 65535 # <MCInst #[[#MCINST11]] LUi_MM
; MMR6-NEXT: # <MCOperand Reg:AT>
@@ -506,12 +506,12 @@ define void @sltiu_beq3(i32 %a) {
; MMR6-NEXT: # <MCOperand Expr:$BB9_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
-; MMR6-NEXT: # <MCOperand Reg:V0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:V0>
+; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB9_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
diff --git a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
index 02c0b3c573d6b..53bf8302300a7 100644
--- a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
+++ b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
@@ -41,6 +41,6 @@ constants:
body: |
bb.0.entry:
$zero = SLL_MMR6 killed $zero, 0
- JRC16_MMR6 undef $ra, implicit $v0
+ JRC16_MMR6 undef $ra, implicit $r2
...
diff --git a/llvm/test/DebugInfo/MIR/Mips/call-site-info-update-delay-slot-filler.mir b/llvm/test/DebugInfo/MIR/Mips/call-site-info-update-delay-slot-filler.mir
index 1ea519dde0c30..d450ee8428464 100644
--- a/llvm/test/DebugInfo/MIR/Mips/call-site-info-update-delay-slot-filler.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/call-site-info-update-delay-slot-filler.mir
@@ -75,9 +75,9 @@ body: |
CFI_INSTRUCTION offset $ra_64, -4
renamable $at = LUi target-flags(mips-abs-hi) @pm_power_off, debug-location !17
renamable $t9 = LW killed renamable $at, target-flags(mips-abs-lo) @pm_power_off, debug-location !17 :: (dereferenceable load (s32) from `i32 ()** bitcast (i32 (...)** @pm_power_off to i32 ()**)`)
- JALRPseudo $t9, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0, debug-location !17
+ JALRPseudo $t9, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2, debug-location !17
$ra = LW $sp, 20, debug-location !17 :: (load (s32) from %stack.0)
$sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit undef $v0, debug-location !17
+ PseudoReturn undef $ra, implicit undef $r2, debug-location !17
...
diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir
index a186de4403d49..42dfa5901cbdc 100644
--- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir
@@ -97,12 +97,12 @@ body: |
$a0_64 = OR64 killed $a1_64, $zero_64, debug-location !18
DBG_VALUE $a0_64, $noreg, !17, !DIExpression(), debug-location !18
$a1 = OR $at, $zero, implicit killed $at_64, debug-location !18
- JAL @foo, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1, implicit killed $a2, implicit-def $sp, implicit-def $v0, debug-location !18 {
+ JAL @foo, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1, implicit killed $a2, implicit-def $sp, implicit-def $r2, debug-location !18 {
$a2 = ADDiu $zero, 0, debug-location !18
}
- renamable $v0_64 = SLL64_32 killed renamable $v0, debug-location !18
+ renamable $r2_64 = SLL64_32 killed renamable $r2, debug-location !18
$ra_64 = LD $sp_64, 8, debug-location !18 :: (load (s64) from %stack.0)
- PseudoReturn64 undef $ra_64, implicit $v0_64, debug-location !18 {
+ PseudoReturn64 undef $ra_64, implicit $r2_64, debug-location !18 {
$sp_64 = DADDiu $sp_64, 16
}
diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir
index b35c3dea82466..085935b589c98 100644
--- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir
@@ -114,10 +114,10 @@ body: |
renamable $s1 = ADDiu renamable $a1, 1, implicit killed $a1_64, implicit-def $s1_64, debug-location !20
DBG_VALUE $s1, $noreg, !19, !DIExpression(), debug-location !20
$a0_64 = OR64 $s1_64, $zero_64, debug-location !20
- JAL @sum, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1_64, implicit-def $sp, implicit-def $v0, debug-location !20 {
+ JAL @sum, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1_64, implicit-def $sp, implicit-def $r2, debug-location !20 {
$a1_64 = OR64 $s1_64, $zero_64, debug-location !20
}
- renamable $at = nsw ADDu killed renamable $v0, renamable $s1, implicit killed $s1_64, debug-location !20
+ renamable $at = nsw ADDu killed renamable $r2, renamable $s1, implicit killed $s1_64, debug-location !20
SW killed renamable $at, killed renamable $s0_64, 0
$s0_64 = LD $sp_64, 8
$s1_64 = LD $sp_64, 16
diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir
index b6eddff967b59..ed2e8c6c96c31 100644
--- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir
@@ -110,10 +110,10 @@ body: |
renamable $s1 = nsw ADDiu killed renamable $a1, 1, debug-location !19
DBG_VALUE $s1, $noreg, !18, !DIExpression(), debug-location !19
$a0 = OR $s1, $zero, debug-location !19
- JAL @sum, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $v0, debug-location !19 {
+ JAL @sum, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $r2, debug-location !19 {
$a1 = OR $s1, $zero, debug-location !19
}
- renamable $at = nsw ADDu killed renamable $v0, killed renamable $s1, debug-location !19
+ renamable $at = nsw ADDu killed renamable $r2, killed renamable $s1, debug-location !19
SW killed renamable $at, killed renamable $s0, 0, debug-location !19 :: (store (s32) into %ir.adr)
$s0 = LW $sp, 20
DBG_VALUE $a0, $noreg, !17, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !19
diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir
index 66fa095650fac..a3936d715b04f 100644
--- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir
@@ -120,16 +120,16 @@ body: |
}
renamable $a2_64 = nsw DADDiu renamable $s0_64, 10, debug-location !20
$a0_64 = DADDiu $zero_64, 44, debug-location !20
- JAL @fn1, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit killed $a1_64, implicit $a2_64, implicit-def $sp, implicit-def $v0, debug-location !20 {
+ JAL @fn1, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit killed $a1_64, implicit $a2_64, implicit-def $sp, implicit-def $r2, debug-location !20 {
$a1_64 = OR64 killed $s0_64, $zero_64, debug-location !20
}
- DBG_VALUE $v0, $noreg, !19, !DIExpression(), debug-location !20
- renamable $at = SLTi renamable $v0, 11, debug-location !20
- renamable $v1 = nsw ADDiu renamable $v0, 10, debug-location !20
- renamable $v0 = MOVZ_I_I killed renamable $v1, killed renamable $at, killed renamable $v0, debug-location !20
- renamable $v0_64 = SLL64_32 killed renamable $v0, debug-location !20
+ DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !20
+ renamable $at = SLTi renamable $r2, 11, debug-location !20
+ renamable $r3 = nsw ADDiu renamable $r2, 10, debug-location !20
+ renamable $r2 = MOVZ_I_I killed renamable $r3, killed renamable $at, killed renamable $r2, debug-location !20
+ renamable $r2_64 = SLL64_32 killed renamable $r2, debug-location !20
$s0_64 = LD $sp_64, 0, debug-location !20 :: (load (s64) from %stack.1)
$ra_64 = LD $sp_64, 8, debug-location !20 :: (load (s64) from %stack.0)
- PseudoReturn64 undef $ra_64, implicit $v0_64, debug-location !20 {
+ PseudoReturn64 undef $ra_64, implicit $r2_64, debug-location !20 {
$sp_64 = DADDiu $sp_64, 16
}
diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir
index 216ae0b98ed76..624538489704c 100644
--- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir
@@ -118,15 +118,15 @@ body: |
}
renamable $a2 = nsw ADDiu renamable $s0, 10, debug-location !18
$a0 = ADDiu $zero, 44, debug-location !18
- JAL @fn1, csr_o32, implicit-def dead $ra, implicit $a0, implicit killed $a1, implicit $a2, implicit-def $sp, implicit-def $v0, debug-location !18 {
+ JAL @fn1, csr_o32, implicit-def dead $ra, implicit $a0, implicit killed $a1, implicit $a2, implicit-def $sp, implicit-def $r2, debug-location !18 {
$a1 = OR killed $s0, $zero, debug-location !18
}
- DBG_VALUE $v0, $noreg, !17, !DIExpression(), debug-location !18
- renamable $at = SLTi renamable $v0, 11, debug-location !18
- renamable $v1 = nsw ADDiu renamable $v0, 10, debug-location !18
- renamable $v0 = MOVZ_I_I killed renamable $v1, killed renamable $at, killed renamable $v0, debug-location !18
+ DBG_VALUE $r2, $noreg, !17, !DIExpression(), debug-location !18
+ renamable $at = SLTi renamable $r2, 11, debug-location !18
+ renamable $r3 = nsw ADDiu renamable $r2, 10, debug-location !18
+ renamable $r2 = MOVZ_I_I killed renamable $r3, killed renamable $at, killed renamable $r2, debug-location !18
$s0 = LW $sp, 16, debug-location !18 :: (load (s32) from %stack.1)
$ra = LW $sp, 20, debug-location !18 :: (load (s32) from %stack.0)
- PseudoReturn undef $ra, implicit $v0, debug-location !18 {
+ PseudoReturn undef $ra, implicit $r2, debug-location !18 {
$sp = ADDiu $sp, 24
}
diff --git a/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir b/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir
index e7786b57d81a8..5cba34e9731f4 100644
--- a/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir
@@ -199,8 +199,8 @@ body: |
JAL @externFunc, csr_n64, implicit-def dead $ra, implicit $f12, implicit-def $sp, implicit-def dead $f0, debug-location !19
renamable $a0_64 = SLL64_32 renamable $s0, implicit $s0_64, debug-location !19
- JAL @externFunc3, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0, debug-location !19
- renamable $f0 = PseudoCVT_S_W killed renamable $v0, debug-location !19
+ JAL @externFunc3, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2, debug-location !19
+ renamable $f0 = PseudoCVT_S_W killed renamable $r2, debug-location !19
; This instruction is inserted additionally in order to test moving from one register to another
$s1_64 = OR64 killed $s0_64, $zero_64, debug-location !19
renamable $at_64 = LUi64 target-flags(mips-highest) %const.2
@@ -228,8 +228,8 @@ body: |
JAL @externFunc2, csr_n64, implicit-def dead $ra, implicit $f12, implicit-def $sp, implicit-def $f0, debug-location !19
renamable $f25 = COPY $f0, debug-location !19
renamable $a0_64 = SLL64_32 renamable $s0, implicit killed $s0_64, debug-location !19
- JAL @externFunc4, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0, debug-location !19
- renamable $s0 = COPY $v0, debug-location !19
+ JAL @externFunc4, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2, debug-location !19
+ renamable $s0 = COPY $r2, debug-location !19
$f12 = COPY renamable $f24, debug-location !19
JAL @externFunc, csr_n64, implicit-def dead $ra, implicit $f12, implicit-def $sp, implicit-def dead $f0, debug-location !19
renamable $f0 = PseudoCVT_S_W killed renamable $s0, debug-location !19
diff --git a/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir b/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
index 43c720f2cf77b..fa45845b72aec 100644
--- a/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
@@ -110,14 +110,14 @@ body: |
$a1 = COPY %2, debug-location !19
DBG_VALUE $a1, $noreg, !14, !DIExpression(), debug-location !16
$a2 = COPY %4, debug-location !19
- JAL @fn1, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit $a2, implicit-def $sp, implicit-def $v0, debug-location !19
+ JAL @fn1, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit $a2, implicit-def $sp, implicit-def $r2, debug-location !19
ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp, debug-location !19
- %5:gpr32 = COPY killed $v0, debug-location !19
+ %5:gpr32 = COPY killed $r2, debug-location !19
DBG_VALUE %5, $noreg, !15, !DIExpression(), debug-location !16
%6:gpr32 = SLTi %5, 11, debug-location !22
%7:gpr32 = nsw ADDiu %5, 10, debug-location !22
%8:gpr32 = MOVZ_I_I %7, %6, %8, debug-location !22
- $v0 = COPY %8, debug-location !23
- RetRA implicit killed $v0, debug-location !23
+ $r2 = COPY %8, debug-location !23
+ RetRA implicit killed $r2, debug-location !23
...
diff --git a/llvm/test/DebugInfo/Mips/livedebugvariables-reorder.mir b/llvm/test/DebugInfo/Mips/livedebugvariables-reorder.mir
index 0fb55dabb3f2d..3108537f569f0 100644
--- a/llvm/test/DebugInfo/Mips/livedebugvariables-reorder.mir
+++ b/llvm/test/DebugInfo/Mips/livedebugvariables-reorder.mir
@@ -68,17 +68,17 @@ machineFunctionInfo: {}
body: |
bb.0.entry:
ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp, debug-location !12
- JAL @foo, csr_o32_fpxx, implicit-def dead $ra, implicit-def $sp, implicit-def $v0, debug-location !12
+ JAL @foo, csr_o32_fpxx, implicit-def dead $ra, implicit-def $sp, implicit-def $r2, debug-location !12
ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp, debug-location !12
- %0:gpr32 = COPY killed $v0, debug-location !12
+ %0:gpr32 = COPY killed $r2, debug-location !12
DBG_VALUE 1001, $noreg, !8, !DIExpression(DW_OP_LLVM_fragment, 0, 16), debug-location !12
DBG_VALUE 1002, $noreg, !8, !DIExpression(DW_OP_LLVM_fragment, 16, 16), debug-location !12
DBG_VALUE 222, $noreg, !9, !DIExpression(), debug-location !12
DBG_VALUE 333, $noreg, !10, !DIExpression(), debug-location !12
DBG_VALUE 444, $noreg, !11, !DIExpression(), debug-location !12
DBG_VALUE %0, $noreg, !8, !DIExpression(), debug-location !12
- INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $v0, 12 /* clobber */, implicit-def dead early-clobber $v1, 12 /* clobber */, implicit-def dead early-clobber $a0, 12 /* clobber */, implicit-def dead early-clobber $a1, 12 /* clobber */, implicit-def dead early-clobber $a2, 12 /* clobber */, implicit-def dead early-clobber $a3, 12 /* clobber */, implicit-def dead early-clobber $t0, 12 /* clobber */, implicit-def dead early-clobber $t1, 12 /* clobber */, implicit-def dead early-clobber $t2, 12 /* clobber */, implicit-def dead early-clobber $t3, 12 /* clobber */, implicit-def dead early-clobber $t4, 12 /* clobber */, implicit-def dead early-clobber $t5, 12 /* clobber */, implicit-def dead early-clobber $t6, 12 /* clobber */, implicit-def dead early-clobber $t7, 12 /* clobber */, implicit-def dead early-clobber $t8, 12 /* clobber */, implicit-def dead early-clobber $t9, 12 /* clobber */, implicit-def dead early-clobber $gp, 12 /* clobber */, implicit-def dead early-clobber $ra, 12 /* clobber */, implicit-def dead early-clobber $s0, 12 /* clobber */, implicit-def dead early-clobber $s1, 12 /* clobber */, implicit-def dead early-clobber $s2, 12 /* clobber */, implicit-def dead early-clobber $s3, 12 /* clobber */, implicit-def dead early-clobber $s4, 12 /* clobber */, implicit-def dead early-clobber $s5, 12 /* clobber */, implicit-def dead early-clobber $s6, 12 /* clobber */, implicit-def dead early-clobber $s7, 12 /* clobber */, implicit-def dead early-clobber $at, !13, debug-location !12
- $v0 = COPY killed %0, debug-location !12
- RetRA implicit killed $v0, debug-location !12
+ INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $r2, 12 /* clobber */, implicit-def dead early-clobber $r3, 12 /* clobber */, implicit-def dead early-clobber $a0, 12 /* clobber */, implicit-def dead early-clobber $a1, 12 /* clobber */, implicit-def dead early-clobber $a2, 12 /* clobber */, implicit-def dead early-clobber $a3, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15, 12 /* clobber */, implicit-def dead early-clobber $t8, 12 /* clobber */, implicit-def dead early-clobber $t9, 12 /* clobber */, implicit-def dead early-clobber $gp, 12 /* clobber */, implicit-def dead early-clobber $ra, 12 /* clobber */, implicit-def dead early-clobber $s0, 12 /* clobber */, implicit-def dead early-clobber $s1, 12 /* clobber */, implicit-def dead early-clobber $s2, 12 /* clobber */, implicit-def dead early-clobber $s3, 12 /* clobber */, implicit-def dead early-clobber $s4, 12 /* clobber */, implicit-def dead early-clobber $s5, 12 /* clobber */, implicit-def dead early-clobber $s6, 12 /* clobber */, implicit-def dead early-clobber $s7, 12 /* clobber */, implicit-def dead early-clobber $at, !13, debug-location !12
+ $r2 = COPY killed %0, debug-location !12
+ RetRA implicit killed $r2, debug-location !12
...
>From 942eb4be756ef6034f1522dc3fba4c42ffca93bc Mon Sep 17 00:00:00 2001
From: Anton Rapetov <anton.rapetov at mediatek.com>
Date: Wed, 7 Oct 2026 12:09:39 -0400
Subject: [PATCH 3/7] [Mips] Rename the remaining GPRs to R<n> names
Continue the rename from the previous commit for the records still named
after O32 roles (ZERO, AT, A0-A3, S0-S7, T8/T9, K0/K1, GP, SP, FP, RA):
they become R0, R1, R4-R7, R16-R25, R26-R31 (plus _64 forms). Assembly
syntax, DWARF numbers and ABI-specific assembler names are unchanged.
The old names stay as aliases (TableGen defvar and constexpr in
MipsMCTargetDesc.h) until the next commits; the `sequence` uses in
MipsCallingConv.td now use R%u format strings. The new enum order
changes some expected outputs, which follow separately.
Co-authored-By: Claude Sonnet <noreply at anthropic.com>
---
.../Mips/MCTargetDesc/MipsMCTargetDesc.h | 52 +++++-
llvm/lib/Target/Mips/MipsCallingConv.td | 42 ++---
llvm/lib/Target/Mips/MipsRegisterInfo.td | 157 ++++++++++++------
3 files changed, 173 insertions(+), 78 deletions(-)
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
index 44b709f3a0410..23d812337a771 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
@@ -83,9 +83,11 @@ namespace llvm {
namespace Mips {
// R2-R3 and R8-R15 have different names in the O32 (O), N32/N64 (N) and
// P32/P64 (P) ABIs. These aliases match the ones in MipsRegisterInfo.td; the
-// unsuffixed O names are kept for compatibility.
+// unsuffixed O names are kept for compatibility. The remaining O32-role
+// aliases (ZERO, AT, A0-A3, S0-S7, T8-T9, K0-K1, GP, SP, FP, RA) below are
+// to be removed in favour of MipsABIInfo accessors or plain R<n> names.
-// O32 names.
+// O32 names for R2-R3/R8-R15.
inline constexpr MCPhysReg V0 = R2;
inline constexpr MCPhysReg V1 = R3;
inline constexpr MCPhysReg T0 = R8;
@@ -150,6 +152,52 @@ inline constexpr MCPhysReg T0_P_64 = R12_64;
inline constexpr MCPhysReg T1_P_64 = R13_64;
inline constexpr MCPhysReg T2_P_64 = R14_64;
inline constexpr MCPhysReg T3_P_64 = R15_64;
+
+// O32-role names for the remaining registers.
+inline constexpr MCPhysReg ZERO = R0;
+inline constexpr MCPhysReg AT = R1;
+inline constexpr MCPhysReg A0 = R4;
+inline constexpr MCPhysReg A1 = R5;
+inline constexpr MCPhysReg A2 = R6;
+inline constexpr MCPhysReg A3 = R7;
+inline constexpr MCPhysReg S0 = R16;
+inline constexpr MCPhysReg S1 = R17;
+inline constexpr MCPhysReg S2 = R18;
+inline constexpr MCPhysReg S3 = R19;
+inline constexpr MCPhysReg S4 = R20;
+inline constexpr MCPhysReg S5 = R21;
+inline constexpr MCPhysReg S6 = R22;
+inline constexpr MCPhysReg S7 = R23;
+inline constexpr MCPhysReg T8 = R24;
+inline constexpr MCPhysReg T9 = R25;
+inline constexpr MCPhysReg K0 = R26;
+inline constexpr MCPhysReg K1 = R27;
+inline constexpr MCPhysReg GP = R28;
+inline constexpr MCPhysReg SP = R29;
+inline constexpr MCPhysReg FP = R30;
+inline constexpr MCPhysReg RA = R31;
+inline constexpr MCPhysReg ZERO_64 = R0_64;
+inline constexpr MCPhysReg AT_64 = R1_64;
+inline constexpr MCPhysReg A0_64 = R4_64;
+inline constexpr MCPhysReg A1_64 = R5_64;
+inline constexpr MCPhysReg A2_64 = R6_64;
+inline constexpr MCPhysReg A3_64 = R7_64;
+inline constexpr MCPhysReg S0_64 = R16_64;
+inline constexpr MCPhysReg S1_64 = R17_64;
+inline constexpr MCPhysReg S2_64 = R18_64;
+inline constexpr MCPhysReg S3_64 = R19_64;
+inline constexpr MCPhysReg S4_64 = R20_64;
+inline constexpr MCPhysReg S5_64 = R21_64;
+inline constexpr MCPhysReg S6_64 = R22_64;
+inline constexpr MCPhysReg S7_64 = R23_64;
+inline constexpr MCPhysReg T8_64 = R24_64;
+inline constexpr MCPhysReg T9_64 = R25_64;
+inline constexpr MCPhysReg K0_64 = R26_64;
+inline constexpr MCPhysReg K1_64 = R27_64;
+inline constexpr MCPhysReg GP_64 = R28_64;
+inline constexpr MCPhysReg SP_64 = R29_64;
+inline constexpr MCPhysReg FP_64 = R30_64;
+inline constexpr MCPhysReg RA_64 = R31_64;
} // namespace Mips
} // namespace llvm
diff --git a/llvm/lib/Target/Mips/MipsCallingConv.td b/llvm/lib/Target/Mips/MipsCallingConv.td
index e6f14f9234ea6..d30b4bc686f70 100644
--- a/llvm/lib/Target/Mips/MipsCallingConv.td
+++ b/llvm/lib/Target/Mips/MipsCallingConv.td
@@ -348,74 +348,74 @@ def CC_Mips : CallingConv<[
//===----------------------------------------------------------------------===//
def CSR_O32_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 20), RA, FP,
- (sequence "S%u", 7, 0))>;
+ (sequence "R%u", 23, 16))>;
def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
- (sequence "S%u", 7, 0))> {
+ (sequence "R%u", 23, 16))> {
let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
}
def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
- (sequence "S%u", 7, 0))>;
+ (sequence "R%u", 23, 16))>;
def CSR_O32_FP64 :
CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
- (sequence "S%u", 7, 0))>;
+ (sequence "R%u", 23, 16))>;
def CSR_N32 : CalleeSavedRegs<(add(decimate(sequence "D%u_64", 30, 20), 2),
- RA_64, FP_64, GP_64, (sequence "S%u_64", 7, 0))>;
+ RA_64, FP_64, GP_64, (sequence "R%u_64", 23, 16))>;
def CSR_N32_NoGP : CalleeSavedRegs<(add(decimate(sequence "D%u_64", 30, 20), 2),
- RA_64, FP_64, (sequence "S%u_64", 7, 0))>;
+ RA_64, FP_64, (sequence "R%u_64", 23, 16))>;
def CSR_N32_SingleFloat
: CalleeSavedRegs<(add(decimate(sequence "F%u", 30, 20), 2), RA_64, FP_64,
- GP_64, (sequence "S%u_64", 7, 0))>;
+ GP_64, (sequence "R%u_64", 23, 16))>;
def CSR_N32_SingleFloat_NoGP
: CalleeSavedRegs<(add(decimate(sequence "F%u", 30, 20), 2), RA_64, FP_64,
- (sequence "S%u_64", 7, 0))>;
+ (sequence "R%u_64", 23, 16))>;
def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
- GP_64, (sequence "S%u_64", 7, 0))>;
+ GP_64, (sequence "R%u_64", 23, 16))>;
def CSR_N64_NoGP : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
- (sequence "S%u_64", 7, 0))>;
+ (sequence "R%u_64", 23, 16))>;
def CSR_N64_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 24), RA_64,
- FP_64, GP_64, (sequence "S%u_64", 7, 0))>;
+ FP_64, GP_64, (sequence "R%u_64", 23, 16))>;
def CSR_N64_SingleFloat_NoGP : CalleeSavedRegs<(add(sequence "F%u", 31, 24), RA_64,
- FP_64, (sequence "S%u_64", 7, 0))>;
+ FP_64, (sequence "R%u_64", 23, 16))>;
def CSR_Mips16RetHelper :
CalleeSavedRegs<(add V0, V1, FP,
- (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
+ (sequence "R%u", 7, 4), (sequence "R%u", 23, 16),
(sequence "D%u", 15, 10))>;
-def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
- (sequence "S%u", 7, 0),
+def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "R%u", 7, 4),
+ (sequence "R%u", 23, 16),
(sequence "R%u", 3, 2),
T9, T8,
(sequence "R%u", 15, 8),
RA, FP, GP, AT)>;
-def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
- (sequence "S%u", 7, 0),
+def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "R%u", 7, 4),
+ (sequence "R%u", 23, 16),
(sequence "R%u", 3, 2),
T9, T8,
(sequence "R%u", 15, 8),
RA, FP, GP, AT, LO0, HI0)>;
-def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
+def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "R%u_64", 7, 4),
(sequence "R%u_64", 3, 2),
- (sequence "S%u_64", 7, 0),
+ (sequence "R%u_64", 23, 16),
T9_64, T8_64,
(sequence "R%u_64", 15, 8),
RA_64, FP_64, GP_64, AT_64)>;
-def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
- (sequence "S%u_64", 7, 0),
+def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "R%u_64", 7, 4),
+ (sequence "R%u_64", 23, 16),
T9_64, T8_64,
(sequence "R%u_64", 15, 8),
(sequence "R%u_64", 3, 2),
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td
index e25ca335cdb0e..06291bca61303 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.td
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td
@@ -105,17 +105,16 @@ let Namespace = "Mips" in {
// General Purpose Registers
// Registers whose ABI names differ between the O, N and P ABIs use
// ABI-independent R<n> record names; see the ABI aliases below.
- // TODO: Use R0-R31/R0_64-R31_64 record names for the remaining registers.
// Use MipsABIInfo accessors for ABI roles.
let isConstant = true in
- def ZERO : MipsGPRReg< 0, "zero", "zero">, DwarfRegNum<[0]>;
- def AT : MipsGPRReg< 1, "1", "at">, DwarfRegNum<[1]>;
+ def R0 : MipsGPRReg< 0, "zero", "zero">, DwarfRegNum<[0]>;
+ def R1 : MipsGPRReg< 1, "1", "at">, DwarfRegNum<[1]>;
def R2 : MipsGPRReg< 2, "2", "v0", "v0", "t4">, DwarfRegNum<[2]>;
def R3 : MipsGPRReg< 3, "3", "v1", "v1", "t5">, DwarfRegNum<[3]>;
- def A0 : MipsGPRReg< 4, "4", "a0">, DwarfRegNum<[4]>;
- def A1 : MipsGPRReg< 5, "5", "a1">, DwarfRegNum<[5]>;
- def A2 : MipsGPRReg< 6, "6", "a2">, DwarfRegNum<[6]>;
- def A3 : MipsGPRReg< 7, "7", "a3">, DwarfRegNum<[7]>;
+ def R4 : MipsGPRReg< 4, "4", "a0">, DwarfRegNum<[4]>;
+ def R5 : MipsGPRReg< 5, "5", "a1">, DwarfRegNum<[5]>;
+ def R6 : MipsGPRReg< 6, "6", "a2">, DwarfRegNum<[6]>;
+ def R7 : MipsGPRReg< 7, "7", "a3">, DwarfRegNum<[7]>;
def R8 : MipsGPRReg< 8, "8", "t0", "a4">, DwarfRegNum<[8]>;
def R9 : MipsGPRReg< 9, "9", "t1", "a5">, DwarfRegNum<[9]>;
def R10 : MipsGPRReg<10, "10", "t2", "a6">, DwarfRegNum<[10]>;
@@ -124,57 +123,57 @@ let Namespace = "Mips" in {
def R13 : MipsGPRReg<13, "13", "t5", "t1">, DwarfRegNum<[13]>;
def R14 : MipsGPRReg<14, "14", "t6", "t2">, DwarfRegNum<[14]>;
def R15 : MipsGPRReg<15, "15", "t7", "t3">, DwarfRegNum<[15]>;
- def S0 : MipsGPRReg<16, "16", "s0">, DwarfRegNum<[16]>;
- def S1 : MipsGPRReg<17, "17", "s1">, DwarfRegNum<[17]>;
- def S2 : MipsGPRReg<18, "18", "s2">, DwarfRegNum<[18]>;
- def S3 : MipsGPRReg<19, "19", "s3">, DwarfRegNum<[19]>;
- def S4 : MipsGPRReg<20, "20", "s4">, DwarfRegNum<[20]>;
- def S5 : MipsGPRReg<21, "21", "s5">, DwarfRegNum<[21]>;
- def S6 : MipsGPRReg<22, "22", "s6">, DwarfRegNum<[22]>;
- def S7 : MipsGPRReg<23, "23", "s7">, DwarfRegNum<[23]>;
- def T8 : MipsGPRReg<24, "24", "t8">, DwarfRegNum<[24]>;
- def T9 : MipsGPRReg<25, "25", "t9">, DwarfRegNum<[25]>;
- def K0 : MipsGPRReg<26, "26", "k0">, DwarfRegNum<[26]>;
- def K1 : MipsGPRReg<27, "27", "k1">, DwarfRegNum<[27]>;
- def GP : MipsGPRReg<28, "gp", "gp">, DwarfRegNum<[28]>;
- def SP : MipsGPRReg<29, "sp", "sp">, DwarfRegNum<[29]>;
- def FP : MipsGPRReg<30, "fp", "fp">, DwarfRegNum<[30]>;
- def RA : MipsGPRReg<31, "ra", "ra">, DwarfRegNum<[31]>;
+ def R16 : MipsGPRReg<16, "16", "s0">, DwarfRegNum<[16]>;
+ def R17 : MipsGPRReg<17, "17", "s1">, DwarfRegNum<[17]>;
+ def R18 : MipsGPRReg<18, "18", "s2">, DwarfRegNum<[18]>;
+ def R19 : MipsGPRReg<19, "19", "s3">, DwarfRegNum<[19]>;
+ def R20 : MipsGPRReg<20, "20", "s4">, DwarfRegNum<[20]>;
+ def R21 : MipsGPRReg<21, "21", "s5">, DwarfRegNum<[21]>;
+ def R22 : MipsGPRReg<22, "22", "s6">, DwarfRegNum<[22]>;
+ def R23 : MipsGPRReg<23, "23", "s7">, DwarfRegNum<[23]>;
+ def R24 : MipsGPRReg<24, "24", "t8">, DwarfRegNum<[24]>;
+ def R25 : MipsGPRReg<25, "25", "t9">, DwarfRegNum<[25]>;
+ def R26 : MipsGPRReg<26, "26", "k0">, DwarfRegNum<[26]>;
+ def R27 : MipsGPRReg<27, "27", "k1">, DwarfRegNum<[27]>;
+ def R28 : MipsGPRReg<28, "gp", "gp">, DwarfRegNum<[28]>;
+ def R29 : MipsGPRReg<29, "sp", "sp">, DwarfRegNum<[29]>;
+ def R30 : MipsGPRReg<30, "fp", "fp">, DwarfRegNum<[30]>;
+ def R31 : MipsGPRReg<31, "ra", "ra">, DwarfRegNum<[31]>;
// General Purpose 64-bit Registers
let isConstant = true in
- def ZERO_64 : Mips64GPRReg<ZERO>, DwarfRegNum<[0]>;
- def AT_64 : Mips64GPRReg<AT>, DwarfRegNum<[1]>;
- def R2_64 : Mips64GPRReg<R2>, DwarfRegNum<[2]>;
- def R3_64 : Mips64GPRReg<R3>, DwarfRegNum<[3]>;
- def A0_64 : Mips64GPRReg<A0>, DwarfRegNum<[4]>;
- def A1_64 : Mips64GPRReg<A1>, DwarfRegNum<[5]>;
- def A2_64 : Mips64GPRReg<A2>, DwarfRegNum<[6]>;
- def A3_64 : Mips64GPRReg<A3>, DwarfRegNum<[7]>;
- def R8_64 : Mips64GPRReg<R8>, DwarfRegNum<[8]>;
- def R9_64 : Mips64GPRReg<R9>, DwarfRegNum<[9]>;
- def R10_64 : Mips64GPRReg<R10>, DwarfRegNum<[10]>;
- def R11_64 : Mips64GPRReg<R11>, DwarfRegNum<[11]>;
- def R12_64 : Mips64GPRReg<R12>, DwarfRegNum<[12]>;
- def R13_64 : Mips64GPRReg<R13>, DwarfRegNum<[13]>;
- def R14_64 : Mips64GPRReg<R14>, DwarfRegNum<[14]>;
- def R15_64 : Mips64GPRReg<R15>, DwarfRegNum<[15]>;
- def S0_64 : Mips64GPRReg<S0>, DwarfRegNum<[16]>;
- def S1_64 : Mips64GPRReg<S1>, DwarfRegNum<[17]>;
- def S2_64 : Mips64GPRReg<S2>, DwarfRegNum<[18]>;
- def S3_64 : Mips64GPRReg<S3>, DwarfRegNum<[19]>;
- def S4_64 : Mips64GPRReg<S4>, DwarfRegNum<[20]>;
- def S5_64 : Mips64GPRReg<S5>, DwarfRegNum<[21]>;
- def S6_64 : Mips64GPRReg<S6>, DwarfRegNum<[22]>;
- def S7_64 : Mips64GPRReg<S7>, DwarfRegNum<[23]>;
- def T8_64 : Mips64GPRReg<T8>, DwarfRegNum<[24]>;
- def T9_64 : Mips64GPRReg<T9>, DwarfRegNum<[25]>;
- def K0_64 : Mips64GPRReg<K0>, DwarfRegNum<[26]>;
- def K1_64 : Mips64GPRReg<K1>, DwarfRegNum<[27]>;
- def GP_64 : Mips64GPRReg<GP>, DwarfRegNum<[28]>;
- def SP_64 : Mips64GPRReg<SP>, DwarfRegNum<[29]>;
- def FP_64 : Mips64GPRReg<FP>, DwarfRegNum<[30]>;
- def RA_64 : Mips64GPRReg<RA>, DwarfRegNum<[31]>;
+ def R0_64 : Mips64GPRReg<R0>, DwarfRegNum<[0]>;
+ def R1_64 : Mips64GPRReg<R1>, DwarfRegNum<[1]>;
+ def R2_64 : Mips64GPRReg<R2>, DwarfRegNum<[2]>;
+ def R3_64 : Mips64GPRReg<R3>, DwarfRegNum<[3]>;
+ def R4_64 : Mips64GPRReg<R4>, DwarfRegNum<[4]>;
+ def R5_64 : Mips64GPRReg<R5>, DwarfRegNum<[5]>;
+ def R6_64 : Mips64GPRReg<R6>, DwarfRegNum<[6]>;
+ def R7_64 : Mips64GPRReg<R7>, DwarfRegNum<[7]>;
+ def R8_64 : Mips64GPRReg<R8>, DwarfRegNum<[8]>;
+ def R9_64 : Mips64GPRReg<R9>, DwarfRegNum<[9]>;
+ def R10_64 : Mips64GPRReg<R10>, DwarfRegNum<[10]>;
+ def R11_64 : Mips64GPRReg<R11>, DwarfRegNum<[11]>;
+ def R12_64 : Mips64GPRReg<R12>, DwarfRegNum<[12]>;
+ def R13_64 : Mips64GPRReg<R13>, DwarfRegNum<[13]>;
+ def R14_64 : Mips64GPRReg<R14>, DwarfRegNum<[14]>;
+ def R15_64 : Mips64GPRReg<R15>, DwarfRegNum<[15]>;
+ def R16_64 : Mips64GPRReg<R16>, DwarfRegNum<[16]>;
+ def R17_64 : Mips64GPRReg<R17>, DwarfRegNum<[17]>;
+ def R18_64 : Mips64GPRReg<R18>, DwarfRegNum<[18]>;
+ def R19_64 : Mips64GPRReg<R19>, DwarfRegNum<[19]>;
+ def R20_64 : Mips64GPRReg<R20>, DwarfRegNum<[20]>;
+ def R21_64 : Mips64GPRReg<R21>, DwarfRegNum<[21]>;
+ def R22_64 : Mips64GPRReg<R22>, DwarfRegNum<[22]>;
+ def R23_64 : Mips64GPRReg<R23>, DwarfRegNum<[23]>;
+ def R24_64 : Mips64GPRReg<R24>, DwarfRegNum<[24]>;
+ def R25_64 : Mips64GPRReg<R25>, DwarfRegNum<[25]>;
+ def R26_64 : Mips64GPRReg<R26>, DwarfRegNum<[26]>;
+ def R27_64 : Mips64GPRReg<R27>, DwarfRegNum<[27]>;
+ def R28_64 : Mips64GPRReg<R28>, DwarfRegNum<[28]>;
+ def R29_64 : Mips64GPRReg<R29>, DwarfRegNum<[29]>;
+ def R30_64 : Mips64GPRReg<R30>, DwarfRegNum<[30]>;
+ def R31_64 : Mips64GPRReg<R31>, DwarfRegNum<[31]>;
/// Mips Single point precision FPU Registers
foreach I = 0-31 in
@@ -375,6 +374,54 @@ defvar T1_P_64 = R13_64;
defvar T2_P_64 = R14_64;
defvar T3_P_64 = R15_64;
+// O32-role aliases for the remaining registers; ABI-independent names
+// above. MipsMCTargetDesc.h has the matching C++ aliases. To be removed
+// in favour of MipsABIInfo accessors or plain R<n> names.
+defvar ZERO = R0;
+defvar AT = R1;
+defvar A0 = R4;
+defvar A1 = R5;
+defvar A2 = R6;
+defvar A3 = R7;
+defvar S0 = R16;
+defvar S1 = R17;
+defvar S2 = R18;
+defvar S3 = R19;
+defvar S4 = R20;
+defvar S5 = R21;
+defvar S6 = R22;
+defvar S7 = R23;
+defvar T8 = R24;
+defvar T9 = R25;
+defvar K0 = R26;
+defvar K1 = R27;
+defvar GP = R28;
+defvar SP = R29;
+defvar FP = R30;
+defvar RA = R31;
+defvar ZERO_64 = R0_64;
+defvar AT_64 = R1_64;
+defvar A0_64 = R4_64;
+defvar A1_64 = R5_64;
+defvar A2_64 = R6_64;
+defvar A3_64 = R7_64;
+defvar S0_64 = R16_64;
+defvar S1_64 = R17_64;
+defvar S2_64 = R18_64;
+defvar S3_64 = R19_64;
+defvar S4_64 = R20_64;
+defvar S5_64 = R21_64;
+defvar S6_64 = R22_64;
+defvar S7_64 = R23_64;
+defvar T8_64 = R24_64;
+defvar T9_64 = R25_64;
+defvar K0_64 = R26_64;
+defvar K1_64 = R27_64;
+defvar GP_64 = R28_64;
+defvar SP_64 = R29_64;
+defvar FP_64 = R30_64;
+defvar RA_64 = R31_64;
+
//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//
>From 4b547f76ce07cf3a8e858d0e0f5484f8d9cba930 Mon Sep 17 00:00:00 2001
From: Anton Rapetov <anton.rapetov at mediatek.com>
Date: Wed, 7 Oct 2026 15:28:15 -0400
Subject: [PATCH 4/7] [Mips][test] Rename GPRs in test inputs
Rename all remaining references to the O32-role GPR records
(ZERO/AT/A0-A3/S0-S7/T8-T9/K0-K1/GP/SP/FP/RA and their _64 forms)
in the MIR test inputs, in the MIR/GlobalISel dump CHECK lines, and in
records printed by tools (DWARF register names, llvm-exegesis
DEFREG names). Asm-printed register names are unchanged.
Each file is byte-identical (after inverting the name substitution) to
its pre-rename version: only register name spellings change, no CHECK
directive kinds or assertions are touched.
Co-authored-By: Claude Sonnet <noreply at anthropic.com>
---
...lobal-value-or-symbol-after-call-entry.mir | 16 +-
.../test/CodeGen/MIR/Mips/memory-operands.mir | 56 +-
.../mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir | 2 +-
.../CodeGen/MIR/Mips/setRegClassOrRegBank.ll | 6 +-
.../CodeGen/MIR/Mips/setRegClassOrRegBank.mir | 12 +-
.../CodeGen/Mips/Fast-ISel/branch-dead-at.ll | 8 +-
.../CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll | 6 +-
.../GlobalISel/instruction-select/add.mir | 38 +-
.../GlobalISel/instruction-select/add_vec.mir | 64 +-
.../GlobalISel/instruction-select/bitwise.mir | 148 +--
.../GlobalISel/instruction-select/branch.mir | 32 +-
.../instruction-select/brindirect.mir | 12 +-
.../GlobalISel/instruction-select/bswap.mir | 8 +-
.../instruction-select/constants.mir | 4 +-
.../GlobalISel/instruction-select/ctlz.mir | 8 +-
.../instruction-select/fabs_vec.mir | 24 +-
.../GlobalISel/instruction-select/fcmp.mir | 240 ++--
.../GlobalISel/instruction-select/fence.mir | 8 +-
.../instruction-select/float_args.mir | 174 +--
...oating_point_vec_arithmetic_operations.mir | 128 +-
.../instruction-select/fsqrt_vec.mir | 24 +-
.../instruction-select/gloal_address.mir | 22 +-
.../instruction-select/gloal_address_pic.mir | 104 +-
.../GlobalISel/instruction-select/icmp.mir | 134 +--
.../instruction-select/implicit_def.mir | 60 +-
.../inttoptr_and_ptrtoint.mir | 16 +-
.../jump_table_and_brjt.mir | 54 +-
.../GlobalISel/instruction-select/load.mir | 36 +-
.../instruction-select/load_store_fold.mir | 78 +-
.../instruction-select/load_store_vec.mir | 72 +-
.../GlobalISel/instruction-select/mul.mir | 34 +-
.../GlobalISel/instruction-select/mul_vec.mir | 64 +-
.../GlobalISel/instruction-select/phi.mir | 120 +-
.../instruction-select/pointers.mir | 28 +-
.../instruction-select/rem_and_div.mir | 48 +-
.../instruction-select/rem_and_div_vec.mir | 256 ++--
.../GlobalISel/instruction-select/select.mir | 72 +-
.../instruction-select/sitofp_and_uitofp.mir | 40 +-
.../instruction-select/stack_args.mir | 52 +-
.../GlobalISel/instruction-select/store.mir | 42 +-
.../instruction-select/store_4_unaligned.mir | 8 +-
.../store_4_unaligned_r6.mir | 8 +-
.../GlobalISel/instruction-select/sub.mir | 12 +-
.../GlobalISel/instruction-select/sub_vec.mir | 64 +-
.../truncStore_and_aExtLoad.mir | 36 +-
.../GlobalISel/instruction-select/var_arg.mir | 44 +-
.../zextLoad_and_sextLoad.mir | 32 +-
.../Mips/GlobalISel/irtranslator/add.ll | 6 +-
.../irtranslator/aggregate_struct_return.ll | 32 +-
.../GlobalISel/irtranslator/big-endian.ll | 32 +-
.../Mips/GlobalISel/irtranslator/bitwise.ll | 30 +-
.../Mips/GlobalISel/irtranslator/call.ll | 170 +--
.../GlobalISel/irtranslator/extend_args.ll | 180 +--
.../GlobalISel/irtranslator/float_args.ll | 164 +--
.../GlobalISel/irtranslator/global_address.ll | 10 +-
.../irtranslator/global_address_pic.ll | 46 +-
.../Mips/GlobalISel/irtranslator/pointers.ll | 18 +-
.../GlobalISel/irtranslator/split_args.ll | 42 +-
.../GlobalISel/irtranslator/sret_pointer.ll | 16 +-
.../GlobalISel/irtranslator/stack_args.ll | 26 +-
.../Mips/GlobalISel/irtranslator/var_arg.ll | 20 +-
.../CodeGen/Mips/GlobalISel/legalizer/add.mir | 156 +--
.../Mips/GlobalISel/legalizer/add_vec.mir | 64 +-
.../GlobalISel/legalizer/add_vec_builtin.mir | 112 +-
.../Mips/GlobalISel/legalizer/bitreverse.mir | 30 +-
.../Mips/GlobalISel/legalizer/bitwise.mir | 350 +++---
.../Mips/GlobalISel/legalizer/branch.mir | 24 +-
.../Mips/GlobalISel/legalizer/brindirect.mir | 8 +-
.../Mips/GlobalISel/legalizer/bswap.mir | 30 +-
.../GlobalISel/legalizer/ceil_and_floor.mir | 48 +-
.../Mips/GlobalISel/legalizer/ctlz.mir | 20 +-
.../Mips/GlobalISel/legalizer/ctpop.mir | 20 +-
.../Mips/GlobalISel/legalizer/cttz.mir | 40 +-
.../GlobalISel/legalizer/dyn_stackalloc.mir | 44 +-
.../Mips/GlobalISel/legalizer/fabs_vec.mir | 24 +-
.../GlobalISel/legalizer/fabs_vec_builtin.mir | 24 +-
.../Mips/GlobalISel/legalizer/fence.mir | 8 +-
...oating_point_vec_arithmetic_operations.mir | 128 +-
...oint_vec_arithmetic_operations_builtin.mir | 128 +-
.../legalizer/fptosi_and_fptoui.mir | 48 +-
.../Mips/GlobalISel/legalizer/fsqrt_vec.mir | 24 +-
.../legalizer/fsqrt_vec_builtin.mir | 24 +-
.../GlobalISel/legalizer/global_address.mir | 20 +-
.../Mips/GlobalISel/legalizer/icmp.mir | 248 ++--
.../GlobalISel/legalizer/implicit_def.mir | 60 +-
.../legalizer/inttoptr_and_ptrtoint.mir | 16 +-
.../legalizer/jump_table_and_brjt.mir | 8 +-
.../Mips/GlobalISel/legalizer/load.mir | 32 +-
.../GlobalISel/legalizer/load_store_vec.mir | 72 +-
.../CodeGen/Mips/GlobalISel/legalizer/mul.mir | 176 +--
.../Mips/GlobalISel/legalizer/mul_vec.mir | 64 +-
.../GlobalISel/legalizer/mul_vec_builtin.mir | 64 +-
.../CodeGen/Mips/GlobalISel/legalizer/phi.mir | 136 +--
.../Mips/GlobalISel/legalizer/pointers.mir | 36 +-
.../Mips/GlobalISel/legalizer/rem_and_div.mir | 280 ++---
.../GlobalISel/legalizer/rem_and_div_vec.mir | 256 ++--
.../legalizer/rem_and_div_vec_builtin.mir | 256 ++--
.../Mips/GlobalISel/legalizer/select.mir | 116 +-
.../legalizer/sitofp_and_uitofp.mir | 296 ++---
.../Mips/GlobalISel/legalizer/stack_args.mir | 52 +-
.../Mips/GlobalISel/legalizer/store.mir | 44 +-
.../legalizer/store_4_unaligned.mir | 48 +-
...tore_split_because_of_memsize_or_align.mir | 432 +++----
.../CodeGen/Mips/GlobalISel/legalizer/sub.mir | 136 +--
.../Mips/GlobalISel/legalizer/sub_vec.mir | 64 +-
.../GlobalISel/legalizer/sub_vec_builtin.mir | 112 +-
.../Mips/GlobalISel/legalizer/trunc.mir | 10 +-
.../legalizer/truncStore_and_aExtLoad.mir | 64 +-
.../Mips/GlobalISel/legalizer/var_arg.mir | 42 +-
.../legalizer/zextLoad_and_sextLoad.mir | 80 +-
.../GlobalISel/legalizer/zext_and_sext.mir | 16 +-
.../GlobalISel/llvm-ir/big-endian-memory.ll | 8 +-
.../Mips/GlobalISel/llvm-ir/implicit_def.ll | 8 +-
.../GlobalISel/llvm-ir/load_4_unaligned.ll | 4 +-
.../load_split_because_of_memsize_or_align.ll | 14 +-
.../inline-memcpy.mir | 16 +-
.../inline-memset.mir | 16 +-
.../truncStore_and_aExtLoad.mir | 16 +-
.../mips-prelegalizer-combiner/tryCombine.mir | 16 +-
.../zextLoad_and_sextLoad.mir | 80 +-
.../TypeInfoforMF_skipCopies.mir | 28 +-
.../Mips/GlobalISel/regbankselect/add.mir | 12 +-
.../Mips/GlobalISel/regbankselect/add_vec.mir | 64 +-
.../Mips/GlobalISel/regbankselect/bitwise.mir | 96 +-
.../Mips/GlobalISel/regbankselect/branch.mir | 24 +-
.../GlobalISel/regbankselect/brindirect.mir | 8 +-
.../Mips/GlobalISel/regbankselect/bswap.mir | 8 +-
.../Mips/GlobalISel/regbankselect/ctlz.mir | 8 +-
.../GlobalISel/regbankselect/fabs_vec.mir | 24 +-
.../Mips/GlobalISel/regbankselect/fence.mir | 8 +-
.../GlobalISel/regbankselect/float_args.mir | 174 +--
...oating_point_vec_arithmetic_operations.mir | 128 +-
.../GlobalISel/regbankselect/fsqrt_vec.mir | 24 +-
.../regbankselect/global_address.mir | 20 +-
.../regbankselect/global_address_pic.mir | 40 +-
.../Mips/GlobalISel/regbankselect/icmp.mir | 24 +-
.../GlobalISel/regbankselect/implicit_def.mir | 60 +-
.../regbankselect/inttoptr_and_ptrtoint.mir | 16 +-
.../regbankselect/jump_table_and_brjt.mir | 8 +-
.../Mips/GlobalISel/regbankselect/load.mir | 56 +-
.../regbankselect/load_store_vec.mir | 72 +-
.../long_ambiguous_chain_s32.mir | 80 +-
.../long_ambiguous_chain_s64.mir | 80 +-
.../Mips/GlobalISel/regbankselect/mul.mir | 32 +-
.../Mips/GlobalISel/regbankselect/mul_vec.mir | 64 +-
.../Mips/GlobalISel/regbankselect/phi.mir | 88 +-
.../GlobalISel/regbankselect/pointers.mir | 36 +-
.../GlobalISel/regbankselect/rem_and_div.mir | 48 +-
.../regbankselect/rem_and_div_vec.mir | 256 ++--
.../Mips/GlobalISel/regbankselect/select.mir | 104 +-
.../regbankselect/sitofp_and_uitofp.mir | 36 +-
.../GlobalISel/regbankselect/stack_args.mir | 52 +-
.../Mips/GlobalISel/regbankselect/store.mir | 44 +-
.../regbankselect/store_4_unaligned.mir | 12 +-
.../Mips/GlobalISel/regbankselect/sub.mir | 12 +-
.../Mips/GlobalISel/regbankselect/sub_vec.mir | 64 +-
.../regbankselect/test_TypeInfoforMF.mir | 100 +-
.../regbankselect/truncStore_and_aExtLoad.mir | 36 +-
.../Mips/GlobalISel/regbankselect/var_arg.mir | 42 +-
.../regbankselect/zextLoad_and_sextLoad.mir | 48 +-
.../regbankselect/zext_and_sext.mir | 16 +-
llvm/test/CodeGen/Mips/atomic-min-max.ll | 32 +-
llvm/test/CodeGen/Mips/atomic.ll | 18 +-
llvm/test/CodeGen/Mips/avoid-zero-copy.mir | 30 +-
llvm/test/CodeGen/Mips/branch-dead-at.mir | 84 +-
...ldpairf64-extractelementf64-implicit-sp.ll | 12 +-
.../CodeGen/Mips/call-site-info-output.ll | 12 +-
.../CodeGen/Mips/cconv/illegal-vectors.ll | 4 +-
...ce-partial-redundant-reguse-terminator.mir | 10 +-
.../compact-branch-implicit-def.mir | 90 +-
.../Mips/compactbranches/empty-block.mir | 24 +-
llvm/test/CodeGen/Mips/copy-fp64.ll | 12 +-
.../isel-materialization.ll | 6 +-
.../Mips/dbg-call-site-info-reg-d-split.ll | 4 +-
...elay-slot-filler-bundled-insts-def-use.mir | 32 +-
.../Mips/delay-slot-filler-bundled-insts.mir | 66 +-
llvm/test/CodeGen/Mips/fake-use.ll | 2 +-
.../guards-verify-call.mir | 12 +-
.../guards-verify-tailcall.mir | 12 +-
.../test/CodeGen/Mips/instverify/dext-pos.mir | 6 +-
.../CodeGen/Mips/instverify/dext-size.mir | 6 +-
.../Mips/instverify/dextm-pos-size.mir | 6 +-
.../CodeGen/Mips/instverify/dextm-pos.mir | 6 +-
.../CodeGen/Mips/instverify/dextm-size.mir | 6 +-
.../Mips/instverify/dextu-pos-size.mir | 6 +-
.../CodeGen/Mips/instverify/dextu-pos.mir | 6 +-
.../Mips/instverify/dextu-size-valid.mir | 6 +-
.../CodeGen/Mips/instverify/dextu-size.mir | 6 +-
.../CodeGen/Mips/instverify/dins-pos-size.mir | 6 +-
.../test/CodeGen/Mips/instverify/dins-pos.mir | 6 +-
.../CodeGen/Mips/instverify/dins-size.mir | 6 +-
.../Mips/instverify/dinsm-pos-size.mir | 6 +-
.../CodeGen/Mips/instverify/dinsm-pos.mir | 6 +-
.../CodeGen/Mips/instverify/dinsm-size.mir | 6 +-
.../Mips/instverify/dinsu-pos-size.mir | 6 +-
.../CodeGen/Mips/instverify/dinsu-pos.mir | 6 +-
.../CodeGen/Mips/instverify/dinsu-size.mir | 6 +-
.../CodeGen/Mips/instverify/ext-pos-size.mir | 6 +-
llvm/test/CodeGen/Mips/instverify/ext-pos.mir | 6 +-
.../test/CodeGen/Mips/instverify/ext-size.mir | 6 +-
.../CodeGen/Mips/instverify/ins-pos-size.mir | 10 +-
llvm/test/CodeGen/Mips/instverify/ins-pos.mir | 10 +-
.../test/CodeGen/Mips/instverify/ins-size.mir | 10 +-
llvm/test/CodeGen/Mips/llvm-ir/call.ll | 4 +-
llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll | 172 +--
llvm/test/CodeGen/Mips/llvm-ir/load.ll | 1046 ++++++++---------
llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll | 26 +-
llvm/test/CodeGen/Mips/llvm-ir/store.ll | 604 +++++-----
.../longbranch/branch-limits-fp-micromips.mir | 78 +-
.../branch-limits-fp-micromipsr6.mir | 84 +-
.../Mips/longbranch/branch-limits-fp-mips.mir | 124 +-
.../longbranch/branch-limits-fp-mipsr6.mir | 108 +-
.../branch-limits-int-microMIPS.mir | 376 +++---
.../branch-limits-int-micromipsr6.mir | 480 ++++----
.../longbranch/branch-limits-int-mips64.mir | 372 +++---
.../longbranch/branch-limits-int-mips64r6.mir | 648 +++++-----
.../longbranch/branch-limits-int-mipsr6.mir | 480 ++++----
.../Mips/longbranch/branch-limits-int.mir | 312 ++---
.../Mips/longbranch/branch-limits-msa.mir | 820 ++++++-------
llvm/test/CodeGen/Mips/micromips-eva.mir | 10 +-
.../Mips/micromips-pseudo-mtlohi-expand.ll | 12 +-
.../Mips/micromips-short-delay-slot.mir | 22 +-
.../micromips-lwp-swp.mir | 176 +--
.../micromips-movep.mir | 76 +-
.../micromips-no-lwp-swp.mir | 128 +-
llvm/test/CodeGen/Mips/mips64-f128.ll | 4 +-
.../mirparser/target-flags-pic-mxgot-tls.mir | 102 +-
.../Mips/mirparser/target-flags-pic-o32.mir | 20 +-
.../Mips/mirparser/target-flags-pic.mir | 20 +-
.../mirparser/target-flags-static-tls.mir | 46 +-
.../test/CodeGen/Mips/msa/emergency-spill.mir | 104 +-
llvm/test/CodeGen/Mips/msa/ldr_str.ll | 8 +-
.../CodeGen/Mips/optimize-pic-call-dead-gp.ll | 58 +-
llvm/test/CodeGen/Mips/setcc-se.ll | 134 +--
...nk-wrap-buildpairf64-extractelementf64.mir | 40 +-
.../Mips/sll-micromips-r6-encoding.mir | 6 +-
.../CodeGen/Mips/sll64_64-is-not-a-copy.mir | 38 +-
.../CodeGen/Mips/unaligned-memops-mapping.mir | 20 +-
llvm/test/CodeGen/Mips/unaligned-memops.ll | 12 +-
...all-site-info-update-delay-slot-filler.mir | 22 +-
.../MIR/Mips/dbg-call-site-copy-sub-reg.mir | 50 +-
...l-site-delay-slot-interpretation-64bit.mir | 68 +-
...bg-call-site-delay-slot-interpretation.mir | 68 +-
.../Mips/dbg-call-site-param-addiu-64bit.mir | 60 +-
.../MIR/Mips/dbg-call-site-param-addiu.mir | 60 +-
.../DebugInfo/MIR/Mips/last-inst-bundled.mir | 48 +-
.../MIR/Mips/live-debug-values-reg-copy.mir | 126 +-
.../Mips/livedebugvars-stop-trimming-loc.mir | 44 +-
llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll | 8 +-
.../DebugInfo/Mips/dsr-non-fixed-objects.ll | 4 +-
.../DebugInfo/Mips/dw_op_entry_value_32bit.ll | 8 +-
.../DebugInfo/Mips/dw_op_entry_value_64bit.ll | 8 +-
.../Mips/livedebugvariables-reorder.mir | 8 +-
llvm/test/MC/Mips/eh-frame.s | 4 +-
.../Mips/print-assembled-snippet.s | 4 +-
255 files changed, 9122 insertions(+), 9122 deletions(-)
diff --git a/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir b/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
index 0ce54eb41d761..f5dfa12e53f85 100644
--- a/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
+++ b/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
@@ -12,7 +12,7 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '$a0' }
+ - { reg: '$r4' }
frameInfo:
stackSize: 24
maxAlignment: 4
@@ -21,21 +21,21 @@ frameInfo:
maxCallFrameSize: 16
stack:
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
- callee-saved-register: '$ra' }
+ callee-saved-register: '$r31' }
body: |
bb.0.entry:
- liveins: $a0, $ra
+ liveins: $r4, $r31
- Save16 $ra, 24, implicit-def $sp, implicit $sp
+ Save16 $r31, 24, implicit-def $r29, implicit $r29
$r2, $r3 = GotPrologue16 &_gp_disp, &_gp_disp
$r2 = SllX16 killed $r2, 16
$r2 = AdduRxRyRz16 killed $r3, killed $r2
; CHECK: [[@LINE+1]]:71: expected a global value or an external symbol after 'call-entry'
$r3 = LwRxRyOffMemX16 $r2, @foo, 0 :: (load (s32) from call-entry foo)
- $t9 = COPY $r3
- $gp = COPY killed $r2
- JumpLinkReg16 killed $r3, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $r2
+ $r25 = COPY $r3
+ $r28 = COPY killed $r2
+ JumpLinkReg16 killed $r3, csr_o32, implicit-def $r31, implicit killed $r25, implicit $r4, implicit killed $r28, implicit-def $r29, implicit-def dead $r2
$r2 = LiRxImmX16 0
- $ra = Restore16 24, implicit-def $sp, implicit $sp
+ $r31 = Restore16 24, implicit-def $r29, implicit $r29
RetRA16 implicit $r2
...
diff --git a/llvm/test/CodeGen/MIR/Mips/memory-operands.mir b/llvm/test/CodeGen/MIR/Mips/memory-operands.mir
index 22ed276a2dcf4..4371b37308b56 100644
--- a/llvm/test/CodeGen/MIR/Mips/memory-operands.mir
+++ b/llvm/test/CodeGen/MIR/Mips/memory-operands.mir
@@ -29,7 +29,7 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '$a0' }
+ - { reg: '$r4' }
frameInfo:
stackSize: 24
maxAlignment: 4
@@ -38,25 +38,25 @@ frameInfo:
maxCallFrameSize: 16
stack:
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
- callee-saved-register: '$ra' }
+ callee-saved-register: '$r31' }
body: |
bb.0.entry:
- liveins: $a0, $ra
+ liveins: $r4, $r31
- Save16 $ra, 24, implicit-def $sp, implicit $sp
+ Save16 $r31, 24, implicit-def $r29, implicit $r29
CFI_INSTRUCTION def_cfa_offset 24
- CFI_INSTRUCTION offset $ra_64, -4
+ CFI_INSTRUCTION offset $r31_64, -4
$r2, $r3 = GotPrologue16 &_gp_disp, &_gp_disp
$r2 = SllX16 killed $r2, 16
$r2 = AdduRxRyRz16 killed $r3, killed $r2
; CHECK-LABEL: name: test
; CHECK: $r3 = LwRxRyOffMemX16 $r2, @foo :: (load (s32) from call-entry @foo)
$r3 = LwRxRyOffMemX16 $r2, @foo :: (load (s32) from call-entry @foo)
- $t9 = COPY $r3
- $gp = COPY killed $r2
- JumpLinkReg16 killed $r3, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $r2
+ $r25 = COPY $r3
+ $r28 = COPY killed $r2
+ JumpLinkReg16 killed $r3, csr_o32, implicit-def $r31, implicit killed $r25, implicit $r4, implicit killed $r28, implicit-def $r29, implicit-def dead $r2
$r2 = LiRxImmX16 0
- $ra = Restore16 24, implicit-def $sp, implicit $sp
+ $r31 = Restore16 24, implicit-def $r29, implicit $r29
RetRA16 implicit $r2
...
---
@@ -70,33 +70,33 @@ frameInfo:
maxCallFrameSize: 16
stack:
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
- callee-saved-register: '$ra' }
+ callee-saved-register: '$r31' }
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4,
- callee-saved-register: '$s2' }
+ callee-saved-register: '$r18' }
- { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4,
- callee-saved-register: '$s0' }
+ callee-saved-register: '$r16' }
body: |
bb.0.entry:
- liveins: $ra, $s2, $s0, $ra, $s2, $s0
+ liveins: $r31, $r18, $r16, $r31, $r18, $r16
- SaveX16 $s0, $ra, $s2, 32, implicit-def $sp, implicit $sp
+ SaveX16 $r16, $r31, $r18, 32, implicit-def $r29, implicit $r29
CFI_INSTRUCTION def_cfa_offset 32
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s2_64, -8
- CFI_INSTRUCTION offset $s0_64, -12
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r18_64, -8
+ CFI_INSTRUCTION offset $r16_64, -12
$r2, $r3 = GotPrologue16 &_gp_disp, &_gp_disp
$r2 = SllX16 killed $r2, 16
- $s0 = AdduRxRyRz16 killed $r3, killed $r2
- $r2 = LwRxRyOffMemX16 $s0, @g :: (load (s32) from call-entry @g)
+ $r16 = AdduRxRyRz16 killed $r3, killed $r2
+ $r2 = LwRxRyOffMemX16 $r16, @g :: (load (s32) from call-entry @g)
; CHECK-LABEL: test2
- ; CHECK: $r3 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load (s32) from call-entry &__mips16_call_stub_sf_0)
- $r3 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load (s32) from call-entry &__mips16_call_stub_sf_0)
- $gp = COPY $s0
- JumpLinkReg16 killed $r3, csr_o32, implicit-def $ra, implicit $r2, implicit killed $gp, implicit-def $sp, implicit-def $r2
- $r3 = LwRxRyOffMemX16 $s0, @__mips16_ret_sf :: (load (s32) from call-entry @__mips16_ret_sf)
- $t9 = COPY $r3
- $gp = COPY killed $s0
- JumpLinkReg16 killed $r3, csr_mips16rethelper, implicit-def $ra, implicit killed $t9, implicit $r2, implicit killed $gp, implicit-def $sp
- $s0, $ra, $s2 = RestoreX16 32, implicit-def $sp, implicit $sp
+ ; CHECK: $r3 = LwRxRyOffMemX16 $r16, &__mips16_call_stub_sf_0 :: (load (s32) from call-entry &__mips16_call_stub_sf_0)
+ $r3 = LwRxRyOffMemX16 $r16, &__mips16_call_stub_sf_0 :: (load (s32) from call-entry &__mips16_call_stub_sf_0)
+ $r28 = COPY $r16
+ JumpLinkReg16 killed $r3, csr_o32, implicit-def $r31, implicit $r2, implicit killed $r28, implicit-def $r29, implicit-def $r2
+ $r3 = LwRxRyOffMemX16 $r16, @__mips16_ret_sf :: (load (s32) from call-entry @__mips16_ret_sf)
+ $r25 = COPY $r3
+ $r28 = COPY killed $r16
+ JumpLinkReg16 killed $r3, csr_mips16rethelper, implicit-def $r31, implicit killed $r25, implicit $r2, implicit killed $r28, implicit-def $r29
+ $r16, $r31, $r18 = RestoreX16 32, implicit-def $r29, implicit $r29
RetRA16 implicit $r2
...
diff --git a/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir b/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir
index cf2210adb1637..7a60535296ae4 100644
--- a/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir
+++ b/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir
@@ -15,7 +15,7 @@ body: |
%3:gpr32 = COPY renamable %1:fgr64cc
; CHECK: mfc1
%4:gpr32 = SUBu %3:gpr32, %2:gpr32
- BEQ %3:gpr32, $zero, %bb.2, implicit-def dead $at
+ BEQ %3:gpr32, $r0, %bb.2, implicit-def dead $r1
bb.1:
$r2 = ADDiu %4:gpr32, 1
diff --git a/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll b/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
index f2632d8dc05ac..de10564e47cc7 100644
--- a/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
+++ b/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
@@ -12,9 +12,9 @@ declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
define void @add_v4i32_builtin_imm(ptr %a, ptr %c) {
; P5600-LABEL: name: add_v4i32_builtin_imm
; P5600: bb.1.entry:
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
diff --git a/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir b/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
index f387a6cc604f7..ece84a8040091 100644
--- a/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
+++ b/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
@@ -19,18 +19,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: add_v4i32_builtin_imm
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/branch-dead-at.ll b/llvm/test/CodeGen/Mips/Fast-ISel/branch-dead-at.ll
index e9d5d957a5965..97466f3e843a9 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/branch-dead-at.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/branch-dead-at.ll
@@ -8,13 +8,13 @@ define void @cond_br(i1 %c) {
; CHECK-LABEL: name: cond_br
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK-NEXT: liveins: $a0
+ ; CHECK-NEXT: liveins: $r4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
; CHECK-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY1]], 1
- ; CHECK-NEXT: BGTZ [[ANDi]], %bb.1, implicit-def dead $at
- ; CHECK-NEXT: B %bb.2, implicit-def dead $at
+ ; CHECK-NEXT: BGTZ [[ANDi]], %bb.1, implicit-def dead $r1
+ ; CHECK-NEXT: B %bb.2, implicit-def dead $r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1 (%ir-block.1):
; CHECK-NEXT: RetRA
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll b/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
index bf4a1a65c9acd..cecb9d5820fba 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
@@ -4,10 +4,10 @@
define i32 @mul(i32 %a, i32 %b) {
; CHECK-LABEL: name: mul
; CHECK: bb.0.entry:
- ; CHECK-NEXT: liveins: $a0, $a1
+ ; CHECK-NEXT: liveins: $r4, $r5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r5
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $r4
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY]]
; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY2]], [[COPY3]], implicit-def dead $hi0, implicit-def dead $lo0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
index 80fa5ee8fab41..b58d9b7901f84 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
@@ -16,17 +16,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: add_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[ADDu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_ADD %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -40,15 +40,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: add_imm
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[COPY]], 3
; MIPS32: $r2 = COPY [[ADDiu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 3
%2:gprb(s32) = G_ADD %0, %1
$r2 = COPY %2(s32)
@@ -63,15 +63,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: add_negative_imm
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[COPY]], -3
; MIPS32: $r2 = COPY [[ADDiu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 -3
%2:gprb(s32) = G_ADD %0, %1
$r2 = COPY %2(s32)
@@ -86,16 +86,16 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: add_not_imm32SExt16
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 65535
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 65535
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY]], [[ORi]]
; MIPS32: $r2 = COPY [[ADDu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 65535
%2:gprb(s32) = G_ADD %0, %1
$r2 = COPY %2(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir
index 72ddaa48c9f74..ec7a551e0f8ca 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir
@@ -16,21 +16,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
; P5600: [[ADDV_B:%[0-9]+]]:msa128b = ADDV_B [[LD_B1]], [[LD_B]]
; P5600: ST_B [[ADDV_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:fprb(<16 x s8>) = G_ADD %4, %3
@@ -46,21 +46,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
; P5600: [[ADDV_H:%[0-9]+]]:msa128h = ADDV_H [[LD_H1]], [[LD_H]]
; P5600: ST_H [[ADDV_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:fprb(<8 x s16>) = G_ADD %4, %3
@@ -76,21 +76,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[ADDV_W:%[0-9]+]]:msa128w = ADDV_W [[LD_W1]], [[LD_W]]
; P5600: ST_W [[ADDV_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_ADD %4, %3
@@ -106,21 +106,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[ADDV_D:%[0-9]+]]:msa128d = ADDV_D [[LD_D1]], [[LD_D]]
; P5600: ST_D [[ADDV_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_ADD %4, %3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir
index 18ed022619f2b..b7afa51865890 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir
@@ -27,17 +27,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: and_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[AND]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_AND %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -51,15 +51,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: and_imm
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 255
; MIPS32: $r2 = COPY [[ANDi]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 255
%2:gprb(s32) = G_AND %0, %1
$r2 = COPY %2(s32)
@@ -74,16 +74,16 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: and_not_imm32ZExt16
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65280
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 65280
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ADDiu]]
; MIPS32: $r2 = COPY [[AND]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 -256
%2:gprb(s32) = G_AND %0, %1
$r2 = COPY %2(s32)
@@ -98,17 +98,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: or_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[OR]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_OR %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -122,15 +122,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: or_imm
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[COPY]], 65535
; MIPS32: $r2 = COPY [[ORi]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 65535
%2:gprb(s32) = G_OR %0, %1
$r2 = COPY %2(s32)
@@ -145,16 +145,16 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: or_not_imm32ZExt16
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 1
; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY]], [[LUi]]
; MIPS32: $r2 = COPY [[OR]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 65536
%2:gprb(s32) = G_OR %0, %1
$r2 = COPY %2(s32)
@@ -169,17 +169,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: xor_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[XOR]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_XOR %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -193,15 +193,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: xor_imm
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[COPY]], 1
; MIPS32: $r2 = COPY [[XORi]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 1
%2:gprb(s32) = G_XOR %0, %1
$r2 = COPY %2(s32)
@@ -216,15 +216,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: xor_not_imm32ZExt16
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[NOR:%[0-9]+]]:gpr32 = NOR [[COPY]], $zero
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[NOR:%[0-9]+]]:gpr32 = NOR [[COPY]], $r0
; MIPS32: $r2 = COPY [[NOR]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 -1
%2:gprb(s32) = G_XOR %0, %1
$r2 = COPY %2(s32)
@@ -239,15 +239,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: shl
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[SLL:%[0-9]+]]:gpr32 = SLL [[COPY]], 1
; MIPS32: $r2 = COPY [[SLL]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 1
%2:gprb(s32) = G_SHL %0, %1
$r2 = COPY %2(s32)
@@ -262,15 +262,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ashr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[SRA:%[0-9]+]]:gpr32 = SRA [[COPY]], 1
; MIPS32: $r2 = COPY [[SRA]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 1
%2:gprb(s32) = G_ASHR %0, %1
$r2 = COPY %2(s32)
@@ -285,15 +285,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: lshr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[SRL:%[0-9]+]]:gpr32 = SRL [[COPY]], 1
; MIPS32: $r2 = COPY [[SRL]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 1
%2:gprb(s32) = G_LSHR %0, %1
$r2 = COPY %2(s32)
@@ -308,17 +308,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: shlv
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SLLV:%[0-9]+]]:gpr32 = SLLV [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[SLLV]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_SHL %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -332,17 +332,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ashrv
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SRAV:%[0-9]+]]:gpr32 = SRAV [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[SRAV]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_ASHR %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -356,17 +356,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: lshrv
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SRLV:%[0-9]+]]:gpr32 = SRLV [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[SRLV]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_LSHR %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
index c97de3f7d4d15..51a3062a6ae01 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
@@ -34,10 +34,10 @@ body: |
; MIPS32-LABEL: name: Unconditional_branch
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.2(0x80000000)
- ; MIPS32-NEXT: liveins: $a0, $a1
+ ; MIPS32-NEXT: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32-NEXT: J %bb.2, implicit-def dead $at
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32-NEXT: J %bb.2, implicit-def dead $r1
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.1.end:
; MIPS32-NEXT: $r2 = COPY [[COPY]]
@@ -46,11 +46,11 @@ body: |
; MIPS32-NEXT: bb.2.block:
; MIPS32-NEXT: successors: %bb.1(0x80000000)
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: J %bb.1, implicit-def dead $at
+ ; MIPS32-NEXT: J %bb.1, implicit-def dead $r1
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
G_BR %bb.3
bb.2.end:
@@ -71,14 +71,14 @@ body: |
; MIPS32-LABEL: name: Conditional_branch
; MIPS32: bb.0 (%ir-block.0):
; MIPS32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
- ; MIPS32-NEXT: J %bb.2, implicit-def dead $at
+ ; MIPS32-NEXT: BNE [[ANDi]], $r0, %bb.1, implicit-def dead $r1
+ ; MIPS32-NEXT: J %bb.2, implicit-def dead $r1
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.1.if.then:
; MIPS32-NEXT: $r2 = COPY [[COPY1]]
@@ -88,11 +88,11 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[COPY2]]
; MIPS32-NEXT: RetRA implicit $r2
bb.1 (%ir-block.0):
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- %2:gprb(s32) = COPY $a2
+ %3:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ %2:gprb(s32) = COPY $r6
%5:gprb(s32) = G_CONSTANT i32 1
%6:gprb(s32) = COPY %3(s32)
%4:gprb(s32) = G_AND %6, %5
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir
index 1041d8a50656a..d91ff5816329b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir
@@ -24,10 +24,10 @@ body: |
; MIPS32-LABEL: name: indirectbr
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
- ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 1
+ ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $r0, 0
; MIPS32: PseudoIndirectBranch [[COPY]]
; MIPS32: bb.1.L1:
; MIPS32: $r2 = COPY [[ORi1]]
@@ -37,9 +37,9 @@ body: |
; MIPS32: RetRA implicit $r2
bb.1.entry:
successors: %bb.2, %bb.3
- liveins: $a0
+ liveins: $r4
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 1
%2:gprb(s32) = G_CONSTANT i32 0
G_BRINDIRECT %0(p0)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir
index 0c2fc16f3cb4a..e04d3b6b6042e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir
@@ -13,16 +13,16 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32R2-LABEL: name: bswap_i32
- ; MIPS32R2: liveins: $a0
- ; MIPS32R2: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32R2: liveins: $r4
+ ; MIPS32R2: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32R2: [[WSBH:%[0-9]+]]:gpr32 = WSBH [[COPY]]
; MIPS32R2: [[ROTR:%[0-9]+]]:gpr32 = ROTR [[WSBH]], 16
; MIPS32R2: $r2 = COPY [[ROTR]]
; MIPS32R2: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_BSWAP %0
$r2 = COPY %1(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir
index 7408789aa5ea0..4ffd04b13f991 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir
@@ -34,7 +34,7 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: _0x00008000
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 32768
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 32768
; MIPS32: $r2 = COPY [[ORi]]
; MIPS32: RetRA implicit $r2
%0:gprb(s32) = G_CONSTANT i32 32768
@@ -51,7 +51,7 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: _0xFFFFFFF6
- ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65526
+ ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 65526
; MIPS32: $r2 = COPY [[ADDiu]]
; MIPS32: RetRA implicit $r2
%0:gprb(s32) = G_CONSTANT i32 -10
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ctlz.mir
index 1ea90ab4cd2b5..dcd5088fbf629 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ctlz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ctlz.mir
@@ -8,15 +8,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ctlz_i32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[CLZ:%[0-9]+]]:gpr32 = CLZ [[COPY]]
; MIPS32: $r2 = COPY [[CLZ]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(s32) = G_CTLZ %0(s32)
$r2 = COPY %1(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs_vec.mir
index 2e7dd7a2432ed..fe339caa45009 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs_vec.mir
@@ -14,18 +14,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: fabs_v4f32
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[FABS_W:%[0-9]+]]:msa128w = FABS_W [[LD_W]]
; P5600: ST_W [[FABS_W]], [[COPY1]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:fprb(<4 x s32>) = G_FABS %2
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
@@ -40,18 +40,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: fabs_v2f64
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[FABS_D:%[0-9]+]]:msa128d = FABS_D [[LD_D]]
; P5600: ST_D [[FABS_D]], [[COPY1]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:fprb(<2 x s64>) = G_FABS %2
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir
index 32eabec16962d..ecab5b79184bf 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir
@@ -50,12 +50,12 @@ body: |
; FP32-LABEL: name: false_s
; FP32: liveins: $f12, $f14
- ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 0
; FP32: $r2 = COPY [[ORi]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: false_s
; FP64: liveins: $f12, $f14
- ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 0
; FP64: $r2 = COPY [[ORi]]
; FP64: RetRA implicit $r2
%5:gprb(s32) = G_CONSTANT i32 0
@@ -76,12 +76,12 @@ body: |
; FP32-LABEL: name: true_s
; FP32: liveins: $f12, $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 65535
; FP32: $r2 = COPY [[ADDiu]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: true_s
; FP64: liveins: $f12, $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 65535
; FP64: $r2 = COPY [[ADDiu]]
; FP64: RetRA implicit $r2
%5:gprb(s32) = G_CONSTANT i32 -1
@@ -104,18 +104,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: uno_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -140,18 +140,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ord_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -176,18 +176,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: oeq_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -212,18 +212,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: une_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -248,18 +248,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ueq_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -284,18 +284,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: one_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -320,18 +320,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: olt_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -356,18 +356,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: uge_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -392,18 +392,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ult_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -428,18 +428,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: oge_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -464,18 +464,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ole_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -500,18 +500,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ugt_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -536,18 +536,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ule_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -572,18 +572,18 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ogt_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s32) = COPY $f12
@@ -606,12 +606,12 @@ body: |
; FP32-LABEL: name: false_d
; FP32: liveins: $d6, $d7
- ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 0
; FP32: $r2 = COPY [[ORi]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: false_d
; FP64: liveins: $d6, $d7
- ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 0
; FP64: $r2 = COPY [[ORi]]
; FP64: RetRA implicit $r2
%5:gprb(s32) = G_CONSTANT i32 0
@@ -632,12 +632,12 @@ body: |
; FP32-LABEL: name: true_d
; FP32: liveins: $d6, $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 65535
; FP32: $r2 = COPY [[ADDiu]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: true_d
; FP64: liveins: $d6, $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 65535
; FP64: $r2 = COPY [[ADDiu]]
; FP64: RetRA implicit $r2
%5:gprb(s32) = G_CONSTANT i32 -1
@@ -660,18 +660,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: uno_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -696,18 +696,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ord_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -732,18 +732,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: oeq_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -768,18 +768,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: une_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -804,18 +804,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ueq_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -840,18 +840,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: one_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -876,18 +876,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: olt_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -912,18 +912,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: uge_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -948,18 +948,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ult_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -984,18 +984,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: oge_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -1020,18 +1020,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ole_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -1056,18 +1056,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ugt_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -1092,18 +1092,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
- ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVF_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ule_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
- ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVF_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
@@ -1128,18 +1128,18 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP32: FCMP_D32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
- ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP32: $r2 = COPY [[MOVT_I]]
; FP32: RetRA implicit $r2
; FP64-LABEL: name: ogt_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
+ ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 1
; FP64: FCMP_D64 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
- ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
+ ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $r0, $fcc0, [[ADDiu]]
; FP64: $r2 = COPY [[MOVT_I]]
; FP64: RetRA implicit $r2
%0:fprb(s64) = COPY $d6
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
index 25ca5279f5478..6e8b2c80531dd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
@@ -13,16 +13,16 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: atomic_load_i32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load monotonic (s32) from %ir.ptr)
; MIPS32: SYNC 0
; MIPS32: $r2 = COPY [[LW]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:gprb(s32) = G_LOAD %0(p0) :: (load monotonic (s32) from %ir.ptr)
G_FENCE 4, 1
$r2 = COPY %1(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_args.mir
index 78e52013e1aa3..75c7ef7197b76 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_args.mir
@@ -71,19 +71,19 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; FP32-LABEL: name: float_in_gpr
- ; FP32: liveins: $a0, $a1
- ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a1
+ ; FP32: liveins: $r4, $r5
+ ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r5
; FP32: $f0 = COPY [[COPY]]
; FP32: RetRA implicit $f0
; FP64-LABEL: name: float_in_gpr
- ; FP64: liveins: $a0, $a1
- ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a1
+ ; FP64: liveins: $r4, $r5
+ ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r5
; FP64: $f0 = COPY [[COPY]]
; FP64: RetRA implicit $f0
- %1:gprb(s32) = COPY $a1
+ %1:gprb(s32) = COPY $r5
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -96,24 +96,24 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; FP32-LABEL: name: double_in_gpr
- ; FP32: liveins: $a0, $a2, $a3
- ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a2
- ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a3
+ ; FP32: liveins: $r4, $r6, $r7
+ ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r6
+ ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r7
; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 [[COPY]], [[COPY1]]
; FP32: $d0 = COPY [[BuildPairF64_]]
; FP32: RetRA implicit $d0
; FP64-LABEL: name: double_in_gpr
- ; FP64: liveins: $a0, $a2, $a3
- ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a2
- ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a3
+ ; FP64: liveins: $r4, $r6, $r7
+ ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r6
+ ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $r7
; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64 = BuildPairF64_64 [[COPY]], [[COPY1]]
; FP64: $d0 = COPY [[BuildPairF64_64_]]
; FP64: RetRA implicit $d0
- %2:gprb(s32) = COPY $a2
- %3:gprb(s32) = COPY $a3
+ %2:gprb(s32) = COPY $r6
+ %3:gprb(s32) = COPY $r7
%1:fprb(s64) = G_MERGE_VALUES %2(s32), %3(s32)
$d0 = COPY %1(s64)
RetRA implicit $d0
@@ -133,34 +133,34 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32: $f12 = COPY [[COPY]]
; FP32: $f14 = COPY [[COPY1]]
- ; FP32: JAL @float_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ ; FP32: JAL @float_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit $f14, implicit-def $f0
; FP32: [[COPY2:%[0-9]+]]:fgr32 = COPY $f0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $f0 = COPY [[COPY2]]
; FP32: RetRA implicit $f0
; FP64-LABEL: name: call_float_in_fpr
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64: $f12 = COPY [[COPY]]
; FP64: $f14 = COPY [[COPY1]]
- ; FP64: JAL @float_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ ; FP64: JAL @float_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit $f14, implicit-def $f0
; FP64: [[COPY2:%[0-9]+]]:fgr32 = COPY $f0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $f0 = COPY [[COPY2]]
; FP64: RetRA implicit $f0
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = COPY $f14
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
$f12 = COPY %0(s32)
$f14 = COPY %1(s32)
- JAL @float_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ JAL @float_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit $f14, implicit-def $f0
%2:fprb(s32) = COPY $f0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$f0 = COPY %2(s32)
RetRA implicit $f0
@@ -179,34 +179,34 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32: $d6 = COPY [[COPY]]
; FP32: $d7 = COPY [[COPY1]]
- ; FP32: JAL @double_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+ ; FP32: JAL @double_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit $d7, implicit-def $d0
; FP32: [[COPY2:%[0-9]+]]:afgr64 = COPY $d0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $d0 = COPY [[COPY2]]
; FP32: RetRA implicit $d0
; FP64-LABEL: name: call_double_in_fpr
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64: $d6 = COPY [[COPY]]
; FP64: $d7 = COPY [[COPY1]]
- ; FP64: JAL @double_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+ ; FP64: JAL @double_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit $d7, implicit-def $d0
; FP64: [[COPY2:%[0-9]+]]:fgr64 = COPY $d0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $d0 = COPY [[COPY2]]
; FP64: RetRA implicit $d0
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = COPY $d7
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
$d6 = COPY %0(s64)
$d7 = COPY %1(s64)
- JAL @double_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+ JAL @double_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit $d7, implicit-def $d0
%2:fprb(s64) = COPY $d0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$d0 = COPY %2(s64)
RetRA implicit $d0
@@ -219,40 +219,40 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; FP32-LABEL: name: call_float_in_gpr
- ; FP32: liveins: $a0, $a1
- ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32: $a0 = COPY [[COPY]]
- ; FP32: $a1 = COPY [[COPY1]]
- ; FP32: JAL @float_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+ ; FP32: liveins: $r4, $r5
+ ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP32: $r4 = COPY [[COPY]]
+ ; FP32: $r5 = COPY [[COPY1]]
+ ; FP32: JAL @float_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $f0
; FP32: [[COPY2:%[0-9]+]]:fgr32 = COPY $f0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $f0 = COPY [[COPY2]]
; FP32: RetRA implicit $f0
; FP64-LABEL: name: call_float_in_gpr
- ; FP64: liveins: $a0, $a1
- ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64: $a0 = COPY [[COPY]]
- ; FP64: $a1 = COPY [[COPY1]]
- ; FP64: JAL @float_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+ ; FP64: liveins: $r4, $r5
+ ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP64: $r4 = COPY [[COPY]]
+ ; FP64: $r5 = COPY [[COPY1]]
+ ; FP64: JAL @float_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $f0
; FP64: [[COPY2:%[0-9]+]]:fgr32 = COPY $f0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $f0 = COPY [[COPY2]]
; FP64: RetRA implicit $f0
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %0(s32)
- $a1 = COPY %1(s32)
- JAL @float_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %0(s32)
+ $r5 = COPY %1(s32)
+ JAL @float_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $f0
%2:fprb(s32) = COPY $f0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$f0 = COPY %2(s32)
RetRA implicit $f0
@@ -265,46 +265,46 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; FP32-LABEL: name: call_double_in_gpr
- ; FP32: liveins: $a0, $a2, $a3
- ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
- ; FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32: $a0 = COPY [[COPY]]
- ; FP32: $a2 = COPY [[COPY1]]
- ; FP32: $a3 = COPY [[COPY2]]
- ; FP32: JAL @double_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+ ; FP32: liveins: $r4, $r6, $r7
+ ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r6
+ ; FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r7
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP32: $r4 = COPY [[COPY]]
+ ; FP32: $r6 = COPY [[COPY1]]
+ ; FP32: $r7 = COPY [[COPY2]]
+ ; FP32: JAL @double_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $d0
; FP32: [[COPY3:%[0-9]+]]:afgr64 = COPY $d0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $d0 = COPY [[COPY3]]
; FP32: RetRA implicit $d0
; FP64-LABEL: name: call_double_in_gpr
- ; FP64: liveins: $a0, $a2, $a3
- ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
- ; FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64: $a0 = COPY [[COPY]]
- ; FP64: $a2 = COPY [[COPY1]]
- ; FP64: $a3 = COPY [[COPY2]]
- ; FP64: JAL @double_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+ ; FP64: liveins: $r4, $r6, $r7
+ ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $r6
+ ; FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $r7
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP64: $r4 = COPY [[COPY]]
+ ; FP64: $r6 = COPY [[COPY1]]
+ ; FP64: $r7 = COPY [[COPY2]]
+ ; FP64: JAL @double_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $d0
; FP64: [[COPY3:%[0-9]+]]:fgr64 = COPY $d0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $d0 = COPY [[COPY3]]
; FP64: RetRA implicit $d0
- %0:gprb(s32) = COPY $a0
- %2:gprb(s32) = COPY $a2
- %3:gprb(s32) = COPY $a3
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %0(s32)
- $a2 = COPY %2(s32)
- $a3 = COPY %3(s32)
- JAL @double_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+ %0:gprb(s32) = COPY $r4
+ %2:gprb(s32) = COPY $r6
+ %3:gprb(s32) = COPY $r7
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %0(s32)
+ $r6 = COPY %2(s32)
+ $r7 = COPY %3(s32)
+ JAL @double_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $d0
%4:fprb(s64) = COPY $d0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$d0 = COPY %4(s64)
RetRA implicit $d0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/floating_point_vec_arithmetic_operations.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/floating_point_vec_arithmetic_operations.mir
index c19b123b30a34..fd5a786c411e6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/floating_point_vec_arithmetic_operations.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/floating_point_vec_arithmetic_operations.mir
@@ -23,21 +23,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fadd_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[FADD_W:%[0-9]+]]:msa128w = FADD_W [[LD_W]], [[LD_W1]]
; P5600: ST_W [[FADD_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_FADD %3, %4
@@ -53,21 +53,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fadd_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[FADD_D:%[0-9]+]]:msa128d = FADD_D [[LD_D]], [[LD_D1]]
; P5600: ST_D [[FADD_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_FADD %3, %4
@@ -83,21 +83,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fsub_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[FSUB_W:%[0-9]+]]:msa128w = FSUB_W [[LD_W]], [[LD_W1]]
; P5600: ST_W [[FSUB_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_FSUB %3, %4
@@ -113,21 +113,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fsub_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[FSUB_D:%[0-9]+]]:msa128d = FSUB_D [[LD_D]], [[LD_D1]]
; P5600: ST_D [[FSUB_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_FSUB %3, %4
@@ -143,21 +143,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fmul_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[FMUL_W:%[0-9]+]]:msa128w = FMUL_W [[LD_W]], [[LD_W1]]
; P5600: ST_W [[FMUL_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_FMUL %3, %4
@@ -173,21 +173,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fmul_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[FMUL_D:%[0-9]+]]:msa128d = FMUL_D [[LD_D]], [[LD_D1]]
; P5600: ST_D [[FMUL_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_FMUL %3, %4
@@ -203,21 +203,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fdiv_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[FDIV_W:%[0-9]+]]:msa128w = FDIV_W [[LD_W]], [[LD_W1]]
; P5600: ST_W [[FDIV_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_FDIV %3, %4
@@ -233,21 +233,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fdiv_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[FDIV_D:%[0-9]+]]:msa128d = FDIV_D [[LD_D]], [[LD_D1]]
; P5600: ST_D [[FDIV_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_FDIV %3, %4
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt_vec.mir
index 4458b39212c37..ff48635928772 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt_vec.mir
@@ -14,18 +14,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: sqrt_v4f32
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[FSQRT_W:%[0-9]+]]:msa128w = FSQRT_W [[LD_W]]
; P5600: ST_W [[FSQRT_W]], [[COPY1]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:fprb(<4 x s32>) = G_FSQRT %2
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
@@ -40,18 +40,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: sqrt_v2f64
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[FSQRT_D:%[0-9]+]]:msa128d = FSQRT_D [[LD_D]]
; P5600: ST_D [[FSQRT_D]], [[COPY1]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:fprb(<2 x s64>) = G_FSQRT %2
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
index f24d2dcb33b9e..efcf72f8af5a5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
@@ -21,24 +21,24 @@ body: |
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @.str
; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 18838
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi1]], 722
- ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[ADDiu]]
- ; MIPS32: $a1 = COPY [[ORi]]
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $r0, 0
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[ADDiu]]
+ ; MIPS32: $r5 = COPY [[ORi]]
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[ORi1]]
; MIPS32: RetRA implicit $r2
%2:gprb(p0) = G_GLOBAL_VALUE @.str
%1:gprb(p0) = COPY %2(p0)
%3:gprb(s32) = G_CONSTANT i32 1234567890
%4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %1(p0)
- $a1 = COPY %3(s32)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %1(p0)
+ $r5 = COPY %3(s32)
+ JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
%0:gprb(s32) = COPY $r2
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$r2 = COPY %4(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir
index 482f630ffacec..29a394a6539ce 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir
@@ -21,17 +21,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: f_with_local_linkage
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[ADDu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_ADD %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -45,35 +45,35 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $t9, $r2
+ liveins: $r4, $r5, $r25, $r2
; MIPS32-LABEL: name: call_global
- ; MIPS32: liveins: $a0, $a1, $t9, $r2, $t9, $r2
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: liveins: $r4, $r5, $r25, $r2, $r25, $r2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got-call) @f :: (load (s32) from got)
- ; MIPS32: $a0 = COPY [[COPY]]
- ; MIPS32: $a1 = COPY [[COPY1]]
- ; MIPS32: $gp = COPY [[ADDu1]]
- ; MIPS32: JALRPseudo [[LW]], csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ ; MIPS32: $r4 = COPY [[COPY]]
+ ; MIPS32: $r5 = COPY [[COPY1]]
+ ; MIPS32: $r28 = COPY [[ADDu1]]
+ ; MIPS32: JALRPseudo [[LW]], csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r28, implicit-def $r2
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY2]]
; MIPS32: RetRA implicit $r2
- %4:gpr32 = ADDu $r2, $t9
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ %4:gpr32 = ADDu $r2, $r25
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
%3:gpr32(p0) = G_GLOBAL_VALUE target-flags(mips-got-call) @f
- $a0 = COPY %0(s32)
- $a1 = COPY %1(s32)
- $gp = COPY %4
- JALRPseudo %3(p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ $r4 = COPY %0(s32)
+ $r5 = COPY %1(s32)
+ $r28 = COPY %4
+ JALRPseudo %3(p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r28, implicit-def $r2
%2:gprb(s32) = COPY $r2
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -86,36 +86,36 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $t9, $r2
+ liveins: $r4, $r5, $r25, $r2
; MIPS32-LABEL: name: call_global_with_local_linkage
- ; MIPS32: liveins: $a0, $a1, $t9, $r2, $t9, $r2
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: liveins: $r4, $r5, $r25, $r2, $r25, $r2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) @f_with_local_linkage :: (load (s32) from got)
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LW]], target-flags(mips-abs-lo) @f_with_local_linkage
- ; MIPS32: $a0 = COPY [[COPY]]
- ; MIPS32: $a1 = COPY [[COPY1]]
- ; MIPS32: $gp = COPY [[ADDu1]]
- ; MIPS32: JALRPseudo [[ADDiu]], csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ ; MIPS32: $r4 = COPY [[COPY]]
+ ; MIPS32: $r5 = COPY [[COPY1]]
+ ; MIPS32: $r28 = COPY [[ADDu1]]
+ ; MIPS32: JALRPseudo [[ADDiu]], csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r28, implicit-def $r2
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY2]]
; MIPS32: RetRA implicit $r2
- %4:gpr32 = ADDu $r2, $t9
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ %4:gpr32 = ADDu $r2, $r25
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
%3:gpr32(p0) = G_GLOBAL_VALUE @f_with_local_linkage
- $a0 = COPY %0(s32)
- $a1 = COPY %1(s32)
- $gp = COPY %4
- JALRPseudo %3(p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ $r4 = COPY %0(s32)
+ $r5 = COPY %1(s32)
+ $r28 = COPY %4
+ JALRPseudo %3(p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r28, implicit-def $r2
%2:gprb(s32) = COPY $r2
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -129,8 +129,8 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: ret_global_int
- ; MIPS32: liveins: $t9, $r2
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
+ ; MIPS32: liveins: $r25, $r2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) @val :: (load (s32) from got)
; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[LW]], 0 :: (load (s32) from @val)
; MIPS32: $r2 = COPY [[LW1]]
@@ -150,8 +150,8 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: ret_global_int_with_local_linkage
- ; MIPS32: liveins: $t9, $r2
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
+ ; MIPS32: liveins: $r25, $r2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) @val_with_local_linkage :: (load (s32) from got)
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LW]], target-flags(mips-abs-lo) @val_with_local_linkage
; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from @val_with_local_linkage)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
index 5a870264bba7f..8a8ac93fa25b4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
@@ -24,18 +24,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: eq_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
; MIPS32: $r2 = COPY [[SLTiu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(eq), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -50,18 +50,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ne_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
- ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
+ ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $r0, [[XOR]]
; MIPS32: $r2 = COPY [[SLTu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(ne), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -76,17 +76,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sgt_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[SLT]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(sgt), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -101,18 +101,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sge_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
; MIPS32: $r2 = COPY [[XORi]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(sge), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -127,17 +127,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: slt_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[SLT]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(slt), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -152,18 +152,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sle_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
; MIPS32: $r2 = COPY [[XORi]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(sle), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -178,17 +178,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ugt_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[SLTu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(ugt), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -203,18 +203,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: uge_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
; MIPS32: $r2 = COPY [[XORi]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(uge), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -229,17 +229,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ult_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[SLTu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(ult), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -254,18 +254,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ule_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
; MIPS32: $r2 = COPY [[XORi]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(ule), %0(s32), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -280,18 +280,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: eq_ptr
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
; MIPS32: $r2 = COPY [[SLTiu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%4:gprb(s32) = G_ICMP intpred(eq), %0(p0), %1
%3:gprb(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/implicit_def.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/implicit_def.mir
index 5ee7cf94d4f46..c6a8cde950cd2 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/implicit_def.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/implicit_def.mir
@@ -25,16 +25,16 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: g_i32
; MIPS32: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[DEF]]
- ; MIPS32: JAL @f_i32, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[DEF]]
+ ; MIPS32: JAL @f_i32, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
%0:gprb(s32) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %0(s32)
- JAL @f_i32, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %0(s32)
+ JAL @f_i32, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
@@ -49,19 +49,19 @@ body: |
; MIPS32-LABEL: name: g_i64
; MIPS32: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; MIPS32: [[DEF1:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[DEF]]
- ; MIPS32: $a1 = COPY [[DEF1]]
- ; MIPS32: JAL @f_i64, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[DEF]]
+ ; MIPS32: $r5 = COPY [[DEF1]]
+ ; MIPS32: JAL @f_i64, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
%3:gprb(s32) = G_IMPLICIT_DEF
%4:gprb(s32) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %3(s32)
- $a1 = COPY %4(s32)
- JAL @f_i64, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %3(s32)
+ $r5 = COPY %4(s32)
+ JAL @f_i64, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
@@ -75,16 +75,16 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: g_float
; MIPS32: [[DEF:%[0-9]+]]:fgr32 = IMPLICIT_DEF
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $f12 = COPY [[DEF]]
- ; MIPS32: JAL @f_float, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: JAL @f_float, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
%0:fprb(s32) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
$f12 = COPY %0(s32)
- JAL @f_float, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ JAL @f_float, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
@@ -98,16 +98,16 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: g_double
; MIPS32: [[DEF:%[0-9]+]]:afgr64 = IMPLICIT_DEF
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $d6 = COPY [[DEF]]
- ; MIPS32: JAL @f_double, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: JAL @f_double, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
%0:fprb(s64) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
$d6 = COPY %0(s64)
- JAL @f_double, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ JAL @f_double, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir
index 606dd2b813e17..976389fc70e8e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir
@@ -14,14 +14,14 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: inttoptr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: $r2 = COPY [[COPY]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(p0) = G_INTTOPTR %0(s32)
$r2 = COPY %1(p0)
RetRA implicit $r2
@@ -35,14 +35,14 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ptrtoint
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: $r2 = COPY [[COPY]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:gprb(s32) = G_PTRTOINT %0(p0)
$r2 = COPY %1(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
index 2f8a8b9a6c3cf..4c154550f56d3 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
@@ -74,20 +74,20 @@ body: |
; MIPS32-LABEL: name: mod4_0_to_11
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
- ; MIPS32-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
- ; MIPS32-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
- ; MIPS32-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
- ; MIPS32-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; MIPS32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
- ; MIPS32-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 7
+ ; MIPS32-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $r0, 3
+ ; MIPS32-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $r0, 2
+ ; MIPS32-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $r0, 1
+ ; MIPS32-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $r0, 0
+ ; MIPS32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 65535
+ ; MIPS32-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $r0, 0
; MIPS32-NEXT: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
; MIPS32-NEXT: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
; MIPS32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
- ; MIPS32-NEXT: BNE [[ANDi]], $zero, %bb.6, implicit-def dead $at
+ ; MIPS32-NEXT: BNE [[ANDi]], $r0, %bb.6, implicit-def dead $r1
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.1.entry:
; MIPS32-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
@@ -120,11 +120,11 @@ body: |
; MIPS32-NEXT: bb.7.sw.epilog:
; MIPS32-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000)
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
+ ; MIPS32-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $r0, 8
; MIPS32-NEXT: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
; MIPS32-NEXT: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
; MIPS32-NEXT: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
- ; MIPS32-NEXT: BNE [[ANDi1]], $zero, %bb.13, implicit-def dead $at
+ ; MIPS32-NEXT: BNE [[ANDi1]], $r0, %bb.13, implicit-def dead $r1
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.8.sw.epilog:
; MIPS32-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
@@ -158,21 +158,21 @@ body: |
; MIPS32_PIC-LABEL: name: mod4_0_to_11
; MIPS32_PIC: bb.0.entry:
; MIPS32_PIC-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)
- ; MIPS32_PIC-NEXT: liveins: $a0, $t9, $r2
+ ; MIPS32_PIC-NEXT: liveins: $r4, $r25, $r2
; MIPS32_PIC-NEXT: {{ $}}
- ; MIPS32_PIC-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32_PIC-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32_PIC-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
- ; MIPS32_PIC-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
- ; MIPS32_PIC-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
- ; MIPS32_PIC-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
- ; MIPS32_PIC-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; MIPS32_PIC-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
- ; MIPS32_PIC-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32_PIC-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32_PIC-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32_PIC-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 7
+ ; MIPS32_PIC-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $r0, 3
+ ; MIPS32_PIC-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $r0, 2
+ ; MIPS32_PIC-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $r0, 1
+ ; MIPS32_PIC-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $r0, 0
+ ; MIPS32_PIC-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $r0, 65535
+ ; MIPS32_PIC-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $r0, 0
; MIPS32_PIC-NEXT: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
; MIPS32_PIC-NEXT: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
; MIPS32_PIC-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
- ; MIPS32_PIC-NEXT: BNE [[ANDi]], $zero, %bb.6, implicit-def dead $at
+ ; MIPS32_PIC-NEXT: BNE [[ANDi]], $r0, %bb.6, implicit-def dead $r1
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.1.entry:
; MIPS32_PIC-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
@@ -206,11 +206,11 @@ body: |
; MIPS32_PIC-NEXT: bb.7.sw.epilog:
; MIPS32_PIC-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000)
; MIPS32_PIC-NEXT: {{ $}}
- ; MIPS32_PIC-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
+ ; MIPS32_PIC-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $r0, 8
; MIPS32_PIC-NEXT: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
; MIPS32_PIC-NEXT: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
; MIPS32_PIC-NEXT: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
- ; MIPS32_PIC-NEXT: BNE [[ANDi1]], $zero, %bb.13, implicit-def dead $at
+ ; MIPS32_PIC-NEXT: BNE [[ANDi1]], $r0, %bb.13, implicit-def dead $r1
; MIPS32_PIC-NEXT: {{ $}}
; MIPS32_PIC-NEXT: bb.8.sw.epilog:
; MIPS32_PIC-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
@@ -242,9 +242,9 @@ body: |
; MIPS32_PIC-NEXT: $r2 = COPY [[ADDiu]]
; MIPS32_PIC-NEXT: RetRA implicit $r2
bb.1.entry:
- liveins: $a0
+ liveins: $r4
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%4:gprb(s32) = G_CONSTANT i32 7
%8:gprb(s32) = G_CONSTANT i32 3
%9:gprb(s32) = G_CONSTANT i32 2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir
index 4e2c5ea1bf58d..1d798a42a78f1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir
@@ -16,21 +16,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32FP32-LABEL: name: load_i32
- ; MIPS32FP32: liveins: $a0
- ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32FP32: liveins: $r4
+ ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load (s32) from %ir.ptr)
; MIPS32FP32: $r2 = COPY [[LW]]
; MIPS32FP32: RetRA implicit $r2
; MIPS32FP64-LABEL: name: load_i32
- ; MIPS32FP64: liveins: $a0
- ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32FP64: liveins: $r4
+ ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load (s32) from %ir.ptr)
; MIPS32FP64: $r2 = COPY [[LW]]
; MIPS32FP64: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:gprb(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr)
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -44,21 +44,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32FP32-LABEL: name: load_float
- ; MIPS32FP32: liveins: $a0
- ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32FP32: liveins: $r4
+ ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32FP32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[COPY]], 0 :: (load (s32) from %ir.ptr)
; MIPS32FP32: $f0 = COPY [[LWC1_]]
; MIPS32FP32: RetRA implicit $f0
; MIPS32FP64-LABEL: name: load_float
- ; MIPS32FP64: liveins: $a0
- ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32FP64: liveins: $r4
+ ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32FP64: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[COPY]], 0 :: (load (s32) from %ir.ptr)
; MIPS32FP64: $f0 = COPY [[LWC1_]]
; MIPS32FP64: RetRA implicit $f0
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:fprb(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr)
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -72,21 +72,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32FP32-LABEL: name: load_double
- ; MIPS32FP32: liveins: $a0
- ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32FP32: liveins: $r4
+ ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32FP32: [[LDC1_:%[0-9]+]]:afgr64 = LDC1 [[COPY]], 0 :: (load (s64) from %ir.ptr)
; MIPS32FP32: $d0 = COPY [[LDC1_]]
; MIPS32FP32: RetRA implicit $d0
; MIPS32FP64-LABEL: name: load_double
- ; MIPS32FP64: liveins: $a0
- ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32FP64: liveins: $r4
+ ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32FP64: [[LDC164_:%[0-9]+]]:fgr64 = LDC164 [[COPY]], 0 :: (load (s64) from %ir.ptr)
; MIPS32FP64: $d0 = COPY [[LDC164_]]
; MIPS32FP64: RetRA implicit $d0
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:fprb(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
$d0 = COPY %1(s64)
RetRA implicit $d0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
index 0dbe4cb4d8788..e7d5b8fa5dfaf 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
@@ -20,15 +20,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: _16_bit_positive_offset
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY]], 32767 :: (load (s8))
; MIPS32: $r2 = COPY [[LBu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 32767
%2:gprb(p0) = G_PTR_ADD %0, %1(s32)
%4:gprb(s32) = G_ZEXTLOAD %2(p0) :: (load (s8))
@@ -44,16 +44,16 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: _16_bit_negative_offset
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: SB [[COPY]], [[COPY1]], -32768 :: (store (s8))
; MIPS32: RetRA
- %2:gprb(s32) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %2:gprb(s32) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%3:gprb(s32) = G_CONSTANT i32 -32768
%4:gprb(p0) = G_PTR_ADD %1, %3(s32)
%5:gprb(s32) = COPY %2(s32)
@@ -69,18 +69,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: _large_positive_offset
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 32768
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 32768
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY1]], [[ORi]]
; MIPS32: SB [[COPY]], [[ADDu]], 0 :: (store (s8))
; MIPS32: RetRA
- %2:gprb(s32) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %2:gprb(s32) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%3:gprb(s32) = G_CONSTANT i32 32768
%4:gprb(p0) = G_PTR_ADD %1, %3(s32)
%5:gprb(s32) = COPY %2(s32)
@@ -96,18 +96,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: _large_negative_offset
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 65535
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 32767
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY]], [[ORi]]
; MIPS32: [[LB:%[0-9]+]]:gpr32 = LB [[ADDu]], 0 :: (load (s8))
; MIPS32: $r2 = COPY [[LB]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 -32769
%2:gprb(p0) = G_PTR_ADD %0, %1(s32)
%4:gprb(s32) = G_SEXTLOAD %2(p0) :: (load (s8))
@@ -123,15 +123,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: fold_f32_load
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[COPY]], 40 :: (load (s32))
; MIPS32: $f0 = COPY [[LWC1_]]
; MIPS32: RetRA implicit $f0
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 40
%2:gprb(p0) = G_PTR_ADD %0, %1(s32)
%3:fprb(s32) = G_LOAD %2(p0) :: (load (s32))
@@ -147,16 +147,16 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a2, $d6
+ liveins: $r6, $d6
; MIPS32-LABEL: name: fold_f64_store
- ; MIPS32: liveins: $a2, $d6
+ ; MIPS32: liveins: $r6, $d6
; MIPS32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32: SDC1 [[COPY]], [[COPY1]], -80 :: (store (s64))
; MIPS32: RetRA
%0:fprb(s64) = COPY $d6
- %1:gprb(p0) = COPY $a2
+ %1:gprb(p0) = COPY $r6
%2:gprb(s32) = G_CONSTANT i32 -80
%3:gprb(p0) = G_PTR_ADD %1, %2(s32)
G_STORE %0(s64), %3(p0) :: (store (s64))
@@ -171,15 +171,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: fold_i16_load
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY]], -20 :: (load (s16))
; MIPS32: $r2 = COPY [[LHu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:gprb(s32) = G_CONSTANT i32 -20
%2:gprb(p0) = G_PTR_ADD %0, %1(s32)
%4:gprb(s32) = G_LOAD %2(p0) :: (load (s16))
@@ -195,16 +195,16 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: fold_i32_store
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: SW [[COPY]], [[COPY1]], 40 :: (store (s32))
; MIPS32: RetRA
- %0:gprb(s32) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:gprb(s32) = G_CONSTANT i32 40
%3:gprb(p0) = G_PTR_ADD %1, %2(s32)
G_STORE %0(s32), %3(p0) :: (store (s32))
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir
index eafe5af13a90c..84ca3a60bc57e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir
@@ -18,17 +18,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v16i8
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
; P5600: ST_B [[LD_B]], [[COPY]], 0 :: (store (<16 x s8>) into %ir.a)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
G_STORE %2(<16 x s8>), %0(p0) :: (store (<16 x s8>) into %ir.a)
RetRA
@@ -42,17 +42,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v8i16
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
; P5600: ST_H [[LD_H]], [[COPY]], 0 :: (store (<8 x s16>) into %ir.a)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
G_STORE %2(<8 x s16>), %0(p0) :: (store (<8 x s16>) into %ir.a)
RetRA
@@ -66,17 +66,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v4i32
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store (<4 x s32>) into %ir.a)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>) into %ir.a)
RetRA
@@ -90,17 +90,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v2i64
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: ST_D [[LD_D]], [[COPY]], 0 :: (store (<2 x s64>) into %ir.a)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>) into %ir.a)
RetRA
@@ -114,17 +114,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v4f32
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store (<4 x s32>) into %ir.a)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>) into %ir.a)
RetRA
@@ -138,17 +138,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v2f64
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: ST_D [[LD_D]], [[COPY]], 0 :: (store (<2 x s64>) into %ir.a)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>) into %ir.a)
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
index 4b5b0d3d6aadc..ea189e55edde6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
@@ -14,17 +14,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: mul_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
; MIPS32: $r2 = COPY [[MUL]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_MUL %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -38,26 +38,26 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: umul_with_overflow
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $r7
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
- ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[PseudoMFHI]]
+ ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $r0, [[PseudoMFHI]]
; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
; MIPS32: SB [[ANDi]], [[COPY3]], 0 :: (store (s8) into %ir.pcarry_flag)
; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store (s32) into %ir.pmul)
; MIPS32: RetRA
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- %2:gprb(p0) = COPY $a2
- %3:gprb(p0) = COPY $a3
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ %2:gprb(p0) = COPY $r6
+ %3:gprb(p0) = COPY $r7
%4:gprb(s32) = G_MUL %0, %1
%7:gprb(s32) = G_UMULH %0, %1
%8:gprb(s32) = G_CONSTANT i32 0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
index e3538928a094d..b7c02bbf90589 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
@@ -16,21 +16,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
; P5600: [[MULV_B:%[0-9]+]]:msa128b = MULV_B [[LD_B1]], [[LD_B]]
; P5600: ST_B [[MULV_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:fprb(<16 x s8>) = G_MUL %4, %3
@@ -46,21 +46,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
; P5600: [[MULV_H:%[0-9]+]]:msa128h = MULV_H [[LD_H1]], [[LD_H]]
; P5600: ST_H [[MULV_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:fprb(<8 x s16>) = G_MUL %4, %3
@@ -76,21 +76,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[MULV_W:%[0-9]+]]:msa128w = MULV_W [[LD_W1]], [[LD_W]]
; P5600: ST_W [[MULV_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_MUL %4, %3
@@ -106,21 +106,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[MULV_D:%[0-9]+]]:msa128d = MULV_D [[LD_D1]], [[LD_D]]
; P5600: ST_D [[MULV_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_MUL %4, %3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
index 74ca62367aa83..098643b47c249 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
@@ -74,19 +74,19 @@ body: |
; MIPS32FP32-LABEL: name: phi_i32
; MIPS32FP32: bb.0.entry:
; MIPS32FP32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32FP32-NEXT: liveins: $a0, $a1, $a2
+ ; MIPS32FP32-NEXT: liveins: $r4, $r5, $r6
; MIPS32FP32-NEXT: {{ $}}
- ; MIPS32FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
- ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at
+ ; MIPS32FP32-NEXT: BNE [[ANDi]], $r0, %bb.1, implicit-def dead $r1
+ ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $r1
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.1.cond.true:
; MIPS32FP32-NEXT: successors: %bb.3(0x80000000)
; MIPS32FP32-NEXT: {{ $}}
- ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $at
+ ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $r1
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.2.cond.false:
; MIPS32FP32-NEXT: successors: %bb.3(0x80000000)
@@ -99,19 +99,19 @@ body: |
; MIPS32FP64-LABEL: name: phi_i32
; MIPS32FP64: bb.0.entry:
; MIPS32FP64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32FP64-NEXT: liveins: $a0, $a1, $a2
+ ; MIPS32FP64-NEXT: liveins: $r4, $r5, $r6
; MIPS32FP64-NEXT: {{ $}}
- ; MIPS32FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
- ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at
+ ; MIPS32FP64-NEXT: BNE [[ANDi]], $r0, %bb.1, implicit-def dead $r1
+ ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $r1
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.1.cond.true:
; MIPS32FP64-NEXT: successors: %bb.3(0x80000000)
; MIPS32FP64-NEXT: {{ $}}
- ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $at
+ ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $r1
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.2.cond.false:
; MIPS32FP64-NEXT: successors: %bb.3(0x80000000)
@@ -121,11 +121,11 @@ body: |
; MIPS32FP64-NEXT: $r2 = COPY [[PHI]]
; MIPS32FP64-NEXT: RetRA implicit $r2
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- %2:gprb(s32) = COPY $a2
+ %3:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ %2:gprb(s32) = COPY $r6
%6:gprb(s32) = G_CONSTANT i32 1
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
@@ -156,23 +156,23 @@ body: |
; MIPS32FP32-LABEL: name: phi_i64
; MIPS32FP32: bb.0.entry:
; MIPS32FP32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32FP32-NEXT: liveins: $a0, $a2, $a3
+ ; MIPS32FP32-NEXT: liveins: $r4, $r6, $r7
; MIPS32FP32-NEXT: {{ $}}
- ; MIPS32FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
- ; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
+ ; MIPS32FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $r6
+ ; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $r7
; MIPS32FP32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32FP32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32FP32-NEXT: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
; MIPS32FP32-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load (s32) from %fixed-stack.1)
; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
- ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at
+ ; MIPS32FP32-NEXT: BNE [[ANDi]], $r0, %bb.1, implicit-def dead $r1
+ ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $r1
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.1.cond.true:
; MIPS32FP32-NEXT: successors: %bb.3(0x80000000)
; MIPS32FP32-NEXT: {{ $}}
- ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $at
+ ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $r1
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.2.cond.false:
; MIPS32FP32-NEXT: successors: %bb.3(0x80000000)
@@ -187,23 +187,23 @@ body: |
; MIPS32FP64-LABEL: name: phi_i64
; MIPS32FP64: bb.0.entry:
; MIPS32FP64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32FP64-NEXT: liveins: $a0, $a2, $a3
+ ; MIPS32FP64-NEXT: liveins: $r4, $r6, $r7
; MIPS32FP64-NEXT: {{ $}}
- ; MIPS32FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
- ; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
+ ; MIPS32FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $r6
+ ; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $r7
; MIPS32FP64-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32FP64-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32FP64-NEXT: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
; MIPS32FP64-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load (s32) from %fixed-stack.1)
; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
- ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at
+ ; MIPS32FP64-NEXT: BNE [[ANDi]], $r0, %bb.1, implicit-def dead $r1
+ ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $r1
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.1.cond.true:
; MIPS32FP64-NEXT: successors: %bb.3(0x80000000)
; MIPS32FP64-NEXT: {{ $}}
- ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $at
+ ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $r1
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.2.cond.false:
; MIPS32FP64-NEXT: successors: %bb.3(0x80000000)
@@ -215,11 +215,11 @@ body: |
; MIPS32FP64-NEXT: $r3 = COPY [[PHI1]]
; MIPS32FP64-NEXT: RetRA implicit $r2, implicit $r3
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
- %3:gprb(s32) = COPY $a0
- %4:gprb(s32) = COPY $a2
- %5:gprb(s32) = COPY $a3
+ %3:gprb(s32) = COPY $r4
+ %4:gprb(s32) = COPY $r6
+ %5:gprb(s32) = COPY $r7
%8:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
%6:gprb(s32) = G_LOAD %8(p0) :: (load (s32) from %fixed-stack.1, align 8)
%9:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -253,19 +253,19 @@ body: |
; MIPS32FP32-LABEL: name: phi_float
; MIPS32FP32: bb.0.entry:
; MIPS32FP32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32FP32-NEXT: liveins: $a0, $a1, $a2
+ ; MIPS32FP32-NEXT: liveins: $r4, $r5, $r6
; MIPS32FP32-NEXT: {{ $}}
- ; MIPS32FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
- ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at
+ ; MIPS32FP32-NEXT: BNE [[ANDi]], $r0, %bb.1, implicit-def dead $r1
+ ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $r1
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.1.cond.true:
; MIPS32FP32-NEXT: successors: %bb.3(0x80000000)
; MIPS32FP32-NEXT: {{ $}}
- ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $at
+ ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $r1
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.2.cond.false:
; MIPS32FP32-NEXT: successors: %bb.3(0x80000000)
@@ -278,19 +278,19 @@ body: |
; MIPS32FP64-LABEL: name: phi_float
; MIPS32FP64: bb.0.entry:
; MIPS32FP64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32FP64-NEXT: liveins: $a0, $a1, $a2
+ ; MIPS32FP64-NEXT: liveins: $r4, $r5, $r6
; MIPS32FP64-NEXT: {{ $}}
- ; MIPS32FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
- ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at
+ ; MIPS32FP64-NEXT: BNE [[ANDi]], $r0, %bb.1, implicit-def dead $r1
+ ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $r1
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.1.cond.true:
; MIPS32FP64-NEXT: successors: %bb.3(0x80000000)
; MIPS32FP64-NEXT: {{ $}}
- ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $at
+ ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $r1
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.2.cond.false:
; MIPS32FP64-NEXT: successors: %bb.3(0x80000000)
@@ -300,11 +300,11 @@ body: |
; MIPS32FP64-NEXT: $f0 = COPY [[PHI]]
; MIPS32FP64-NEXT: RetRA implicit $f0
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- %2:gprb(s32) = COPY $a2
+ %3:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ %2:gprb(s32) = COPY $r6
%6:gprb(s32) = G_CONSTANT i32 1
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
@@ -341,13 +341,13 @@ body: |
; MIPS32FP32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32FP32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
- ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
- ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at
+ ; MIPS32FP32-NEXT: BNE [[ANDi]], $r0, %bb.1, implicit-def dead $r1
+ ; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $r1
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.1.cond.true:
; MIPS32FP32-NEXT: successors: %bb.3(0x80000000)
; MIPS32FP32-NEXT: {{ $}}
- ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $at
+ ; MIPS32FP32-NEXT: J %bb.3, implicit-def dead $r1
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.2.cond.false:
; MIPS32FP32-NEXT: successors: %bb.3(0x80000000)
@@ -367,13 +367,13 @@ body: |
; MIPS32FP64-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32FP64-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
- ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
- ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at
+ ; MIPS32FP64-NEXT: BNE [[ANDi]], $r0, %bb.1, implicit-def dead $r1
+ ; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $r1
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.1.cond.true:
; MIPS32FP64-NEXT: successors: %bb.3(0x80000000)
; MIPS32FP64-NEXT: {{ $}}
- ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $at
+ ; MIPS32FP64-NEXT: J %bb.3, implicit-def dead $r1
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.2.cond.false:
; MIPS32FP64-NEXT: successors: %bb.3(0x80000000)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
index 0cb6245b8ad8d..307f9aa2373c6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
@@ -15,15 +15,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ptr_arg_in_regs
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load (s32) from %ir.p)
; MIPS32: $r2 = COPY [[LW]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%1:gprb(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.p)
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -39,19 +39,19 @@ fixedStack:
- { id: 0, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: ptr_arg_on_stack
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[LW]], 0 :: (load (s32) from %ir.p)
; MIPS32: $r2 = COPY [[LW1]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- %2:gprb(s32) = COPY $a2
- %3:gprb(s32) = COPY $a3
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ %2:gprb(s32) = COPY $r6
+ %3:gprb(s32) = COPY $r7
%5:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
%4:gprb(p0) = G_LOAD %5(p0) :: (load (p0) from %fixed-stack.0, align 8)
%6:gprb(s32) = G_LOAD %4(p0) :: (load (s32) from %ir.p)
@@ -67,14 +67,14 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ret_ptr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: $r2 = COPY [[COPY]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
$r2 = COPY %0(p0)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir
index f01defd8c2c21..76f04c7f762b7 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir
@@ -16,18 +16,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sdiv_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[PseudoSDIV:%[0-9]+]]:acc64 = PseudoSDIV [[COPY1]], [[COPY]]
; MIPS32: [[PseudoMFLO:%[0-9]+]]:gpr32 = PseudoMFLO [[PseudoSDIV]]
; MIPS32: $r2 = COPY [[PseudoMFLO]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_SDIV %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -41,18 +41,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: srem_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[PseudoSDIV:%[0-9]+]]:acc64 = PseudoSDIV [[COPY1]], [[COPY]]
; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoSDIV]]
; MIPS32: $r2 = COPY [[PseudoMFHI]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_SREM %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -66,18 +66,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: udiv_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[PseudoUDIV:%[0-9]+]]:acc64 = PseudoUDIV [[COPY1]], [[COPY]]
; MIPS32: [[PseudoMFLO:%[0-9]+]]:gpr32 = PseudoMFLO [[PseudoUDIV]]
; MIPS32: $r2 = COPY [[PseudoMFLO]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_UDIV %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -91,18 +91,18 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: urem_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[PseudoUDIV:%[0-9]+]]:acc64 = PseudoUDIV [[COPY1]], [[COPY]]
; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoUDIV]]
; MIPS32: $r2 = COPY [[PseudoMFHI]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_UREM %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div_vec.mir
index 05c40e515712c..4cdeb82ea46a6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div_vec.mir
@@ -31,21 +31,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
; P5600: [[DIV_S_B:%[0-9]+]]:msa128b = DIV_S_B [[LD_B]], [[LD_B1]]
; P5600: ST_B [[DIV_S_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:fprb(<16 x s8>) = G_SDIV %3, %4
@@ -61,21 +61,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
; P5600: [[DIV_S_H:%[0-9]+]]:msa128h = DIV_S_H [[LD_H]], [[LD_H1]]
; P5600: ST_H [[DIV_S_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:fprb(<8 x s16>) = G_SDIV %3, %4
@@ -91,21 +91,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[DIV_S_W:%[0-9]+]]:msa128w = DIV_S_W [[LD_W]], [[LD_W1]]
; P5600: ST_W [[DIV_S_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_SDIV %3, %4
@@ -121,21 +121,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[DIV_S_D:%[0-9]+]]:msa128d = DIV_S_D [[LD_D]], [[LD_D1]]
; P5600: ST_D [[DIV_S_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_SDIV %3, %4
@@ -151,21 +151,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
; P5600: [[MOD_S_B:%[0-9]+]]:msa128b = MOD_S_B [[LD_B]], [[LD_B1]]
; P5600: ST_B [[MOD_S_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:fprb(<16 x s8>) = G_SREM %3, %4
@@ -181,21 +181,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
; P5600: [[MOD_S_H:%[0-9]+]]:msa128h = MOD_S_H [[LD_H]], [[LD_H1]]
; P5600: ST_H [[MOD_S_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:fprb(<8 x s16>) = G_SREM %3, %4
@@ -211,21 +211,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[MOD_S_W:%[0-9]+]]:msa128w = MOD_S_W [[LD_W]], [[LD_W1]]
; P5600: ST_W [[MOD_S_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_SREM %3, %4
@@ -241,21 +241,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[MOD_S_D:%[0-9]+]]:msa128d = MOD_S_D [[LD_D]], [[LD_D1]]
; P5600: ST_D [[MOD_S_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_SREM %3, %4
@@ -271,21 +271,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v16u8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
; P5600: [[DIV_U_B:%[0-9]+]]:msa128b = DIV_U_B [[LD_B]], [[LD_B1]]
; P5600: ST_B [[DIV_U_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:fprb(<16 x s8>) = G_UDIV %3, %4
@@ -301,21 +301,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v8u16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
; P5600: [[DIV_U_H:%[0-9]+]]:msa128h = DIV_U_H [[LD_H]], [[LD_H1]]
; P5600: ST_H [[DIV_U_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:fprb(<8 x s16>) = G_UDIV %3, %4
@@ -331,21 +331,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v4u32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[DIV_U_W:%[0-9]+]]:msa128w = DIV_U_W [[LD_W]], [[LD_W1]]
; P5600: ST_W [[DIV_U_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_UDIV %3, %4
@@ -361,21 +361,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v2u64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[DIV_U_D:%[0-9]+]]:msa128d = DIV_U_D [[LD_D]], [[LD_D1]]
; P5600: ST_D [[DIV_U_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_UDIV %3, %4
@@ -391,21 +391,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v16u8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
; P5600: [[MOD_U_B:%[0-9]+]]:msa128b = MOD_U_B [[LD_B]], [[LD_B1]]
; P5600: ST_B [[MOD_U_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:fprb(<16 x s8>) = G_UREM %3, %4
@@ -421,21 +421,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v8u16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
; P5600: [[MOD_U_H:%[0-9]+]]:msa128h = MOD_U_H [[LD_H]], [[LD_H1]]
; P5600: ST_H [[MOD_U_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:fprb(<8 x s16>) = G_UREM %3, %4
@@ -451,21 +451,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v4u32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[MOD_U_W:%[0-9]+]]:msa128w = MOD_U_W [[LD_W]], [[LD_W1]]
; P5600: ST_W [[MOD_U_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_UREM %3, %4
@@ -481,21 +481,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v2u64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[MOD_U_D:%[0-9]+]]:msa128d = MOD_U_D [[LD_D]], [[LD_D1]]
; P5600: ST_D [[MOD_U_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_UREM %3, %4
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
index 74a8d61959787..3c8bea09231e4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
@@ -17,29 +17,29 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32FP32-LABEL: name: select_i32
- ; MIPS32FP32: liveins: $a0, $a1, $a2
- ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP32: liveins: $r4, $r5, $r6
+ ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
; MIPS32FP32: $r2 = COPY [[MOVN_I_I]]
; MIPS32FP32: RetRA implicit $r2
; MIPS32FP64-LABEL: name: select_i32
- ; MIPS32FP64: liveins: $a0, $a1, $a2
- ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP64: liveins: $r4, $r5, $r6
+ ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
; MIPS32FP64: $r2 = COPY [[MOVN_I_I]]
; MIPS32FP64: RetRA implicit $r2
- %3:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- %2:gprb(s32) = COPY $a2
+ %3:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ %2:gprb(s32) = COPY $r6
%6:gprb(s32) = G_CONSTANT i32 1
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
@@ -56,29 +56,29 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32FP32-LABEL: name: select_ptr
- ; MIPS32FP32: liveins: $a0, $a1, $a2
- ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP32: liveins: $r4, $r5, $r6
+ ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
; MIPS32FP32: $r2 = COPY [[MOVN_I_I]]
; MIPS32FP32: RetRA implicit $r2
; MIPS32FP64-LABEL: name: select_ptr
- ; MIPS32FP64: liveins: $a0, $a1, $a2
- ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP64: liveins: $r4, $r5, $r6
+ ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
; MIPS32FP64: $r2 = COPY [[MOVN_I_I]]
; MIPS32FP64: RetRA implicit $r2
- %3:gprb(s32) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %3:gprb(s32) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%6:gprb(s32) = G_CONSTANT i32 1
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
@@ -95,13 +95,13 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32FP32-LABEL: name: select_float
- ; MIPS32FP32: liveins: $a0, $a1, $a2
- ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP32: liveins: $r4, $r5, $r6
+ ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
; MIPS32FP32: [[COPY3:%[0-9]+]]:fgr32 = COPY [[COPY1]]
; MIPS32FP32: [[COPY4:%[0-9]+]]:fgr32 = COPY [[COPY2]]
@@ -109,19 +109,19 @@ body: |
; MIPS32FP32: $f0 = COPY [[MOVN_I_S]]
; MIPS32FP32: RetRA implicit $f0
; MIPS32FP64-LABEL: name: select_float
- ; MIPS32FP64: liveins: $a0, $a1, $a2
- ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP64: liveins: $r4, $r5, $r6
+ ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
; MIPS32FP64: [[COPY3:%[0-9]+]]:fgr32 = COPY [[COPY1]]
; MIPS32FP64: [[COPY4:%[0-9]+]]:fgr32 = COPY [[COPY2]]
; MIPS32FP64: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[COPY3]], [[ANDi]], [[COPY4]]
; MIPS32FP64: $f0 = COPY [[MOVN_I_S]]
; MIPS32FP64: RetRA implicit $f0
- %3:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- %2:gprb(s32) = COPY $a2
+ %3:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ %2:gprb(s32) = COPY $r6
%6:gprb(s32) = G_CONSTANT i32 1
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir
index a9d4a6d93402f..4162b16513bb9 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir
@@ -16,24 +16,24 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: i32tof32
- ; FP32: liveins: $a0
+ ; FP32: liveins: $r4
; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; FP32-NEXT: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]
; FP32-NEXT: $f0 = COPY [[PseudoCVT_S_W]]
; FP32-NEXT: RetRA implicit $f0
;
; FP64-LABEL: name: i32tof32
- ; FP64: liveins: $a0
+ ; FP64: liveins: $r4
; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; FP64-NEXT: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]
; FP64-NEXT: $f0 = COPY [[PseudoCVT_S_W]]
; FP64-NEXT: RetRA implicit $f0
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:fprb(s32) = G_SITOFP %0(s32)
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -47,24 +47,24 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: i32tof64
- ; FP32: liveins: $a0
+ ; FP32: liveins: $r4
; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; FP32-NEXT: [[PseudoCVT_D32_W:%[0-9]+]]:afgr64 = PseudoCVT_D32_W [[COPY]]
; FP32-NEXT: $d0 = COPY [[PseudoCVT_D32_W]]
; FP32-NEXT: RetRA implicit $d0
;
; FP64-LABEL: name: i32tof64
- ; FP64: liveins: $a0
+ ; FP64: liveins: $r4
; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; FP64-NEXT: [[PseudoCVT_D64_W:%[0-9]+]]:fgr64 = PseudoCVT_D64_W [[COPY]]
; FP64-NEXT: $d0 = COPY [[PseudoCVT_D64_W]]
; FP64-NEXT: RetRA implicit $d0
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:fprb(s64) = G_SITOFP %0(s32)
$d0 = COPY %1(s64)
RetRA implicit $d0
@@ -78,34 +78,34 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: u32tof64
- ; FP32: liveins: $a0
+ ; FP32: liveins: $r4
; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; FP32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; FP32-NEXT: [[LUi:%[0-9]+]]:gpr32 = LUi 17200
; FP32-NEXT: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 [[COPY]], [[LUi]]
; FP32-NEXT: [[LUi1:%[0-9]+]]:gpr32 = LUi 17200
- ; FP32-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; FP32-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 0
; FP32-NEXT: [[BuildPairF64_1:%[0-9]+]]:afgr64 = BuildPairF64 [[ORi]], [[LUi1]]
; FP32-NEXT: [[FSUB_D32_:%[0-9]+]]:afgr64 = nofpexcept FSUB_D32 [[BuildPairF64_]], [[BuildPairF64_1]], implicit $fcr31
; FP32-NEXT: $d0 = COPY [[FSUB_D32_]]
; FP32-NEXT: RetRA implicit $d0
;
; FP64-LABEL: name: u32tof64
- ; FP64: liveins: $a0
+ ; FP64: liveins: $r4
; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; FP64-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; FP64-NEXT: [[LUi:%[0-9]+]]:gpr32 = LUi 17200
; FP64-NEXT: [[BuildPairF64_64_:%[0-9]+]]:fgr64 = BuildPairF64_64 [[COPY]], [[LUi]]
; FP64-NEXT: [[LUi1:%[0-9]+]]:gpr32 = LUi 17200
- ; FP64-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; FP64-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 0
; FP64-NEXT: [[BuildPairF64_64_1:%[0-9]+]]:fgr64 = BuildPairF64_64 [[ORi]], [[LUi1]]
; FP64-NEXT: [[FSUB_D64_:%[0-9]+]]:fgr64 = nofpexcept FSUB_D64 [[BuildPairF64_64_]], [[BuildPairF64_64_1]], implicit $fcr31
; FP64-NEXT: $d0 = COPY [[FSUB_D64_]]
; FP64-NEXT: RetRA implicit $d0
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%2:gprb(s32) = G_CONSTANT i32 1127219200
%3:fprb(s64) = G_MERGE_VALUES %0(s32), %2(s32)
%4:fprb(s64) = G_FCONSTANT double 0x4330000000000000
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
index e057deb2335f1..5df91642e65f5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
@@ -16,46 +16,46 @@ fixedStack:
- { id: 0, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: g
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $r7
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
- ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY]]
- ; MIPS32: $a1 = COPY [[COPY1]]
- ; MIPS32: $a2 = COPY [[COPY2]]
- ; MIPS32: $a3 = COPY [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:gpr32 = COPY $sp
+ ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY]]
+ ; MIPS32: $r5 = COPY [[COPY1]]
+ ; MIPS32: $r6 = COPY [[COPY2]]
+ ; MIPS32: $r7 = COPY [[COPY3]]
+ ; MIPS32: [[COPY4:%[0-9]+]]:gpr32 = COPY $r29
; MIPS32: SW [[LW]], [[COPY4]], 16 :: (store (s32) into stack + 16)
- ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32: JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
; MIPS32: [[COPY5:%[0-9]+]]:gpr32 = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY5]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
- %2:gprb(s32) = COPY $a2
- %3:gprb(s32) = COPY $a3
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
+ %2:gprb(s32) = COPY $r6
+ %3:gprb(s32) = COPY $r7
%5:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
%4:gprb(s32) = G_LOAD %5(p0) :: (load (s32) from %fixed-stack.0, align 8)
- ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %0(s32)
- $a1 = COPY %1(s32)
- $a2 = COPY %2(s32)
- $a3 = COPY %3(s32)
- %7:gprb(p0) = COPY $sp
+ ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %0(s32)
+ $r5 = COPY %1(s32)
+ $r6 = COPY %2(s32)
+ $r7 = COPY %3(s32)
+ %7:gprb(p0) = COPY $r29
%8:gprb(s32) = G_CONSTANT i32 16
%9:gprb(p0) = G_PTR_ADD %7, %8(s32)
G_STORE %4(s32), %9(p0) :: (store (s32) into stack + 16, align 4)
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
%6:gprb(s32) = COPY $r2
- ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
$r2 = COPY %6(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir
index 89a06032f404e..ff9260b45ad51 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir
@@ -16,22 +16,22 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32FP32-LABEL: name: store_i32
- ; MIPS32FP32: liveins: $a0, $a1
- ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32FP32: liveins: $r4, $r5
+ ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32FP32: SW [[COPY]], [[COPY1]], 0 :: (store (s32) into %ir.ptr)
; MIPS32FP32: RetRA
; MIPS32FP64-LABEL: name: store_i32
- ; MIPS32FP64: liveins: $a0, $a1
- ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32FP64: liveins: $r4, $r5
+ ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32FP64: SW [[COPY]], [[COPY1]], 0 :: (store (s32) into %ir.ptr)
; MIPS32FP64: RetRA
- %0:gprb(s32) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(p0) = COPY $r5
G_STORE %0(s32), %1(p0) :: (store (s32) into %ir.ptr)
RetRA
@@ -44,22 +44,22 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a1, $f12
+ liveins: $r5, $f12
; MIPS32FP32-LABEL: name: store_float
- ; MIPS32FP32: liveins: $a1, $f12
+ ; MIPS32FP32: liveins: $r5, $f12
; MIPS32FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
- ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32FP32: SWC1 [[COPY]], [[COPY1]], 0 :: (store (s32) into %ir.ptr)
; MIPS32FP32: RetRA
; MIPS32FP64-LABEL: name: store_float
- ; MIPS32FP64: liveins: $a1, $f12
+ ; MIPS32FP64: liveins: $r5, $f12
; MIPS32FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
- ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32FP64: SWC1 [[COPY]], [[COPY1]], 0 :: (store (s32) into %ir.ptr)
; MIPS32FP64: RetRA
%0:fprb(s32) = COPY $f12
- %1:gprb(p0) = COPY $a1
+ %1:gprb(p0) = COPY $r5
G_STORE %0(s32), %1(p0) :: (store (s32) into %ir.ptr)
RetRA
@@ -72,22 +72,22 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a2, $d6
+ liveins: $r6, $d6
; MIPS32FP32-LABEL: name: store_double
- ; MIPS32FP32: liveins: $a2, $d6
+ ; MIPS32FP32: liveins: $r6, $d6
; MIPS32FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
- ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP32: SDC1 [[COPY]], [[COPY1]], 0 :: (store (s64) into %ir.ptr)
; MIPS32FP32: RetRA
; MIPS32FP64-LABEL: name: store_double
- ; MIPS32FP64: liveins: $a2, $d6
+ ; MIPS32FP64: liveins: $r6, $d6
; MIPS32FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
- ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32FP64: SDC164 [[COPY]], [[COPY1]], 0 :: (store (s64) into %ir.ptr)
; MIPS32FP64: RetRA
%0:fprb(s64) = COPY $d6
- %1:gprb(p0) = COPY $a2
+ %1:gprb(p0) = COPY $r6
G_STORE %0(s64), %1(p0) :: (store (s64) into %ir.ptr)
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned.mir
index 8bbfa34de1dfd..f081171b277c6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned.mir
@@ -82,16 +82,16 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: store_i32_align8
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
; MIPS32: SW [[COPY]], [[ADDiu]], 0 :: (store (s32) into @i32_align8, align 8)
; MIPS32: RetRA
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align8
G_STORE %0(s32), %1(p0) :: (store (s32) into @i32_align8, align 8)
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned_r6.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned_r6.mir
index 7bcd1ebb9253c..9fe3730b6faa8 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned_r6.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned_r6.mir
@@ -79,16 +79,16 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32R6-LABEL: name: store_i32_align2
- ; MIPS32R6: liveins: $a0
- ; MIPS32R6: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32R6: liveins: $r4
+ ; MIPS32R6: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
; MIPS32R6: SW [[COPY]], [[ADDiu]], 0 :: (store (s32) into @i32_align2, align 2)
; MIPS32R6: RetRA
- %0:gprb(s32) = COPY $a0
+ %0:gprb(s32) = COPY $r4
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align2
G_STORE %0(s32), %1(p0) :: (store (s32) into @i32_align2, align 2)
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir
index 3be681afaafe1..95144a0444356 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir
@@ -13,17 +13,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sub_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[SUBu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(s32) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(s32) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(s32) = G_SUB %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir
index 229b1104e3f6a..bef0347fd9b5f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir
@@ -16,21 +16,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
; P5600: [[SUBV_B:%[0-9]+]]:msa128b = SUBV_B [[LD_B1]], [[LD_B]]
; P5600: ST_B [[SUBV_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:fprb(<16 x s8>) = G_SUB %4, %3
@@ -46,21 +46,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
; P5600: [[SUBV_H:%[0-9]+]]:msa128h = SUBV_H [[LD_H1]], [[LD_H]]
; P5600: ST_H [[SUBV_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:fprb(<8 x s16>) = G_SUB %4, %3
@@ -76,21 +76,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
; P5600: [[SUBV_W:%[0-9]+]]:msa128w = SUBV_W [[LD_W1]], [[LD_W]]
; P5600: ST_W [[SUBV_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:fprb(<4 x s32>) = G_SUB %4, %3
@@ -106,21 +106,21 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
; P5600: [[SUBV_D:%[0-9]+]]:msa128d = SUBV_D [[LD_D1]], [[LD_D]]
; P5600: ST_D [[SUBV_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
- %2:gprb(p0) = COPY $a2
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
+ %2:gprb(p0) = COPY $r6
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:fprb(<2 x s64>) = G_SUB %4, %3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir
index eed965fe3f06a..eb06d58a117f1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir
@@ -15,17 +15,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_store_i8
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY1]], 0 :: (load (s8) from %ir.py)
; MIPS32: SB [[LBu]], [[COPY]], 0 :: (store (s8) into %ir.px)
; MIPS32: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%4:gprb(s32) = G_LOAD %1(p0) :: (load (s8) from %ir.py)
%3:gprb(s32) = COPY %4(s32)
G_STORE %3(s32), %0(p0) :: (store (s8) into %ir.px)
@@ -40,17 +40,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_store_i16
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY1]], 0 :: (load (s16) from %ir.py)
; MIPS32: SH [[LHu]], [[COPY]], 0 :: (store (s16) into %ir.px)
; MIPS32: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%4:gprb(s32) = G_LOAD %1(p0) :: (load (s16) from %ir.py)
%3:gprb(s32) = COPY %4(s32)
G_STORE %3(s32), %0(p0) :: (store (s16) into %ir.px)
@@ -65,17 +65,17 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_store_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY1]], 0 :: (load (s32) from %ir.py)
; MIPS32: SW [[LW]], [[COPY]], 0 :: (store (s32) into %ir.px)
; MIPS32: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(p0) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(p0) = COPY $r5
%2:gprb(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.py)
G_STORE %2(s32), %0(p0) :: (store (s32) into %ir.px)
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
index b653746e2ba16..b00de9ed2e552 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
@@ -38,7 +38,7 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- - { reg: '$a0' }
+ - { reg: '$r4' }
fixedStack:
- { id: 0, offset: 12, size: 4, alignment: 4, isImmutable: true }
- { id: 1, offset: 8, size: 4, alignment: 8, isImmutable: true }
@@ -52,18 +52,18 @@ stack:
machineFunctionInfo: {}
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: testVaCopyArg
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $r5
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
; MIPS32: SW [[COPY1]], [[ADDiu]], 0 :: (store (s32) into %fixed-stack.1)
- ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+ ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $r6
; MIPS32: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.2, 0
; MIPS32: SW [[COPY2]], [[ADDiu1]], 0 :: (store (s32) into %fixed-stack.2)
- ; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
+ ; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $r7
; MIPS32: [[ADDiu2:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.3, 0
; MIPS32: SW [[COPY3]], [[ADDiu2]], 0 :: (store (s32) into %fixed-stack.3)
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @.str
@@ -78,26 +78,26 @@ body: |
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu5]], 0 :: (load (s32))
; MIPS32: SW [[LW]], [[ADDiu6]], 0 :: (store (s32))
; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu6]], 0 :: (load (p0) from %ir.aq)
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 4
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $r0, 4
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ORi]]
; MIPS32: SW [[ADDu]], [[ADDiu6]], 0 :: (store (p0) into %ir.aq)
; MIPS32: [[LW2:%[0-9]+]]:gpr32 = LW [[LW1]], 0 :: (load (p0) from %ir.2)
; MIPS32: SW [[LW2]], [[ADDiu7]], 0 :: (store (p0) into %ir.s)
; MIPS32: [[LW3:%[0-9]+]]:gpr32 = LW [[ADDiu7]], 0 :: (load (p0) from %ir.s)
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[ADDiu3]]
- ; MIPS32: $a1 = COPY [[LW3]]
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[ADDiu3]]
+ ; MIPS32: $r5 = COPY [[LW3]]
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
- %0:gprb(p0) = COPY $a0
- %1:gprb(s32) = COPY $a1
+ %0:gprb(p0) = COPY $r4
+ %1:gprb(s32) = COPY $r5
%2:gprb(p0) = G_FRAME_INDEX %fixed-stack.2
G_STORE %1(s32), %2(p0) :: (store (s32) into %fixed-stack.2)
- %3:gprb(s32) = COPY $a2
+ %3:gprb(s32) = COPY $r6
%4:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
G_STORE %3(s32), %4(p0) :: (store (s32) into %fixed-stack.1)
- %5:gprb(s32) = COPY $a3
+ %5:gprb(s32) = COPY $r7
%6:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
G_STORE %5(s32), %6(p0) :: (store (s32) into %fixed-stack.0)
%18:gprb(p0) = G_GLOBAL_VALUE @.str
@@ -117,11 +117,11 @@ body: |
%14:gprb(p0) = G_LOAD %11(p0) :: (load (p0) from %ir.2)
G_STORE %14(p0), %10(p0) :: (store (p0) into %ir.s)
%15:gprb(p0) = G_LOAD %10(p0) :: (load (p0) from %ir.s)
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %17(p0)
- $a1 = COPY %15(p0)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %17(p0)
+ $r5 = COPY %15(p0)
+ JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir
index a442a9853ef85..a204c74cb45a2 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir
@@ -16,15 +16,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY]], 0 :: (load (s8) from %ir.px)
; MIPS32: $r2 = COPY [[LBu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%2:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -38,15 +38,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY]], 0 :: (load (s16) from %ir.px)
; MIPS32: $r2 = COPY [[LHu]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%2:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -60,15 +60,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LB:%[0-9]+]]:gpr32 = LB [[COPY]], 0 :: (load (s8) from %ir.px)
; MIPS32: $r2 = COPY [[LB]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%2:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -82,15 +82,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $r4
; MIPS32: [[LH:%[0-9]+]]:gpr32 = LH [[COPY]], 0 :: (load (s16) from %ir.px)
; MIPS32: $r2 = COPY [[LH]]
; MIPS32: RetRA implicit $r2
- %0:gprb(p0) = COPY $a0
+ %0:gprb(p0) = COPY $r4
%2:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
index 2f0739e428509..7dad63ae0ad5d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
@@ -4,9 +4,9 @@
define i32 @add_i32(i32 %x, i32 %y) {
; MIPS32-LABEL: name: add_i32
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
index bc795fe5f0a16..c159edeeab639 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
@@ -5,10 +5,10 @@
define { float, float } @add_complex_float(ptr %a, ptr %b) {
; MIPS32-LABEL: name: add_complex_float
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0, $a1
+ ; MIPS32-NEXT: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; MIPS32-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir..realp)
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
@@ -41,10 +41,10 @@ entry:
define { double, double } @add_complex_double(ptr %a, ptr %b) {
; MIPS32-LABEL: name: add_complex_double
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0, $a1
+ ; MIPS32-NEXT: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; MIPS32-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir..realp)
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -78,14 +78,14 @@ declare { float, float } @ret_complex_float()
define void @call_ret_complex_float(ptr %z) {
; MIPS32-LABEL: name: call_ret_complex_float
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32-NEXT: JAL @ret_complex_float, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $f0, implicit-def $f2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32-NEXT: JAL @ret_complex_float, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def $f0, implicit-def $f2
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f2
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir..realp)
@@ -106,14 +106,14 @@ declare { double, double } @ret_complex_double()
define void @call_ret_complex_double(ptr %z) {
; MIPS32-LABEL: name: call_ret_complex_double
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32-NEXT: JAL @ret_complex_double, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $d0, implicit-def $d1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32-NEXT: JAL @ret_complex_double, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def $d0, implicit-def $d1
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d1
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64) into %ir..realp)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll
index 6344c78ba0817..d3f641e816c13 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/big-endian.ll
@@ -8,10 +8,10 @@
; Check high-word-first ABI assignments on BE.
define i64 @integer_regs(i64 %x) {
; CHECK-LABEL: name: integer_regs
-; BE: [[LO:%[0-9]+]]:_(s32) = COPY $a1
-; BE-NEXT: [[HI:%[0-9]+]]:_(s32) = COPY $a0
-; LE: [[LO:%[0-9]+]]:_(s32) = COPY $a0
-; LE-NEXT: [[HI:%[0-9]+]]:_(s32) = COPY $a1
+; BE: [[LO:%[0-9]+]]:_(s32) = COPY $r5
+; BE-NEXT: [[HI:%[0-9]+]]:_(s32) = COPY $r4
+; LE: [[LO:%[0-9]+]]:_(s32) = COPY $r4
+; LE-NEXT: [[HI:%[0-9]+]]:_(s32) = COPY $r5
; CHECK-NEXT: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LO]](s32), [[HI]](s32)
; CHECK-NEXT: [[RLO:%[0-9]+]]:_(s32), [[RHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64)
; BE-NEXT: $r3 = COPY [[RLO]](s32)
@@ -27,11 +27,11 @@ define i64 @integer_call(i64 %x) {
; CHECK-LABEL: name: integer_call
; CHECK: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES
; CHECK: [[LO:%[0-9]+]]:_(s32), [[HI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64)
-; CHECK: $a0 = COPY
-; BE-NEXT: $a3 = COPY [[LO]](s32)
-; BE-NEXT: $a2 = COPY [[HI]](s32)
-; LE-NEXT: $a2 = COPY [[LO]](s32)
-; LE-NEXT: $a3 = COPY [[HI]](s32)
+; CHECK: $r4 = COPY
+; BE-NEXT: $r7 = COPY [[LO]](s32)
+; BE-NEXT: $r6 = COPY [[HI]](s32)
+; LE-NEXT: $r6 = COPY [[LO]](s32)
+; LE-NEXT: $r7 = COPY [[HI]](s32)
; CHECK-NEXT: JAL @callee_integer,
; BE-NEXT: [[RLO:%[0-9]+]]:_(s32) = COPY $r3
; BE-NEXT: [[RHI:%[0-9]+]]:_(s32) = COPY $r2
@@ -74,8 +74,8 @@ define void @integer_stack_call(i64 %x) {
; Doubles passed in GPRs use the target's custom assignment handler.
define double @double_regs(i32 %a, double %x) {
; CHECK-LABEL: name: double_regs
-; CHECK: [[A2:%[0-9]+]]:_(s32) = COPY $a2
-; CHECK-NEXT: [[A3:%[0-9]+]]:_(s32) = COPY $a3
+; CHECK: [[A2:%[0-9]+]]:_(s32) = COPY $r6
+; CHECK-NEXT: [[A3:%[0-9]+]]:_(s32) = COPY $r7
; BE-NEXT: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A3]](s32), [[A2]](s32)
; LE-NEXT: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A3]](s32)
; FP32-NEXT: $d0 = COPY [[X]](s64)
@@ -89,11 +89,11 @@ define double @double_call(double %x) {
; FP32: [[X:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[X:%[0-9]+]]:_(s64) = COPY $d12_64
; CHECK: [[LO:%[0-9]+]]:_(s32), [[HI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64)
-; CHECK: $a0 = COPY
-; BE-NEXT: $a2 = COPY [[HI]](s32)
-; BE-NEXT: $a3 = COPY [[LO]](s32)
-; LE-NEXT: $a2 = COPY [[LO]](s32)
-; LE-NEXT: $a3 = COPY [[HI]](s32)
+; CHECK: $r4 = COPY
+; BE-NEXT: $r6 = COPY [[HI]](s32)
+; BE-NEXT: $r7 = COPY [[LO]](s32)
+; LE-NEXT: $r6 = COPY [[LO]](s32)
+; LE-NEXT: $r7 = COPY [[HI]](s32)
; CHECK-NEXT: JAL @callee_double,
; FP32-NEXT: [[R:%[0-9]+]]:_(s64) = COPY $d0
; FP64-NEXT: [[R:%[0-9]+]]:_(s64) = COPY $d0_64
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll
index 6409b58fc32df..4fad75d2feb02 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll
@@ -4,8 +4,8 @@
define i32 @shl(i32 %a) {
; MIPS32-LABEL: name: shl
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]]
; MIPS32: $r2 = COPY [[SHL]](s32)
@@ -18,8 +18,8 @@ entry:
define i32 @ashr(i32 %a) {
; MIPS32-LABEL: name: ashr
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]]
; MIPS32: $r2 = COPY [[ASHR]](s32)
@@ -32,8 +32,8 @@ entry:
define i32 @lshr(i32 %a) {
; MIPS32-LABEL: name: lshr
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]]
; MIPS32: $r2 = COPY [[LSHR]](s32)
@@ -46,9 +46,9 @@ entry:
define i32 @shlv(i32 %a, i32 %b) {
; MIPS32-LABEL: name: shlv
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[SHL]](s32)
; MIPS32: RetRA implicit $r2
@@ -60,9 +60,9 @@ entry:
define i32 @ashrv(i32 %a, i32 %b) {
; MIPS32-LABEL: name: ashrv
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $r2
@@ -74,9 +74,9 @@ entry:
define i32 @lshrv(i32 %a, i32 %b) {
; MIPS32-LABEL: name: lshrv
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[LSHR]](s32)
; MIPS32: RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
index b9fcdd0b57d29..1016e6f0ec7df 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
@@ -7,36 +7,36 @@ declare i32 @f(i32 %a, i32 %b);
define i32 @call_global(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32-LABEL: name: call_global
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY2]](s32)
- ; MIPS32: $a1 = COPY [[COPY3]](s32)
- ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY2]](s32)
+ ; MIPS32: $r5 = COPY [[COPY3]](s32)
+ ; MIPS32: JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
; MIPS32: $r2 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $r2
; MIPS32_PIC-LABEL: name: call_global
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1, $a2, $a3, $r2, $t9
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32_PIC: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: liveins: $r4, $r5, $r6, $r7, $r25, $r2
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32_PIC: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
+ ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: [[GV:%[0-9]+]]:gpr32(p0) = G_GLOBAL_VALUE target-flags(mips-got-call) @f
- ; MIPS32_PIC: $a0 = COPY [[COPY2]](s32)
- ; MIPS32_PIC: $a1 = COPY [[COPY3]](s32)
- ; MIPS32_PIC: $gp = COPY [[ADDu]]
- ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $r2
+ ; MIPS32_PIC: $r4 = COPY [[COPY2]](s32)
+ ; MIPS32_PIC: $r5 = COPY [[COPY3]](s32)
+ ; MIPS32_PIC: $r28 = COPY [[ADDu]]
+ ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r28, implicit-def $r2
; MIPS32_PIC: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
; MIPS32_PIC: $r2 = COPY [[ADD]](s32)
; MIPS32_PIC: RetRA implicit $r2
@@ -49,17 +49,17 @@ entry:
define internal i32 @f_with_local_linkage(i32 %x, i32 %y) {
; MIPS32-LABEL: name: f_with_local_linkage
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $r2
; MIPS32_PIC-LABEL: name: f_with_local_linkage
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1
- ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32_PIC: liveins: $r4, $r5
+ ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32_PIC: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32_PIC: $r2 = COPY [[ADD]](s32)
; MIPS32_PIC: RetRA implicit $r2
@@ -71,36 +71,36 @@ entry:
define i32 @call_global_with_local_linkage(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32-LABEL: name: call_global_with_local_linkage
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY2]](s32)
- ; MIPS32: $a1 = COPY [[COPY3]](s32)
- ; MIPS32: JAL @f_with_local_linkage, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY2]](s32)
+ ; MIPS32: $r5 = COPY [[COPY3]](s32)
+ ; MIPS32: JAL @f_with_local_linkage, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
; MIPS32: $r2 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $r2
; MIPS32_PIC-LABEL: name: call_global_with_local_linkage
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1, $a2, $a3, $r2, $t9
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32_PIC: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: liveins: $r4, $r5, $r6, $r7, $r25, $r2
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32_PIC: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
+ ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: [[GV:%[0-9]+]]:gpr32(p0) = G_GLOBAL_VALUE @f_with_local_linkage
- ; MIPS32_PIC: $a0 = COPY [[COPY2]](s32)
- ; MIPS32_PIC: $a1 = COPY [[COPY3]](s32)
- ; MIPS32_PIC: $gp = COPY [[ADDu]]
- ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $r2
+ ; MIPS32_PIC: $r4 = COPY [[COPY2]](s32)
+ ; MIPS32_PIC: $r5 = COPY [[COPY3]](s32)
+ ; MIPS32_PIC: $r28 = COPY [[ADDu]]
+ ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r28, implicit-def $r2
; MIPS32_PIC: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
; MIPS32_PIC: $r2 = COPY [[ADD]](s32)
; MIPS32_PIC: RetRA implicit $r2
@@ -113,30 +113,30 @@ entry:
define i32 @call_reg(ptr %f_ptr, i32 %x, i32 %y) {
; MIPS32-LABEL: name: call_reg
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY1]](s32)
- ; MIPS32: $a1 = COPY [[COPY2]](s32)
- ; MIPS32: JALRPseudo [[COPY]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY1]](s32)
+ ; MIPS32: $r5 = COPY [[COPY2]](s32)
+ ; MIPS32: JALRPseudo [[COPY]](p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY3]](s32)
; MIPS32: RetRA implicit $r2
; MIPS32_PIC-LABEL: name: call_reg
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1, $a2
- ; MIPS32_PIC: [[COPY:%[0-9]+]]:gpr32(p0) = COPY $a0
- ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32_PIC: $a0 = COPY [[COPY1]](s32)
- ; MIPS32_PIC: $a1 = COPY [[COPY2]](s32)
- ; MIPS32_PIC: JALRPseudo [[COPY]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32_PIC: liveins: $r4, $r5, $r6
+ ; MIPS32_PIC: [[COPY:%[0-9]+]]:gpr32(p0) = COPY $r4
+ ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32_PIC: $r4 = COPY [[COPY1]](s32)
+ ; MIPS32_PIC: $r5 = COPY [[COPY2]](s32)
+ ; MIPS32_PIC: JALRPseudo [[COPY]](p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
; MIPS32_PIC: [[COPY3:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: $r2 = COPY [[COPY3]](s32)
; MIPS32_PIC: RetRA implicit $r2
entry:
@@ -149,18 +149,18 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado
define void @call_symbol(ptr nocapture readonly %src, ptr nocapture %dest, i32 signext %length) {
; MIPS32-LABEL: name: call_symbol
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32: G_MEMCPY [[COPY1]](p0), [[COPY]](p0), [[COPY2]](s32), 0 :: (store (s8) into %ir.dest), (load (s8) from %ir.src)
; MIPS32: RetRA
; MIPS32_PIC-LABEL: name: call_symbol
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1, $a2
- ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32_PIC: liveins: $r4, $r5, $r6
+ ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32_PIC: G_MEMCPY [[COPY1]](p0), [[COPY]](p0), [[COPY2]](s32), 0 :: (store (s8) into %ir.dest), (load (s8) from %ir.src)
; MIPS32_PIC: RetRA
entry:
@@ -173,19 +173,19 @@ declare void @f_with_void_ret();
define void @call_f_with_void_ret() {
; MIPS32-LABEL: name: call_f_with_void_ret
; MIPS32: bb.1.entry:
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: JAL @f_with_void_ret, csr_o32, implicit-def dead $ra, implicit-def $sp
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: JAL @f_with_void_ret, csr_o32, implicit-def dead $r31, implicit-def $r29
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
; MIPS32_PIC-LABEL: name: call_f_with_void_ret
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $r2, $t9
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: liveins: $r25, $r2
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: [[GV:%[0-9]+]]:gpr32(p0) = G_GLOBAL_VALUE target-flags(mips-got-call) @f_with_void_ret
- ; MIPS32_PIC: $gp = COPY [[ADDu]]
- ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $gp
- ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: $r28 = COPY [[ADDu]]
+ ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r28
+ ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: RetRA
entry:
call void @f_with_void_ret()
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
index 90cb341d20af5..587b90a7ed747 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
@@ -6,9 +6,9 @@
define signext i8 @sext_arg_i8(i8 signext %a) {
; MIPS32-LABEL: name: sext_arg_i8
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
; MIPS32-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s8)
@@ -21,9 +21,9 @@ entry:
define zeroext i8 @zext_arg_i8(i8 zeroext %a) {
; MIPS32-LABEL: name: zext_arg_i8
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32)
; MIPS32-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
@@ -36,9 +36,9 @@ entry:
define i8 @aext_arg_i8(i8 %a) {
; MIPS32-LABEL: name: aext_arg_i8
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; MIPS32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
; MIPS32-NEXT: $r2 = COPY [[ANYEXT]](s32)
@@ -54,31 +54,31 @@ declare i8 @aext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 %a)
define signext i8 @call_sext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 signext %a) {
; MIPS32-LABEL: name: call_sext_stack_arg_i8
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD]], 8
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s8)
- ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
+ ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $r29
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[SEXT]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack + 16, align 8)
- ; MIPS32-NEXT: $a0 = COPY [[COPY]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
- ; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
- ; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @sext_stack_arg_i8, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: $r4 = COPY [[COPY]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32-NEXT: $r6 = COPY [[COPY2]](s32)
+ ; MIPS32-NEXT: $r7 = COPY [[COPY3]](s32)
+ ; MIPS32-NEXT: JAL @sext_stack_arg_i8, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY5]], 8
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT1]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC1]](s8)
; MIPS32-NEXT: $r2 = COPY [[SEXT1]](s32)
; MIPS32-NEXT: RetRA implicit $r2
@@ -90,31 +90,31 @@ entry:
define zeroext i8 @call_zext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 zeroext %a) {
; MIPS32-LABEL: name: call_zext_stack_arg_i8
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[LOAD]], 8
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
- ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
+ ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $r29
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[ZEXT]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack + 16, align 8)
- ; MIPS32-NEXT: $a0 = COPY [[COPY]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
- ; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
- ; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @zext_stack_arg_i8, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: $r4 = COPY [[COPY]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32-NEXT: $r6 = COPY [[COPY2]](s32)
+ ; MIPS32-NEXT: $r7 = COPY [[COPY3]](s32)
+ ; MIPS32-NEXT: JAL @zext_stack_arg_i8, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY5]], 8
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT1]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s8)
; MIPS32-NEXT: $r2 = COPY [[ZEXT1]](s32)
; MIPS32-NEXT: RetRA implicit $r2
@@ -126,29 +126,29 @@ entry:
define i8 @call_aext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 %a) {
; MIPS32-LABEL: name: call_aext_stack_arg_i8
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[LOAD]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
+ ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $r29
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack + 16, align 8)
- ; MIPS32-NEXT: $a0 = COPY [[COPY]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
- ; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
- ; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @aext_stack_arg_i8, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: $r4 = COPY [[COPY]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32-NEXT: $r6 = COPY [[COPY2]](s32)
+ ; MIPS32-NEXT: $r7 = COPY [[COPY3]](s32)
+ ; MIPS32-NEXT: JAL @aext_stack_arg_i8, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY5]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8)
; MIPS32-NEXT: $r2 = COPY [[ANYEXT1]](s32)
; MIPS32-NEXT: RetRA implicit $r2
@@ -161,9 +161,9 @@ entry:
define signext i16 @sext_arg_i16(i16 signext %a) {
; MIPS32-LABEL: name: sext_arg_i16
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
; MIPS32-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
@@ -176,9 +176,9 @@ entry:
define zeroext i16 @zext_arg_i16(i16 zeroext %a) {
; MIPS32-LABEL: name: zext_arg_i16
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
; MIPS32-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
@@ -191,9 +191,9 @@ entry:
define i16 @aext_arg_i16(i16 %a) {
; MIPS32-LABEL: name: aext_arg_i16
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; MIPS32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
; MIPS32-NEXT: $r2 = COPY [[ANYEXT]](s32)
@@ -209,31 +209,31 @@ declare i16 @aext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 %a)
define signext i16 @call_sext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 signext %a) {
; MIPS32-LABEL: name: call_sext_stack_arg_i16
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD]], 16
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
- ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
+ ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $r29
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[SEXT]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack + 16, align 8)
- ; MIPS32-NEXT: $a0 = COPY [[COPY]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
- ; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
- ; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @sext_stack_arg_i16, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: $r4 = COPY [[COPY]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32-NEXT: $r6 = COPY [[COPY2]](s32)
+ ; MIPS32-NEXT: $r7 = COPY [[COPY3]](s32)
+ ; MIPS32-NEXT: JAL @sext_stack_arg_i16, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY5]], 16
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT1]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC1]](s16)
; MIPS32-NEXT: $r2 = COPY [[SEXT1]](s32)
; MIPS32-NEXT: RetRA implicit $r2
@@ -245,31 +245,31 @@ entry:
define zeroext i16 @call_zext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 zeroext %a) {
; MIPS32-LABEL: name: call_zext_stack_arg_i16
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[LOAD]], 16
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
+ ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $r29
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[ZEXT]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack + 16, align 8)
- ; MIPS32-NEXT: $a0 = COPY [[COPY]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
- ; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
- ; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @zext_stack_arg_i16, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: $r4 = COPY [[COPY]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32-NEXT: $r6 = COPY [[COPY2]](s32)
+ ; MIPS32-NEXT: $r7 = COPY [[COPY3]](s32)
+ ; MIPS32-NEXT: JAL @zext_stack_arg_i16, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY5]], 16
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT1]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16)
; MIPS32-NEXT: $r2 = COPY [[ZEXT1]](s32)
; MIPS32-NEXT: RetRA implicit $r2
@@ -281,29 +281,29 @@ entry:
define i16 @call_aext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 %a) {
; MIPS32-LABEL: name: call_aext_stack_arg_i16
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
- ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
+ ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $r29
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack + 16, align 8)
- ; MIPS32-NEXT: $a0 = COPY [[COPY]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
- ; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
- ; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @aext_stack_arg_i16, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: $r4 = COPY [[COPY]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32-NEXT: $r6 = COPY [[COPY2]](s32)
+ ; MIPS32-NEXT: $r7 = COPY [[COPY3]](s32)
+ ; MIPS32-NEXT: JAL @aext_stack_arg_i16, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32)
- ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
; MIPS32-NEXT: $r2 = COPY [[ANYEXT1]](s32)
; MIPS32-NEXT: RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
index d8212c9a3a38d..fa0e793f51f40 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
@@ -50,19 +50,19 @@ entry:
define float @float_in_gpr(i32 %a, float %b) {
; FP32-LABEL: name: float_in_gpr
; FP32: bb.1.entry:
- ; FP32-NEXT: liveins: $a0, $a1
+ ; FP32-NEXT: liveins: $r4, $r5
; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; FP32-NEXT: $f0 = COPY [[COPY1]](s32)
; FP32-NEXT: RetRA implicit $f0
;
; FP64-LABEL: name: float_in_gpr
; FP64: bb.1.entry:
- ; FP64-NEXT: liveins: $a0, $a1
+ ; FP64-NEXT: liveins: $r4, $r5
; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; FP64-NEXT: $f0 = COPY [[COPY1]](s32)
; FP64-NEXT: RetRA implicit $f0
entry:
@@ -72,22 +72,22 @@ entry:
define double @double_in_gpr(i32 %a, double %b) {
; FP32-LABEL: name: double_in_gpr
; FP32: bb.1.entry:
- ; FP32-NEXT: liveins: $a0, $a2, $a3
+ ; FP32-NEXT: liveins: $r4, $r6, $r7
; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; FP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; FP32-NEXT: $d0 = COPY [[MV]](s64)
; FP32-NEXT: RetRA implicit $d0
;
; FP64-LABEL: name: double_in_gpr
; FP64: bb.1.entry:
- ; FP64-NEXT: liveins: $a0, $a2, $a3
+ ; FP64-NEXT: liveins: $r4, $r6, $r7
; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; FP64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; FP64-NEXT: $d0_64 = COPY [[MV]](s64)
; FP64-NEXT: RetRA implicit $d0_64
@@ -98,11 +98,11 @@ entry:
define double @two_double_in_gpr(i32 %a, double %b, double %c) {
; FP32-LABEL: name: two_double_in_gpr
; FP32: bb.1.entry:
- ; FP32-NEXT: liveins: $a0, $a2, $a3
+ ; FP32-NEXT: liveins: $r4, $r6, $r7
; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; FP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; FP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; FP32-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %fixed-stack.0)
@@ -111,11 +111,11 @@ define double @two_double_in_gpr(i32 %a, double %b, double %c) {
;
; FP64-LABEL: name: two_double_in_gpr
; FP64: bb.1.entry:
- ; FP64-NEXT: liveins: $a0, $a2, $a3
+ ; FP64-NEXT: liveins: $r4, $r6, $r7
; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; FP64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; FP64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; FP64-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %fixed-stack.0)
@@ -132,12 +132,12 @@ define float @call_float_in_fpr(float %a, float %b) {
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $f12 = COPY [[COPY]](s32)
; FP32-NEXT: $f14 = COPY [[COPY1]](s32)
- ; FP32-NEXT: JAL @float_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ ; FP32-NEXT: JAL @float_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit $f14, implicit-def $f0
; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $f0 = COPY [[COPY2]](s32)
; FP32-NEXT: RetRA implicit $f0
;
@@ -147,12 +147,12 @@ define float @call_float_in_fpr(float %a, float %b) {
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $f12 = COPY [[COPY]](s32)
; FP64-NEXT: $f14 = COPY [[COPY1]](s32)
- ; FP64-NEXT: JAL @float_in_fpr, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ ; FP64-NEXT: JAL @float_in_fpr, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit $f14, implicit-def $f0
; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $f0 = COPY [[COPY2]](s32)
; FP64-NEXT: RetRA implicit $f0
entry:
@@ -167,12 +167,12 @@ define double @call_double_in_fpr(double %a, double %b) {
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $d6 = COPY [[COPY]](s64)
; FP32-NEXT: $d7 = COPY [[COPY1]](s64)
- ; FP32-NEXT: JAL @double_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+ ; FP32-NEXT: JAL @double_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit $d7, implicit-def $d0
; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $d0 = COPY [[COPY2]](s64)
; FP32-NEXT: RetRA implicit $d0
;
@@ -182,12 +182,12 @@ define double @call_double_in_fpr(double %a, double %b) {
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d12_64
; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d14_64
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $d12_64 = COPY [[COPY]](s64)
; FP64-NEXT: $d14_64 = COPY [[COPY1]](s64)
- ; FP64-NEXT: JAL @double_in_fpr, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $d12_64, implicit $d14_64, implicit-def $d0_64
+ ; FP64-NEXT: JAL @double_in_fpr, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $d12_64, implicit $d14_64, implicit-def $d0_64
; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0_64
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $d0_64 = COPY [[COPY2]](s64)
; FP64-NEXT: RetRA implicit $d0_64
entry:
@@ -198,31 +198,31 @@ entry:
define float @call_float_in_gpr(i32 %a, float %b) {
; FP32-LABEL: name: call_float_in_gpr
; FP32: bb.1.entry:
- ; FP32-NEXT: liveins: $a0, $a1
+ ; FP32-NEXT: liveins: $r4, $r5
; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $a0 = COPY [[COPY]](s32)
- ; FP32-NEXT: $a1 = COPY [[COPY1]](s32)
- ; FP32-NEXT: JAL @float_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
+ ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP32-NEXT: $r4 = COPY [[COPY]](s32)
+ ; FP32-NEXT: $r5 = COPY [[COPY1]](s32)
+ ; FP32-NEXT: JAL @float_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $f0
; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $f0 = COPY [[COPY2]](s32)
; FP32-NEXT: RetRA implicit $f0
;
; FP64-LABEL: name: call_float_in_gpr
; FP64: bb.1.entry:
- ; FP64-NEXT: liveins: $a0, $a1
+ ; FP64-NEXT: liveins: $r4, $r5
; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $a0 = COPY [[COPY]](s32)
- ; FP64-NEXT: $a1 = COPY [[COPY1]](s32)
- ; FP64-NEXT: JAL @float_in_gpr, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
+ ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP64-NEXT: $r4 = COPY [[COPY]](s32)
+ ; FP64-NEXT: $r5 = COPY [[COPY1]](s32)
+ ; FP64-NEXT: JAL @float_in_gpr, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $f0
; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $f0 = COPY [[COPY2]](s32)
; FP64-NEXT: RetRA implicit $f0
entry:
@@ -234,39 +234,39 @@ entry:
define double @call_double_in_gpr(i32 %a, double %b) {
; FP32-LABEL: name: call_double_in_gpr
; FP32: bb.1.entry:
- ; FP32-NEXT: liveins: $a0, $a2, $a3
+ ; FP32-NEXT: liveins: $r4, $r6, $r7
; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; FP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
- ; FP32-NEXT: $a0 = COPY [[COPY]](s32)
- ; FP32-NEXT: $a2 = COPY [[UV]](s32)
- ; FP32-NEXT: $a3 = COPY [[UV1]](s32)
- ; FP32-NEXT: JAL @double_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a2, implicit $a3, implicit $a0, implicit-def $d0
+ ; FP32-NEXT: $r4 = COPY [[COPY]](s32)
+ ; FP32-NEXT: $r6 = COPY [[UV]](s32)
+ ; FP32-NEXT: $r7 = COPY [[UV1]](s32)
+ ; FP32-NEXT: JAL @double_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r6, implicit $r7, implicit $r4, implicit-def $d0
; FP32-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $d0
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $d0 = COPY [[COPY3]](s64)
; FP32-NEXT: RetRA implicit $d0
;
; FP64-LABEL: name: call_double_in_gpr
; FP64: bb.1.entry:
- ; FP64-NEXT: liveins: $a0, $a2, $a3
+ ; FP64-NEXT: liveins: $r4, $r6, $r7
; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; FP64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
- ; FP64-NEXT: $a0 = COPY [[COPY]](s32)
- ; FP64-NEXT: $a2 = COPY [[UV]](s32)
- ; FP64-NEXT: $a3 = COPY [[UV1]](s32)
- ; FP64-NEXT: JAL @double_in_gpr, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $a2, implicit $a3, implicit $a0, implicit-def $d0_64
+ ; FP64-NEXT: $r4 = COPY [[COPY]](s32)
+ ; FP64-NEXT: $r6 = COPY [[UV]](s32)
+ ; FP64-NEXT: $r7 = COPY [[UV1]](s32)
+ ; FP64-NEXT: JAL @double_in_gpr, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $r6, implicit $r7, implicit $r4, implicit-def $d0_64
; FP64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $d0_64
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $d0_64 = COPY [[COPY3]](s64)
; FP64-NEXT: RetRA implicit $d0_64
entry:
@@ -283,14 +283,14 @@ define double @call_double_fpr_to_gpr(double %a) {
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; FP32-NEXT: $a0 = COPY [[C]](s32)
- ; FP32-NEXT: $a2 = COPY [[UV]](s32)
- ; FP32-NEXT: $a3 = COPY [[UV1]](s32)
- ; FP32-NEXT: JAL @double_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a2, implicit $a3, implicit $a0, implicit-def $d0
+ ; FP32-NEXT: $r4 = COPY [[C]](s32)
+ ; FP32-NEXT: $r6 = COPY [[UV]](s32)
+ ; FP32-NEXT: $r7 = COPY [[UV1]](s32)
+ ; FP32-NEXT: JAL @double_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r6, implicit $r7, implicit $r4, implicit-def $d0
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $d0 = COPY [[COPY1]](s64)
; FP32-NEXT: RetRA implicit $d0
;
@@ -300,14 +300,14 @@ define double @call_double_fpr_to_gpr(double %a) {
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d12_64
; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; FP64-NEXT: $a0 = COPY [[C]](s32)
- ; FP64-NEXT: $a2 = COPY [[UV]](s32)
- ; FP64-NEXT: $a3 = COPY [[UV1]](s32)
- ; FP64-NEXT: JAL @double_in_gpr, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $a2, implicit $a3, implicit $a0, implicit-def $d0_64
+ ; FP64-NEXT: $r4 = COPY [[C]](s32)
+ ; FP64-NEXT: $r6 = COPY [[UV]](s32)
+ ; FP64-NEXT: $r7 = COPY [[UV1]](s32)
+ ; FP64-NEXT: JAL @double_in_gpr, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $r6, implicit $r7, implicit $r4, implicit-def $d0_64
; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0_64
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $d0_64 = COPY [[COPY1]](s64)
; FP64-NEXT: RetRA implicit $d0_64
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
index eaa279cfe17c0..8b54e22b46677 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
@@ -9,12 +9,12 @@ define i32 @main() {
; MIPS32-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @.str
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1234567890
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32-NEXT: $a0 = COPY [[GV]](p0)
- ; MIPS32-NEXT: $a1 = COPY [[C]](s32)
- ; MIPS32-NEXT: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32-NEXT: $r4 = COPY [[GV]](p0)
+ ; MIPS32-NEXT: $r5 = COPY [[C]](s32)
+ ; MIPS32-NEXT: JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: $r2 = COPY [[C1]](s32)
; MIPS32-NEXT: RetRA implicit $r2
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
index 97c7fafbc4758..483f4aff874f0 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
@@ -6,9 +6,9 @@ declare i32 @f(i32 %a, i32 %b);
define internal i32 @f_with_local_linkage(i32 %x, i32 %y) {
; MIPS32_PIC-LABEL: name: f_with_local_linkage
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1
- ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32_PIC: liveins: $r4, $r5
+ ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32_PIC: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32_PIC: $r2 = COPY [[ADD]](s32)
; MIPS32_PIC: RetRA implicit $r2
@@ -20,18 +20,18 @@ entry:
define i32 @call_global(i32 %a, i32 %b) {
; MIPS32_PIC-LABEL: name: call_global
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1, $r2, $t9
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: liveins: $r4, $r5, $r25, $r2
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: [[GV:%[0-9]+]]:gpr32(p0) = G_GLOBAL_VALUE target-flags(mips-got-call) @f
- ; MIPS32_PIC: $a0 = COPY [[COPY]](s32)
- ; MIPS32_PIC: $a1 = COPY [[COPY1]](s32)
- ; MIPS32_PIC: $gp = COPY [[ADDu]]
- ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $r2
+ ; MIPS32_PIC: $r4 = COPY [[COPY]](s32)
+ ; MIPS32_PIC: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32_PIC: $r28 = COPY [[ADDu]]
+ ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r28, implicit-def $r2
; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: $r2 = COPY [[COPY2]](s32)
; MIPS32_PIC: RetRA implicit $r2
entry:
@@ -42,18 +42,18 @@ entry:
define i32 @call_global_with_local_linkage(i32 %a, i32 %b) {
; MIPS32_PIC-LABEL: name: call_global_with_local_linkage
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $a0, $a1, $r2, $t9
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: liveins: $r4, $r5, $r25, $r2
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: [[GV:%[0-9]+]]:gpr32(p0) = G_GLOBAL_VALUE @f_with_local_linkage
- ; MIPS32_PIC: $a0 = COPY [[COPY]](s32)
- ; MIPS32_PIC: $a1 = COPY [[COPY1]](s32)
- ; MIPS32_PIC: $gp = COPY [[ADDu]]
- ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $gp, implicit-def $r2
+ ; MIPS32_PIC: $r4 = COPY [[COPY]](s32)
+ ; MIPS32_PIC: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32_PIC: $r28 = COPY [[ADDu]]
+ ; MIPS32_PIC: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r28, implicit-def $r2
; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32_PIC: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: $r2 = COPY [[COPY2]](s32)
; MIPS32_PIC: RetRA implicit $r2
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
index 646d3a3409e95..38baab58512f1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
@@ -5,8 +5,8 @@
define i32 @ptr_arg_in_regs(ptr %p) {
; MIPS32-LABEL: name: ptr_arg_in_regs
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.p)
; MIPS32: $r2 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $r2
@@ -18,11 +18,11 @@ entry:
define i32 @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, ptr %p) {
; MIPS32-LABEL: name: ptr_arg_on_stack
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.p)
@@ -36,8 +36,8 @@ entry:
define ptr @ret_ptr(ptr %p) {
; MIPS32-LABEL: name: ret_ptr
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: $r2 = COPY [[COPY]](p0)
; MIPS32: RetRA implicit $r2
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll
index 768ea7b970b01..48dfd1a53a8bb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll
@@ -3,9 +3,9 @@
define i64 @i64_reg(i64 %a) {
; MIPS32-LABEL: name: i64_reg
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $r2 = COPY [[UV]](s32)
@@ -21,11 +21,11 @@ define i64 @i64_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i64 %a) {
; MIPS32-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4,
; MIPS32-DAG: - { id: [[STACK1:[0-9]+]], type: default, offset: 16, size: 4, alignment: 8,
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.[[STACK1]], align 8)
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -42,10 +42,10 @@ entry:
define i64 @i64_reg_allign(i32 %a0, i64 %a) {
; MIPS32-LABEL: name: i64_reg_allign
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $r2 = COPY [[UV]](s32)
@@ -62,11 +62,11 @@ define i64 @i64_stack_allign(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %s16, i64 %
; MIPS32-DAG: - { id: [[STACK1:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8,
; MIPS32-DAG: - { id: [[STACK2:[0-9]+]], type: default, offset: 16, size: 4, alignment: 8,
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.[[STACK2]], align 8)
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -88,10 +88,10 @@ define i64 @i64_reg_stack(i32 %a0, i32 %a1, i32 %a2, i64 %a) {
; MIPS32-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4,
; MIPS32-DAG: - { id: [[STACK1:[0-9]+]], type: default, offset: 16, size: 4, alignment: 8,
; MIPS32: bb.1.entry:
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.[[STACK1]], align 8)
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
index ef1d59e936492..58ba321979de8 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
@@ -6,9 +6,9 @@
define void @ZeroInit(ptr noalias sret(%struct.S) %agg.result) {
; MIPS32-LABEL: name: ZeroInit
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.x)
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
@@ -26,13 +26,13 @@ entry:
define void @CallZeroInit(ptr noalias sret(%struct.S) %agg.result) {
; MIPS32-LABEL: name: CallZeroInit
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32-NEXT: $a0 = COPY [[COPY]](p0)
- ; MIPS32-NEXT: JAL @ZeroInit, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32-NEXT: $r4 = COPY [[COPY]](p0)
+ ; MIPS32-NEXT: JAL @ZeroInit, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: RetRA
entry:
call void @ZeroInit(ptr sret(%struct.S) %agg.result)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
index 8420e44996789..93703dbe6cbdb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
@@ -6,26 +6,26 @@ declare i32 @f(i32, i32, i32, i32, i32)
define i32 @g(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5){
; MIPS32-LABEL: name: g
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
- ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
+ ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $r29
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[LOAD]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack + 16, align 8)
- ; MIPS32-NEXT: $a0 = COPY [[COPY]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[COPY1]](s32)
- ; MIPS32-NEXT: $a2 = COPY [[COPY2]](s32)
- ; MIPS32-NEXT: $a3 = COPY [[COPY3]](s32)
- ; MIPS32-NEXT: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32-NEXT: $r4 = COPY [[COPY]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32-NEXT: $r6 = COPY [[COPY2]](s32)
+ ; MIPS32-NEXT: $r7 = COPY [[COPY3]](s32)
+ ; MIPS32-NEXT: JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
; MIPS32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: $r2 = COPY [[COPY5]](s32)
; MIPS32-NEXT: RetRA implicit $r2
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
index 96797c95fafe6..480da52a7f77c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
@@ -9,16 +9,16 @@ declare i32 @printf(ptr, ...)
define void @testVaCopyArg(ptr %fmt, ...) {
; MIPS32-LABEL: name: testVaCopyArg
; MIPS32: bb.1.entry:
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
; MIPS32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.2)
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; MIPS32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.1)
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.0)
; MIPS32-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @.str
@@ -36,12 +36,12 @@ define void @testVaCopyArg(ptr %fmt, ...) {
; MIPS32-NEXT: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[LOAD]](p0) :: (load (p0) from %ir.argp.cur)
; MIPS32-NEXT: G_STORE [[LOAD1]](p0), [[FRAME_INDEX6]](p0) :: (store (p0) into %ir.s)
; MIPS32-NEXT: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX6]](p0) :: (load (p0) from %ir.s)
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32-NEXT: $a0 = COPY [[GV]](p0)
- ; MIPS32-NEXT: $a1 = COPY [[LOAD2]](p0)
- ; MIPS32-NEXT: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32-NEXT: $r4 = COPY [[GV]](p0)
+ ; MIPS32-NEXT: $r5 = COPY [[LOAD2]](p0)
+ ; MIPS32-NEXT: JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: RetRA
entry:
%fmt.addr = alloca ptr, align 4
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
index fb205853e6ab8..37d62bf129c2e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
@@ -20,18 +20,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: add_i32
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; MIPS32-NEXT: $r2 = COPY [[ADD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_ADD %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -43,22 +43,22 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: add_i8_sext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_ADD %1, %0
%5:_(s32) = G_SEXT %4(s8)
@@ -72,21 +72,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: add_i8_zext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_ADD %1, %0
%5:_(s32) = G_ZEXT %4(s8)
@@ -100,19 +100,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: add_i8_aext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[ADD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_ADD %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
@@ -126,22 +126,22 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: add_i16_sext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_ADD %1, %0
%5:_(s32) = G_SEXT %4(s16)
@@ -155,21 +155,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: add_i16_zext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_ADD %1, %0
%5:_(s32) = G_ZEXT %4(s16)
@@ -183,19 +183,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: add_i16_aext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[ADD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_ADD %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
@@ -209,15 +209,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: add_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY1]]
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
@@ -227,11 +227,11 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[COPY5]](s32)
; MIPS32-NEXT: $r3 = COPY [[COPY4]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %5(s32), %4(s32)
%6:_(s64) = G_ADD %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -251,15 +251,15 @@ fixedStack:
- { id: 3, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: add_i128
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -294,13 +294,13 @@ body: |
; MIPS32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD6]](s32)
; MIPS32-NEXT: $r2 = COPY [[COPY4]](s32)
; MIPS32-NEXT: $r3 = COPY [[COPY5]](s32)
- ; MIPS32-NEXT: $a0 = COPY [[COPY6]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[COPY7]](s32)
- ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ ; MIPS32-NEXT: $r4 = COPY [[COPY6]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[COPY7]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3, implicit $r4, implicit $r5
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
%10:_(p0) = G_FRAME_INDEX %fixed-stack.3
%6:_(s32) = G_LOAD %10(p0) :: (load (s32) from %fixed-stack.3, align 4)
@@ -315,9 +315,9 @@ body: |
%15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
$r2 = COPY %15(s32)
$r3 = COPY %16(s32)
- $a0 = COPY %17(s32)
- $a1 = COPY %18(s32)
- RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
+ $r4 = COPY %17(s32)
+ $r5 = COPY %18(s32)
+ RetRA implicit $r2, implicit $r3, implicit $r4, implicit $r5
...
---
@@ -326,15 +326,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: uadd_with_overflow
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $r7
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
@@ -343,10 +343,10 @@ body: |
; MIPS32-NEXT: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
; MIPS32-NEXT: G_STORE [[COPY4]](s32), [[COPY2]](p0) :: (store (s32) into %ir.padd)
; MIPS32-NEXT: RetRA
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(p0) = COPY $a2
- %3:_(p0) = COPY $a3
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(p0) = COPY $r6
+ %3:_(p0) = COPY $r7
%4:_(s32), %5:_(s1) = G_UADDO %0, %1
G_STORE %5(s1), %3(p0) :: (store (s1) into %ir.pcarry_flag)
G_STORE %4(s32), %2(p0) :: (store (s32) into %ir.padd)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir
index a7005566d6a4a..6236da7ec14d6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir
@@ -14,21 +14,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_ADD %4, %3
@@ -42,21 +42,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_ADD %4, %3
@@ -70,21 +70,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_ADD %4, %3
@@ -98,21 +98,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_ADD %4, %3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
index f4ba16e09487f..25ac2f59d3b71 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
@@ -33,21 +33,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v16i8_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.addv.b), %3(<16 x s8>), %4(<16 x s8>)
@@ -61,21 +61,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v8i16_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.addv.h), %3(<8 x s16>), %4(<8 x s16>)
@@ -89,21 +89,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v4i32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addv.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -117,21 +117,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v2i64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.addv.d), %3(<2 x s64>), %4(<2 x s64>)
@@ -145,18 +145,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: add_v16i8_builtin_imm
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128b(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[ADDVI_B:%[0-9]+]]:msa128b(<16 x s8>) = ADDVI_B [[LOAD]](<16 x s8>), 3
; P5600: G_STORE [[ADDVI_B]](<16 x s8>), [[COPY1]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%3:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.b), %2(<16 x s8>), 3
G_STORE %3(<16 x s8>), %1(p0) :: (store (<16 x s8>) into %ir.c)
@@ -169,18 +169,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: add_v8i16_builtin_imm
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128h(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[ADDVI_H:%[0-9]+]]:msa128h(<8 x s16>) = ADDVI_H [[LOAD]](<8 x s16>), 18
; P5600: G_STORE [[ADDVI_H]](<8 x s16>), [[COPY1]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%3:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.h), %2(<8 x s16>), 18
G_STORE %3(<8 x s16>), %1(p0) :: (store (<8 x s16>) into %ir.c)
@@ -193,18 +193,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: add_v4i32_builtin_imm
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
@@ -217,18 +217,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: add_v2i64_builtin_imm
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128d(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[ADDVI_D:%[0-9]+]]:msa128d(<2 x s64>) = ADDVI_D [[LOAD]](<2 x s64>), 31
; P5600: G_STORE [[ADDVI_D]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.d), %2(<2 x s64>), 31
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
index 84fe5971904de..fdab247104a85 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
@@ -13,11 +13,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: bitreverse_i32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
@@ -54,8 +54,8 @@ body: |
; MIPS32: $r2 = COPY [[OR5]](s32)
; MIPS32: RetRA implicit $r2
; MIPS32R2-LABEL: name: bitreverse_i32
- ; MIPS32R2: liveins: $a0
- ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32R2: liveins: $r4
+ ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; MIPS32R2: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R2: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
@@ -80,7 +80,7 @@ body: |
; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND5]]
; MIPS32R2: $r2 = COPY [[OR2]](s32)
; MIPS32R2: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_BITREVERSE %0
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -92,12 +92,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: bitreverse_i64
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
@@ -159,9 +159,9 @@ body: |
; MIPS32: $r3 = COPY [[OR11]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
; MIPS32R2-LABEL: name: bitreverse_i64
- ; MIPS32R2: liveins: $a0, $a1
- ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32R2: liveins: $r4, $r5
+ ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
; MIPS32R2: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R2: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
@@ -203,8 +203,8 @@ body: |
; MIPS32R2: $r2 = COPY [[OR2]](s32)
; MIPS32R2: $r3 = COPY [[OR5]](s32)
; MIPS32R2: RetRA implicit $r2, implicit $r3
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_BITREVERSE %0
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
index e948758409fab..76e29175aed07 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
@@ -38,19 +38,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: and_i1
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s1) = G_TRUNC %3(s32)
%4:_(s1) = G_AND %1, %0
%5:_(s32) = G_ANYEXT %4(s1)
@@ -64,19 +64,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: and_i8
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_AND %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
@@ -90,19 +90,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: and_i16
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_AND %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
@@ -116,18 +116,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: and_i32
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_AND %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -139,25 +139,25 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: and_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY1]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: $r3 = COPY [[AND1]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_AND %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -172,19 +172,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: or_i1
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[OR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s1) = G_TRUNC %3(s32)
%4:_(s1) = G_OR %1, %0
%5:_(s32) = G_ANYEXT %4(s1)
@@ -198,19 +198,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: or_i8
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[OR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_OR %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
@@ -224,19 +224,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: or_i16
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[OR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_OR %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
@@ -250,18 +250,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: or_i32
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[OR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_OR %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -273,25 +273,25 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: or_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY1]]
; MIPS32-NEXT: $r2 = COPY [[OR]](s32)
; MIPS32-NEXT: $r3 = COPY [[OR1]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_OR %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -306,19 +306,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: xor_i1
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[XOR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s1) = G_TRUNC %3(s32)
%4:_(s1) = G_XOR %1, %0
%5:_(s32) = G_ANYEXT %4(s1)
@@ -332,19 +332,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: xor_i8
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[XOR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_XOR %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
@@ -358,19 +358,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: xor_i16
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[XOR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_XOR %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
@@ -384,18 +384,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: xor_i32
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[XOR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_XOR %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -407,25 +407,25 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: xor_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[COPY1]]
; MIPS32-NEXT: $r2 = COPY [[XOR]](s32)
; MIPS32-NEXT: $r3 = COPY [[XOR1]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_XOR %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -440,17 +440,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: shl
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[SHL]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_SHL %0, %1
$r2 = COPY %2(s32)
@@ -463,17 +463,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ashr
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_ASHR %0, %1
$r2 = COPY %2(s32)
@@ -486,17 +486,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: lshr
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[LSHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_LSHR %0, %1
$r2 = COPY %2(s32)
@@ -509,17 +509,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: lshr_i64_shift_amount
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[LSHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s64) = G_CONSTANT i64 1
%2:_(s32) = G_LSHR %0, %1
$r2 = COPY %2(s32)
@@ -532,18 +532,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: shlv
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; MIPS32-NEXT: $r2 = COPY [[SHL]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_SHL %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -555,18 +555,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ashrv
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_ASHR %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -578,18 +578,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: lshrv
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
; MIPS32-NEXT: $r2 = COPY [[LSHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_LSHR %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -601,17 +601,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: shl_i16
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[SHL]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CONSTANT i16 2
%3:_(s16) = G_SHL %0, %2(s16)
@@ -626,12 +626,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ashr_i8
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
@@ -639,7 +639,7 @@ body: |
; MIPS32-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[ASHR1]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s8) = G_CONSTANT i8 2
%3:_(s8) = G_ASHR %0, %2(s8)
@@ -654,19 +654,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: lshr_i16
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[LSHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CONSTANT i16 2
%3:_(s16) = G_LSHR %0, %2(s16)
@@ -681,14 +681,14 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: shl_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
@@ -706,11 +706,11 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: $r3 = COPY [[SELECT2]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_SHL %0, %1(s64)
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -725,14 +725,14 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: ashl_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
@@ -752,11 +752,11 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[SELECT1]](s32)
; MIPS32-NEXT: $r3 = COPY [[SELECT2]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_ASHR %0, %1(s64)
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -771,14 +771,14 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: lshr_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
@@ -796,11 +796,11 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[SELECT1]](s32)
; MIPS32-NEXT: $r3 = COPY [[SELECT2]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_LSHR %0, %1(s64)
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
index 49330e61d0305..25937a3495777 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
@@ -32,8 +32,8 @@ body: |
; MIPS32-LABEL: name: Unconditional_branch
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.2(0x80000000)
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.end:
; MIPS32: $r2 = COPY [[COPY]](s32)
@@ -42,9 +42,9 @@ body: |
; MIPS32: successors: %bb.1(0x80000000)
; MIPS32: G_BR %bb.1
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
G_BR %bb.3
bb.2.end:
@@ -63,10 +63,10 @@ body: |
; MIPS32-LABEL: name: Conditional_branch
; MIPS32: bb.0 (%ir-block.0):
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
@@ -78,12 +78,12 @@ body: |
; MIPS32: $r2 = COPY [[COPY2]](s32)
; MIPS32: RetRA implicit $r2
bb.1 (%ir-block.0):
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
G_BRCOND %0(s1), %bb.2
G_BR %bb.3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir
index d5f183974e4bd..9256224197a7c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir
@@ -22,8 +22,8 @@ body: |
; MIPS32-LABEL: name: indirectbr
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: G_BRINDIRECT [[COPY]](p0)
@@ -35,9 +35,9 @@ body: |
; MIPS32: RetRA implicit $r2
bb.1.entry:
successors: %bb.2, %bb.3
- liveins: $a0
+ liveins: $r4
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_CONSTANT i32 0
G_BRINDIRECT %0(p0)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir
index 4708706ec6c3e..5e8ae5d7cdda1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir
@@ -13,11 +13,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: bswap_i32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
@@ -33,12 +33,12 @@ body: |
; MIPS32: $r2 = COPY [[OR2]](s32)
; MIPS32: RetRA implicit $r2
; MIPS32R2-LABEL: name: bswap_i32
- ; MIPS32R2: liveins: $a0
- ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32R2: liveins: $r4
+ ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; MIPS32R2: $r2 = COPY [[BSWAP]](s32)
; MIPS32R2: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_BSWAP %0
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -50,12 +50,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: bswap_i64
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
@@ -81,16 +81,16 @@ body: |
; MIPS32: $r3 = COPY [[OR5]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
; MIPS32R2-LABEL: name: bswap_i64
- ; MIPS32R2: liveins: $a0, $a1
- ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32R2: liveins: $r4, $r5
+ ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
; MIPS32R2: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; MIPS32R2: $r2 = COPY [[BSWAP]](s32)
; MIPS32R2: $r3 = COPY [[BSWAP1]](s32)
; MIPS32R2: RetRA implicit $r2, implicit $r3
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_BSWAP %0
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir
index f32367f3386d1..0147a52814155 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir
@@ -20,21 +20,21 @@ body: |
; FP32-LABEL: name: ceil_f32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32: $f12 = COPY [[COPY]](s32)
- ; FP32: JAL &ceilf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $f0
+ ; FP32: JAL &ceilf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit-def $f0
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $f0 = COPY [[COPY1]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: ceil_f32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64: $f12 = COPY [[COPY]](s32)
- ; FP64: JAL &ceilf, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $f0
+ ; FP64: JAL &ceilf, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit-def $f0
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $f0 = COPY [[COPY1]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = COPY $f12
@@ -54,21 +54,21 @@ body: |
; FP32-LABEL: name: ceil_f64
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32: $d6 = COPY [[COPY]](s64)
- ; FP32: JAL &ceil, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit-def $d0
+ ; FP32: JAL &ceil, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit-def $d0
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $d0 = COPY [[COPY1]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: ceil_f64
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64: $d12_64 = COPY [[COPY]](s64)
- ; FP64: JAL &ceil, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $d12_64, implicit-def $d0_64
+ ; FP64: JAL &ceil, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $d12_64, implicit-def $d0_64
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0_64
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $d0 = COPY [[COPY1]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = COPY $d6
@@ -88,21 +88,21 @@ body: |
; FP32-LABEL: name: floor_f32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32: $f12 = COPY [[COPY]](s32)
- ; FP32: JAL &floorf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $f0
+ ; FP32: JAL &floorf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit-def $f0
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $f0 = COPY [[COPY1]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: floor_f32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64: $f12 = COPY [[COPY]](s32)
- ; FP64: JAL &floorf, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $f0
+ ; FP64: JAL &floorf, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit-def $f0
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $f0 = COPY [[COPY1]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = COPY $f12
@@ -122,21 +122,21 @@ body: |
; FP32-LABEL: name: floor_f64
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32: $d6 = COPY [[COPY]](s64)
- ; FP32: JAL &floor, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit-def $d0
+ ; FP32: JAL &floor, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit-def $d0
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $d0 = COPY [[COPY1]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: floor_f64
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64: $d12_64 = COPY [[COPY]](s64)
- ; FP64: JAL &floor, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $d12_64, implicit-def $d0_64
+ ; FP64: JAL &floor, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $d12_64, implicit-def $d0_64
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0_64
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $d0 = COPY [[COPY1]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = COPY $d6
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
index 6e382cc3801f5..aa31674d23434 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
@@ -6,16 +6,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ctlz_i32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
; MIPS32-NEXT: $r2 = COPY [[CTLZ]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_CTLZ %0(s32)
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -27,13 +27,13 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ctlz_i64
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; MIPS32-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
@@ -44,8 +44,8 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: $r3 = COPY [[C]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_CTLZ %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctpop.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctpop.mir
index 04ae7c91f9f72..69b68deddd0a4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctpop.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctpop.mir
@@ -6,12 +6,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ctpop_i32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
@@ -34,7 +34,7 @@ body: |
; MIPS32-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
; MIPS32-NEXT: $r2 = COPY [[LSHR3]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_CTPOP %0(s32)
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -46,13 +46,13 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ctpop_i64
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
@@ -90,8 +90,8 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[ADD4]](s32)
; MIPS32-NEXT: $r3 = COPY [[C8]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_CTPOP %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
index 87cbe47367c0f..8f6513ddd890d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
@@ -6,12 +6,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: cttz_i32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]
; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]
@@ -21,7 +21,7 @@ body: |
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[CTLZ]]
; MIPS32-NEXT: $r2 = COPY [[SUB]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_CTTZ %0(s32)
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -33,13 +33,13 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: cttz_i64
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@@ -59,8 +59,8 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: $r3 = COPY [[C]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_CTTZ %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
@@ -75,12 +75,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ffs_i32_expansion
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@@ -95,7 +95,7 @@ body: |
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C1]], [[ADD1]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%2:_(s32) = G_CONSTANT i32 1
%4:_(s32) = G_CONSTANT i32 0
%1:_(s32) = G_CTTZ_ZERO_POISON %0(s32)
@@ -112,13 +112,13 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ffs_i64_expansion
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C1]](s32)
@@ -153,8 +153,8 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[UV]](s32)
; MIPS32-NEXT: $r3 = COPY [[UV1]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%4:_(s64) = G_CONSTANT i64 1
%6:_(s64) = G_CONSTANT i64 0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
index 89ae5cbad7f05..04b5cb101fa08 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
@@ -25,12 +25,12 @@ stack:
- { id: 0, name: vla, type: variable-sized, alignment: 1 }
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: Print_c_N_times
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C]]
@@ -39,29 +39,29 @@ body: |
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = nuw G_ADD [[MUL]], [[C2]]
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -8
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C3]]
- ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $sp
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $r29
; MIPS32: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[PTRTOINT]], [[AND]]
; MIPS32: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s32)
- ; MIPS32: $sp = COPY [[INTTOPTR]](p0)
+ ; MIPS32: $r29 = COPY [[INTTOPTR]](p0)
; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY3]](p0)
- ; MIPS32: $a1 = COPY [[COPY]](s32)
- ; MIPS32: $a2 = COPY [[COPY1]](s32)
- ; MIPS32: JAL &memset, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY3]](p0)
+ ; MIPS32: $r5 = COPY [[COPY]](s32)
+ ; MIPS32: $r6 = COPY [[COPY1]](s32)
+ ; MIPS32: JAL &memset, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY3]], [[COPY1]](s32)
; MIPS32: [[COPY4:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; MIPS32: G_STORE [[C1]](s32), [[COPY4]](p0) :: (store (s8) into %ir.arrayidx)
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY3]](p0)
- ; MIPS32: JAL @puts, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY3]](p0)
+ ; MIPS32: JAL @puts, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $r2
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %1:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r5
%3:_(s32) = G_CONSTANT i32 1
%13:_(s8) = G_CONSTANT i8 0
%4:_(s32) = G_ADD %1, %3
@@ -75,10 +75,10 @@ body: |
%11:_(p0) = G_PTR_ADD %10, %1(s32)
%12:_(p0) = COPY %11(p0)
G_STORE %13(s8), %12(p0) :: (store (s8) into %ir.arrayidx)
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %10(p0)
- JAL @puts, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $r2
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %10(p0)
+ JAL @puts, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $r2
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec.mir
index a6a7d8e873c56..8ee7a9a58e398 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec.mir
@@ -12,18 +12,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: fabs_v4f32
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[FABS:%[0-9]+]]:_(<4 x s32>) = G_FABS [[LOAD]]
; P5600: G_STORE [[FABS]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:_(<4 x s32>) = G_FABS %2
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
@@ -36,18 +36,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: fabs_v2f64
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[FABS:%[0-9]+]]:_(<2 x s64>) = G_FABS [[LOAD]]
; P5600: G_STORE [[FABS]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:_(<2 x s64>) = G_FABS %2
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec_builtin.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec_builtin.mir
index f8cc8298fb70b..612a4a30a1305 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec_builtin.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec_builtin.mir
@@ -15,18 +15,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: fabs_v4f32_builtin
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[FMAX_A_W:%[0-9]+]]:msa128w(<4 x s32>) = FMAX_A_W [[LOAD]](<4 x s32>), [[LOAD]](<4 x s32>)
; P5600: G_STORE [[FMAX_A_W]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fmax.a.w), %2(<4 x s32>), %2(<4 x s32>)
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
@@ -39,18 +39,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: fabs_v2f64_builtin
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128d(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[FMAX_A_D:%[0-9]+]]:msa128d(<2 x s64>) = FMAX_A_D [[LOAD]](<2 x s64>), [[LOAD]](<2 x s64>)
; P5600: G_STORE [[FMAX_A_D]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fmax.a.d), %2(<2 x s64>), %2(<2 x s64>)
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
index 5e38867ad0e33..6b247ff737f12 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
@@ -11,16 +11,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: atomic_load_i32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic (s32) from %ir.ptr)
; MIPS32: G_FENCE 4, 1
; MIPS32: $r2 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load monotonic (s32) from %ir.ptr)
G_FENCE 4, 1
$r2 = COPY %1(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations.mir
index ddc5f34245232..fabe9843b4b6c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations.mir
@@ -21,21 +21,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fadd_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_FADD %3, %4
@@ -49,21 +49,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fadd_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_FADD %3, %4
@@ -77,21 +77,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fsub_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FSUB:%[0-9]+]]:_(<4 x s32>) = G_FSUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FSUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_FSUB %3, %4
@@ -105,21 +105,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fsub_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FSUB:%[0-9]+]]:_(<2 x s64>) = G_FSUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FSUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_FSUB %3, %4
@@ -133,21 +133,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fmul_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FMUL:%[0-9]+]]:_(<4 x s32>) = G_FMUL [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FMUL]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_FMUL %3, %4
@@ -161,21 +161,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fmul_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FMUL:%[0-9]+]]:_(<2 x s64>) = G_FMUL [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FMUL]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_FMUL %3, %4
@@ -189,21 +189,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fdiv_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FDIV:%[0-9]+]]:_(<4 x s32>) = G_FDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_FDIV %3, %4
@@ -217,21 +217,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fdiv_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FDIV:%[0-9]+]]:_(<2 x s64>) = G_FDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_FDIV %3, %4
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations_builtin.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations_builtin.mir
index 252584abcc2ea..a6c37cbda8845 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations_builtin.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations_builtin.mir
@@ -33,21 +33,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fadd_v4f32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fadd.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -61,21 +61,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fadd_v2f64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fadd.d), %3(<2 x s64>), %4(<2 x s64>)
@@ -89,21 +89,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fsub_v4f32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FSUB:%[0-9]+]]:_(<4 x s32>) = G_FSUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FSUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fsub.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -117,21 +117,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fsub_v2f64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FSUB:%[0-9]+]]:_(<2 x s64>) = G_FSUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FSUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fsub.d), %3(<2 x s64>), %4(<2 x s64>)
@@ -145,21 +145,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fmul_v4f32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FMUL:%[0-9]+]]:_(<4 x s32>) = G_FMUL [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FMUL]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fmul.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -173,21 +173,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fmul_v2f64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FMUL:%[0-9]+]]:_(<2 x s64>) = G_FMUL [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FMUL]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fmul.d), %3(<2 x s64>), %4(<2 x s64>)
@@ -201,21 +201,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fdiv_v4f32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FDIV:%[0-9]+]]:_(<4 x s32>) = G_FDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fdiv.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -229,21 +229,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fdiv_v2f64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FDIV:%[0-9]+]]:_(<2 x s64>) = G_FDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fdiv.d), %3(<2 x s64>), %4(<2 x s64>)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
index 627f58bc304f7..6f40d3cb084bc 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
@@ -33,12 +33,12 @@ body: |
; FP32: liveins: $f12
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP32-NEXT: JAL &__fixsfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $r2, implicit-def $r3
+ ; FP32-NEXT: JAL &__fixsfdi, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit-def $r2, implicit-def $r3
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $r2 = COPY [[COPY1]](s32)
; FP32-NEXT: $r3 = COPY [[COPY2]](s32)
; FP32-NEXT: RetRA implicit $r2, implicit $r3
@@ -47,12 +47,12 @@ body: |
; FP64: liveins: $f12
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP64-NEXT: JAL &__fixsfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $r2, implicit-def $r3
+ ; FP64-NEXT: JAL &__fixsfdi, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit-def $r2, implicit-def $r3
; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $r2 = COPY [[COPY1]](s32)
; FP64-NEXT: $r3 = COPY [[COPY2]](s32)
; FP64-NEXT: RetRA implicit $r2, implicit $r3
@@ -177,12 +177,12 @@ body: |
; FP32: liveins: $d6
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $d6 = COPY [[COPY]](s64)
- ; FP32-NEXT: JAL &__fixdfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit-def $r2, implicit-def $r3
+ ; FP32-NEXT: JAL &__fixdfdi, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit-def $r2, implicit-def $r3
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $r2 = COPY [[COPY1]](s32)
; FP32-NEXT: $r3 = COPY [[COPY2]](s32)
; FP32-NEXT: RetRA implicit $r2, implicit $r3
@@ -191,12 +191,12 @@ body: |
; FP64: liveins: $d6
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $d12_64 = COPY [[COPY]](s64)
- ; FP64-NEXT: JAL &__fixdfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $d12_64, implicit-def $r2, implicit-def $r3
+ ; FP64-NEXT: JAL &__fixdfdi, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $d12_64, implicit-def $r2, implicit-def $r3
; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $r2 = COPY [[COPY1]](s32)
; FP64-NEXT: $r3 = COPY [[COPY2]](s32)
; FP64-NEXT: RetRA implicit $r2, implicit $r3
@@ -321,12 +321,12 @@ body: |
; FP32: liveins: $f12
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP32-NEXT: JAL &__fixunssfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $r2, implicit-def $r3
+ ; FP32-NEXT: JAL &__fixunssfdi, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit-def $r2, implicit-def $r3
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $r2 = COPY [[COPY1]](s32)
; FP32-NEXT: $r3 = COPY [[COPY2]](s32)
; FP32-NEXT: RetRA implicit $r2, implicit $r3
@@ -335,12 +335,12 @@ body: |
; FP64: liveins: $f12
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP64-NEXT: JAL &__fixunssfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit-def $r2, implicit-def $r3
+ ; FP64-NEXT: JAL &__fixunssfdi, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit-def $r2, implicit-def $r3
; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $r2 = COPY [[COPY1]](s32)
; FP64-NEXT: $r3 = COPY [[COPY2]](s32)
; FP64-NEXT: RetRA implicit $r2, implicit $r3
@@ -503,12 +503,12 @@ body: |
; FP32: liveins: $d6
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $d6 = COPY [[COPY]](s64)
- ; FP32-NEXT: JAL &__fixunsdfdi, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit-def $r2, implicit-def $r3
+ ; FP32-NEXT: JAL &__fixunsdfdi, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit-def $r2, implicit-def $r3
; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32-NEXT: $r2 = COPY [[COPY1]](s32)
; FP32-NEXT: $r3 = COPY [[COPY2]](s32)
; FP32-NEXT: RetRA implicit $r2, implicit $r3
@@ -517,12 +517,12 @@ body: |
; FP64: liveins: $d6
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $d12_64 = COPY [[COPY]](s64)
- ; FP64-NEXT: JAL &__fixunsdfdi, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $d12_64, implicit-def $r2, implicit-def $r3
+ ; FP64-NEXT: JAL &__fixunsdfdi, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $d12_64, implicit-def $r2, implicit-def $r3
; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64-NEXT: $r2 = COPY [[COPY1]](s32)
; FP64-NEXT: $r3 = COPY [[COPY2]](s32)
; FP64-NEXT: RetRA implicit $r2, implicit $r3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec.mir
index cae3ab4fc875b..e313cbf1cb642 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec.mir
@@ -12,18 +12,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: sqrt_v4f32
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[FSQRT:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[LOAD]]
; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:_(<4 x s32>) = G_FSQRT %2
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
@@ -36,18 +36,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: sqrt_v2f64
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[FSQRT:%[0-9]+]]:_(<2 x s64>) = G_FSQRT [[LOAD]]
; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:_(<2 x s64>) = G_FSQRT %2
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec_builtin.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec_builtin.mir
index eeb1a9484ba96..6cffab5c8562c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec_builtin.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec_builtin.mir
@@ -15,18 +15,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: fsqrt_v4f32_builtin
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[FSQRT:%[0-9]+]]:_(<4 x s32>) = G_FSQRT [[LOAD]]
; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.fsqrt.w), %2(<4 x s32>)
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
@@ -39,18 +39,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: fsqrt_v2f64_builtin
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[FSQRT:%[0-9]+]]:_(<2 x s64>) = G_FSQRT [[LOAD]]
; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.fsqrt.d), %2(<2 x s64>)
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir
index cf95cc19badf5..6273788c1620f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir
@@ -19,24 +19,24 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY [[GV]](p0)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1234567890
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY]](p0)
- ; MIPS32: $a1 = COPY [[C]](s32)
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY]](p0)
+ ; MIPS32: $r5 = COPY [[C]](s32)
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[C1]](s32)
; MIPS32: RetRA implicit $r2
%2:_(p0) = G_GLOBAL_VALUE @.str
%1:_(p0) = COPY %2(p0)
%3:_(s32) = G_CONSTANT i32 1234567890
%4:_(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %1(p0)
- $a1 = COPY %3(s32)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %1(p0)
+ $r5 = COPY %3(s32)
+ JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
%0:_(s32) = COPY $r2
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$r2 = COPY %4(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
index abe5cceef848c..72429f10bbdef 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
@@ -24,18 +24,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ne_i32
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s1) = G_ICMP intpred(ne), %0(s32), %1
%3:_(s32) = G_ANYEXT %2(s1)
$r2 = COPY %3(s32)
@@ -48,18 +48,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: eq_ptr
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s1) = G_ICMP intpred(eq), %0(p0), %1
%3:_(s32) = G_ANYEXT %2(s1)
$r2 = COPY %3(s32)
@@ -72,22 +72,22 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ult_i8
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s1) = G_ICMP intpred(ult), %0(s8), %1
%5:_(s32) = G_ANYEXT %4(s1)
@@ -101,13 +101,13 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: slt_i16
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
@@ -116,9 +116,9 @@ body: |
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s1) = G_ICMP intpred(slt), %0(s16), %1
%5:_(s32) = G_ANYEXT %4(s1)
@@ -132,15 +132,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: eq_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]]
; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
@@ -148,11 +148,11 @@ body: |
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(eq), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
@@ -166,15 +166,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: ne_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]]
; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
@@ -182,11 +182,11 @@ body: |
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C]]
; MIPS32-NEXT: $r2 = COPY [[ICMP]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(ne), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
@@ -200,26 +200,26 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: sgt_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
@@ -233,26 +233,26 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: sge_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(sge), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
@@ -266,26 +266,26 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: slt_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(slt), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
@@ -299,26 +299,26 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: sle_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(sle), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
@@ -332,26 +332,26 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: ugt_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(ugt), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
@@ -365,26 +365,26 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: uge_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(uge), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
@@ -398,26 +398,26 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: ult_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(ult), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
@@ -431,26 +431,26 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: ule_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s1) = G_ICMP intpred(ule), %0(s64), %1
%7:_(s32) = G_ANYEXT %6(s1)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/implicit_def.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/implicit_def.mir
index 78fbf23c8c08a..c07e3ae353ce0 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/implicit_def.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/implicit_def.mir
@@ -23,16 +23,16 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: g_i32
; MIPS32: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32-NEXT: $a0 = COPY [[DEF]](s32)
- ; MIPS32-NEXT: JAL @f_i32, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32-NEXT: $r4 = COPY [[DEF]](s32)
+ ; MIPS32-NEXT: JAL @f_i32, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: RetRA
%0:_(s32) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %0(s32)
- JAL @f_i32, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %0(s32)
+ JAL @f_i32, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
@@ -44,19 +44,19 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: g_i64
; MIPS32: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32-NEXT: $a0 = COPY [[DEF]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[DEF]](s32)
- ; MIPS32-NEXT: JAL @f_i64, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32-NEXT: $r4 = COPY [[DEF]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[DEF]](s32)
+ ; MIPS32-NEXT: JAL @f_i64, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: RetRA
%0:_(s64) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64)
- $a0 = COPY %1(s32)
- $a1 = COPY %2(s32)
- JAL @f_i64, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ $r4 = COPY %1(s32)
+ $r5 = COPY %2(s32)
+ JAL @f_i64, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
@@ -68,16 +68,16 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: g_float
; MIPS32: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: $f12 = COPY [[DEF]](s32)
- ; MIPS32-NEXT: JAL @f_float, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: JAL @f_float, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: RetRA
%0:_(s32) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
$f12 = COPY %0(s32)
- JAL @f_float, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ JAL @f_float, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
@@ -89,16 +89,16 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: g_double
; MIPS32: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: $d6 = COPY [[DEF]](s64)
- ; MIPS32-NEXT: JAL @f_double, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32-NEXT: JAL @f_double, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32-NEXT: RetRA
%0:_(s64) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
$d6 = COPY %0(s64)
- JAL @f_double, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ JAL @f_double, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir
index d0c12814d6c4f..fbafdf1af95f4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir
@@ -12,15 +12,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: inttoptr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s32)
; MIPS32: $r2 = COPY [[INTTOPTR]](p0)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(p0) = G_INTTOPTR %0(s32)
$r2 = COPY %1(p0)
RetRA implicit $r2
@@ -32,15 +32,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ptrtoint
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
; MIPS32: $r2 = COPY [[PTRTOINT]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_PTRTOINT %0(p0)
$r2 = COPY %1(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
index 8285b2408644a..f347b87cc619b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
@@ -71,9 +71,9 @@ body: |
; MIPS32-LABEL: name: mod4_0_to_11
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; MIPS32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
@@ -148,9 +148,9 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[C5]](s32)
; MIPS32-NEXT: RetRA implicit $r2
bb.1.entry:
- liveins: $a0
+ liveins: $r4
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%4:_(s32) = G_CONSTANT i32 7
%8:_(s32) = G_CONSTANT i32 3
%9:_(s32) = G_CONSTANT i32 2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
index c9dfb19e0e07e..ed87c4d2d531c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
@@ -6,16 +6,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load_i32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load (s32))
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -27,18 +27,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load_i64
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
; MIPS32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
; MIPS32-NEXT: $r2 = COPY [[UV]](s32)
; MIPS32-NEXT: $r3 = COPY [[UV1]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s64) = G_LOAD %0(p0) :: (load (s64))
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$r2 = COPY %2(s32)
@@ -52,16 +52,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load_float
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; MIPS32-NEXT: $f0 = COPY [[LOAD]](s32)
; MIPS32-NEXT: RetRA implicit $f0
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load (s32))
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -73,16 +73,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load_double
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
; MIPS32-NEXT: $d0 = COPY [[LOAD]](s64)
; MIPS32-NEXT: RetRA implicit $d0
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s64) = G_LOAD %0(p0) :: (load (s64))
$d0 = COPY %1(s64)
RetRA implicit $d0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
index 636bf35f44c23..26ddf051c47b7 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
@@ -6,18 +6,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v16i8
- ; P5600: liveins: $a0, $a1
+ ; P5600: liveins: $r4, $r5
; P5600-NEXT: {{ $}}
- ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>))
; P5600-NEXT: G_STORE [[LOAD]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>))
; P5600-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>))
G_STORE %2(<16 x s8>), %0(p0) :: (store (<16 x s8>))
RetRA
@@ -29,18 +29,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v8i16
- ; P5600: liveins: $a0, $a1
+ ; P5600: liveins: $r4, $r5
; P5600-NEXT: {{ $}}
- ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>))
; P5600-NEXT: G_STORE [[LOAD]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>))
; P5600-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>))
G_STORE %2(<8 x s16>), %0(p0) :: (store (<8 x s16>))
RetRA
@@ -52,18 +52,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v4i32
- ; P5600: liveins: $a0, $a1
+ ; P5600: liveins: $r4, $r5
; P5600-NEXT: {{ $}}
- ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>))
; P5600-NEXT: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>))
; P5600-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>))
G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>))
RetRA
@@ -75,18 +75,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v2i64
- ; P5600: liveins: $a0, $a1
+ ; P5600: liveins: $r4, $r5
; P5600-NEXT: {{ $}}
- ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>))
; P5600-NEXT: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
; P5600-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>))
G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>))
RetRA
@@ -98,18 +98,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v4f32
- ; P5600: liveins: $a0, $a1
+ ; P5600: liveins: $r4, $r5
; P5600-NEXT: {{ $}}
- ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>))
; P5600-NEXT: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>))
; P5600-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>))
G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>))
RetRA
@@ -121,18 +121,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v2f64
- ; P5600: liveins: $a0, $a1
+ ; P5600: liveins: $r4, $r5
; P5600-NEXT: {{ $}}
- ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>))
; P5600-NEXT: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
; P5600-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>))
G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>))
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
index 79709c734145b..88d3361f06388 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
@@ -21,18 +21,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: mul_i32
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
; MIPS32-NEXT: $r2 = COPY [[MUL]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_MUL %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -44,22 +44,22 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: mul_i8_sext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_MUL %1, %0
%5:_(s32) = G_SEXT %4(s8)
@@ -73,21 +73,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: mul_i8_zext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_MUL %1, %0
%5:_(s32) = G_ZEXT %4(s8)
@@ -101,19 +101,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: mul_i8_aext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[MUL]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_MUL %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
@@ -127,22 +127,22 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: mul_i16_sext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_MUL %1, %0
%5:_(s32) = G_SEXT %4(s16)
@@ -156,21 +156,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: mul_i16_zext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_MUL %1, %0
%5:_(s32) = G_ZEXT %4(s16)
@@ -184,19 +184,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: mul_i16_aext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[MUL]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_MUL %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
@@ -210,15 +210,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: mul_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
@@ -228,11 +228,11 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[MUL]](s32)
; MIPS32-NEXT: $r3 = COPY [[ADD1]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_MUL %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -252,15 +252,15 @@ fixedStack:
- { id: 3, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: mul_i128
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -320,13 +320,13 @@ body: |
; MIPS32-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[ADD11]]
; MIPS32-NEXT: $r2 = COPY [[MUL]](s32)
; MIPS32-NEXT: $r3 = COPY [[COPY5]](s32)
- ; MIPS32-NEXT: $a0 = COPY [[COPY10]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[ADD18]](s32)
- ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ ; MIPS32-NEXT: $r4 = COPY [[COPY10]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[ADD18]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3, implicit $r4, implicit $r5
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
%10:_(p0) = G_FRAME_INDEX %fixed-stack.3
%6:_(s32) = G_LOAD %10(p0) :: (load (s32) from %fixed-stack.3, align 8)
@@ -341,9 +341,9 @@ body: |
%15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
$r2 = COPY %15(s32)
$r3 = COPY %16(s32)
- $a0 = COPY %17(s32)
- $a1 = COPY %18(s32)
- RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
+ $r4 = COPY %17(s32)
+ $r5 = COPY %18(s32)
+ RetRA implicit $r2, implicit $r3, implicit $r4, implicit $r5
...
---
@@ -352,15 +352,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: umulh_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
; MIPS32-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY]]
@@ -390,11 +390,11 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[COPY8]](s32)
; MIPS32-NEXT: $r3 = COPY [[ADD8]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_UMULH %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -409,15 +409,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: umul_with_overflow
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $r7
; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
@@ -427,10 +427,10 @@ body: |
; MIPS32-NEXT: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
; MIPS32-NEXT: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store (s32) into %ir.pmul)
; MIPS32-NEXT: RetRA
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(p0) = COPY $a2
- %3:_(p0) = COPY $a3
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(p0) = COPY $r6
+ %3:_(p0) = COPY $r7
%4:_(s32), %5:_(s1) = G_UMULO %0, %1
G_STORE %5(s1), %3(p0) :: (store (s1) into %ir.pcarry_flag)
G_STORE %4(s32), %2(p0) :: (store (s32) into %ir.pmul)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
index d61656b470fb0..37416d50d42d8 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
@@ -14,21 +14,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[MUL]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_MUL %4, %3
@@ -42,21 +42,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[MUL]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_MUL %4, %3
@@ -70,21 +70,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[MUL]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_MUL %4, %3
@@ -98,21 +98,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[MUL]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_MUL %4, %3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
index 65d2b075fad2a..0f78e69b84dc0 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
@@ -21,21 +21,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v16i8_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[MUL]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.b), %3(<16 x s8>), %4(<16 x s8>)
@@ -49,21 +49,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v8i16_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[MUL]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.h), %3(<8 x s16>), %4(<8 x s16>)
@@ -77,21 +77,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v4i32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[MUL]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -105,21 +105,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v2i64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[MUL]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.d), %3(<2 x s64>), %4(<2 x s64>)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
index 82f740dce7897..ed180adfc1c53 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
@@ -152,10 +152,10 @@ body: |
; MIPS32-LABEL: name: phi_i1
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
@@ -170,13 +170,13 @@ body: |
; MIPS32: $r2 = COPY [[PHI]](s32)
; MIPS32: RetRA implicit $r2
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %4:_(s32) = COPY $a1
+ %4:_(s32) = COPY $r5
%1:_(s1) = G_TRUNC %4(s32)
- %5:_(s32) = COPY $a2
+ %5:_(s32) = COPY $r6
%2:_(s1) = G_TRUNC %5(s32)
G_BRCOND %0(s1), %bb.2
G_BR %bb.3
@@ -201,10 +201,10 @@ body: |
; MIPS32-LABEL: name: phi_i8
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
@@ -219,13 +219,13 @@ body: |
; MIPS32: $r2 = COPY [[PHI]](s32)
; MIPS32: RetRA implicit $r2
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %4:_(s32) = COPY $a1
+ %4:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %4(s32)
- %5:_(s32) = COPY $a2
+ %5:_(s32) = COPY $r6
%2:_(s8) = G_TRUNC %5(s32)
G_BRCOND %0(s1), %bb.2
G_BR %bb.3
@@ -250,10 +250,10 @@ body: |
; MIPS32-LABEL: name: phi_i16
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
@@ -268,13 +268,13 @@ body: |
; MIPS32: $r2 = COPY [[PHI]](s32)
; MIPS32: RetRA implicit $r2
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %4:_(s32) = COPY $a1
+ %4:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %4(s32)
- %5:_(s32) = COPY $a2
+ %5:_(s32) = COPY $r6
%2:_(s16) = G_TRUNC %5(s32)
G_BRCOND %0(s1), %bb.2
G_BR %bb.3
@@ -299,10 +299,10 @@ body: |
; MIPS32-LABEL: name: phi_i32
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
@@ -317,12 +317,12 @@ body: |
; MIPS32: $r2 = COPY [[PHI]](s32)
; MIPS32: RetRA implicit $r2
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
G_BRCOND %0(s1), %bb.2
G_BR %bb.3
@@ -348,10 +348,10 @@ body: |
; MIPS32-LABEL: name: phi_i64
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
@@ -374,12 +374,12 @@ body: |
; MIPS32: $r3 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%8:_(p0) = G_FRAME_INDEX %fixed-stack.1
%6:_(s32) = G_LOAD %8(p0) :: (load (s32) from %fixed-stack.1, align 8)
@@ -410,11 +410,11 @@ body: |
; MIPS32-LABEL: name: phi_ambiguous_i64_in_fpr
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $r7
; MIPS32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY1]](p0) :: (load (s64) from %ir.i64_ptr_a)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[COPY2]](p0) :: (load (s64) from %ir.i64_ptr_b)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -431,13 +431,13 @@ body: |
; MIPS32: G_STORE [[PHI]](s64), [[COPY3]](p0) :: (store (s64) into %ir.i64_ptr_c)
; MIPS32: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %4:_(s32) = COPY $a0
+ %4:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %4(s32)
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
- %3:_(p0) = COPY $a3
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
+ %3:_(p0) = COPY $r7
%5:_(s64) = G_LOAD %1(p0) :: (load (s64) from %ir.i64_ptr_a)
%6:_(s64) = G_LOAD %2(p0) :: (load (s64) from %ir.i64_ptr_b)
G_BRCOND %0(s1), %bb.2
@@ -462,10 +462,10 @@ body: |
; MIPS32-LABEL: name: phi_float
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
@@ -480,12 +480,12 @@ body: |
; MIPS32: $f0 = COPY [[PHI]](s32)
; MIPS32: RetRA implicit $f0
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
G_BRCOND %0(s1), %bb.2
G_BR %bb.3
@@ -508,11 +508,11 @@ body: |
; MIPS32-LABEL: name: phi_ambiguous_float_in_gpr
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $r7
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.f32_ptr_a)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.f32_ptr_b)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -529,13 +529,13 @@ body: |
; MIPS32: G_STORE [[PHI]](s32), [[COPY3]](p0) :: (store (s32) into %ir.f32_ptr_c)
; MIPS32: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %4:_(s32) = COPY $a0
+ %4:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %4(s32)
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
- %3:_(p0) = COPY $a3
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
+ %3:_(p0) = COPY $r7
%5:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.f32_ptr_a)
%6:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.f32_ptr_b)
G_BRCOND %0(s1), %bb.2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
index d4f2f76df7d3f..8be0b6f0b2906 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
@@ -13,15 +13,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ptr_arg_in_regs
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.p)
; MIPS32: $r2 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.p)
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -35,23 +35,23 @@ fixedStack:
- { id: 0, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: ptr_arg_on_stack
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.p)
; MIPS32: $r2 = COPY [[LOAD1]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%5:_(p0) = G_FRAME_INDEX %fixed-stack.0
%4:_(p0) = G_LOAD %5(p0) :: (load (p0) from %fixed-stack.0, align 4)
%6:_(s32) = G_LOAD %4(p0) :: (load (s32) from %ir.p)
@@ -65,14 +65,14 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ret_ptr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: $r2 = COPY [[COPY]](p0)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
$r2 = COPY %0(p0)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
index 36014a04a534b..0de491334b76c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
@@ -26,12 +26,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sdiv_i8
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
@@ -42,9 +42,9 @@ body: |
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $r2 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SDIV %1, %0
%5:_(s32) = G_SEXT %4(s8)
@@ -58,12 +58,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sdiv_i16
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
@@ -74,9 +74,9 @@ body: |
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $r2 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SDIV %1, %0
%5:_(s32) = G_SEXT %4(s16)
@@ -90,17 +90,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sdiv_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[SDIV]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_SDIV %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -112,31 +112,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: sdiv_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY2]](s32)
- ; MIPS32: $a1 = COPY [[COPY3]](s32)
- ; MIPS32: $a2 = COPY [[COPY]](s32)
- ; MIPS32: $a3 = COPY [[COPY1]](s32)
- ; MIPS32: JAL &__divdi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2, implicit-def $r3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY2]](s32)
+ ; MIPS32: $r5 = COPY [[COPY3]](s32)
+ ; MIPS32: $r6 = COPY [[COPY]](s32)
+ ; MIPS32: $r7 = COPY [[COPY1]](s32)
+ ; MIPS32: JAL &__divdi3, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2, implicit-def $r3
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $r3
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY4]](s32)
; MIPS32: $r3 = COPY [[COPY5]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_SDIV %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -151,12 +151,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: srem_i8
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
@@ -165,9 +165,9 @@ body: |
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; MIPS32: $r2 = COPY [[SREM]](s32)
; MIPS32: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SREM %1, %0
%5:_(s32) = G_SEXT %4(s8)
@@ -181,12 +181,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: srem_i16
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
@@ -195,9 +195,9 @@ body: |
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; MIPS32: $r2 = COPY [[SREM]](s32)
; MIPS32: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SREM %1, %0
%5:_(s32) = G_SEXT %4(s16)
@@ -211,17 +211,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: srem_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[SREM]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_SREM %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -233,31 +233,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: srem_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY2]](s32)
- ; MIPS32: $a1 = COPY [[COPY3]](s32)
- ; MIPS32: $a2 = COPY [[COPY]](s32)
- ; MIPS32: $a3 = COPY [[COPY1]](s32)
- ; MIPS32: JAL &__moddi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2, implicit-def $r3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY2]](s32)
+ ; MIPS32: $r5 = COPY [[COPY3]](s32)
+ ; MIPS32: $r6 = COPY [[COPY]](s32)
+ ; MIPS32: $r7 = COPY [[COPY1]](s32)
+ ; MIPS32: JAL &__moddi3, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2, implicit-def $r3
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $r3
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY4]](s32)
; MIPS32: $r3 = COPY [[COPY5]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_SREM %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -272,12 +272,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: udiv_i8
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
@@ -287,9 +287,9 @@ body: |
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $r2 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_UDIV %1, %0
%5:_(s32) = G_SEXT %4(s8)
@@ -303,12 +303,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: udiv_i16
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
@@ -318,9 +318,9 @@ body: |
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $r2 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_UDIV %1, %0
%5:_(s32) = G_SEXT %4(s16)
@@ -334,17 +334,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: udiv_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[UDIV]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_UDIV %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -356,31 +356,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: udiv_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY2]](s32)
- ; MIPS32: $a1 = COPY [[COPY3]](s32)
- ; MIPS32: $a2 = COPY [[COPY]](s32)
- ; MIPS32: $a3 = COPY [[COPY1]](s32)
- ; MIPS32: JAL &__udivdi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2, implicit-def $r3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY2]](s32)
+ ; MIPS32: $r5 = COPY [[COPY3]](s32)
+ ; MIPS32: $r6 = COPY [[COPY]](s32)
+ ; MIPS32: $r7 = COPY [[COPY1]](s32)
+ ; MIPS32: JAL &__udivdi3, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2, implicit-def $r3
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $r3
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY4]](s32)
; MIPS32: $r3 = COPY [[COPY5]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_UDIV %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -395,12 +395,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: urem_i8
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
@@ -410,9 +410,9 @@ body: |
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $r2 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_UREM %1, %0
%5:_(s32) = G_SEXT %4(s8)
@@ -426,12 +426,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: urem_i16
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
@@ -441,9 +441,9 @@ body: |
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $r2 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_UREM %1, %0
%5:_(s32) = G_SEXT %4(s16)
@@ -457,17 +457,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: urem_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[UREM]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_UREM %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -479,31 +479,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: urem_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY2]](s32)
- ; MIPS32: $a1 = COPY [[COPY3]](s32)
- ; MIPS32: $a2 = COPY [[COPY]](s32)
- ; MIPS32: $a3 = COPY [[COPY1]](s32)
- ; MIPS32: JAL &__umoddi3, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2, implicit-def $r3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY2]](s32)
+ ; MIPS32: $r5 = COPY [[COPY3]](s32)
+ ; MIPS32: $r6 = COPY [[COPY]](s32)
+ ; MIPS32: $r7 = COPY [[COPY1]](s32)
+ ; MIPS32: JAL &__umoddi3, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2, implicit-def $r3
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $r2
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $r3
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY4]](s32)
; MIPS32: $r3 = COPY [[COPY5]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_UREM %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec.mir
index 7d58e1ad132b4..b1c4a1ccd8b2e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec.mir
@@ -29,21 +29,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_SDIV %3, %4
@@ -57,21 +57,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<8 x s16>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_SDIV %3, %4
@@ -85,21 +85,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<4 x s32>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_SDIV %3, %4
@@ -113,21 +113,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<2 x s64>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_SDIV %3, %4
@@ -141,21 +141,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_SREM %3, %4
@@ -169,21 +169,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_SREM %3, %4
@@ -197,21 +197,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_SREM %3, %4
@@ -225,21 +225,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_SREM %3, %4
@@ -253,21 +253,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v16u8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<16 x s8>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_UDIV %3, %4
@@ -281,21 +281,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v8u16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<8 x s16>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_UDIV %3, %4
@@ -309,21 +309,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v4u32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<4 x s32>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_UDIV %3, %4
@@ -337,21 +337,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v2u64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<2 x s64>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_UDIV %3, %4
@@ -365,21 +365,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v16u8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_UREM %3, %4
@@ -393,21 +393,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v8u16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_UREM %3, %4
@@ -421,21 +421,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v4u32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_UREM %3, %4
@@ -449,21 +449,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v2u64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_UREM %3, %4
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec_builtin.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec_builtin.mir
index 7d7749bd5de9c..f84ef88389e67 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec_builtin.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec_builtin.mir
@@ -57,21 +57,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v16i8_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.b), %3(<16 x s8>), %4(<16 x s8>)
@@ -85,21 +85,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v8i16_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<8 x s16>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.h), %3(<8 x s16>), %4(<8 x s16>)
@@ -113,21 +113,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v4i32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<4 x s32>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -141,21 +141,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v2i64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<2 x s64>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.d), %3(<2 x s64>), %4(<2 x s64>)
@@ -169,21 +169,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: smod_v16i8_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.b), %3(<16 x s8>), %4(<16 x s8>)
@@ -197,21 +197,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: smod_v8i16_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.h), %3(<8 x s16>), %4(<8 x s16>)
@@ -225,21 +225,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: smod_v4i32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -253,21 +253,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: smod_v2i64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.d), %3(<2 x s64>), %4(<2 x s64>)
@@ -281,21 +281,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v16i8_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<16 x s8>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.b), %3(<16 x s8>), %4(<16 x s8>)
@@ -309,21 +309,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v8i16_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<8 x s16>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.h), %3(<8 x s16>), %4(<8 x s16>)
@@ -337,21 +337,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v4i32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<4 x s32>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -365,21 +365,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v2i64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<2 x s64>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.d), %3(<2 x s64>), %4(<2 x s64>)
@@ -393,21 +393,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: umod_v16i8_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.b), %3(<16 x s8>), %4(<16 x s8>)
@@ -421,21 +421,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: umod_v8i16_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.h), %3(<8 x s16>), %4(<8 x s16>)
@@ -449,21 +449,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: umod_v4i32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -477,21 +477,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: umod_v2i64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.d), %3(<2 x s64>), %4(<2 x s64>)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
index 28b12f586b214..e608d4b154e7e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
@@ -18,24 +18,24 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: select_i8
- ; MIPS32: liveins: $a0, $a1, $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %4:_(s32) = COPY $a1
+ %4:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %4(s32)
- %5:_(s32) = COPY $a2
+ %5:_(s32) = COPY $r6
%2:_(s8) = G_TRUNC %5(s32)
%6:_(s8) = G_SELECT %0(s1), %1, %2
%7:_(s32) = G_ANYEXT %6(s8)
@@ -49,24 +49,24 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: select_i16
- ; MIPS32: liveins: $a0, $a1, $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %4:_(s32) = COPY $a1
+ %4:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %4(s32)
- %5:_(s32) = COPY $a2
+ %5:_(s32) = COPY $r6
%2:_(s16) = G_TRUNC %5(s32)
%6:_(s16) = G_SELECT %0(s1), %1, %2
%7:_(s32) = G_ANYEXT %6(s16)
@@ -80,23 +80,23 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: select_i32
- ; MIPS32: liveins: $a0, $a1, $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
%4:_(s32) = G_SELECT %0(s1), %1, %2
$r2 = COPY %4(s32)
RetRA implicit $r2
@@ -108,23 +108,23 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: select_ptr
- ; MIPS32: liveins: $a0, $a1, $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](p0)
; MIPS32-NEXT: RetRA implicit $r2
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%4:_(p0) = G_SELECT %0(s1), %1, %2
$r2 = COPY %4(p0)
RetRA implicit $r2
@@ -136,25 +136,25 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: select_with_negation
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[COPY2]], [[COPY3]]
; MIPS32-NEXT: $r2 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%5:_(s1) = G_CONSTANT i1 true
%4:_(s1) = G_ICMP intpred(slt), %0(s32), %1
%6:_(s1) = G_XOR %4, %5
@@ -172,14 +172,14 @@ fixedStack:
- { id: 1, offset: 16, size: 4, alignment: 8, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: select_i64
- ; MIPS32: liveins: $a0, $a2, $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
@@ -193,10 +193,10 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[UV]](s32)
; MIPS32-NEXT: $r3 = COPY [[UV1]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%8:_(p0) = G_FRAME_INDEX %fixed-stack.1
%6:_(s32) = G_LOAD %8(p0) :: (load (s32) from %fixed-stack.1, align 8)
@@ -216,23 +216,23 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: select_float
- ; MIPS32: liveins: $a0, $a1, $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32-NEXT: $f0 = COPY [[SELECT]](s32)
; MIPS32-NEXT: RetRA implicit $f0
- %3:_(s32) = COPY $a0
+ %3:_(s32) = COPY $r4
%0:_(s1) = G_TRUNC %3(s32)
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
%4:_(s32) = G_SELECT %0(s1), %1, %2
$f0 = COPY %4(s32)
RetRA implicit $f0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
index 561a33267bcd0..de4c34f1b813a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
@@ -27,34 +27,34 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; FP32-LABEL: name: i64tof32
- ; FP32: liveins: $a0, $a1
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32: $a0 = COPY [[COPY]](s32)
- ; FP32: $a1 = COPY [[COPY1]](s32)
- ; FP32: JAL &__floatdisf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
+ ; FP32: liveins: $r4, $r5
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP32: $r4 = COPY [[COPY]](s32)
+ ; FP32: $r5 = COPY [[COPY1]](s32)
+ ; FP32: JAL &__floatdisf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $f0
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $f0 = COPY [[COPY2]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: i64tof32
- ; FP64: liveins: $a0, $a1
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64: $a0 = COPY [[COPY]](s32)
- ; FP64: $a1 = COPY [[COPY1]](s32)
- ; FP64: JAL &__floatdisf, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
+ ; FP64: liveins: $r4, $r5
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP64: $r4 = COPY [[COPY]](s32)
+ ; FP64: $r5 = COPY [[COPY1]](s32)
+ ; FP64: JAL &__floatdisf, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $f0
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $f0 = COPY [[COPY2]](s32)
; FP64: RetRA implicit $f0
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s32) = G_SITOFP %0(s64)
$f0 = COPY %3(s32)
@@ -67,21 +67,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: i32tof32
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
; FP32: $f0 = COPY [[SITOFP]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: i32tof32
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
; FP64: $f0 = COPY [[SITOFP]](s32)
; FP64: RetRA implicit $f0
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_SITOFP %0(s32)
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -93,11 +93,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: i16tof32
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
@@ -105,15 +105,15 @@ body: |
; FP32: $f0 = COPY [[SITOFP]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: i16tof32
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; FP64: $f0 = COPY [[SITOFP]](s32)
; FP64: RetRA implicit $f0
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s32) = G_SITOFP %0(s16)
$f0 = COPY %2(s32)
@@ -126,11 +126,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: i8tof32
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
@@ -138,15 +138,15 @@ body: |
; FP32: $f0 = COPY [[SITOFP]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: i8tof32
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; FP64: $f0 = COPY [[SITOFP]](s32)
; FP64: RetRA implicit $f0
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s32) = G_SITOFP %0(s8)
$f0 = COPY %2(s32)
@@ -159,34 +159,34 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; FP32-LABEL: name: i64tof64
- ; FP32: liveins: $a0, $a1
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32: $a0 = COPY [[COPY]](s32)
- ; FP32: $a1 = COPY [[COPY1]](s32)
- ; FP32: JAL &__floatdidf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0
+ ; FP32: liveins: $r4, $r5
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP32: $r4 = COPY [[COPY]](s32)
+ ; FP32: $r5 = COPY [[COPY1]](s32)
+ ; FP32: JAL &__floatdidf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $d0
; FP32: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $d0 = COPY [[COPY2]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: i64tof64
- ; FP64: liveins: $a0, $a1
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64: $a0 = COPY [[COPY]](s32)
- ; FP64: $a1 = COPY [[COPY1]](s32)
- ; FP64: JAL &__floatdidf, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0_64
+ ; FP64: liveins: $r4, $r5
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP64: $r4 = COPY [[COPY]](s32)
+ ; FP64: $r5 = COPY [[COPY1]](s32)
+ ; FP64: JAL &__floatdidf, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $d0_64
; FP64: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0_64
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $d0 = COPY [[COPY2]](s64)
; FP64: RetRA implicit $d0
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_SITOFP %0(s64)
$d0 = COPY %3(s64)
@@ -199,21 +199,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: i32tof64
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
; FP32: $d0 = COPY [[SITOFP]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: i32tof64
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
; FP64: $d0 = COPY [[SITOFP]](s64)
; FP64: RetRA implicit $d0
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s64) = G_SITOFP %0(s32)
$d0 = COPY %1(s64)
RetRA implicit $d0
@@ -225,11 +225,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: i16tof64
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
@@ -237,15 +237,15 @@ body: |
; FP32: $d0 = COPY [[SITOFP]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: i16tof64
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; FP64: $d0 = COPY [[SITOFP]](s64)
; FP64: RetRA implicit $d0
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s64) = G_SITOFP %0(s16)
$d0 = COPY %2(s64)
@@ -258,11 +258,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: i8tof64
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
@@ -270,15 +270,15 @@ body: |
; FP32: $d0 = COPY [[SITOFP]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: i8tof64
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; FP64: $d0 = COPY [[SITOFP]](s64)
; FP64: RetRA implicit $d0
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s64) = G_SITOFP %0(s8)
$d0 = COPY %2(s64)
@@ -291,34 +291,34 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; FP32-LABEL: name: u64tof32
- ; FP32: liveins: $a0, $a1
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32: $a0 = COPY [[COPY]](s32)
- ; FP32: $a1 = COPY [[COPY1]](s32)
- ; FP32: JAL &__floatundisf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
+ ; FP32: liveins: $r4, $r5
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP32: $r4 = COPY [[COPY]](s32)
+ ; FP32: $r5 = COPY [[COPY1]](s32)
+ ; FP32: JAL &__floatundisf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $f0
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $f0 = COPY [[COPY2]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: u64tof32
- ; FP64: liveins: $a0, $a1
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64: $a0 = COPY [[COPY]](s32)
- ; FP64: $a1 = COPY [[COPY1]](s32)
- ; FP64: JAL &__floatundisf, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
+ ; FP64: liveins: $r4, $r5
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP64: $r4 = COPY [[COPY]](s32)
+ ; FP64: $r5 = COPY [[COPY1]](s32)
+ ; FP64: JAL &__floatundisf, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $f0
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $f0 = COPY [[COPY2]](s32)
; FP64: RetRA implicit $f0
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s32) = G_UITOFP %0(s64)
$f0 = COPY %3(s32)
@@ -331,11 +331,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: u32tof32
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
@@ -344,8 +344,8 @@ body: |
; FP32: $f0 = COPY [[FPTRUNC]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: u32tof32
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
@@ -353,7 +353,7 @@ body: |
; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
; FP64: $f0 = COPY [[FPTRUNC]](s32)
; FP64: RetRA implicit $f0
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_UITOFP %0(s32)
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -365,11 +365,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: u16tof32
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
@@ -380,8 +380,8 @@ body: |
; FP32: $f0 = COPY [[FPTRUNC]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: u16tof32
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
@@ -391,7 +391,7 @@ body: |
; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
; FP64: $f0 = COPY [[FPTRUNC]](s32)
; FP64: RetRA implicit $f0
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s32) = G_UITOFP %0(s16)
$f0 = COPY %2(s32)
@@ -404,11 +404,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: u8tof32
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
@@ -419,8 +419,8 @@ body: |
; FP32: $f0 = COPY [[FPTRUNC]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: u8tof32
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
@@ -430,7 +430,7 @@ body: |
; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
; FP64: $f0 = COPY [[FPTRUNC]](s32)
; FP64: RetRA implicit $f0
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s32) = G_UITOFP %0(s8)
$f0 = COPY %2(s32)
@@ -443,34 +443,34 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; FP32-LABEL: name: u64tof64
- ; FP32: liveins: $a0, $a1
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32: $a0 = COPY [[COPY]](s32)
- ; FP32: $a1 = COPY [[COPY1]](s32)
- ; FP32: JAL &__floatundidf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0
+ ; FP32: liveins: $r4, $r5
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP32: $r4 = COPY [[COPY]](s32)
+ ; FP32: $r5 = COPY [[COPY1]](s32)
+ ; FP32: JAL &__floatundidf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $d0
; FP32: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $d0 = COPY [[COPY2]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: u64tof64
- ; FP64: liveins: $a0, $a1
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64: $a0 = COPY [[COPY]](s32)
- ; FP64: $a1 = COPY [[COPY1]](s32)
- ; FP64: JAL &__floatundidf, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0_64
+ ; FP64: liveins: $r4, $r5
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP64: $r4 = COPY [[COPY]](s32)
+ ; FP64: $r5 = COPY [[COPY1]](s32)
+ ; FP64: JAL &__floatundidf, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $d0_64
; FP64: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0_64
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $d0 = COPY [[COPY2]](s64)
; FP64: RetRA implicit $d0
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_UITOFP %0(s64)
$d0 = COPY %3(s64)
@@ -483,11 +483,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: u32tof64
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
@@ -495,15 +495,15 @@ body: |
; FP32: $d0 = COPY [[FSUB]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: u32tof64
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C1]]
; FP64: $d0 = COPY [[FSUB]](s64)
; FP64: RetRA implicit $d0
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s64) = G_UITOFP %0(s32)
$d0 = COPY %1(s64)
RetRA implicit $d0
@@ -515,11 +515,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: u16tof64
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
@@ -529,8 +529,8 @@ body: |
; FP32: $d0 = COPY [[FSUB]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: u16tof64
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
@@ -539,7 +539,7 @@ body: |
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
; FP64: $d0 = COPY [[FSUB]](s64)
; FP64: RetRA implicit $d0
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s64) = G_UITOFP %0(s16)
$d0 = COPY %2(s64)
@@ -552,11 +552,11 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: u8tof64
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
@@ -566,8 +566,8 @@ body: |
; FP32: $d0 = COPY [[FSUB]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: u8tof64
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
@@ -576,7 +576,7 @@ body: |
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
; FP64: $d0 = COPY [[FSUB]](s64)
; FP64: RetRA implicit $d0
- %1:_(s32) = COPY $a0
+ %1:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s64) = G_UITOFP %0(s8)
$d0 = COPY %2(s64)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
index 89d77c3aa29cf..8d47c7374dd57 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
@@ -14,48 +14,48 @@ fixedStack:
- { id: 0, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: g
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
- ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY]](s32)
- ; MIPS32: $a1 = COPY [[COPY1]](s32)
- ; MIPS32: $a2 = COPY [[COPY2]](s32)
- ; MIPS32: $a3 = COPY [[COPY3]](s32)
- ; MIPS32: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
+ ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY]](s32)
+ ; MIPS32: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32: $r6 = COPY [[COPY2]](s32)
+ ; MIPS32: $r7 = COPY [[COPY3]](s32)
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(p0) = COPY $r29
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store (s32) into stack + 16)
- ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32: JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY5]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%5:_(p0) = G_FRAME_INDEX %fixed-stack.0
%4:_(s32) = G_LOAD %5(p0) :: (load (s32) from %fixed-stack.0, align 8)
- ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %0(s32)
- $a1 = COPY %1(s32)
- $a2 = COPY %2(s32)
- $a3 = COPY %3(s32)
- %7:_(p0) = COPY $sp
+ ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %0(s32)
+ $r5 = COPY %1(s32)
+ $r6 = COPY %2(s32)
+ $r7 = COPY %3(s32)
+ %7:_(p0) = COPY $r29
%8:_(s32) = G_CONSTANT i32 16
%9:_(p0) = G_PTR_ADD %7, %8(s32)
G_STORE %4(s32), %9(p0) :: (store (s32) into stack + 16, align 4)
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
%6:_(s32) = COPY $r2
- ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
$r2 = COPY %6(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir
index c24beeff750ac..21260329a9cfd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir
@@ -7,17 +7,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: store_i32
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; MIPS32-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32))
; MIPS32-NEXT: RetRA
- %0:_(s32) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(p0) = COPY $r5
G_STORE %0(s32), %1(p0) :: (store (s32))
RetRA
@@ -29,21 +29,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: store_i64
- ; MIPS32: liveins: $a0, $a1, $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; MIPS32-NEXT: G_STORE [[MV]](s64), [[COPY2]](p0) :: (store (s64))
; MIPS32-NEXT: RetRA
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %1:_(p0) = COPY $a2
+ %1:_(p0) = COPY $r6
G_STORE %0(s64), %1(p0) :: (store (s64))
RetRA
@@ -55,17 +55,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a1, $f12
+ liveins: $r5, $f12
; MIPS32-LABEL: name: store_float
- ; MIPS32: liveins: $a1, $f12
+ ; MIPS32: liveins: $r5, $f12
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; MIPS32-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32))
; MIPS32-NEXT: RetRA
%0:_(s32) = COPY $f12
- %1:_(p0) = COPY $a1
+ %1:_(p0) = COPY $r5
G_STORE %0(s32), %1(p0) :: (store (s32))
RetRA
@@ -77,17 +77,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a2, $d6
+ liveins: $r6, $d6
; MIPS32-LABEL: name: store_double
- ; MIPS32: liveins: $a2, $d6
+ ; MIPS32: liveins: $r6, $d6
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a2
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r6
; MIPS32-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64))
; MIPS32-NEXT: RetRA
%0:_(s64) = COPY $d6
- %1:_(p0) = COPY $a2
+ %1:_(p0) = COPY $r6
G_STORE %0(s64), %1(p0) :: (store (s64))
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_4_unaligned.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_4_unaligned.mir
index 698972063702f..b6246a5bad4ff 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_4_unaligned.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_4_unaligned.mir
@@ -171,21 +171,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: store_i32_align1
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store (s32) into @i32_align1, align 1)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i32_align1
- ; MIPS32R6: liveins: $a0
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32R6: liveins: $r4
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store (s32) into @i32_align1, align 1)
; MIPS32R6: RetRA
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(p0) = G_GLOBAL_VALUE @i32_align1
G_STORE %0(s32), %1(p0) :: (store (s32) into @i32_align1, align 1)
RetRA
@@ -197,21 +197,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: store_i32_align2
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store (s32) into @i32_align2, align 2)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i32_align2
- ; MIPS32R6: liveins: $a0
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32R6: liveins: $r4
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store (s32) into @i32_align2, align 2)
; MIPS32R6: RetRA
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(p0) = G_GLOBAL_VALUE @i32_align2
G_STORE %0(s32), %1(p0) :: (store (s32) into @i32_align2, align 2)
RetRA
@@ -223,21 +223,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: store_i32_align4
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store (s32) into @i32_align4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i32_align4
- ; MIPS32R6: liveins: $a0
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32R6: liveins: $r4
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store (s32) into @i32_align4)
; MIPS32R6: RetRA
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(p0) = G_GLOBAL_VALUE @i32_align4
G_STORE %0(s32), %1(p0) :: (store (s32) into @i32_align4)
RetRA
@@ -249,21 +249,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: store_i32_align8
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store (s32) into @i32_align8, align 8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i32_align8
- ; MIPS32R6: liveins: $a0
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32R6: liveins: $r4
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store (s32) into @i32_align8, align 8)
; MIPS32R6: RetRA
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
G_STORE %0(s32), %1(p0) :: (store (s32) into @i32_align8, align 8)
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
index 1038571cea7e6..b337df3db0362 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
@@ -212,12 +212,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: store3align1
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -231,9 +231,9 @@ body: |
; MIPS32: G_STORE [[LSHR1]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store3align1
- ; MIPS32R6: liveins: $a0, $a1
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32R6: liveins: $r4, $r5
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 1)
@@ -241,8 +241,8 @@ body: |
; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32R6: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s24) = G_TRUNC %1(s32)
G_STORE %2(s24), %0(p0) :: (store (s24) into %ir.0, align 1)
RetRA
@@ -254,12 +254,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: store3align2
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0)
@@ -268,9 +268,9 @@ body: |
; MIPS32: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store3align2
- ; MIPS32R6: liveins: $a0, $a1
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32R6: liveins: $r4, $r5
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0)
@@ -278,8 +278,8 @@ body: |
; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32R6: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s24) = G_TRUNC %1(s32)
G_STORE %2(s24), %0(p0) :: (store (s24) into %ir.0, align 2)
RetRA
@@ -291,12 +291,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: store3align4
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 4)
@@ -305,9 +305,9 @@ body: |
; MIPS32: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2, basealign 4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store3align4
- ; MIPS32R6: liveins: $a0, $a1
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32R6: liveins: $r4, $r5
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 4)
@@ -315,8 +315,8 @@ body: |
; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32R6: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2, basealign 4)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s24) = G_TRUNC %1(s32)
G_STORE %2(s24), %0(p0) :: (store (s24) into %ir.0, align 4)
RetRA
@@ -328,12 +328,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: store3align8
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 8)
@@ -342,9 +342,9 @@ body: |
; MIPS32: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2, basealign 8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store3align8
- ; MIPS32R6: liveins: $a0, $a1
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32R6: liveins: $r4, $r5
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 8)
@@ -352,8 +352,8 @@ body: |
; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32R6: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2, basealign 8)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s24) = G_TRUNC %1(s32)
G_STORE %2(s24), %0(p0) :: (store (s24) into %ir.0, align 8)
RetRA
@@ -365,31 +365,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store5align1
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 1)
; MIPS32: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store5align1
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 1)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 4)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s40) = G_TRUNC %1(s64)
G_STORE %4(s40), %0(p0) :: (store (s40) into %ir.0, align 1)
@@ -402,31 +402,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store5align2
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 2)
; MIPS32: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 4, align 2)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store5align2
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 2)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 4, align 2)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s40) = G_TRUNC %1(s64)
G_STORE %4(s40), %0(p0) :: (store (s40) into %ir.0, align 2)
@@ -439,31 +439,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store5align4
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0)
; MIPS32: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 4, align 4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store5align4
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 4, align 4)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s40) = G_TRUNC %1(s64)
G_STORE %4(s40), %0(p0) :: (store (s40) into %ir.0, align 4)
@@ -476,31 +476,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store5align8
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 8)
; MIPS32: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 4, align 4, basealign 8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store5align8
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 8)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 4, align 4, basealign 8)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s40) = G_TRUNC %1(s64)
G_STORE %4(s40), %0(p0) :: (store (s40) into %ir.0, align 8)
@@ -513,13 +513,13 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store6align1
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 1)
@@ -531,18 +531,18 @@ body: |
; MIPS32: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p0) :: (store (s8) into %ir.0 + 5)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store6align1
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 1)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4, align 1)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s48) = G_TRUNC %1(s64)
G_STORE %4(s48), %0(p0) :: (store (s48) into %ir.0, align 1)
@@ -555,31 +555,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store6align2
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 2)
; MIPS32: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store6align2
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 2)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s48) = G_TRUNC %1(s64)
G_STORE %4(s48), %0(p0) :: (store (s48) into %ir.0, align 2)
@@ -592,31 +592,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store6align4
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0)
; MIPS32: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4, align 4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store6align4
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4, align 4)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s48) = G_TRUNC %1(s64)
G_STORE %4(s48), %0(p0) :: (store (s48) into %ir.0, align 4)
@@ -629,31 +629,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store6align8
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 8)
; MIPS32: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4, align 4, basealign 8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store6align8
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 8)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4, align 4, basealign 8)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s48) = G_TRUNC %1(s64)
G_STORE %4(s48), %0(p0) :: (store (s48) into %ir.0, align 8)
@@ -666,13 +666,13 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store7align1
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 1)
@@ -684,18 +684,18 @@ body: |
; MIPS32: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p0) :: (store (s8) into %ir.0 + 5)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store7align1
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 1)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4, align 1)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s56) = G_TRUNC %1(s64)
G_STORE %4(s56), %0(p0) :: (store (s42) into %ir.0, align 1)
@@ -708,31 +708,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store7align2
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 2)
; MIPS32: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store7align2
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 2)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s56) = G_TRUNC %1(s64)
G_STORE %4(s56), %0(p0) :: (store (s42) into %ir.0, align 2)
@@ -745,31 +745,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store7align4
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0)
; MIPS32: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4, align 4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store7align4
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4, align 4)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s56) = G_TRUNC %1(s64)
G_STORE %4(s56), %0(p0) :: (store (s42) into %ir.0, align 4)
@@ -782,31 +782,31 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: store7align8
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 8)
; MIPS32: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4, align 4, basealign 8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store7align8
- ; MIPS32R6: liveins: $a0, $a2, $a3
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32R6: liveins: $r4, $r6, $r7
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.0, align 8)
; MIPS32R6: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s16) into %ir.0 + 4, align 4, basealign 8)
; MIPS32R6: RetRA
- %0:_(p0) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(p0) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s56) = G_TRUNC %1(s64)
G_STORE %4(s56), %0(p0) :: (store (s42) into %ir.0, align 8)
@@ -935,12 +935,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: store_i64_align1
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[C]](s32)
@@ -948,15 +948,15 @@ body: |
; MIPS32: G_STORE [[COPY1]](s32), [[PTR_ADD]](p0) :: (store (s32) into @i64_align1 + 4, align 1)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i64_align1
- ; MIPS32R6: liveins: $a0, $a1
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32R6: liveins: $r4, $r5
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align1
; MIPS32R6: G_STORE [[MV]](s64), [[GV]](p0) :: (store (s64) into @i64_align1, align 1)
; MIPS32R6: RetRA
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(p0) = G_GLOBAL_VALUE @i64_align1
G_STORE %0(s64), %3(p0) :: (store (s64) into @i64_align1, align 1)
@@ -969,12 +969,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: store_i64_align2
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[C]](s32)
@@ -982,15 +982,15 @@ body: |
; MIPS32: G_STORE [[COPY1]](s32), [[PTR_ADD]](p0) :: (store (s32) into @i64_align2 + 4, align 2)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i64_align2
- ; MIPS32R6: liveins: $a0, $a1
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32R6: liveins: $r4, $r5
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align2
; MIPS32R6: G_STORE [[MV]](s64), [[GV]](p0) :: (store (s64) into @i64_align2, align 2)
; MIPS32R6: RetRA
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(p0) = G_GLOBAL_VALUE @i64_align2
G_STORE %0(s64), %3(p0) :: (store (s64) into @i64_align2, align 2)
@@ -1003,12 +1003,12 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: store_i64_align4
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[C]](s32)
@@ -1016,15 +1016,15 @@ body: |
; MIPS32: G_STORE [[COPY1]](s32), [[PTR_ADD]](p0) :: (store (s32) into @i64_align4 + 4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i64_align4
- ; MIPS32R6: liveins: $a0, $a1
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32R6: liveins: $r4, $r5
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align4
; MIPS32R6: G_STORE [[MV]](s64), [[GV]](p0) :: (store (s64) into @i64_align4, align 4)
; MIPS32R6: RetRA
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(p0) = G_GLOBAL_VALUE @i64_align4
G_STORE %0(s64), %3(p0) :: (store (s64) into @i64_align4, align 4)
@@ -1037,26 +1037,26 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: store_i64_align8
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align8
; MIPS32: G_STORE [[MV]](s64), [[GV]](p0) :: (store (s64) into @i64_align8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i64_align8
- ; MIPS32R6: liveins: $a0, $a1
- ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32R6: liveins: $r4, $r5
+ ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align8
; MIPS32R6: G_STORE [[MV]](s64), [[GV]](p0) :: (store (s64) into @i64_align8)
; MIPS32R6: RetRA
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(p0) = G_GLOBAL_VALUE @i64_align8
G_STORE %0(s64), %3(p0) :: (store (s64) into @i64_align8)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
index d78a49ec46791..b3940376ea723 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
@@ -19,18 +19,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sub_i32
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
; MIPS32-NEXT: $r2 = COPY [[SUB]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_SUB %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -42,22 +42,22 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sub_i8_sext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SUB %1, %0
%5:_(s32) = G_SEXT %4(s8)
@@ -71,21 +71,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sub_i8_zext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SUB %1, %0
%5:_(s32) = G_ZEXT %4(s8)
@@ -99,19 +99,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sub_i8_aext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[SUB]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SUB %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
@@ -125,22 +125,22 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sub_i16_sext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[ASHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SUB %1, %0
%5:_(s32) = G_SEXT %4(s16)
@@ -154,21 +154,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sub_i16_zext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; MIPS32-NEXT: $r2 = COPY [[AND]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SUB %1, %0
%5:_(s32) = G_ZEXT %4(s16)
@@ -182,19 +182,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sub_i16_aext
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32-NEXT: $r2 = COPY [[SUB]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %2:_(s32) = COPY $a0
+ %2:_(s32) = COPY $r4
%0:_(s16) = G_TRUNC %2(s32)
- %3:_(s32) = COPY $a1
+ %3:_(s32) = COPY $r5
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SUB %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
@@ -208,15 +208,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: sub_i64
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]]
; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY3]](s32), [[COPY1]]
; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]
@@ -224,11 +224,11 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[SUB2]](s32)
; MIPS32-NEXT: $r3 = COPY [[SUB]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32)
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %5(s32), %4(s32)
%6:_(s64) = G_SUB %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
@@ -248,15 +248,15 @@ fixedStack:
- { id: 3, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: sub_i128
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -287,13 +287,13 @@ body: |
; MIPS32-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND3]]
; MIPS32-NEXT: $r2 = COPY [[SUB]](s32)
; MIPS32-NEXT: $r3 = COPY [[SUB2]](s32)
- ; MIPS32-NEXT: $a0 = COPY [[SUB4]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[SUB6]](s32)
- ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ ; MIPS32-NEXT: $r4 = COPY [[SUB4]](s32)
+ ; MIPS32-NEXT: $r5 = COPY [[SUB6]](s32)
+ ; MIPS32-NEXT: RetRA implicit $r2, implicit $r3, implicit $r4, implicit $r5
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
%10:_(p0) = G_FRAME_INDEX %fixed-stack.3
%6:_(s32) = G_LOAD %10(p0) :: (load (s32) from %fixed-stack.3, align 8)
@@ -308,8 +308,8 @@ body: |
%15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
$r2 = COPY %15(s32)
$r3 = COPY %16(s32)
- $a0 = COPY %17(s32)
- $a1 = COPY %18(s32)
- RetRA implicit $r2, implicit $r3, implicit $a0, implicit $a1
+ $r4 = COPY %17(s32)
+ $r5 = COPY %18(s32)
+ RetRA implicit $r2, implicit $r3, implicit $r4, implicit $r5
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir
index 645c63b915f7c..0a3de324b1d90 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir
@@ -14,21 +14,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_SUB %4, %3
@@ -42,21 +42,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_SUB %4, %3
@@ -70,21 +70,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_SUB %4, %3
@@ -98,21 +98,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_SUB %4, %3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir
index fd246645b2b2a..859d0249d3266 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir
@@ -33,21 +33,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v16i8_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SUB]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.subv.b), %3(<16 x s8>), %4(<16 x s8>)
@@ -61,21 +61,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v8i16_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SUB]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.subv.h), %3(<8 x s16>), %4(<8 x s16>)
@@ -89,21 +89,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v4i32_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.subv.w), %3(<4 x s32>), %4(<4 x s32>)
@@ -117,21 +117,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v2i64_builtin
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.subv.d), %3(<2 x s64>), %4(<2 x s64>)
@@ -145,18 +145,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: sub_v16i8_builtin_imm
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128b(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[SUBVI_B:%[0-9]+]]:msa128b(<16 x s8>) = SUBVI_B [[LOAD]](<16 x s8>), 3
; P5600: G_STORE [[SUBVI_B]](<16 x s8>), [[COPY1]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%3:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.subvi.b), %2(<16 x s8>), 3
G_STORE %3(<16 x s8>), %1(p0) :: (store (<16 x s8>) into %ir.c)
@@ -169,18 +169,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: sub_v8i16_builtin_imm
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128h(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[SUBVI_H:%[0-9]+]]:msa128h(<8 x s16>) = SUBVI_H [[LOAD]](<8 x s16>), 18
; P5600: G_STORE [[SUBVI_H]](<8 x s16>), [[COPY1]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%3:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.subvi.h), %2(<8 x s16>), 18
G_STORE %3(<8 x s16>), %1(p0) :: (store (<8 x s16>) into %ir.c)
@@ -193,18 +193,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: sub_v4i32_builtin_imm
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[SUBVI_W:%[0-9]+]]:msa128w(<4 x s32>) = SUBVI_W [[LOAD]](<4 x s32>), 25
; P5600: G_STORE [[SUBVI_W]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.subvi.w), %2(<4 x s32>), 25
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
@@ -217,18 +217,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: sub_v2i64_builtin_imm
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:msa128d(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[SUBVI_D:%[0-9]+]]:msa128d(<2 x s64>) = SUBVI_D [[LOAD]](<2 x s64>), 31
; P5600: G_STORE [[SUBVI_D]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.subvi.d), %2(<2 x s64>), 31
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir
index 3f539775312d2..70b62b12784ae 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir
@@ -11,15 +11,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: trunc
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: $r2 = COPY [[COPY]](s32)
; MIPS32: RetRA implicit $r2
- %1:_(s32) = COPY $a0
- %2:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s32) = G_TRUNC %0(s64)
$r2 = COPY %3(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
index d298395ac4368..6d6d90cf50da3 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
@@ -6,16 +6,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.0:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_load1_s32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s32) = G_LOAD %0(p0) :: (load (s8))
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -27,16 +27,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.0:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load2_s16_to_load2_s32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s32) = G_LOAD %0(p0) :: (load (s16))
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -48,21 +48,21 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.0:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_store_i1
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s8))
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; MIPS32-NEXT: G_STORE [[AND1]](s32), [[COPY]](p0) :: (store (s8))
; MIPS32-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s1) = G_LOAD %1(p0) :: (load (s1))
G_STORE %2(s1), %0(p0) :: (store (s1))
RetRA
@@ -74,18 +74,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.0:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_store_i8
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s8))
; MIPS32-NEXT: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s8))
; MIPS32-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s8) = G_LOAD %1(p0) :: (load (s8))
G_STORE %2(s8), %0(p0) :: (store (s8))
RetRA
@@ -97,18 +97,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.0:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_store_i16
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s16))
; MIPS32-NEXT: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s16))
; MIPS32-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s16) = G_LOAD %1(p0) :: (load (s16))
G_STORE %2(s16), %0(p0) :: (store (s16))
RetRA
@@ -120,18 +120,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.0:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_store_i32
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32))
; MIPS32-NEXT: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s32))
; MIPS32-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s32) = G_LOAD %1(p0) :: (load (s32))
G_STORE %2(s32), %0(p0) :: (store (s32))
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
index 721b10a14e347..8f9c7ed364bb8 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
@@ -36,7 +36,7 @@ name: testVaCopyArg
alignment: 4
tracksRegLiveness: true
liveins:
- - { reg: '$a0' }
+ - { reg: '$r4' }
fixedStack:
- { id: 0, offset: 12, size: 4, alignment: 4, isImmutable: true }
- { id: 1, offset: 8, size: 4, alignment: 8, isImmutable: true }
@@ -50,18 +50,18 @@ stack:
machineFunctionInfo: {}
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: testVaCopyArg
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; MIPS32: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $r6
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
; MIPS32: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.2)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
; MIPS32: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.3)
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @.str
@@ -81,20 +81,20 @@ body: |
; MIPS32: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[LOAD1]](p0) :: (load (p0) from %ir.2)
; MIPS32: G_STORE [[LOAD2]](p0), [[FRAME_INDEX6]](p0) :: (store (p0) into %ir.s)
; MIPS32: [[LOAD3:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX6]](p0) :: (load (p0) from %ir.s)
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY4]](p0)
- ; MIPS32: $a1 = COPY [[LOAD3]](p0)
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY4]](p0)
+ ; MIPS32: $r5 = COPY [[LOAD3]](p0)
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
- %0:_(p0) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(p0) = G_FRAME_INDEX %fixed-stack.2
G_STORE %1(s32), %2(p0) :: (store (s32) into %fixed-stack.2)
- %3:_(s32) = COPY $a2
+ %3:_(s32) = COPY $r6
%4:_(p0) = G_FRAME_INDEX %fixed-stack.1
G_STORE %3(s32), %4(p0) :: (store (s32) into %fixed-stack.1)
- %5:_(s32) = COPY $a3
+ %5:_(s32) = COPY $r7
%6:_(p0) = G_FRAME_INDEX %fixed-stack.0
G_STORE %5(s32), %6(p0) :: (store (s32) into %fixed-stack.0)
%18:_(p0) = G_GLOBAL_VALUE @.str
@@ -113,11 +113,11 @@ body: |
%14:_(p0) = G_LOAD %11(p0) :: (load (p0) from %ir.2)
G_STORE %14(p0), %10(p0) :: (store (p0) into %ir.s)
%15:_(p0) = G_LOAD %10(p0) :: (load (p0) from %ir.s)
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %17(p0)
- $a1 = COPY %15(p0)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %17(p0)
+ $r5 = COPY %15(p0)
+ JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
index cfbdb58707ab4..9cf0e70133ca4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
@@ -20,16 +20,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32-NEXT: $r2 = COPY [[ZEXTLOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -41,16 +41,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
; MIPS32-NEXT: $r2 = COPY [[ZEXTLOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -62,16 +62,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32-NEXT: $r2 = COPY [[ZEXTLOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
%3:_(s32) = G_ANYEXT %2(s16)
$r2 = COPY %3(s32)
@@ -84,16 +84,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32-NEXT: $r2 = COPY [[ZEXTLOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$r2 = COPY %3(s32)
RetRA implicit $r2
@@ -105,18 +105,18 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
; MIPS32-NEXT: $r3 = COPY [[C]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32) from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$r2 = COPY %3(s32)
@@ -130,16 +130,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32-NEXT: $r2 = COPY [[SEXTLOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -151,16 +151,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
; MIPS32-NEXT: $r2 = COPY [[SEXTLOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -172,16 +172,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32-NEXT: $r2 = COPY [[SEXTLOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
%3:_(s32) = G_ANYEXT %2(s16)
$r2 = COPY %3(s32)
@@ -194,16 +194,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32-NEXT: $r2 = COPY [[SEXTLOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$r2 = COPY %3(s32)
RetRA implicit $r2
@@ -215,19 +215,19 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
; MIPS32-NEXT: $r3 = COPY [[ASHR]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32) from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$r2 = COPY %3(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
index b067cfd72152b..876422d7d1b7c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
@@ -12,16 +12,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: zext
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: $r2 = COPY [[COPY]](s32)
; MIPS32: $r3 = COPY [[C]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s64) = G_ZEXT %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$r2 = COPY %2(s32)
@@ -35,17 +35,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: sext
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
; MIPS32: $r2 = COPY [[COPY]](s32)
; MIPS32: $r3 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s64) = G_SEXT %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$r2 = COPY %2(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/big-endian-memory.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/big-endian-memory.ll
index c121531ca8bdc..9fb4ceba3ab17 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/big-endian-memory.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/big-endian-memory.ll
@@ -7,7 +7,7 @@
define i32 @load_i16(ptr %p) {
; BE-LABEL: load_i16:
; BE: # %bb.0:
-; BE-NEXT: # implicit-def: $at
+; BE-NEXT: # implicit-def: $r1
; BE-NEXT: lwl $1, 0($4)
; BE-NEXT: lwr $1, 3($4)
; BE-NEXT: srl $2, $1, 16
@@ -16,7 +16,7 @@ define i32 @load_i16(ptr %p) {
;
; LE-LABEL: load_i16:
; LE: # %bb.0:
-; LE-NEXT: # implicit-def: $at
+; LE-NEXT: # implicit-def: $r1
; LE-NEXT: lwl $1, 3($4)
; LE-NEXT: lwr $1, 0($4)
; LE-NEXT: andi $2, $1, 65535
@@ -40,7 +40,7 @@ define i32 @load_i16(ptr %p) {
define i32 @load_i24(ptr %p) {
; BE-LABEL: load_i24:
; BE: # %bb.0:
-; BE-NEXT: # implicit-def: $at
+; BE-NEXT: # implicit-def: $r1
; BE-NEXT: lwl $1, 0($4)
; BE-NEXT: lwr $1, 3($4)
; BE-NEXT: srl $1, $1, 8
@@ -51,7 +51,7 @@ define i32 @load_i24(ptr %p) {
;
; LE-LABEL: load_i24:
; LE: # %bb.0:
-; LE-NEXT: # implicit-def: $at
+; LE-NEXT: # implicit-def: $r1
; LE-NEXT: lwl $1, 3($4)
; LE-NEXT: lwr $1, 0($4)
; LE-NEXT: sll $1, $1, 8
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/implicit_def.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/implicit_def.ll
index 0b41eb7cd90fc..1a9cde7724d0e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/implicit_def.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/implicit_def.ll
@@ -8,7 +8,7 @@ define void @g_i32() nounwind {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MIPS32-NEXT: # implicit-def: $a0
+; MIPS32-NEXT: # implicit-def: $r4
; MIPS32-NEXT: jal f_i32
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
@@ -20,7 +20,7 @@ define void @g_i32() nounwind {
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: daddiu $sp, $sp, -16
; MIPS64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
-; MIPS64-NEXT: # implicit-def: $a0_64
+; MIPS64-NEXT: # implicit-def: $r4_64
; MIPS64-NEXT: jal f_i32
; MIPS64-NEXT: nop
; MIPS64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
@@ -38,7 +38,7 @@ define void @g_i64() nounwind {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MIPS32-NEXT: # implicit-def: $a1
+; MIPS32-NEXT: # implicit-def: $r5
; MIPS32-NEXT: move $4, $5
; MIPS32-NEXT: jal f_i64
; MIPS32-NEXT: nop
@@ -51,7 +51,7 @@ define void @g_i64() nounwind {
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: daddiu $sp, $sp, -16
; MIPS64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
-; MIPS64-NEXT: # implicit-def: $a0_64
+; MIPS64-NEXT: # implicit-def: $r4_64
; MIPS64-NEXT: jal f_i64
; MIPS64-NEXT: nop
; MIPS64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
index c1418284b570b..c282d59d1de40 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
@@ -16,7 +16,7 @@ define float @load_float_align1() {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align1)
; MIPS32-NEXT: addiu $2, $1, %lo(float_align1)
-; MIPS32-NEXT: # implicit-def: $at
+; MIPS32-NEXT: # implicit-def: $r1
; MIPS32-NEXT: lwl $1, 3($2)
; MIPS32-NEXT: lwr $1, 0($2)
; MIPS32-NEXT: mtc1 $1, $f0
@@ -39,7 +39,7 @@ define float @load_float_align2() {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align2)
; MIPS32-NEXT: addiu $2, $1, %lo(float_align2)
-; MIPS32-NEXT: # implicit-def: $at
+; MIPS32-NEXT: # implicit-def: $r1
; MIPS32-NEXT: lwl $1, 3($2)
; MIPS32-NEXT: lwr $1, 0($2)
; MIPS32-NEXT: mtc1 $1, $f0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
index 60b7bb16131e1..50bbc8c14bfaa 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
@@ -31,7 +31,7 @@
define i32 @load3align1(ptr %S) {
; MIPS32-LABEL: load3align1:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: # implicit-def: $at
+; MIPS32-NEXT: # implicit-def: $r1
; MIPS32-NEXT: lwl $1, 3($4)
; MIPS32-NEXT: lwr $1, 0($4)
; MIPS32-NEXT: lui $2, 255
@@ -56,7 +56,7 @@ entry:
define i32 @load3align2(ptr %S) {
; MIPS32-LABEL: load3align2:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: # implicit-def: $at
+; MIPS32-NEXT: # implicit-def: $r1
; MIPS32-NEXT: lwl $1, 3($4)
; MIPS32-NEXT: lwr $1, 0($4)
; MIPS32-NEXT: lui $2, 255
@@ -234,7 +234,7 @@ define i64 @load6align1(ptr %S) {
; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
-; MIPS32-NEXT: # implicit-def: $at
+; MIPS32-NEXT: # implicit-def: $r1
; MIPS32-NEXT: lwl $1, 7($4)
; MIPS32-NEXT: lwr $1, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
@@ -340,7 +340,7 @@ define i64 @load7align1(ptr %S) {
; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
-; MIPS32-NEXT: # implicit-def: $at
+; MIPS32-NEXT: # implicit-def: $r1
; MIPS32-NEXT: lwl $1, 7($4)
; MIPS32-NEXT: lwr $1, 4($4)
; MIPS32-NEXT: addiu $4, $zero, 65535
@@ -373,7 +373,7 @@ define i64 @load7align2(ptr %S) {
; MIPS32-NEXT: # implicit-def: $r2
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
-; MIPS32-NEXT: # implicit-def: $at
+; MIPS32-NEXT: # implicit-def: $r1
; MIPS32-NEXT: lwl $1, 7($4)
; MIPS32-NEXT: lwr $1, 4($4)
; MIPS32-NEXT: addiu $4, $zero, 65535
@@ -463,7 +463,7 @@ define double @load_double_align1() {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(double_align1)
; MIPS32-NEXT: addiu $3, $1, %lo(double_align1)
-; MIPS32-NEXT: # implicit-def: $at
+; MIPS32-NEXT: # implicit-def: $r1
; MIPS32-NEXT: lwl $1, 3($3)
; MIPS32-NEXT: lwr $1, 0($3)
; MIPS32-NEXT: # implicit-def: $r2
@@ -490,7 +490,7 @@ define double @load_double_align2() {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(double_align2)
; MIPS32-NEXT: addiu $3, $1, %lo(double_align2)
-; MIPS32-NEXT: # implicit-def: $at
+; MIPS32-NEXT: # implicit-def: $r1
; MIPS32-NEXT: lwl $1, 3($3)
; MIPS32-NEXT: lwr $1, 0($3)
; MIPS32-NEXT: # implicit-def: $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir
index 54003f050b99c..0aa5c347565d1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir
@@ -29,20 +29,20 @@ registers:
- { id: 2, class: _ }
- { id: 3, class: _ }
liveins:
- - { reg: '$a0' }
- - { reg: '$a1' }
+ - { reg: '$r4' }
+ - { reg: '$r5' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: test_memcpy_inline
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $r5
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.1, align 4)
; MIPS32-NEXT: G_STORE [[LOAD]](s8), [[COPY]](p0) :: (store (s8) into %ir.0, align 4)
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -51,8 +51,8 @@ body: |
; MIPS32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[LOAD1]](s8), [[PTR_ADD1]](p0) :: (store (s8) into %ir.0 + 1, basealign 4)
; MIPS32-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s64) = G_CONSTANT i64 2
%3:_(s32) = G_TRUNC %2(s64)
G_MEMCPY_INLINE %0(p0), %1(p0), %3(s32) :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memset.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memset.mir
index 48a8052da0d72..99dc485db4c01 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memset.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memset.mir
@@ -26,28 +26,28 @@ registers:
- { id: 3, class: _ }
- { id: 4, class: _ }
liveins:
- - { reg: '$a0' }
- - { reg: '$a1' }
+ - { reg: '$r4' }
+ - { reg: '$r5' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: test_memset_inline
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; MIPS32-NEXT: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (s8) into %ir.dst, align 4)
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[TRUNC]](s8), [[PTR_ADD]](p0) :: (store (s8) into %ir.dst + 1, basealign 4)
; MIPS32-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s8) = G_TRUNC %1(s32)
%3:_(s64) = G_CONSTANT i64 2
%4:_(s32) = G_TRUNC %3(s64)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
index b5304cf89e873..17d528e06a59f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
@@ -12,15 +12,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_load1_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: $r2 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s32) = G_ANYEXT %1(s8)
$r2 = COPY %2(s32)
@@ -33,15 +33,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load2_s16_to_load2_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16) from %ir.px)
; MIPS32: $r2 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s16) = G_LOAD %0(p0) :: (load (s16) from %ir.px)
%2:_(s32) = G_ANYEXT %1(s16)
$r2 = COPY %2(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir
index 570ce07ee20f6..f569a71a3a3ae 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir
@@ -10,8 +10,8 @@
# since none of them gets changed in this test.
# MIPS32-LABEL: Generic MI Combiner for: f
-# MIPS32: Try combining %0:_(s32) = COPY $a0
-# MIPS32: Try combining %1:_(s32) = COPY $a1
+# MIPS32: Try combining %0:_(s32) = COPY $r4
+# MIPS32: Try combining %1:_(s32) = COPY $r5
# MIPS32: Try combining %2:_(s32) = G_ADD %1:_, %0:_
# MIPS32: Try combining $r2 = COPY %2:_(s32)
# MIPS32: Try combining RetRA implicit $r2
@@ -20,17 +20,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: f
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_ADD %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
index f9cb66b46aacf..b9efe54a129cc 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
@@ -20,15 +20,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: $r2 = COPY [[ZEXTLOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s32) = G_ZEXT %1(s8)
$r2 = COPY %2(s32)
@@ -41,15 +41,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
; MIPS32: $r2 = COPY [[ZEXTLOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s16) = G_LOAD %0(p0) :: (load (s16) from %ir.px)
%2:_(s32) = G_ZEXT %1(s16)
$r2 = COPY %2(s32)
@@ -62,16 +62,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s16) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXTLOAD]](s16)
; MIPS32: $r2 = COPY [[ANYEXT]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s16) = G_ZEXT %1(s8)
%3:_(s32) = G_ANYEXT %2(s16)
@@ -85,15 +85,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: $r2 = COPY [[ZEXTLOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s16) = G_ZEXT %1(s8)
%3:_(s32) = G_ZEXT %2(s16)
@@ -107,17 +107,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXTLOAD]](s64)
; MIPS32: $r2 = COPY [[UV]](s32)
; MIPS32: $r3 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
%2:_(s64) = G_ZEXT %1(s32)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
@@ -132,15 +132,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: $r2 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s32) = G_SEXT %1(s8)
$r2 = COPY %2(s32)
@@ -153,15 +153,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
; MIPS32: $r2 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s16) = G_LOAD %0(p0) :: (load (s16) from %ir.px)
%2:_(s32) = G_SEXT %1(s16)
$r2 = COPY %2(s32)
@@ -174,16 +174,16 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)
; MIPS32: $r2 = COPY [[ANYEXT]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s16) = G_SEXT %1(s8)
%3:_(s32) = G_ANYEXT %2(s16)
@@ -197,15 +197,15 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: $r2 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
%2:_(s16) = G_SEXT %1(s8)
%3:_(s32) = G_SEXT %2(s16)
@@ -219,17 +219,17 @@ alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $r4
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXTLOAD]](s64)
; MIPS32: $r2 = COPY [[UV]](s32)
; MIPS32: $r3 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
%2:_(s64) = G_SEXT %1(s32)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
index c2c6c84c0c821..49f3f7226b08d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
@@ -13,13 +13,13 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: skipCopiesOutgoing
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.ptr_a)
; MIPS32: [[COPY3:%[0-9]+]]:fprb(s32) = COPY [[LOAD]](s32)
; MIPS32: G_STORE [[COPY3]](s32), [[COPY1]](p0) :: (store (s32) into %ir.ptr_b)
@@ -27,9 +27,9 @@ body: |
; MIPS32: G_STORE [[COPY4]](s32), [[COPY2]](p0) :: (store (s32) into %ir.ptr_c)
; MIPS32: $f0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $f0
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr_a)
%4:_(s32) = COPY %3(s32)
G_STORE %4(s32), %1(p0) :: (store (s32) into %ir.ptr_b)
@@ -46,14 +46,14 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a2, $a3, $f12, $f14
+ liveins: $r6, $r7, $f12, $f14
; MIPS32-LABEL: name: skipCopiesIncoming
- ; MIPS32: liveins: $a2, $a3, $f12, $f14
+ ; MIPS32: liveins: $r6, $r7, $f12, $f14
; MIPS32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; MIPS32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $r7
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.float_ptr)
; MIPS32: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY]]
; MIPS32: [[COPY4:%[0-9]+]]:fprb(s32) = COPY [[FADD]](s32)
@@ -66,8 +66,8 @@ body: |
; MIPS32: RetRA implicit $f0
%0:_(s32) = COPY $f12
%1:_(s32) = COPY $f14
- %2:_(p0) = COPY $a2
- %4:_(s32) = COPY $a3
+ %2:_(p0) = COPY $r6
+ %4:_(s32) = COPY $r7
%5:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.float_ptr)
%6:_(s32) = G_FADD %1, %0
%11:_(s32) = COPY %6(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
index b097d791ae809..8af2ceae565f6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
@@ -12,17 +12,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: add_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_ADD %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
index ad01a4d916f0c..74cb5c1bebeb0 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
@@ -15,21 +15,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:fprb(<16 x s8>) = G_ADD [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_ADD %4, %3
@@ -44,21 +44,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:fprb(<8 x s16>) = G_ADD [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_ADD %4, %3
@@ -73,21 +73,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:fprb(<4 x s32>) = G_ADD [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_ADD %4, %3
@@ -102,21 +102,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: add_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[ADD:%[0-9]+]]:fprb(<2 x s64>) = G_ADD [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_ADD %4, %3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
index f4fd7e8c9a4b4..8a3ec8f967ba2 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir
@@ -21,17 +21,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: and_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_AND %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -44,17 +44,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: or_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[OR]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_OR %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -67,17 +67,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: xor_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[XOR]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_XOR %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -90,16 +90,16 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: shl
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[C]]
; MIPS32: $r2 = COPY [[SHL]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_SHL %0, %1
$r2 = COPY %2(s32)
@@ -113,16 +113,16 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ashr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[C]]
; MIPS32: $r2 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_ASHR %0, %1
$r2 = COPY %2(s32)
@@ -136,16 +136,16 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: lshr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[C]]
; MIPS32: $r2 = COPY [[LSHR]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_LSHR %0, %1
$r2 = COPY %2(s32)
@@ -159,17 +159,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: shlv
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[SHL]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_SHL %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -182,17 +182,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ashrv
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_ASHR %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -205,17 +205,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: lshrv
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[LSHR]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_LSHR %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
index d36b4813e31ef..e247b0fd11193 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir
@@ -33,8 +33,8 @@ body: |
; MIPS32-LABEL: name: Unconditional_branch
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.2(0x80000000)
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.end:
; MIPS32: $r2 = COPY [[COPY]](s32)
@@ -43,9 +43,9 @@ body: |
; MIPS32: successors: %bb.1(0x80000000)
; MIPS32: G_BR %bb.1
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
G_BR %bb.3
bb.2.end:
@@ -65,10 +65,10 @@ body: |
; MIPS32-LABEL: name: Conditional_branch
; MIPS32: bb.0 (%ir-block.0):
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
@@ -81,11 +81,11 @@ body: |
; MIPS32: $r2 = COPY [[COPY2]](s32)
; MIPS32: RetRA implicit $r2
bb.1 (%ir-block.0):
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
+ %3:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
%5:_(s32) = G_CONSTANT i32 1
%6:_(s32) = COPY %3(s32)
%4:_(s32) = G_AND %6, %5
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
index 2226dc0312f65..026acc6d27f2e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
@@ -23,8 +23,8 @@ body: |
; MIPS32-LABEL: name: indirectbr
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: G_BRINDIRECT [[COPY]](p0)
@@ -36,9 +36,9 @@ body: |
; MIPS32: RetRA implicit $r2
bb.1.entry:
successors: %bb.2, %bb.3
- liveins: $a0
+ liveins: $r4
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_CONSTANT i32 0
G_BRINDIRECT %0(p0)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
index 3d6699277afa5..05e22a7f204ca 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir
@@ -12,15 +12,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32R2-LABEL: name: bswap_i32
- ; MIPS32R2: liveins: $a0
- ; MIPS32R2: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32R2: liveins: $r4
+ ; MIPS32R2: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32R2: [[BSWAP:%[0-9]+]]:gprb(s32) = G_BSWAP [[COPY]]
; MIPS32R2: $r2 = COPY [[BSWAP]](s32)
; MIPS32R2: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_BSWAP %0
$r2 = COPY %1(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
index a25bc2fe327b3..2e210e09ec52e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ctlz.mir
@@ -7,15 +7,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ctlz_i32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32: [[CTLZ:%[0-9]+]]:gprb(s32) = G_CTLZ [[COPY]](s32)
; MIPS32: $r2 = COPY [[CTLZ]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_CTLZ %0(s32)
$r2 = COPY %1(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
index 3bdf9b86e4260..a822930f266f4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
@@ -13,18 +13,18 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: fabs_v4f32
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[FABS:%[0-9]+]]:fprb(<4 x s32>) = G_FABS [[LOAD]]
; P5600: G_STORE [[FABS]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:_(<4 x s32>) = G_FABS %2
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
@@ -38,18 +38,18 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: fabs_v2f64
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[FABS:%[0-9]+]]:fprb(<2 x s64>) = G_FABS [[LOAD]]
; P5600: G_STORE [[FABS]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:_(<2 x s64>) = G_FABS %2
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
index af862720be6da..efb4d03e5eb84 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
@@ -12,16 +12,16 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: atomic_load_i32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load monotonic (s32) from %ir.ptr)
; MIPS32: G_FENCE 4, 1
; MIPS32: $r2 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load monotonic (s32) from %ir.ptr)
G_FENCE 4, 1
$r2 = COPY %1(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
index 3fd07c7938824..7771af0440c44 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
@@ -69,19 +69,19 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; FP32-LABEL: name: float_in_gpr
- ; FP32: liveins: $a0, $a1
- ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; FP32: liveins: $r4, $r5
+ ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r5
; FP32: $f0 = COPY [[COPY]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: float_in_gpr
- ; FP64: liveins: $a0, $a1
- ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; FP64: liveins: $r4, $r5
+ ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r5
; FP64: $f0 = COPY [[COPY]](s32)
; FP64: RetRA implicit $f0
- %1:_(s32) = COPY $a1
+ %1:_(s32) = COPY $r5
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -93,24 +93,24 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; FP32-LABEL: name: double_in_gpr
- ; FP32: liveins: $a0, $a2, $a3
- ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a2
- ; FP32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a3
+ ; FP32: liveins: $r4, $r6, $r7
+ ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; FP32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r7
; FP32: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; FP32: $d0 = COPY [[MV]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: double_in_gpr
- ; FP64: liveins: $a0, $a2, $a3
- ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a2
- ; FP64: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a3
+ ; FP64: liveins: $r4, $r6, $r7
+ ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; FP64: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r7
; FP64: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; FP64: $d0 = COPY [[MV]](s64)
; FP64: RetRA implicit $d0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
$d0 = COPY %1(s64)
RetRA implicit $d0
@@ -129,34 +129,34 @@ body: |
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32: $f12 = COPY [[COPY]](s32)
; FP32: $f14 = COPY [[COPY1]](s32)
- ; FP32: JAL @float_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ ; FP32: JAL @float_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit $f14, implicit-def $f0
; FP32: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $f0 = COPY [[COPY2]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: call_float_in_fpr
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64: $f12 = COPY [[COPY]](s32)
; FP64: $f14 = COPY [[COPY1]](s32)
- ; FP64: JAL @float_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ ; FP64: JAL @float_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit $f14, implicit-def $f0
; FP64: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $f0 = COPY [[COPY2]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = COPY $f12
%1:_(s32) = COPY $f14
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
$f12 = COPY %0(s32)
$f14 = COPY %1(s32)
- JAL @float_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ JAL @float_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12, implicit $f14, implicit-def $f0
%2:_(s32) = COPY $f0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$f0 = COPY %2(s32)
RetRA implicit $f0
@@ -174,34 +174,34 @@ body: |
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP32: $d6 = COPY [[COPY]](s64)
; FP32: $d7 = COPY [[COPY1]](s64)
- ; FP32: JAL @double_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+ ; FP32: JAL @double_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit $d7, implicit-def $d0
; FP32: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $d0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $d0 = COPY [[COPY2]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: call_double_in_fpr
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; FP64: $d6 = COPY [[COPY]](s64)
; FP64: $d7 = COPY [[COPY1]](s64)
- ; FP64: JAL @double_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+ ; FP64: JAL @double_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit $d7, implicit-def $d0
; FP64: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $d0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $d0 = COPY [[COPY2]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = COPY $d6
%1:_(s64) = COPY $d7
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
$d6 = COPY %0(s64)
$d7 = COPY %1(s64)
- JAL @double_in_fpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+ JAL @double_in_fpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6, implicit $d7, implicit-def $d0
%2:_(s64) = COPY $d0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$d0 = COPY %2(s64)
RetRA implicit $d0
@@ -213,40 +213,40 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; FP32-LABEL: name: call_float_in_gpr
- ; FP32: liveins: $a0, $a1
- ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32: $a0 = COPY [[COPY]](s32)
- ; FP32: $a1 = COPY [[COPY1]](s32)
- ; FP32: JAL @float_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+ ; FP32: liveins: $r4, $r5
+ ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; FP32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP32: $r4 = COPY [[COPY]](s32)
+ ; FP32: $r5 = COPY [[COPY1]](s32)
+ ; FP32: JAL @float_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $f0
; FP32: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $f0 = COPY [[COPY2]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: call_float_in_gpr
- ; FP64: liveins: $a0, $a1
- ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64: $a0 = COPY [[COPY]](s32)
- ; FP64: $a1 = COPY [[COPY1]](s32)
- ; FP64: JAL @float_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+ ; FP64: liveins: $r4, $r5
+ ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; FP64: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP64: $r4 = COPY [[COPY]](s32)
+ ; FP64: $r5 = COPY [[COPY1]](s32)
+ ; FP64: JAL @float_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $f0
; FP64: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $f0 = COPY [[COPY2]](s32)
; FP64: RetRA implicit $f0
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %0(s32)
- $a1 = COPY %1(s32)
- JAL @float_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %0(s32)
+ $r5 = COPY %1(s32)
+ JAL @float_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $f0
%2:_(s32) = COPY $f0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$f0 = COPY %2(s32)
RetRA implicit $f0
@@ -258,46 +258,46 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; FP32-LABEL: name: call_double_in_gpr
- ; FP32: liveins: $a0, $a2, $a3
- ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a2
- ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a3
- ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32: $a0 = COPY [[COPY]](s32)
- ; FP32: $a2 = COPY [[COPY1]](s32)
- ; FP32: $a3 = COPY [[COPY2]](s32)
- ; FP32: JAL @double_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+ ; FP32: liveins: $r4, $r6, $r7
+ ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; FP32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r7
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP32: $r4 = COPY [[COPY]](s32)
+ ; FP32: $r6 = COPY [[COPY1]](s32)
+ ; FP32: $r7 = COPY [[COPY2]](s32)
+ ; FP32: JAL @double_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $d0
; FP32: [[COPY3:%[0-9]+]]:fprb(s64) = COPY $d0
- ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP32: $d0 = COPY [[COPY3]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: call_double_in_gpr
- ; FP64: liveins: $a0, $a2, $a3
- ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a2
- ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a3
- ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64: $a0 = COPY [[COPY]](s32)
- ; FP64: $a2 = COPY [[COPY1]](s32)
- ; FP64: $a3 = COPY [[COPY2]](s32)
- ; FP64: JAL @double_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+ ; FP64: liveins: $r4, $r6, $r7
+ ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; FP64: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r7
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; FP64: $r4 = COPY [[COPY]](s32)
+ ; FP64: $r6 = COPY [[COPY1]](s32)
+ ; FP64: $r7 = COPY [[COPY2]](s32)
+ ; FP64: JAL @double_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $d0
; FP64: [[COPY3:%[0-9]+]]:fprb(s64) = COPY $d0
- ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; FP64: $d0 = COPY [[COPY3]](s64)
; FP64: RetRA implicit $d0
- %0:_(s32) = COPY $a0
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %0(s32)
- $a2 = COPY %2(s32)
- $a3 = COPY %3(s32)
- JAL @double_in_gpr, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+ %0:_(s32) = COPY $r4
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %0(s32)
+ $r6 = COPY %2(s32)
+ $r7 = COPY %3(s32)
+ JAL @double_in_gpr, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit-def $d0
%4:_(s64) = COPY $d0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$d0 = COPY %4(s64)
RetRA implicit $d0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
index e1ffcb87e777f..e283b94d1662f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
@@ -22,21 +22,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fadd_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FADD:%[0-9]+]]:fprb(<4 x s32>) = G_FADD [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_FADD %3, %4
@@ -51,21 +51,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fadd_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FADD:%[0-9]+]]:fprb(<2 x s64>) = G_FADD [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_FADD %3, %4
@@ -80,21 +80,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fsub_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FSUB:%[0-9]+]]:fprb(<4 x s32>) = G_FSUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FSUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_FSUB %3, %4
@@ -109,21 +109,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fsub_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FSUB:%[0-9]+]]:fprb(<2 x s64>) = G_FSUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FSUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_FSUB %3, %4
@@ -138,21 +138,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fmul_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FMUL:%[0-9]+]]:fprb(<4 x s32>) = G_FMUL [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FMUL]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_FMUL %3, %4
@@ -167,21 +167,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fmul_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FMUL:%[0-9]+]]:fprb(<2 x s64>) = G_FMUL [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FMUL]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_FMUL %3, %4
@@ -196,21 +196,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fdiv_v4f32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[FDIV:%[0-9]+]]:fprb(<4 x s32>) = G_FDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_FDIV %3, %4
@@ -225,21 +225,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: fdiv_v2f64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[FDIV:%[0-9]+]]:fprb(<2 x s64>) = G_FDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[FDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_FDIV %3, %4
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
index f152949e22d85..837eeda98e94b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
@@ -13,18 +13,18 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: sqrt_v4f32
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[FSQRT:%[0-9]+]]:fprb(<4 x s32>) = G_FSQRT [[LOAD]]
; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%3:_(<4 x s32>) = G_FSQRT %2
G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)
@@ -38,18 +38,18 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: sqrt_v2f64
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[FSQRT:%[0-9]+]]:fprb(<2 x s64>) = G_FSQRT [[LOAD]]
; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%3:_(<2 x s64>) = G_FSQRT %2
G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
index 53f09fb3f08ff..28abc42730e68 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
@@ -20,24 +20,24 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY [[GV]](p0)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1234567890
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY]](p0)
- ; MIPS32: $a1 = COPY [[C]](s32)
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY]](p0)
+ ; MIPS32: $r5 = COPY [[C]](s32)
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[C1]](s32)
; MIPS32: RetRA implicit $r2
%2:_(p0) = G_GLOBAL_VALUE @.str
%1:_(p0) = COPY %2(p0)
%3:_(s32) = G_CONSTANT i32 1234567890
%4:_(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %1(p0)
- $a1 = COPY %3(s32)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %1(p0)
+ $r5 = COPY %3(s32)
+ JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
%0:_(s32) = COPY $r2
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$r2 = COPY %4(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
index 77b8d044a4f5d..87c3dad6480cd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir
@@ -13,34 +13,34 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $t9, $r2
+ liveins: $r4, $r5, $r25, $r2
; MIPS32-LABEL: name: call_global
- ; MIPS32: liveins: $a0, $a1, $t9, $r2
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: liveins: $r4, $r5, $r25, $r2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32: [[GV:%[0-9]+]]:gpr32(p0) = G_GLOBAL_VALUE target-flags(mips-got-call) @f
- ; MIPS32: $a0 = COPY [[COPY]](s32)
- ; MIPS32: $a1 = COPY [[COPY1]](s32)
- ; MIPS32: $gp = COPY [[ADDu]]
- ; MIPS32: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ ; MIPS32: $r4 = COPY [[COPY]](s32)
+ ; MIPS32: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32: $r28 = COPY [[ADDu]]
+ ; MIPS32: JALRPseudo [[GV]](p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r28, implicit-def $r2
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY2]](s32)
; MIPS32: RetRA implicit $r2
- %4:gpr32 = ADDu $r2, $t9
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ %4:gpr32 = ADDu $r2, $r25
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
%3:gpr32(p0) = G_GLOBAL_VALUE target-flags(mips-got-call) @f
- $a0 = COPY %0(s32)
- $a1 = COPY %1(s32)
- $gp = COPY %4
- JALRPseudo %3(p0), csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $gp, implicit-def $r2
+ $r4 = COPY %0(s32)
+ $r5 = COPY %1(s32)
+ $r28 = COPY %4
+ JALRPseudo %3(p0), csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r28, implicit-def $r2
%2:_(s32) = COPY $r2
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
$r2 = COPY %2(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
index 96408a12c636e..834a5f7958fbd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
@@ -13,18 +13,18 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: ne_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
; MIPS32: $r2 = COPY [[COPY2]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%4:_(s32) = G_ICMP intpred(ne), %0(s32), %1
%3:_(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
@@ -38,18 +38,18 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: eq_ptr
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
; MIPS32: $r2 = COPY [[COPY2]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%4:_(s32) = G_ICMP intpred(eq), %0(p0), %1
%3:_(s32) = COPY %4(s32)
$r2 = COPY %3(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir
index c448451b12e7a..437171255f611 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir
@@ -24,16 +24,16 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: g_i32
; MIPS32: [[DEF:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[DEF]](s32)
- ; MIPS32: JAL @f_i32, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[DEF]](s32)
+ ; MIPS32: JAL @f_i32, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
%0:_(s32) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %0(s32)
- JAL @f_i32, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %0(s32)
+ JAL @f_i32, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
@@ -47,19 +47,19 @@ body: |
; MIPS32-LABEL: name: g_i64
; MIPS32: [[DEF:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF
; MIPS32: [[DEF1:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[DEF]](s32)
- ; MIPS32: $a1 = COPY [[DEF1]](s32)
- ; MIPS32: JAL @f_i64, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[DEF]](s32)
+ ; MIPS32: $r5 = COPY [[DEF1]](s32)
+ ; MIPS32: JAL @f_i64, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
%0:_(s64) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64)
- $a0 = COPY %1(s32)
- $a1 = COPY %2(s32)
- JAL @f_i64, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ $r4 = COPY %1(s32)
+ $r5 = COPY %2(s32)
+ JAL @f_i64, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
@@ -72,16 +72,16 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: g_float
; MIPS32: [[DEF:%[0-9]+]]:fprb(s32) = G_IMPLICIT_DEF
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $f12 = COPY [[DEF]](s32)
- ; MIPS32: JAL @f_float, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: JAL @f_float, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
%0:_(s32) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
$f12 = COPY %0(s32)
- JAL @f_float, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $f12
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ JAL @f_float, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $f12
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
@@ -95,16 +95,16 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: g_double
; MIPS32: [[DEF:%[0-9]+]]:fprb(s64) = G_IMPLICIT_DEF
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32: $d6 = COPY [[DEF]](s64)
- ; MIPS32: JAL @f_double, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: JAL @f_double, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
%0:_(s64) = G_IMPLICIT_DEF
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
$d6 = COPY %0(s64)
- JAL @f_double, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $d6
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ JAL @f_double, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $d6
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
index 2a1d94fa08baf..2eee2246741ea 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir
@@ -13,15 +13,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: inttoptr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32: [[INTTOPTR:%[0-9]+]]:gprb(p0) = G_INTTOPTR [[COPY]](s32)
; MIPS32: $r2 = COPY [[INTTOPTR]](p0)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(p0) = G_INTTOPTR %0(s32)
$r2 = COPY %1(p0)
RetRA implicit $r2
@@ -34,15 +34,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ptrtoint
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[PTRTOINT:%[0-9]+]]:gprb(s32) = G_PTRTOINT [[COPY]](p0)
; MIPS32: $r2 = COPY [[PTRTOINT]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_PTRTOINT %0(p0)
$r2 = COPY %1(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
index 7972126fefb4d..8b80ef472cc12 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
@@ -72,8 +72,8 @@ body: |
; MIPS32-LABEL: name: mod4_0_to_11
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.6(0x40000000), %bb.1(0x40000000)
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 7
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
; MIPS32: [[C2:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 2
@@ -137,9 +137,9 @@ body: |
; MIPS32: $r2 = COPY [[C5]](s32)
; MIPS32: RetRA implicit $r2
bb.1.entry:
- liveins: $a0
+ liveins: $r4
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%4:_(s32) = G_CONSTANT i32 7
%8:_(s32) = G_CONSTANT i32 3
%9:_(s32) = G_CONSTANT i32 2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
index 3dd38467e81df..378808cfe1dbb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
@@ -17,16 +17,16 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load_i32
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.ptr)
; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
; MIPS32-NEXT: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr)
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -39,12 +39,12 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load_i64
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.ptr, align 8)
; MIPS32-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
@@ -52,7 +52,7 @@ body: |
; MIPS32-NEXT: $r2 = COPY [[LOAD]](s32)
; MIPS32-NEXT: $r3 = COPY [[LOAD1]](s32)
; MIPS32-NEXT: RetRA implicit $r2, implicit $r3
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$r2 = COPY %2(s32)
@@ -67,18 +67,18 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_ambiguous_i64_in_fpr
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir.i64_ptr_a)
; MIPS32-NEXT: G_STORE [[LOAD]](s64), [[COPY1]](p0) :: (store (s64) into %ir.i64_ptr_b)
; MIPS32-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.i64_ptr_a)
G_STORE %2(s64), %1(p0) :: (store (s64) into %ir.i64_ptr_b)
RetRA
@@ -91,16 +91,16 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load_float
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.ptr)
; MIPS32-NEXT: $f0 = COPY [[LOAD]](s32)
; MIPS32-NEXT: RetRA implicit $f0
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr)
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -113,18 +113,18 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_ambiguous_float_in_gpr
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.float_ptr_a)
; MIPS32-NEXT: G_STORE [[LOAD]](s32), [[COPY1]](p0) :: (store (s32) into %ir.float_ptr_b)
; MIPS32-NEXT: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.float_ptr_a)
G_STORE %2(s32), %1(p0) :: (store (s32) into %ir.float_ptr_b)
RetRA
@@ -137,16 +137,16 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load_double
- ; MIPS32: liveins: $a0
+ ; MIPS32: liveins: $r4
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir.ptr)
; MIPS32-NEXT: $d0 = COPY [[LOAD]](s64)
; MIPS32-NEXT: RetRA implicit $d0
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
$d0 = COPY %1(s64)
RetRA implicit $d0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
index 76dba09573596..ba99fa4f48f6f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
@@ -17,17 +17,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v16i8
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: G_STORE [[LOAD]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>) into %ir.a)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
G_STORE %2(<16 x s8>), %0(p0) :: (store (<16 x s8>) into %ir.a)
RetRA
@@ -40,17 +40,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v8i16
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: G_STORE [[LOAD]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>) into %ir.a)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
G_STORE %2(<8 x s16>), %0(p0) :: (store (<8 x s16>) into %ir.a)
RetRA
@@ -63,17 +63,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v4i32
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>) into %ir.a)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>) into %ir.a)
RetRA
@@ -86,17 +86,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v2i64
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.a)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>) into %ir.a)
RetRA
@@ -109,17 +109,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v4f32
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>) into %ir.a)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>) into %ir.a)
RetRA
@@ -132,17 +132,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; P5600-LABEL: name: load_store_v2f64
- ; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; P5600: liveins: $r4, $r5
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.a)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>) into %ir.a)
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
index a2cef932b0f08..c033d62deec3f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
@@ -252,12 +252,12 @@ body: |
; MIPS32-LABEL: name: long_chain_ambiguous_i64_in_fpr
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -363,12 +363,12 @@ body: |
; MIPS32-NEXT: G_STORE [[PHI2]](s64), [[LOAD2]](p0) :: (store (s64) into %ir.result)
; MIPS32-NEXT: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %7:_(s32) = COPY $a0
- %8:_(s32) = COPY $a1
- %9:_(s32) = COPY $a2
- %3:_(p0) = COPY $a3
+ %7:_(s32) = COPY $r4
+ %8:_(s32) = COPY $r5
+ %9:_(s32) = COPY $r6
+ %3:_(p0) = COPY $r7
%10:_(p0) = G_FRAME_INDEX %fixed-stack.2
%4:_(p0) = G_LOAD %10(p0) :: (load (p0) from %fixed-stack.2, align 8)
%11:_(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -468,12 +468,12 @@ body: |
; MIPS32-LABEL: name: long_chain_i64_in_gpr
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -613,12 +613,12 @@ body: |
; MIPS32-NEXT: G_STORE [[PHI5]](s32), [[PTR_ADD8]](p0) :: (store (s32) into %ir.result + 4, basealign 8)
; MIPS32-NEXT: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %7:_(s32) = COPY $a0
- %8:_(s32) = COPY $a1
- %9:_(s32) = COPY $a2
- %3:_(p0) = COPY $a3
+ %7:_(s32) = COPY $r4
+ %8:_(s32) = COPY $r5
+ %9:_(s32) = COPY $r6
+ %3:_(p0) = COPY $r7
%10:_(p0) = G_FRAME_INDEX %fixed-stack.2
%4:_(p0) = G_LOAD %10(p0) :: (load (p0) from %fixed-stack.2, align 8)
%11:_(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -720,12 +720,12 @@ body: |
; MIPS32-LABEL: name: long_chain_ambiguous_double_in_fpr
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -831,12 +831,12 @@ body: |
; MIPS32-NEXT: G_STORE [[PHI2]](s64), [[LOAD2]](p0) :: (store (s64) into %ir.result)
; MIPS32-NEXT: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %7:_(s32) = COPY $a0
- %8:_(s32) = COPY $a1
- %9:_(s32) = COPY $a2
- %3:_(p0) = COPY $a3
+ %7:_(s32) = COPY $r4
+ %8:_(s32) = COPY $r5
+ %9:_(s32) = COPY $r6
+ %3:_(p0) = COPY $r7
%10:_(p0) = G_FRAME_INDEX %fixed-stack.2
%4:_(p0) = G_LOAD %10(p0) :: (load (p0) from %fixed-stack.2, align 8)
%11:_(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -936,12 +936,12 @@ body: |
; MIPS32-LABEL: name: long_chain_double_in_fpr
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -1048,12 +1048,12 @@ body: |
; MIPS32-NEXT: G_STORE [[PHI2]](s64), [[LOAD2]](p0) :: (store (s64) into %ir.result)
; MIPS32-NEXT: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %7:_(s32) = COPY $a0
- %8:_(s32) = COPY $a1
- %9:_(s32) = COPY $a2
- %3:_(p0) = COPY $a3
+ %7:_(s32) = COPY $r4
+ %8:_(s32) = COPY $r5
+ %9:_(s32) = COPY $r6
+ %3:_(p0) = COPY $r7
%10:_(p0) = G_FRAME_INDEX %fixed-stack.2
%4:_(p0) = G_LOAD %10(p0) :: (load (p0) from %fixed-stack.2, align 8)
%11:_(p0) = G_FRAME_INDEX %fixed-stack.1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
index a2cef932b0f08..c033d62deec3f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
@@ -252,12 +252,12 @@ body: |
; MIPS32-LABEL: name: long_chain_ambiguous_i64_in_fpr
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -363,12 +363,12 @@ body: |
; MIPS32-NEXT: G_STORE [[PHI2]](s64), [[LOAD2]](p0) :: (store (s64) into %ir.result)
; MIPS32-NEXT: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %7:_(s32) = COPY $a0
- %8:_(s32) = COPY $a1
- %9:_(s32) = COPY $a2
- %3:_(p0) = COPY $a3
+ %7:_(s32) = COPY $r4
+ %8:_(s32) = COPY $r5
+ %9:_(s32) = COPY $r6
+ %3:_(p0) = COPY $r7
%10:_(p0) = G_FRAME_INDEX %fixed-stack.2
%4:_(p0) = G_LOAD %10(p0) :: (load (p0) from %fixed-stack.2, align 8)
%11:_(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -468,12 +468,12 @@ body: |
; MIPS32-LABEL: name: long_chain_i64_in_gpr
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -613,12 +613,12 @@ body: |
; MIPS32-NEXT: G_STORE [[PHI5]](s32), [[PTR_ADD8]](p0) :: (store (s32) into %ir.result + 4, basealign 8)
; MIPS32-NEXT: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %7:_(s32) = COPY $a0
- %8:_(s32) = COPY $a1
- %9:_(s32) = COPY $a2
- %3:_(p0) = COPY $a3
+ %7:_(s32) = COPY $r4
+ %8:_(s32) = COPY $r5
+ %9:_(s32) = COPY $r6
+ %3:_(p0) = COPY $r7
%10:_(p0) = G_FRAME_INDEX %fixed-stack.2
%4:_(p0) = G_LOAD %10(p0) :: (load (p0) from %fixed-stack.2, align 8)
%11:_(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -720,12 +720,12 @@ body: |
; MIPS32-LABEL: name: long_chain_ambiguous_double_in_fpr
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -831,12 +831,12 @@ body: |
; MIPS32-NEXT: G_STORE [[PHI2]](s64), [[LOAD2]](p0) :: (store (s64) into %ir.result)
; MIPS32-NEXT: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %7:_(s32) = COPY $a0
- %8:_(s32) = COPY $a1
- %9:_(s32) = COPY $a2
- %3:_(p0) = COPY $a3
+ %7:_(s32) = COPY $r4
+ %8:_(s32) = COPY $r5
+ %9:_(s32) = COPY $r6
+ %3:_(p0) = COPY $r7
%10:_(p0) = G_FRAME_INDEX %fixed-stack.2
%4:_(p0) = G_LOAD %10(p0) :: (load (p0) from %fixed-stack.2, align 8)
%11:_(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -936,12 +936,12 @@ body: |
; MIPS32-LABEL: name: long_chain_double_in_fpr
; MIPS32: bb.0.entry:
; MIPS32-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0, $a1, $a2, $a3
+ ; MIPS32-NEXT: liveins: $r4, $r5, $r6, $r7
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -1048,12 +1048,12 @@ body: |
; MIPS32-NEXT: G_STORE [[PHI2]](s64), [[LOAD2]](p0) :: (store (s64) into %ir.result)
; MIPS32-NEXT: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %7:_(s32) = COPY $a0
- %8:_(s32) = COPY $a1
- %9:_(s32) = COPY $a2
- %3:_(p0) = COPY $a3
+ %7:_(s32) = COPY $r4
+ %8:_(s32) = COPY $r5
+ %9:_(s32) = COPY $r6
+ %3:_(p0) = COPY $r7
%10:_(p0) = G_FRAME_INDEX %fixed-stack.2
%4:_(p0) = G_LOAD %10(p0) :: (load (p0) from %fixed-stack.2, align 8)
%11:_(p0) = G_FRAME_INDEX %fixed-stack.1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
index 637e4998a2542..147d35219515a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
@@ -13,17 +13,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: mul_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[MUL]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_MUL %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -36,14 +36,14 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: umul_with_overflow
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
; MIPS32: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]]
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
@@ -54,10 +54,10 @@ body: |
; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store (s32) into %ir.pmul)
; MIPS32: RetRA
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(p0) = COPY $a2
- %3:_(p0) = COPY $a3
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(p0) = COPY $r6
+ %3:_(p0) = COPY $r7
%4:_(s32) = G_MUL %0, %1
%7:_(s32) = G_UMULH %0, %1
%8:_(s32) = G_CONSTANT i32 0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
index 2292396bd4844..92aa063b43296 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
@@ -15,21 +15,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:fprb(<16 x s8>) = G_MUL [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[MUL]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_MUL %4, %3
@@ -44,21 +44,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:fprb(<8 x s16>) = G_MUL [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[MUL]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_MUL %4, %3
@@ -73,21 +73,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:fprb(<4 x s32>) = G_MUL [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[MUL]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_MUL %4, %3
@@ -102,21 +102,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: mul_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[MUL:%[0-9]+]]:fprb(<2 x s64>) = G_MUL [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[MUL]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_MUL %4, %3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
index 9c442b064b4ae..fb6514074e437 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
@@ -108,10 +108,10 @@ body: |
; MIPS32-LABEL: name: phi_i32
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
@@ -127,11 +127,11 @@ body: |
; MIPS32: $r2 = COPY [[PHI]](s32)
; MIPS32: RetRA implicit $r2
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
+ %3:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
%6:_(s32) = G_CONSTANT i32 1
%7:_(s32) = COPY %3(s32)
%5:_(s32) = G_AND %7, %6
@@ -161,10 +161,10 @@ body: |
; MIPS32-LABEL: name: phi_i64
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -186,11 +186,11 @@ body: |
; MIPS32: $r3 = COPY [[PHI1]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
- %3:_(s32) = COPY $a0
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %3:_(s32) = COPY $r4
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%8:_(p0) = G_FRAME_INDEX %fixed-stack.1
%6:_(s32) = G_LOAD %8(p0) :: (load (s32) from %fixed-stack.1, align 8)
@@ -225,11 +225,11 @@ body: |
; MIPS32-LABEL: name: phi_ambiguous_i64_in_fpr
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY1]](p0) :: (load (s64) from %ir.i64_ptr_a)
; MIPS32: [[LOAD1:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY2]](p0) :: (load (s64) from %ir.i64_ptr_b)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
@@ -247,12 +247,12 @@ body: |
; MIPS32: G_STORE [[PHI]](s64), [[COPY3]](p0) :: (store (s64) into %ir.i64_ptr_c)
; MIPS32: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %4:_(s32) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
- %3:_(p0) = COPY $a3
+ %4:_(s32) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
+ %3:_(p0) = COPY $r7
%5:_(s64) = G_LOAD %1(p0) :: (load (s64) from %ir.i64_ptr_a)
%6:_(s64) = G_LOAD %2(p0) :: (load (s64) from %ir.i64_ptr_b)
%9:_(s32) = G_CONSTANT i32 1
@@ -281,10 +281,10 @@ body: |
; MIPS32-LABEL: name: phi_float
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
@@ -300,11 +300,11 @@ body: |
; MIPS32: $f0 = COPY [[PHI]](s32)
; MIPS32: RetRA implicit $f0
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- %3:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
+ %3:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
%6:_(s32) = G_CONSTANT i32 1
%7:_(s32) = COPY %3(s32)
%5:_(s32) = G_AND %7, %6
@@ -331,11 +331,11 @@ body: |
; MIPS32-LABEL: name: phi_ambiguous_float_in_gpr
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.f32_ptr_a)
; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.f32_ptr_b)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
@@ -353,12 +353,12 @@ body: |
; MIPS32: G_STORE [[PHI]](s32), [[COPY3]](p0) :: (store (s32) into %ir.f32_ptr_c)
; MIPS32: RetRA
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
- %4:_(s32) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
- %3:_(p0) = COPY $a3
+ %4:_(s32) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
+ %3:_(p0) = COPY $r7
%5:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.f32_ptr_a)
%6:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.f32_ptr_b)
%9:_(s32) = G_CONSTANT i32 1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
index 3111779e28c2a..0e8f1b5db880f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
@@ -14,15 +14,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ptr_arg_in_regs
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.p)
; MIPS32: $r2 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.p)
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -37,23 +37,23 @@ fixedStack:
- { id: 0, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: ptr_arg_on_stack
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.p)
; MIPS32: $r2 = COPY [[LOAD1]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%5:_(p0) = G_FRAME_INDEX %fixed-stack.0
%4:_(p0) = G_LOAD %5(p0) :: (load (p0) from %fixed-stack.0, align 8)
%6:_(s32) = G_LOAD %4(p0) :: (load (s32) from %ir.p)
@@ -68,14 +68,14 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: ret_ptr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: $r2 = COPY [[COPY]](p0)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
$r2 = COPY %0(p0)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
index 5171c8d5f94af..d058774a5806d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir
@@ -15,17 +15,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sdiv_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[SDIV:%[0-9]+]]:gprb(s32) = G_SDIV [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[SDIV]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_SDIV %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -38,17 +38,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: srem_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[SREM:%[0-9]+]]:gprb(s32) = G_SREM [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[SREM]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_SREM %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -61,17 +61,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: udiv_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[UDIV:%[0-9]+]]:gprb(s32) = G_UDIV [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[UDIV]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_UDIV %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -84,17 +84,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: urem_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[UREM:%[0-9]+]]:gprb(s32) = G_UREM [[COPY1]], [[COPY]]
; MIPS32: $r2 = COPY [[UREM]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_UREM %1, %0
$r2 = COPY %2(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
index 68e1cdb90b3e9..e432690b0e3c6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
@@ -30,21 +30,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:fprb(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_SDIV %3, %4
@@ -59,21 +59,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:fprb(<8 x s16>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_SDIV %3, %4
@@ -88,21 +88,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:fprb(<4 x s32>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_SDIV %3, %4
@@ -117,21 +117,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sdiv_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:fprb(<2 x s64>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_SDIV %3, %4
@@ -146,21 +146,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:fprb(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_SREM %3, %4
@@ -175,21 +175,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:fprb(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_SREM %3, %4
@@ -204,21 +204,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:fprb(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_SREM %3, %4
@@ -233,21 +233,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: srem_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:fprb(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_SREM %3, %4
@@ -262,21 +262,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v16u8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:fprb(<16 x s8>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_UDIV %3, %4
@@ -291,21 +291,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v8u16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:fprb(<8 x s16>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_UDIV %3, %4
@@ -320,21 +320,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v4u32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:fprb(<4 x s32>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_UDIV %3, %4
@@ -349,21 +349,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: udiv_v2u64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:fprb(<2 x s64>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_UDIV %3, %4
@@ -378,21 +378,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v16u8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:fprb(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_UREM %3, %4
@@ -407,21 +407,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v8u16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:fprb(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_UREM %3, %4
@@ -436,21 +436,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v4u32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:fprb(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_UREM %3, %4
@@ -465,21 +465,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: urem_v2u64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:fprb(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_UREM %3, %4
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
index 477910bd7dd5b..259c363f2cb0e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
@@ -18,22 +18,22 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: select_i32
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32: $r2 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $r2
- %3:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
+ %3:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
%6:_(s32) = G_CONSTANT i32 1
%7:_(s32) = COPY %3(s32)
%5:_(s32) = G_AND %7, %6
@@ -49,22 +49,22 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: select_ptr
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32: $r2 = COPY [[SELECT]](p0)
; MIPS32: RetRA implicit $r2
- %3:_(s32) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %3:_(s32) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%6:_(s32) = G_CONSTANT i32 1
%7:_(s32) = COPY %3(s32)
%5:_(s32) = G_AND %7, %6
@@ -83,13 +83,13 @@ fixedStack:
- { id: 1, offset: 16, size: 4, alignment: 8, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a2, $a3
+ liveins: $r4, $r6, $r7
; MIPS32-LABEL: name: select_i64
- ; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
@@ -102,9 +102,9 @@ body: |
; MIPS32: $r2 = COPY [[SELECT]](s32)
; MIPS32: $r3 = COPY [[SELECT1]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %3:_(s32) = COPY $a0
- %4:_(s32) = COPY $a2
- %5:_(s32) = COPY $a3
+ %3:_(s32) = COPY $r4
+ %4:_(s32) = COPY $r6
+ %5:_(s32) = COPY $r7
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%8:_(p0) = G_FRAME_INDEX %fixed-stack.1
%6:_(s32) = G_LOAD %8(p0) :: (load (s32) from %fixed-stack.1, align 8)
@@ -128,14 +128,14 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: select_ambiguous_i64_in_fpr
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY1]](p0) :: (load (s64) from %ir.i64_ptr_a)
; MIPS32: [[LOAD1:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY2]](p0) :: (load (s64) from %ir.i64_ptr_b)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
@@ -144,10 +144,10 @@ body: |
; MIPS32: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s32), [[LOAD]], [[LOAD1]]
; MIPS32: G_STORE [[SELECT]](s64), [[COPY3]](p0) :: (store (s64) into %ir.i64_ptr_c)
; MIPS32: RetRA
- %4:_(s32) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
- %3:_(p0) = COPY $a3
+ %4:_(s32) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
+ %3:_(p0) = COPY $r7
%5:_(s64) = G_LOAD %1(p0) :: (load (s64) from %ir.i64_ptr_a)
%6:_(s64) = G_LOAD %2(p0) :: (load (s64) from %ir.i64_ptr_b)
%9:_(s32) = G_CONSTANT i32 1
@@ -165,13 +165,13 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: select_float
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
@@ -180,9 +180,9 @@ body: |
; MIPS32: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
; MIPS32: $f0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $f0
- %3:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
+ %3:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
%6:_(s32) = G_CONSTANT i32 1
%7:_(s32) = COPY %3(s32)
%5:_(s32) = G_AND %7, %6
@@ -198,14 +198,14 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: select_ambiguous_float_in_gpr
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $r7
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.f32_ptr_a)
; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.f32_ptr_b)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
@@ -214,10 +214,10 @@ body: |
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[LOAD]], [[LOAD1]]
; MIPS32: G_STORE [[SELECT]](s32), [[COPY3]](p0) :: (store (s32) into %ir.f32_ptr_c)
; MIPS32: RetRA
- %4:_(s32) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
- %3:_(p0) = COPY $a3
+ %4:_(s32) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
+ %3:_(p0) = COPY $r7
%5:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.f32_ptr_a)
%6:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.f32_ptr_b)
%9:_(s32) = G_CONSTANT i32 1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
index 047ab470cff94..da7fdf033336e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
@@ -15,21 +15,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: i32tof32
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; FP32: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[COPY]](s32)
; FP32: $f0 = COPY [[SITOFP]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: i32tof32
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; FP64: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[COPY]](s32)
; FP64: $f0 = COPY [[SITOFP]](s32)
; FP64: RetRA implicit $f0
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s32) = G_SITOFP %0(s32)
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -42,21 +42,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: i32tof64
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; FP32: [[SITOFP:%[0-9]+]]:fprb(s64) = G_SITOFP [[COPY]](s32)
; FP32: $d0 = COPY [[SITOFP]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: i32tof64
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; FP64: [[SITOFP:%[0-9]+]]:fprb(s64) = G_SITOFP [[COPY]](s32)
; FP64: $d0 = COPY [[SITOFP]](s64)
; FP64: RetRA implicit $d0
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(s64) = G_SITOFP %0(s32)
$d0 = COPY %1(s64)
RetRA implicit $d0
@@ -69,11 +69,11 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; FP32-LABEL: name: u32tof64
- ; FP32: liveins: $a0
- ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; FP32: liveins: $r4
+ ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; FP32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
; FP32: [[C1:%[0-9]+]]:fprb(s64) = G_FCONSTANT double f0x4330000000000000
@@ -81,15 +81,15 @@ body: |
; FP32: $d0 = COPY [[FSUB]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: u32tof64
- ; FP64: liveins: $a0
- ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; FP64: liveins: $r4
+ ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; FP64: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
; FP64: [[C1:%[0-9]+]]:fprb(s64) = G_FCONSTANT double f0x4330000000000000
; FP64: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[MV]], [[C1]]
; FP64: $d0 = COPY [[FSUB]](s64)
; FP64: RetRA implicit $d0
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%2:_(s32) = G_CONSTANT i32 1127219200
%3:_(s64) = G_MERGE_VALUES %0(s32), %2(s32)
%4:_(s64) = G_FCONSTANT double 0x4330000000000000
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
index d82ada7ccfc65..88d365e619aad 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
@@ -15,48 +15,48 @@ fixedStack:
- { id: 0, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: g
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
- ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY]](s32)
- ; MIPS32: $a1 = COPY [[COPY1]](s32)
- ; MIPS32: $a2 = COPY [[COPY2]](s32)
- ; MIPS32: $a3 = COPY [[COPY3]](s32)
- ; MIPS32: [[COPY4:%[0-9]+]]:gprb(p0) = COPY $sp
+ ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY]](s32)
+ ; MIPS32: $r5 = COPY [[COPY1]](s32)
+ ; MIPS32: $r6 = COPY [[COPY2]](s32)
+ ; MIPS32: $r7 = COPY [[COPY3]](s32)
+ ; MIPS32: [[COPY4:%[0-9]+]]:gprb(p0) = COPY $r29
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 16
; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY4]], [[C]](s32)
; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store (s32) into stack + 16)
- ; MIPS32: JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ ; MIPS32: JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
; MIPS32: [[COPY5:%[0-9]+]]:gprb(s32) = COPY $r2
- ; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
; MIPS32: $r2 = COPY [[COPY5]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(s32) = COPY $a2
- %3:_(s32) = COPY $a3
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(s32) = COPY $r6
+ %3:_(s32) = COPY $r7
%5:_(p0) = G_FRAME_INDEX %fixed-stack.0
%4:_(s32) = G_LOAD %5(p0) :: (load (s32) from %fixed-stack.0, align 8)
- ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %0(s32)
- $a1 = COPY %1(s32)
- $a2 = COPY %2(s32)
- $a3 = COPY %3(s32)
- %7:_(p0) = COPY $sp
+ ADJCALLSTACKDOWN 24, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %0(s32)
+ $r5 = COPY %1(s32)
+ $r6 = COPY %2(s32)
+ $r7 = COPY %3(s32)
+ %7:_(p0) = COPY $r29
%8:_(s32) = G_CONSTANT i32 16
%9:_(p0) = G_PTR_ADD %7, %8(s32)
G_STORE %4(s32), %9(p0) :: (store (s32) into stack + 16, align 4)
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $r2
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit-def $r2
%6:_(s32) = COPY $r2
- ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKUP 24, 0, implicit-def $r29, implicit $r29
$r2 = COPY %6(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
index a688060f7ed66..49bb7b182ed33 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
@@ -15,17 +15,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: store_i32
- ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: liveins: $r4, $r5
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; MIPS32-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32) into %ir.ptr)
; MIPS32-NEXT: RetRA
- %0:_(s32) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(p0) = COPY $r5
G_STORE %0(s32), %1(p0) :: (store (s32) into %ir.ptr)
RetRA
@@ -37,23 +37,23 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: store_i64
- ; MIPS32: liveins: $a0, $a1, $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; MIPS32-NEXT: G_STORE [[COPY]](s32), [[COPY2]](p0) :: (store (s32) into %ir.ptr, align 8)
; MIPS32-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = nuw inbounds G_PTR_ADD [[COPY2]], [[C]](s32)
; MIPS32-NEXT: G_STORE [[COPY1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.ptr + 4, basealign 8)
; MIPS32-NEXT: RetRA
- %2:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
+ %2:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- %1:_(p0) = COPY $a2
+ %1:_(p0) = COPY $r6
G_STORE %0(s64), %1(p0) :: (store (s64) into %ir.ptr)
RetRA
@@ -65,17 +65,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a1, $f12
+ liveins: $r5, $f12
; MIPS32-LABEL: name: store_float
- ; MIPS32: liveins: $a1, $f12
+ ; MIPS32: liveins: $r5, $f12
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; MIPS32-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32) into %ir.ptr)
; MIPS32-NEXT: RetRA
%0:_(s32) = COPY $f12
- %1:_(p0) = COPY $a1
+ %1:_(p0) = COPY $r5
G_STORE %0(s32), %1(p0) :: (store (s32) into %ir.ptr)
RetRA
@@ -87,17 +87,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a2, $d6
+ liveins: $r6, $d6
; MIPS32-LABEL: name: store_double
- ; MIPS32: liveins: $a2, $d6
+ ; MIPS32: liveins: $r6, $d6
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r6
; MIPS32-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64) into %ir.ptr)
; MIPS32-NEXT: RetRA
%0:_(s64) = COPY $d6
- %1:_(p0) = COPY $a2
+ %1:_(p0) = COPY $r6
G_STORE %0(s64), %1(p0) :: (store (s64) into %ir.ptr)
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
index 9e0b3608ba3d6..4653051ce7b3b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
@@ -88,21 +88,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: store_i32_align8
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store (s32) into @i32_align8, align 8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i32_align8
- ; MIPS32R6: liveins: $a0
- ; MIPS32R6: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32R6: liveins: $r4
+ ; MIPS32R6: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store (s32) into @i32_align8, align 8)
; MIPS32R6: RetRA
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
G_STORE %0(s32), %1(p0) :: (store (s32) into @i32_align8, align 8)
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
index a21b33cd4a99f..a2b1bc7434b8d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
@@ -12,17 +12,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: sub_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[COPY1]]
; MIPS32: $r2 = COPY [[SUB]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(s32) = G_SUB %0, %1
$r2 = COPY %2(s32)
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
index bc8153b342fc0..76a464cc3fc8e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
@@ -15,21 +15,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v16i8
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:fprb(<16 x s8>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_SUB %4, %3
@@ -44,21 +44,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v8i16
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:fprb(<8 x s16>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_SUB %4, %3
@@ -73,21 +73,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v4i32
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:fprb(<4 x s32>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_SUB %4, %3
@@ -102,21 +102,21 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; P5600-LABEL: name: sub_v2i64
- ; P5600: liveins: $a0, $a1, $a2
- ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
- ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; P5600: liveins: $r4, $r5, $r6
+ ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
+ ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SUB:%[0-9]+]]:fprb(<2 x s64>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
+ %2:_(p0) = COPY $r6
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_SUB %4, %3
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
index 87855bc6a1977..f2327ec2541ac 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
@@ -19,15 +19,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: outgoing_gpr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.i32_ptr)
; MIPS32: $r2 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.i32_ptr)
$r2 = COPY %1(s32)
RetRA implicit $r2
@@ -40,15 +40,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: outgoing_fpr
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.float_ptr)
; MIPS32: $f0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $f0
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.float_ptr)
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -61,19 +61,19 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: outgoing_gpr_instr
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.i32_ptr1)
; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.i32_ptr2)
; MIPS32: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[LOAD1]], [[LOAD]]
; MIPS32: $r2 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.i32_ptr1)
%3:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.i32_ptr2)
%4:_(s32) = G_ADD %3, %2
@@ -88,19 +88,19 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: outgoing_fpr_instr
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.float_ptr1)
; MIPS32: [[LOAD1:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.float_ptr2)
; MIPS32: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[LOAD]], [[LOAD1]]
; MIPS32: $f0 = COPY [[FADD]](s32)
; MIPS32: RetRA implicit $f0
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.float_ptr1)
%3:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.float_ptr2)
%4:_(s32) = G_FADD %2, %3
@@ -115,13 +115,13 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
; MIPS32-LABEL: name: incoming_gpr
- ; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; MIPS32: liveins: $r4, $r5, $r6
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.a)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY1]](s32)
@@ -129,9 +129,9 @@ body: |
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[LOAD]], [[COPY]]
; MIPS32: $r2 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %3:_(s32) = COPY $a1
- %2:_(p0) = COPY $a2
+ %0:_(s32) = COPY $r4
+ %3:_(s32) = COPY $r5
+ %2:_(p0) = COPY $r6
%4:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.a)
%7:_(s32) = G_CONSTANT i32 1
%8:_(s32) = COPY %3(s32)
@@ -148,13 +148,13 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a1, $a2, $f12
+ liveins: $r5, $r6, $f12
; MIPS32-LABEL: name: incoming_fpr
- ; MIPS32: liveins: $a1, $a2, $f12
+ ; MIPS32: liveins: $r5, $r6, $f12
; MIPS32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.a)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY1]](s32)
@@ -163,8 +163,8 @@ body: |
; MIPS32: $f0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $f0
%0:_(s32) = COPY $f12
- %3:_(s32) = COPY $a1
- %2:_(p0) = COPY $a2
+ %3:_(s32) = COPY $r5
+ %2:_(p0) = COPY $r6
%4:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.a)
%7:_(s32) = G_CONSTANT i32 1
%8:_(s32) = COPY %3(s32)
@@ -181,14 +181,14 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: incoming_i32_instr
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $r7
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.i32_ptr)
; MIPS32: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
@@ -197,10 +197,10 @@ body: |
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[LOAD]], [[ADD]]
; MIPS32: $r2 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(s32) = COPY $a0
- %1:_(s32) = COPY $a1
- %2:_(p0) = COPY $a2
- %4:_(s32) = COPY $a3
+ %0:_(s32) = COPY $r4
+ %1:_(s32) = COPY $r5
+ %2:_(p0) = COPY $r6
+ %4:_(s32) = COPY $r7
%5:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.i32_ptr)
%6:_(s32) = G_ADD %1, %0
%9:_(s32) = G_CONSTANT i32 1
@@ -218,14 +218,14 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a2, $a3, $f12, $f14
+ liveins: $r6, $r7, $f12, $f14
; MIPS32-LABEL: name: incoming_float_instr
- ; MIPS32: liveins: $a2, $a3, $f12, $f14
+ ; MIPS32: liveins: $r6, $r7, $f12, $f14
; MIPS32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; MIPS32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $r6
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $r7
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.float_ptr)
; MIPS32: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
@@ -236,8 +236,8 @@ body: |
; MIPS32: RetRA implicit $f0
%0:_(s32) = COPY $f12
%1:_(s32) = COPY $f14
- %2:_(p0) = COPY $a2
- %4:_(s32) = COPY $a3
+ %2:_(p0) = COPY $r6
+ %4:_(s32) = COPY $r7
%5:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.float_ptr)
%6:_(s32) = G_FADD %1, %0
%9:_(s32) = G_CONSTANT i32 1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
index 0a5d01e806eb5..663d1bccb3fca 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
@@ -14,18 +14,18 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_store_i8
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.py)
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[LOAD]](s32)
; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s8) into %ir.px)
; MIPS32: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%4:_(s32) = G_LOAD %1(p0) :: (load (s8) from %ir.py)
%3:_(s32) = COPY %4(s32)
G_STORE %3(s32), %0(p0) :: (store (s8) into %ir.px)
@@ -39,18 +39,18 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_store_i16
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load (s16) from %ir.py)
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[LOAD]](s32)
; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s16) into %ir.px)
; MIPS32: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%4:_(s32) = G_LOAD %1(p0) :: (load (s16) from %ir.py)
%3:_(s32) = COPY %4(s32)
G_STORE %3(s32), %0(p0) :: (store (s16) into %ir.px)
@@ -64,17 +64,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
; MIPS32-LABEL: name: load_store_i32
- ; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $r5
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.py)
; MIPS32: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s32) into %ir.px)
; MIPS32: RetRA
- %0:_(p0) = COPY $a0
- %1:_(p0) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(p0) = COPY $r5
%2:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.py)
G_STORE %2(s32), %0(p0) :: (store (s32) into %ir.px)
RetRA
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
index 6d739b9125e99..cc7ea12c22625 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
@@ -37,7 +37,7 @@ alignment: 4
legalized: true
tracksRegLiveness: true
liveins:
- - { reg: '$a0' }
+ - { reg: '$r4' }
fixedStack:
- { id: 0, offset: 12, size: 4, alignment: 4, isImmutable: true }
- { id: 1, offset: 8, size: 4, alignment: 8, isImmutable: true }
@@ -51,18 +51,18 @@ stack:
machineFunctionInfo: {}
body: |
bb.1.entry:
- liveins: $a0, $a1, $a2, $a3
+ liveins: $r4, $r5, $r6, $r7
; MIPS32-LABEL: name: testVaCopyArg
- ; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+ ; MIPS32: liveins: $r4, $r5, $r6, $r7
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $r5
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
; MIPS32: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)
- ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $r6
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.2
; MIPS32: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.2)
- ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $r7
; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.3
; MIPS32: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.3)
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @.str
@@ -82,20 +82,20 @@ body: |
; MIPS32: [[LOAD1:%[0-9]+]]:gprb(p0) = G_LOAD [[LOAD]](p0) :: (load (p0) from %ir.2)
; MIPS32: G_STORE [[LOAD1]](p0), [[FRAME_INDEX6]](p0) :: (store (p0) into %ir.s)
; MIPS32: [[LOAD2:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX6]](p0) :: (load (p0) from %ir.s)
- ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; MIPS32: $a0 = COPY [[COPY4]](p0)
- ; MIPS32: $a1 = COPY [[LOAD2]](p0)
- ; MIPS32: JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
- ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; MIPS32: $r4 = COPY [[COPY4]](p0)
+ ; MIPS32: $r5 = COPY [[LOAD2]](p0)
+ ; MIPS32: JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
+ ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; MIPS32: RetRA
- %0:_(p0) = COPY $a0
- %1:_(s32) = COPY $a1
+ %0:_(p0) = COPY $r4
+ %1:_(s32) = COPY $r5
%2:_(p0) = G_FRAME_INDEX %fixed-stack.2
G_STORE %1(s32), %2(p0) :: (store (s32) into %fixed-stack.2)
- %3:_(s32) = COPY $a2
+ %3:_(s32) = COPY $r6
%4:_(p0) = G_FRAME_INDEX %fixed-stack.1
G_STORE %3(s32), %4(p0) :: (store (s32) into %fixed-stack.1)
- %5:_(s32) = COPY $a3
+ %5:_(s32) = COPY $r7
%6:_(p0) = G_FRAME_INDEX %fixed-stack.0
G_STORE %5(s32), %6(p0) :: (store (s32) into %fixed-stack.0)
%18:_(p0) = G_GLOBAL_VALUE @.str
@@ -115,11 +115,11 @@ body: |
%14:_(p0) = G_LOAD %11(p0) :: (load (p0) from %ir.2)
G_STORE %14(p0), %10(p0) :: (store (p0) into %ir.s)
%15:_(p0) = G_LOAD %10(p0) :: (load (p0) from %ir.s)
- ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- $a0 = COPY %17(p0)
- $a1 = COPY %15(p0)
- JAL @printf, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $r2
- ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ $r4 = COPY %17(p0)
+ $r5 = COPY %15(p0)
+ JAL @printf, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit $r4, implicit $r5, implicit-def $r2
+ ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
RetRA
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
index 59cc1bb0fca59..43c70681275e5 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
@@ -17,15 +17,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: $r2 = COPY [[ZEXTLOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -38,15 +38,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
; MIPS32: $r2 = COPY [[ZEXTLOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -59,17 +59,17 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: $r2 = COPY [[LOAD]](s32)
; MIPS32: $r3 = COPY [[C]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%5:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
%6:_(s32) = G_CONSTANT i32 0
%2:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
@@ -86,15 +86,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
; MIPS32: $r2 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -107,15 +107,15 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
; MIPS32: $r2 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $r2
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
$r2 = COPY %2(s32)
RetRA implicit $r2
@@ -128,11 +128,11 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $r4
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
@@ -141,7 +141,7 @@ body: |
; MIPS32: $r2 = COPY [[LOAD]](s32)
; MIPS32: $r3 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %0:_(p0) = COPY $a0
+ %0:_(p0) = COPY $r4
%5:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
%9:_(s32) = G_CONSTANT i32 31
%10:_(s32) = G_CONSTANT i32 0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
index efc2caf14921f..93046da99dbc6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
@@ -13,16 +13,16 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: zext
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: $r2 = COPY [[COPY]](s32)
; MIPS32: $r3 = COPY [[C]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%4:_(s32) = G_CONSTANT i32 0
%1:_(s64) = G_MERGE_VALUES %0(s32), %4(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
@@ -38,11 +38,11 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
- liveins: $a0
+ liveins: $r4
; MIPS32-LABEL: name: sext
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: liveins: $r4
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $r4
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
@@ -50,7 +50,7 @@ body: |
; MIPS32: $r2 = COPY [[COPY]](s32)
; MIPS32: $r3 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $r2, implicit $r3
- %0:_(s32) = COPY $a0
+ %0:_(s32) = COPY $r4
%7:_(s32) = G_CONSTANT i32 31
%8:_(s32) = G_CONSTANT i32 0
%6:_(s32) = COPY %7(s32)
diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll b/llvm/test/CodeGen/Mips/atomic-min-max.ll
index 5849ba13cc37a..a57cb98e53b7a 100644
--- a/llvm/test/CodeGen/Mips/atomic-min-max.ll
+++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll
@@ -189,7 +189,7 @@ define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64-LABEL: test_max_32:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64-NEXT: sync
; MIPS64-NEXT: .LBB0_1: # %entry
; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1
@@ -207,7 +207,7 @@ define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64R6-LABEL: test_max_32:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64R6-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64R6-NEXT: sync
; MIPS64R6-NEXT: .LBB0_1: # %entry
; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1
@@ -224,7 +224,7 @@ define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64EL-LABEL: test_max_32:
; MIPS64EL: # %bb.0: # %entry
-; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64EL-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64EL-NEXT: sync
; MIPS64EL-NEXT: .LBB0_1: # %entry
; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1
@@ -242,7 +242,7 @@ define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64ELR6-LABEL: test_max_32:
; MIPS64ELR6: # %bb.0: # %entry
-; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64ELR6-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64ELR6-NEXT: sync
; MIPS64ELR6-NEXT: .LBB0_1: # %entry
; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1
@@ -436,7 +436,7 @@ define i32 @test_min_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64-LABEL: test_min_32:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64-NEXT: sync
; MIPS64-NEXT: .LBB1_1: # %entry
; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1
@@ -454,7 +454,7 @@ define i32 @test_min_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64R6-LABEL: test_min_32:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64R6-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64R6-NEXT: sync
; MIPS64R6-NEXT: .LBB1_1: # %entry
; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1
@@ -471,7 +471,7 @@ define i32 @test_min_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64EL-LABEL: test_min_32:
; MIPS64EL: # %bb.0: # %entry
-; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64EL-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64EL-NEXT: sync
; MIPS64EL-NEXT: .LBB1_1: # %entry
; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1
@@ -489,7 +489,7 @@ define i32 @test_min_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64ELR6-LABEL: test_min_32:
; MIPS64ELR6: # %bb.0: # %entry
-; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64ELR6-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64ELR6-NEXT: sync
; MIPS64ELR6-NEXT: .LBB1_1: # %entry
; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1
@@ -683,7 +683,7 @@ define i32 @test_umax_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64-LABEL: test_umax_32:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64-NEXT: sync
; MIPS64-NEXT: .LBB2_1: # %entry
; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1
@@ -701,7 +701,7 @@ define i32 @test_umax_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64R6-LABEL: test_umax_32:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64R6-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64R6-NEXT: sync
; MIPS64R6-NEXT: .LBB2_1: # %entry
; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1
@@ -718,7 +718,7 @@ define i32 @test_umax_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64EL-LABEL: test_umax_32:
; MIPS64EL: # %bb.0: # %entry
-; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64EL-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64EL-NEXT: sync
; MIPS64EL-NEXT: .LBB2_1: # %entry
; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1
@@ -736,7 +736,7 @@ define i32 @test_umax_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64ELR6-LABEL: test_umax_32:
; MIPS64ELR6: # %bb.0: # %entry
-; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64ELR6-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64ELR6-NEXT: sync
; MIPS64ELR6-NEXT: .LBB2_1: # %entry
; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1
@@ -930,7 +930,7 @@ define i32 @test_umin_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64-LABEL: test_umin_32:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64-NEXT: sync
; MIPS64-NEXT: .LBB3_1: # %entry
; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1
@@ -948,7 +948,7 @@ define i32 @test_umin_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64R6-LABEL: test_umin_32:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64R6-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64R6-NEXT: sync
; MIPS64R6-NEXT: .LBB3_1: # %entry
; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1
@@ -965,7 +965,7 @@ define i32 @test_umin_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64EL-LABEL: test_umin_32:
; MIPS64EL: # %bb.0: # %entry
-; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64EL-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64EL-NEXT: sync
; MIPS64EL-NEXT: .LBB3_1: # %entry
; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1
@@ -983,7 +983,7 @@ define i32 @test_umin_32(ptr nocapture %ptr, i32 signext %val) {
;
; MIPS64ELR6-LABEL: test_umin_32:
; MIPS64ELR6: # %bb.0: # %entry
-; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64
+; MIPS64ELR6-NEXT: # kill: def $r5 killed $r5 killed $r5_64
; MIPS64ELR6-NEXT: sync
; MIPS64ELR6-NEXT: .LBB3_1: # %entry
; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/Mips/atomic.ll b/llvm/test/CodeGen/Mips/atomic.ll
index f83de83b3d037..4e5bc80214f63 100644
--- a/llvm/test/CodeGen/Mips/atomic.ll
+++ b/llvm/test/CodeGen/Mips/atomic.ll
@@ -190,7 +190,7 @@ define i32 @AtomicLoadAdd32(i32 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd32)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd32)))
-; MIPS64R6O0-NEXT: # kill: def $a0 killed $a0 killed $a0_64
+; MIPS64R6O0-NEXT: # kill: def $r4 killed $r4 killed $r4_64
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB0_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
@@ -446,7 +446,7 @@ define i32 @AtomicLoadSub32(i32 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadSub32)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub32)))
-; MIPS64R6O0-NEXT: # kill: def $a0 killed $a0 killed $a0_64
+; MIPS64R6O0-NEXT: # kill: def $r4 killed $r4 killed $r4_64
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB1_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
@@ -702,7 +702,7 @@ define i32 @AtomicLoadXor32(i32 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadXor32)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadXor32)))
-; MIPS64R6O0-NEXT: # kill: def $a0 killed $a0 killed $a0_64
+; MIPS64R6O0-NEXT: # kill: def $r4 killed $r4 killed $r4_64
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB2_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
@@ -957,7 +957,7 @@ define i32 @AtomicLoadOr32(i32 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadOr32)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadOr32)))
-; MIPS64R6O0-NEXT: # kill: def $a0 killed $a0 killed $a0_64
+; MIPS64R6O0-NEXT: # kill: def $r4 killed $r4 killed $r4_64
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB3_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1212,7 +1212,7 @@ define i32 @AtomicLoadAnd32(i32 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAnd32)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAnd32)))
-; MIPS64R6O0-NEXT: # kill: def $a0 killed $a0 killed $a0_64
+; MIPS64R6O0-NEXT: # kill: def $r4 killed $r4 killed $r4_64
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB4_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1476,7 +1476,7 @@ define i32 @AtomicLoadNand32(i32 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadNand32)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand32)))
-; MIPS64R6O0-NEXT: # kill: def $a0 killed $a0 killed $a0_64
+; MIPS64R6O0-NEXT: # kill: def $r4 killed $r4 killed $r4_64
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB5_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
@@ -2094,7 +2094,7 @@ define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicCmpSwap32)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicCmpSwap32)))
-; MIPS64R6O0-NEXT: # kill: def $a0 killed $a0 killed $a0_64
+; MIPS64R6O0-NEXT: # kill: def $r4 killed $r4 killed $r4_64
; MIPS64R6O0-NEXT: move $2, $5
; MIPS64R6O0-NEXT: sw $2, 12($sp)
; MIPS64R6O0-NEXT: lw $5, 12($sp)
@@ -6679,7 +6679,7 @@ define i32 @CheckSync(i32 signext %v) nounwind noinline {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(CheckSync)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(CheckSync)))
-; MIPS64R6O0-NEXT: # kill: def $a0 killed $a0 killed $a0_64
+; MIPS64R6O0-NEXT: # kill: def $r4 killed $r4 killed $r4_64
; MIPS64R6O0-NEXT: sync
; MIPS64R6O0-NEXT: ld $3, %got_disp(countsint)($1)
; MIPS64R6O0-NEXT: .LBB16_1: # %entry
@@ -7370,7 +7370,7 @@ define i32 @AtomicLoadAdd32_OffGt9Bit(i32 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd32_OffGt9Bit)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd32_OffGt9Bit)))
-; MIPS64R6O0-NEXT: # kill: def $a0 killed $a0 killed $a0_64
+; MIPS64R6O0-NEXT: # kill: def $r4 killed $r4 killed $r4_64
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
; MIPS64R6O0-NEXT: daddiu $3, $1, 1024
; MIPS64R6O0-NEXT: .LBB18_1: # %entry
diff --git a/llvm/test/CodeGen/Mips/avoid-zero-copy.mir b/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
index 73e2b66cfddfc..e8f628099ab9a 100644
--- a/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
+++ b/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
@@ -23,21 +23,21 @@ frameInfo:
adjustsStack: true
body: |
bb.0 (%ir-block.0):
- liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
+ liveins: $r4_64, $r25_64, $r31_64, $r30_64, $r28_64
; CHECK-LABEL: name: a
- ; CHECK: liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
+ ; CHECK: liveins: $r4_64, $r25_64, $r31_64, $r30_64, $r28_64
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: $a0_64 = COPY $zero_64
- ; CHECK-NEXT: JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: $a0_64 = COPY $zero_64
- ; CHECK-NEXT: PseudoReturn64 undef $ra_64, implicit $r2_64, implicit killed $a0_64
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- renamable $s0_64 = COPY $zero_64
- $a0_64 = COPY renamable $s0_64
- JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- $a0_64 = COPY killed renamable $s0_64
- PseudoReturn64 undef $ra_64, implicit $r2_64, implicit killed $a0_64
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
+ ; CHECK-NEXT: $r4_64 = COPY $r0_64
+ ; CHECK-NEXT: JALR64Pseudo $r25_64, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
+ ; CHECK-NEXT: $r4_64 = COPY $r0_64
+ ; CHECK-NEXT: PseudoReturn64 undef $r31_64, implicit $r2_64, implicit killed $r4_64
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
+ renamable $r16_64 = COPY $r0_64
+ $r4_64 = COPY renamable $r16_64
+ JALR64Pseudo $r25_64, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
+ $r4_64 = COPY killed renamable $r16_64
+ PseudoReturn64 undef $r31_64, implicit $r2_64, implicit killed $r4_64
...
diff --git a/llvm/test/CodeGen/Mips/branch-dead-at.mir b/llvm/test/CodeGen/Mips/branch-dead-at.mir
index 87cf9146b449a..d8192ab605bab 100644
--- a/llvm/test/CodeGen/Mips/branch-dead-at.mir
+++ b/llvm/test/CodeGen/Mips/branch-dead-at.mir
@@ -11,39 +11,39 @@ body: |
; CHECK-LABEL: name: invert_cond_branch
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x60000000), %bb.1(0x20000000)
- ; CHECK-NEXT: liveins: $a0
+ ; CHECK-NEXT: liveins: $r4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: BEQ renamable $a0, $zero, %bb.1, implicit-def dead $at
+ ; CHECK-NEXT: BEQ renamable $r4, $r0, %bb.1, implicit-def dead $r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: $v0 = ADDiu $zero, 2
- ; CHECK-NEXT: PseudoReturn undef $ra, implicit killed $v0
+ ; CHECK-NEXT: $r2 = ADDiu $r0, 2
+ ; CHECK-NEXT: PseudoReturn undef $r31, implicit killed $r2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: $v0 = ADDiu $zero, 1
- ; CHECK-NEXT: PseudoReturn undef $ra, implicit killed $v0
+ ; CHECK-NEXT: $r2 = ADDiu $r0, 1
+ ; CHECK-NEXT: PseudoReturn undef $r31, implicit killed $r2
bb.0:
successors: %bb.2(0x60000000), %bb.1(0x20000000)
- liveins: $a0
+ liveins: $r4
- BNE renamable $a0, $zero, %bb.2, implicit-def dead $at
- B %bb.1, implicit-def dead $at
+ BNE renamable $r4, $r0, %bb.2, implicit-def dead $r1
+ B %bb.1, implicit-def dead $r1
bb.1:
successors: %bb.3(0x80000000)
- $v0 = ADDiu $zero, 1
- B %bb.3, implicit-def dead $at
+ $r2 = ADDiu $r0, 1
+ B %bb.3, implicit-def dead $r1
bb.2:
successors: %bb.3(0x80000000)
- $v0 = ADDiu $zero, 2
+ $r2 = ADDiu $r0, 2
bb.3:
- liveins: $v0
+ liveins: $r2
- PseudoReturn undef $ra, implicit killed $v0
+ PseudoReturn undef $r31, implicit killed $r2
...
---
name: insert_uncond_branch
@@ -52,57 +52,57 @@ body: |
; CHECK-LABEL: name: insert_uncond_branch
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x70000000), %bb.2(0x10000000)
- ; CHECK-NEXT: liveins: $a0
+ ; CHECK-NEXT: liveins: $r4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: BNE renamable $a0, $zero, %bb.2, implicit-def dead $at
+ ; CHECK-NEXT: BNE renamable $r4, $r0, %bb.2, implicit-def dead $r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $v0 = ADDiu $zero, 1
+ ; CHECK-NEXT: $r2 = ADDiu $r0, 1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
- ; CHECK-NEXT: liveins: $v0
+ ; CHECK-NEXT: liveins: $r2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $v0 = ADDiu killed $v0, 3
- ; CHECK-NEXT: $v0 = ADDiu killed $v0, 4
- ; CHECK-NEXT: $v0 = ADDiu killed $v0, 5
- ; CHECK-NEXT: $v0 = ADDiu killed $v0, 6
- ; CHECK-NEXT: $v0 = ADDiu killed $v0, 7
- ; CHECK-NEXT: $v0 = ADDiu killed $v0, 8
- ; CHECK-NEXT: PseudoReturn undef $ra, implicit killed $v0
+ ; CHECK-NEXT: $r2 = ADDiu killed $r2, 3
+ ; CHECK-NEXT: $r2 = ADDiu killed $r2, 4
+ ; CHECK-NEXT: $r2 = ADDiu killed $r2, 5
+ ; CHECK-NEXT: $r2 = ADDiu killed $r2, 6
+ ; CHECK-NEXT: $r2 = ADDiu killed $r2, 7
+ ; CHECK-NEXT: $r2 = ADDiu killed $r2, 8
+ ; CHECK-NEXT: PseudoReturn undef $r31, implicit killed $r2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $v0 = ADDiu $zero, 2
- ; CHECK-NEXT: J %bb.3, implicit-def dead $at
+ ; CHECK-NEXT: $r2 = ADDiu $r0, 2
+ ; CHECK-NEXT: J %bb.3, implicit-def dead $r1
bb.0:
successors: %bb.1(0x70000000), %bb.2(0x10000000)
- liveins: $a0
+ liveins: $r4
- BNE renamable $a0, $zero, %bb.2, implicit-def dead $at
- B %bb.1, implicit-def dead $at
+ BNE renamable $r4, $r0, %bb.2, implicit-def dead $r1
+ B %bb.1, implicit-def dead $r1
bb.1:
successors: %bb.3(0x80000000)
- $v0 = ADDiu $zero, 1
- B %bb.3, implicit-def dead $at
+ $r2 = ADDiu $r0, 1
+ B %bb.3, implicit-def dead $r1
bb.2:
successors: %bb.3(0x80000000)
- $v0 = ADDiu $zero, 2
+ $r2 = ADDiu $r0, 2
bb.3:
- liveins: $v0
-
- $v0 = ADDiu killed $v0, 3
- $v0 = ADDiu killed $v0, 4
- $v0 = ADDiu killed $v0, 5
- $v0 = ADDiu killed $v0, 6
- $v0 = ADDiu killed $v0, 7
- $v0 = ADDiu killed $v0, 8
- PseudoReturn undef $ra, implicit killed $v0
+ liveins: $r2
+
+ $r2 = ADDiu killed $r2, 3
+ $r2 = ADDiu killed $r2, 4
+ $r2 = ADDiu killed $r2, 5
+ $r2 = ADDiu killed $r2, 6
+ $r2 = ADDiu killed $r2, 7
+ $r2 = ADDiu killed $r2, 8
+ PseudoReturn undef $r31, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll b/llvm/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll
index 2c9eb9f55cd74..9d487405d2b33 100644
--- a/llvm/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll
+++ b/llvm/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll
@@ -15,14 +15,14 @@
define double @foo2(i32 signext %v1, double %d1) {
entry:
-; FPXX-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
-; FPXX-IMPLICIT-SP: ExtractElementF64 %{{[0-9]+}}, 1, implicit $sp
-; FP64-IMPLICIT-SP: BuildPairF64_64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
-; FP64-IMPLICIT-SP: ExtractElementF64_64 %{{[0-9]+}}, 1, implicit $sp
+; FPXX-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $r29
+; FPXX-IMPLICIT-SP: ExtractElementF64 %{{[0-9]+}}, 1, implicit $r29
+; FP64-IMPLICIT-SP: BuildPairF64_64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $r29
+; FP64-IMPLICIT-SP: ExtractElementF64_64 %{{[0-9]+}}, 1, implicit $r29
; NO-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}
-; NO-IMPLICIT-SP-NOT: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
+; NO-IMPLICIT-SP-NOT: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $r29
; NO-IMPLICIT-SP: ExtractElementF64 %{{[0-9]+}}, 1
-; NO-IMPLICIT-SP-NOT: ExtractElementF64 %{{[0-9]+}}, 1, implicit $sp
+; NO-IMPLICIT-SP-NOT: ExtractElementF64 %{{[0-9]+}}, 1, implicit $r29
%conv = fptrunc double %d1 to float
%0 = tail call float @llvm.copysign.f32(float 1.000000e+00, float %conv)
%conv1 = fpext float %0 to double
diff --git a/llvm/test/CodeGen/Mips/call-site-info-output.ll b/llvm/test/CodeGen/Mips/call-site-info-output.ll
index e07c013efd62d..6bd6f17a33f10 100644
--- a/llvm/test/CodeGen/Mips/call-site-info-output.ll
+++ b/llvm/test/CodeGen/Mips/call-site-info-output.ll
@@ -39,17 +39,17 @@
; CHECK: name: fn2
; CHECK: callSites:
; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
-; CHECK-NEXT: arg: 0, reg: '$a0'
-; CHECK-NEXT: arg: 1, reg: '$a1'
-; CHECK-NEXT: arg: 2, reg: '$a2'
+; CHECK-NEXT: arg: 0, reg: '$r4'
+; CHECK-NEXT: arg: 1, reg: '$r5'
+; CHECK-NEXT: arg: 2, reg: '$r6'
;; Test mips64 and mips64el:
; CHECK64: name: fn2
; CHECK64: callSites:
; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
-; CHECK64-NEXT: arg: 0, reg: '$a0_64'
-; CHECK64-NEXT: arg: 1, reg: '$a1_64'
-; CHECK64-NEXT: arg: 2, reg: '$a2_64'
+; CHECK64-NEXT: arg: 0, reg: '$r4_64'
+; CHECK64-NEXT: arg: 1, reg: '$r5_64'
+; CHECK64-NEXT: arg: 2, reg: '$r6_64'
; ModuleID = 'test/CodeGen/Mips/call-site-info-output.c'
source_filename = "test/CodeGen/Mips/call-site-info-output.c"
diff --git a/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll b/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
index 46446eed4f6ca..d605079371afe 100644
--- a/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
+++ b/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
@@ -1279,8 +1279,8 @@ define void @call_v4i18(ptr %p) nounwind {
; MIPS64-NEXT: ori $17, $17, 65280
; MIPS64-NEXT: # kill: def $r2 killed $r2 def $r2_64
; MIPS64-NEXT: # kill: def $r3 killed $r3 def $r3_64
-; MIPS64-NEXT: # kill: def $a0 killed $a0 def $a0_64
-; MIPS64-NEXT: # kill: def $a1 killed $a1 def $a1_64
+; MIPS64-NEXT: # kill: def $r4 killed $r4 def $r4_64
+; MIPS64-NEXT: # kill: def $r5 killed $r5 def $r5_64
; MIPS64-NEXT: dsll $1, $2, 54
; MIPS64-NEXT: and $3, $3, $18
; MIPS64-NEXT: dsll $3, $3, 36
diff --git a/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir b/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
index de7286611f954..555a0cad87f4f 100644
--- a/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
+++ b/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
@@ -5,19 +5,19 @@ name: f
tracksRegLiveness: true
body: |
bb.0:
- %0:gpr32 = ADDiu $zero, 0
+ %0:gpr32 = ADDiu $r0, 0
%1:gpr32 = COPY %0
%1:gpr32 = ADDiu %1, 1
- BEQ %0, $zero, %bb.3, implicit-def $at
- J %bb.1, implicit-def dead $at
+ BEQ %0, $r0, %bb.3, implicit-def $r1
+ J %bb.1, implicit-def dead $r1
bb.1:
- J %bb.2, implicit %1, implicit-def dead $at
+ J %bb.2, implicit %1, implicit-def dead $r1
bb.2:
%1:gpr32 = COPY %0
%0:gpr32 = COPY %1
- BEQ %0:gpr32, $zero, %bb.2, implicit-def $at
+ BEQ %0:gpr32, $r0, %bb.2, implicit-def $r1
bb.3:
%4:gpr32 = ADDiu %1, 1
diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
index a502e0b4f5b59..8f5d761d1c46b 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
+++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
@@ -62,17 +62,17 @@ regBankSelected: false
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '$a0_64' }
- - { reg: '$t9_64' }
-calleeSavedRegisters: [ '$fp', '$gp', '$ra', '$d12', '$d13', '$d14', '$d15',
+ - { reg: '$r4_64' }
+ - { reg: '$r25_64' }
+calleeSavedRegisters: [ '$r30', '$r28', '$r31', '$d12', '$d13', '$d14', '$d15',
'$f24', '$f25', '$f26', '$f27', '$f28', '$f29',
- '$f30', '$f31', '$fp_64', '$f_hi24', '$f_hi25',
+ '$f30', '$f31', '$r30_64', '$f_hi24', '$f_hi25',
'$f_hi26', '$f_hi27', '$f_hi28', '$f_hi29', '$f_hi30',
- '$f_hi31', '$gp_64', '$ra_64', '$s0', '$s1', '$s2',
- '$s3', '$s4', '$s5', '$s6', '$s7', '$d24_64', '$d25_64',
+ '$f_hi31', '$r28_64', '$r31_64', '$r16', '$r17', '$r18',
+ '$r19', '$r20', '$r21', '$r22', '$r23', '$d24_64', '$d25_64',
'$d26_64', '$d27_64', '$d28_64', '$d29_64', '$d30_64',
- '$d31_64', '$s0_64', '$s1_64', '$s2_64', '$s3_64',
- '$s4_64', '$s5_64', '$s6_64', '$s7_64' ]
+ '$d31_64', '$r16_64', '$r17_64', '$r18_64', '$r19_64',
+ '$r20_64', '$r21_64', '$r22_64', '$r23_64' ]
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -90,69 +90,69 @@ frameInfo:
stack:
- { id: 0, name: retval, offset: -28, size: 4, alignment: 4 }
- { id: 1, name: a.addr, offset: -32, size: 4, alignment: 4 }
- - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '$ra_64' }
- - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '$fp_64' }
- - { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$gp_64' }
+ - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '$r31_64' }
+ - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '$r30_64' }
+ - { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$r28_64' }
body: |
bb.0.entry:
successors: %bb.1.if.then(0x40000000), %bb.5.if.else(0x40000000)
- liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
+ liveins: $r4_64, $r25_64, $r31_64, $r30_64, $r28_64
- $sp_64 = DADDiu $sp_64, -32
+ $r29_64 = DADDiu $r29_64, -32
CFI_INSTRUCTION def_cfa_offset 32
- SD killed $ra_64, $sp_64, 24 :: (store (s64) into %stack.2)
- SD killed $fp_64, $sp_64, 16 :: (store (s64) into %stack.3)
- SD killed $gp_64, $sp_64, 8 :: (store (s64) into %stack.4)
- CFI_INSTRUCTION offset $ra_64, -8
- CFI_INSTRUCTION offset $fp_64, -16
- CFI_INSTRUCTION offset $gp_64, -24
- CFI_INSTRUCTION def_cfa_register $fp_64
- $at_64 = LUi64 @f
- $r2_64 = DADDu killed $at_64, $t9_64
- SW $a0, $sp_64, 0 :: (store (s32) into %ir.a.addr)
- BGTZC $a0, %bb.5.if.else, implicit-def $at
+ SD killed $r31_64, $r29_64, 24 :: (store (s64) into %stack.2)
+ SD killed $r30_64, $r29_64, 16 :: (store (s64) into %stack.3)
+ SD killed $r28_64, $r29_64, 8 :: (store (s64) into %stack.4)
+ CFI_INSTRUCTION offset $r31_64, -8
+ CFI_INSTRUCTION offset $r30_64, -16
+ CFI_INSTRUCTION offset $r28_64, -24
+ CFI_INSTRUCTION def_cfa_register $r30_64
+ $r1_64 = LUi64 @f
+ $r2_64 = DADDu killed $r1_64, $r25_64
+ SW $r4, $r29_64, 0 :: (store (s32) into %ir.a.addr)
+ BGTZC $r4, %bb.5.if.else, implicit-def $r1
bb.1.if.then:
successors: %bb.6.return(0x40000000), %bb.2.if.then(0x40000000)
- liveins: $a0
+ liveins: $r4
- BLTZC $a0, %bb.6.return, implicit-def $at
+ BLTZC $r4, %bb.6.return, implicit-def $r1
bb.2.if.then:
successors: %bb.3.if.else(0x80000000)
- $t8 = IMPLICIT_DEF
+ $r24 = IMPLICIT_DEF
bb.3.if.else:
successors: %bb.6.return(0x40000000), %bb.4.if.else(0x40000000)
- liveins: $t8
+ liveins: $r24
- BLEZC $t8, %bb.6.return, implicit-def $at
+ BLEZC $r24, %bb.6.return, implicit-def $r1
bb.4.if.else:
successors: %bb.6.return(0x80000000)
- liveins: $t8
+ liveins: $r24
- $at = LW $sp_64, 0 :: (dereferenceable load (s32) from %ir.a.addr)
- $at = ADDu killed $at, $t8
- SW killed $at, $sp_64, 4 :: (store (s32) into %ir.retval)
- J %bb.6.return, implicit-def dead $at
+ $r1 = LW $r29_64, 0 :: (dereferenceable load (s32) from %ir.a.addr)
+ $r1 = ADDu killed $r1, $r24
+ SW killed $r1, $r29_64, 4 :: (store (s32) into %ir.retval)
+ J %bb.6.return, implicit-def dead $r1
bb.5.if.else:
successors: %bb.6.return(0x80000000)
liveins: $r2_64
- $gp_64 = DADDiu killed $r2_64, @f
- $a0_64 = LW64 $sp_64, 0 :: (dereferenceable load (s32) from %ir.a.addr)
- $t9_64 = LD $gp_64, @g :: (load (s64) from call-entry @g)
- JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
- SW killed $r2, $sp_64, 4 :: (store (s32) into %ir.retval)
+ $r28_64 = DADDiu killed $r2_64, @f
+ $r4_64 = LW64 $r29_64, 0 :: (dereferenceable load (s32) from %ir.a.addr)
+ $r25_64 = LD $r28_64, @g :: (load (s64) from call-entry @g)
+ JALR64Pseudo $r25_64, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2
+ SW killed $r2, $r29_64, 4 :: (store (s32) into %ir.retval)
bb.6.return:
- $r2 = LW $sp_64, 4 :: (dereferenceable load (s32) from %ir.retval)
- $gp_64 = LD $sp_64, 8 :: (load (s64) from %stack.4)
- $fp_64 = LD $sp_64, 16 :: (load (s64) from %stack.3)
- $ra_64 = LD $sp_64, 24 :: (load (s64) from %stack.2)
- $sp_64 = DADDiu $sp_64, 32
- PseudoReturn64 $ra_64
+ $r2 = LW $r29_64, 4 :: (dereferenceable load (s32) from %ir.retval)
+ $r28_64 = LD $r29_64, 8 :: (load (s64) from %stack.4)
+ $r30_64 = LD $r29_64, 16 :: (load (s64) from %stack.3)
+ $r31_64 = LD $r29_64, 24 :: (load (s64) from %stack.2)
+ $r29_64 = DADDiu $r29_64, 32
+ PseudoReturn64 $r31_64
...
diff --git a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
index 3a2da93e6ecec..b8528c3a7d645 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
+++ b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
@@ -58,18 +58,18 @@ frameInfo:
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$ra' }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$r31' }
body: |
bb.0.entry:
successors: %bb.1.if.then(0x50000000), %bb.4.if.end(0x30000000)
- liveins: $ra
+ liveins: $r31
- $sp = ADDiu $sp, -24
+ $r29 = ADDiu $r29, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- CFI_INSTRUCTION offset $ra_64, -4
- JAL @k, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit-def $r2
- BLEZ $r2, %bb.4.if.end, implicit-def $at
+ SW killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ CFI_INSTRUCTION offset $r31_64, -4
+ JAL @k, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit-def $r2
+ BLEZ $r2, %bb.4.if.end, implicit-def $r1
bb.1.if.then:
successors: %bb.2.if.then(0x80000000)
@@ -80,12 +80,12 @@ body: |
bb.3.if.then:
successors: %bb.4.if.end(0x80000000)
- $a0 = ADDiu $zero, 2
- JAL @f, csr_o32_fp64, implicit-def dead $ra, implicit killed $a0, implicit-def $sp
+ $r4 = ADDiu $r0, 2
+ JAL @f, csr_o32_fp64, implicit-def dead $r31, implicit killed $r4, implicit-def $r29
bb.4.if.end:
- $ra = LW $sp, 20 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 24
- PseudoReturn undef $ra
+ $r31 = LW $r29, 20 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 24
+ PseudoReturn undef $r31
...
diff --git a/llvm/test/CodeGen/Mips/copy-fp64.ll b/llvm/test/CodeGen/Mips/copy-fp64.ll
index 8a6e2460690fb..6c15bd54482d9 100644
--- a/llvm/test/CodeGen/Mips/copy-fp64.ll
+++ b/llvm/test/CodeGen/Mips/copy-fp64.ll
@@ -9,13 +9,13 @@ define double @foo(double %self) {
; CHECK-LABEL: name: foo
; CHECK: bb.0.start:
; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $d12_64, $t9, $r2
- ; CHECK: renamable $at = ADDu killed $r2, killed $t9
+ ; CHECK: liveins: $d12_64, $r25, $r2
+ ; CHECK: renamable $r1 = ADDu killed $r2, killed $r25
; CHECK: renamable $d6_64 = COPY killed $d12_64
- ; CHECK: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; CHECK: renamable $t9 = LW killed renamable $at, target-flags(mips-got) @bar
- ; CHECK: dead $ra = JALR killed $t9, csr_o32_fp64, target-flags(mips-jalr) <mcsymbol bar>, implicit-def dead $ra, implicit killed $d6_64, implicit-def $d0_64
- ; CHECK: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; CHECK: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
+ ; CHECK: renamable $r25 = LW killed renamable $r1, target-flags(mips-got) @bar
+ ; CHECK: dead $r31 = JALR killed $r25, csr_o32_fp64, target-flags(mips-jalr) <mcsymbol bar>, implicit-def dead $r31, implicit killed $d6_64, implicit-def $d0_64
+ ; CHECK: ADJCALLSTACKUP 16, 0, implicit-def $r29, implicit $r29
; CHECK: SDC164 killed $d0_64, %stack.0, 0 :: (store (s64) into %stack.0)
; CHECK: bb.1.bb1:
; CHECK: $d0_64 = LDC164 %stack.0, 0 :: (load (s64) from %stack.0)
diff --git a/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll b/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
index dc8efae68fda1..6082532e69604 100644
--- a/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
+++ b/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
@@ -18,8 +18,8 @@ entry:
}
; MIPS-LABEL: ===== Instruction selection ends:
-; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $zero, TargetConstant:i32<1>
-; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $zero, TargetConstant:i32<2048>
+; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $r0, TargetConstant:i32<1>
+; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $r0, TargetConstant:i32<2048>
; MIPS-DAG: t{{[0-9]+}}: i32 = LUi TargetConstant:i32<128>
; MIPS: t{{[0-9]+}}: ch,glue = JAL TargetGlobalAddress:i32<ptr @f>
@@ -28,7 +28,7 @@ entry:
; MM-LABEL: ===== Instruction selection ends:
; MM-DAG: t{{[0-9]+}}: i32 = LI16_MM TargetConstant:i32<1>
-; MM-DAG: t{{[0-9]+}}: i32 = ADDiu_MM Register:i32 $zero, TargetConstant:i32<2048>
+; MM-DAG: t{{[0-9]+}}: i32 = ADDiu_MM Register:i32 $r0, TargetConstant:i32<2048>
; MM-DAG: t{{[0-9]+}}: i32 = LUi_MM TargetConstant:i32<128>
; MM: t{{[0-9]+}}: ch,glue = JAL_MM TargetGlobalAddress:i32<ptr @f>
diff --git a/llvm/test/CodeGen/Mips/dbg-call-site-info-reg-d-split.ll b/llvm/test/CodeGen/Mips/dbg-call-site-info-reg-d-split.ll
index 5878b040bada0..fd14cb1a66786 100644
--- a/llvm/test/CodeGen/Mips/dbg-call-site-info-reg-d-split.ll
+++ b/llvm/test/CodeGen/Mips/dbg-call-site-info-reg-d-split.ll
@@ -17,9 +17,9 @@
; CHECK: name: foo
; CHECK: callSites:
; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
-; CHECK-NOT: arg: 0, reg: '$a0'
+; CHECK-NOT: arg: 0, reg: '$r4'
; CHECK-NOT: arg: 0, reg: '$d6'
-; CHECK-NEXT: arg: 1, reg: '$a2'
+; CHECK-NEXT: arg: 1, reg: '$r6'
; ModuleID = 'm.c'
source_filename = "m.c"
diff --git a/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir b/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
index e010aff459bef..1b301baaf4888 100644
--- a/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
+++ b/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
@@ -34,7 +34,7 @@ tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -63,41 +63,41 @@ body: |
; CHECK-LABEL: name: test
; CHECK: bb.0.entry:
; CHECK: successors: %bb.2(0x00000001), %bb.1(0x7fffffff)
- ; CHECK: renamable $at = SLL renamable $a0, 0, implicit killed $a0_64
- ; CHECK: renamable $at = ANDi killed renamable $at, 1
- ; CHECK: $r2_64 = DADDiu $zero_64, 1
+ ; CHECK: renamable $r1 = SLL renamable $r4, 0, implicit killed $r4_64
+ ; CHECK: renamable $r1 = ANDi killed renamable $r1, 1
+ ; CHECK: $r2_64 = DADDiu $r0_64, 1
; CHECK: $r2_64 = DADDiu $r2_64, 1
; CHECK: BUNDLE implicit-def $r2_64 {
- ; CHECK: $r2_64 = DADDiu $zero_64, 1
+ ; CHECK: $r2_64 = DADDiu $r0_64, 1
; CHECK: $r2_64 = DADDiu $r2_64, 1
; CHECK: }
- ; CHECK: BNE killed renamable $at, $zero, %bb.2, implicit-def $at {
- ; CHECK: $zero = SLL $zero, 0
+ ; CHECK: BNE killed renamable $r1, $r0, %bb.2, implicit-def $r1 {
+ ; CHECK: $r0 = SLL $r0, 0
; CHECK: }
; CHECK: bb.1.return:
- ; CHECK: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; CHECK: $zero = SLL $zero, 0
+ ; CHECK: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; CHECK: $r0 = SLL $r0, 0
; CHECK: }
; CHECK: bb.2.err:
bb.0.entry:
successors: %bb.1(0x00000001), %bb.2(0x7fffffff)
- liveins: $a0_64
+ liveins: $r4_64
- renamable $at = SLL renamable $a0, 0, implicit killed $a0_64
- renamable $at = ANDi killed renamable $at, 1
+ renamable $r1 = SLL renamable $r4, 0, implicit killed $r4_64
+ renamable $r1 = ANDi killed renamable $r1, 1
; Check that none of these instructions are hoisted after the BUNDLE to avoid
; incorrect values from being
- $r2_64 = DADDiu $zero_64, 1
+ $r2_64 = DADDiu $r0_64, 1
$r2_64 = DADDiu $r2_64, 1
BUNDLE implicit-def $r2_64 {
- $r2_64 = DADDiu $zero_64, 1
+ $r2_64 = DADDiu $r0_64, 1
$r2_64 = DADDiu $r2_64, 1
}
- BNE killed renamable $at, $zero, %bb.1, implicit-def $at
+ BNE killed renamable $r1, $r0, %bb.1, implicit-def $r1
bb.2.return:
liveins: $r2_64
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.1.err:
diff --git a/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir b/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
index 792026c7c90ea..bff26cb4e3007 100644
--- a/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
+++ b/llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
@@ -54,7 +54,7 @@ tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -77,7 +77,7 @@ frameInfo:
fixedStack: []
stack:
- { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '$ra_64', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
constants: []
@@ -86,68 +86,68 @@ body: |
; CHECK-LABEL: name: test
; CHECK: bb.0.entry:
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
- ; CHECK: $sp_64 = DADDiu $sp_64, -16
+ ; CHECK: $r29_64 = DADDiu $r29_64, -16
; CHECK: CFI_INSTRUCTION def_cfa_offset 16
- ; CHECK: SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
- ; CHECK: CFI_INSTRUCTION offset $ra_64, -8
+ ; CHECK: SD killed $r31_64, $r29_64, 8 :: (store (s64) into %stack.0)
+ ; CHECK: CFI_INSTRUCTION offset $r31_64, -8
; CHECK: BUNDLE {
- ; CHECK: $sp_64 = DADDiu $sp_64, -16
- ; CHECK: $sp_64 = DADDiu $sp_64, 16
+ ; CHECK: $r29_64 = DADDiu $r29_64, -16
+ ; CHECK: $r29_64 = DADDiu $r29_64, 16
; CHECK: }
- ; CHECK: BEQ64 renamable $a0_64, $zero_64, %bb.2, implicit-def $at {
- ; CHECK: $zero = SLL $zero, 0
+ ; CHECK: BEQ64 renamable $r4_64, $r0_64, %bb.2, implicit-def $r1 {
+ ; CHECK: $r0 = SLL $r0, 0
; CHECK: }
; CHECK: bb.1.if.then:
; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: JAL @func_a, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2_64 {
- ; CHECK: $zero = SLL $zero, 0
+ ; CHECK: JAL @func_a, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit-def $r29, implicit-def $r2_64 {
+ ; CHECK: $r0 = SLL $r0, 0
; CHECK: }
- ; CHECK: J %bb.3, implicit-def dead $at {
- ; CHECK: $zero = SLL $zero, 0
+ ; CHECK: J %bb.3, implicit-def dead $r1 {
+ ; CHECK: $r0 = SLL $r0, 0
; CHECK: }
; CHECK: bb.2.if.else:
; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: JAL @func_b, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2_64 {
- ; CHECK: $a0_64 = DADDiu $zero_64, 0
+ ; CHECK: JAL @func_b, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit-def $r29, implicit-def $r2_64 {
+ ; CHECK: $r4_64 = DADDiu $r0_64, 0
; CHECK: }
; CHECK: bb.3.return:
- ; CHECK: $ra_64 = LD $sp_64, 8 :: (load (s64) from %stack.0)
- ; CHECK: PseudoReturn64 undef $ra_64, implicit $r2_64 {
- ; CHECK: $sp_64 = DADDiu $sp_64, 16
+ ; CHECK: $r31_64 = LD $r29_64, 8 :: (load (s64) from %stack.0)
+ ; CHECK: PseudoReturn64 undef $r31_64, implicit $r2_64 {
+ ; CHECK: $r29_64 = DADDiu $r29_64, 16
; CHECK: }
bb.0.entry:
successors: %bb.2(0x30000000), %bb.1(0x50000000)
- liveins: $a0_64, $ra_64
+ liveins: $r4_64, $r31_64
- $sp_64 = DADDiu $sp_64, -16
+ $r29_64 = DADDiu $r29_64, -16
CFI_INSTRUCTION def_cfa_offset 16
- SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
- CFI_INSTRUCTION offset $ra_64, -8
+ SD killed $r31_64, $r29_64, 8 :: (store (s64) into %stack.0)
+ CFI_INSTRUCTION offset $r31_64, -8
; This BUNDLE instruction must not be split by the delay slot filler:
BUNDLE {
- $sp_64 = DADDiu $sp_64, -16
- $sp_64 = DADDiu $sp_64, 16
+ $r29_64 = DADDiu $r29_64, -16
+ $r29_64 = DADDiu $r29_64, 16
}
- BEQ64 renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+ BEQ64 renamable $r4_64, $r0_64, %bb.2, implicit-def $r1
bb.1.if.then:
successors: %bb.3(0x80000000)
- liveins: $a0_64
+ liveins: $r4_64
- JAL @func_a, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2_64
- J %bb.3, implicit-def dead $at
+ JAL @func_a, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit-def $r29, implicit-def $r2_64
+ J %bb.3, implicit-def dead $r1
bb.2.if.else:
successors: %bb.3(0x80000000)
- $a0_64 = DADDiu $zero_64, 0
- JAL @func_b, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2_64
+ $r4_64 = DADDiu $r0_64, 0
+ JAL @func_b, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit-def $r29, implicit-def $r2_64
bb.3.return:
liveins: $r2_64
- $ra_64 = LD $sp_64, 8 :: (load (s64) from %stack.0)
- $sp_64 = DADDiu $sp_64, 16
- PseudoReturn64 undef $ra_64, implicit $r2_64
+ $r31_64 = LD $r29_64, 8 :: (load (s64) from %stack.0)
+ $r29_64 = DADDiu $r29_64, 16
+ PseudoReturn64 undef $r31_64, implicit $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/fake-use.ll b/llvm/test/CodeGen/Mips/fake-use.ll
index c8c7f83624314..8bccadfc3b7ca 100644
--- a/llvm/test/CodeGen/Mips/fake-use.ll
+++ b/llvm/test/CodeGen/Mips/fake-use.ll
@@ -3,7 +3,7 @@
define void @fake_use(ptr %aaaa) {
; CHECK-LABEL: fake_use:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # fake_use: $a0
+; CHECK-NEXT: # fake_use: $r4
; CHECK-NEXT: jr $ra
; CHECK-NEXT: nop
entry:
diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir
index bce0ea1cdb356..b36530916071c 100644
--- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir
+++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir
@@ -25,7 +25,7 @@ registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$r4', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -48,11 +48,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0
+ liveins: $r4
- %0:gpr32 = COPY $a0
- %1:gpr32 = ADDiu $zero, 14
- $a0 = COPY %1
- TAILCALLREG %0, csr_o32, implicit-def dead $at, implicit $a0
+ %0:gpr32 = COPY $r4
+ %1:gpr32 = ADDiu $r0, 14
+ $r4 = COPY %1
+ TAILCALLREG %0, csr_o32, implicit-def dead $r1, implicit $r4
...
diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir
index 7bad3ff8c21fb..eb7e44e91f77b 100644
--- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir
+++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir
@@ -26,7 +26,7 @@ registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$r4', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -49,11 +49,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0
+ liveins: $r4
- %0:gpr32 = COPY $a0
- %1:gpr32 = ADDiu $zero, 14
- $a0 = COPY %1
- TAILCALLREG %0, csr_o32, implicit-def dead $at, implicit $a0
+ %0:gpr32 = COPY $r4
+ %1:gpr32 = ADDiu $r0, 14
+ $r4 = COPY %1
+ TAILCALLREG %0, csr_o32, implicit-def dead $r1, implicit $r4
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
index f8a57ce5078cc..1c5988e80b284 100644
--- a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DEXT %0, 55, 10
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dext-size.mir b/llvm/test/CodeGen/Mips/instverify/dext-size.mir
index a870679fa878a..d0b111134b852 100644
--- a/llvm/test/CodeGen/Mips/instverify/dext-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dext-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DEXT %0, 5, 50
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
index b9c6cf18e5834..2bb2f5afc5ff0 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DEXTM %0, 3, 62
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
index 35ab1a2d97096..c4d513db4df26 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DEXTM %0, 65, 5
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
index ef6da5cbd1222..1a440e900b726 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DEXTM %0, 31, 67
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
index 0dd646d28c1f8..c9979484ebab3 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DEXTU %0, 43, 30
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
index 1da64f1432249..4dca64813d95f 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DEXTU %0, 64, 5
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
index 6ff76b327b594..59333eacf4676 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DEXTU %0, 63, 1
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
index 9ab835e708378..01c71ea1ad31a 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DEXTU %0, 33, 67
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
index e13d1f86946e2..7244002a97bad 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DINS %0, 17, 17
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
index eda7c0e778d96..a7700c9c7947e 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DINS %0, 55, 10
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-size.mir
index 08ae7d6053f79..64473836b907b 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DINS %0, 5, 50
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
index a33f16fabf0fa..c7e85cbab9668 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DINSM %0, 20, 50
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
index 7d5f81ddf2ed7..a03d8b3cb88fd 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DINSM %0, 65, 5
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
index 458549e8053ba..3729a48b7aeef 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DINSM %0, 31, 67
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
index 30d3108f2d7bb..4ec3ed517c814 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DINSU %0, 50, 20
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
index f78a33888b347..ce11da896e4c8 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DINSU %0, 65, 5
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
index d086e5c3bfd54..dc371e9e01d56 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64
+ liveins: $r4_64
- %0 = COPY $a0_64
+ %0 = COPY $r4_64
%1 = DINSU %0, 33, 67
$r2_64 = COPY %1
RetRA implicit $r2_64
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
index 90835c138eb3d..3933758b7eff4 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$r4', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0
+ liveins: $r4
- %0 = COPY $a0
+ %0 = COPY $r4
%1 = EXT %0, 17, 17
$r2 = COPY %1
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
index 47df1b150e43b..a799221444df9 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$r4', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0
+ liveins: $r4
- %0 = COPY $a0
+ %0 = COPY $r4
%1 = EXT %0, 44, 21
$r2 = COPY %1
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-size.mir
index 135486ecc76f4..29153118a7485 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-size.mir
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$r4', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,9 +39,9 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0
+ liveins: $r4
- %0 = COPY $a0
+ %0 = COPY $r4
%1 = EXT %0, 0, 33
$r2 = COPY %1
RetRA implicit $r2
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
index f4f6c71a32df8..1dbfdd133b80e 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
@@ -18,8 +18,8 @@ registers:
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
- - { reg: '$a1', virtual-reg: '%1' }
+ - { reg: '$r4', virtual-reg: '%0' }
+ - { reg: '$r5', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -42,10 +42,10 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
- %1 = COPY $a1
- %0 = COPY $a0
+ %1 = COPY $r5
+ %0 = COPY $r4
%2 = ANDi %1, 15
%3 = INS killed %2, 17, 17, %0
$r2 = COPY %3
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
index 822f464c89995..2ec872d21e466 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
@@ -18,8 +18,8 @@ registers:
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
- - { reg: '$a1', virtual-reg: '%1' }
+ - { reg: '$r4', virtual-reg: '%0' }
+ - { reg: '$r5', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -42,10 +42,10 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
- %1 = COPY $a1
- %0 = COPY $a0
+ %1 = COPY $r5
+ %0 = COPY $r4
%2 = ANDi %1, 15
%3 = INS killed %2, 32, 4, %0
$r2 = COPY %3
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-size.mir
index 29e45d60fce06..7f1da42ed4d90 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-size.mir
@@ -18,8 +18,8 @@ registers:
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
- - { reg: '$a1', virtual-reg: '%1' }
+ - { reg: '$r4', virtual-reg: '%0' }
+ - { reg: '$r5', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -42,10 +42,10 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
- %1 = COPY $a1
- %0 = COPY $a0
+ %1 = COPY $r5
+ %0 = COPY $r4
%2 = ANDi %1, 15
%3 = INS killed %2, 0, 40, %0
$r2 = COPY %3
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/call.ll b/llvm/test/CodeGen/Mips/llvm-ir/call.ll
index a962e1763618a..9ffe33cf37c49 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/call.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/call.ll
@@ -161,8 +161,8 @@ declare hidden void @undef_double(i32 %this, double %volume) unnamed_addr align
define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 {
; ALL-LABEL: thunk_undef_double:
-; O32: # implicit-def: $a2
-; O32: # implicit-def: $a3
+; O32: # implicit-def: $r6
+; O32: # implicit-def: $r7
; NOT-R6C: jr $[[TGT]]
; R6C: jrc $[[TGT]]
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
index 097fb322c8df5..56690c0ad6194 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
@@ -42,7 +42,7 @@ define i32 @test1(float %t) {
; M32-NEXT: # <MCOperand Reg:F0>
; M32-NEXT: # <MCOperand Reg:F12>>
; M32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; M32-NEXT: # <MCOperand Reg:RA>>
+; M32-NEXT: # <MCOperand Reg:R31>>
; M32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
; M32-NEXT: # <MCOperand Reg:R2>
; M32-NEXT: # <MCOperand Reg:F0>>
@@ -53,7 +53,7 @@ define i32 @test1(float %t) {
; M32R2-FP64-NEXT: # <MCOperand Reg:F0>
; M32R2-FP64-NEXT: # <MCOperand Reg:F12>>
; M32R2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; M32R2-FP64-NEXT: # <MCOperand Reg:RA>>
+; M32R2-FP64-NEXT: # <MCOperand Reg:R31>>
; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
; M32R2-FP64-NEXT: # <MCOperand Reg:R2>
; M32R2-FP64-NEXT: # <MCOperand Reg:F0>>
@@ -61,32 +61,32 @@ define i32 @test1(float %t) {
; M32R2-SF-LABEL: test1:
; M32R2-SF: # %bb.0: # %entry
; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4:]] ADDiu
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; M32R2-SF-NEXT: # <MCInst #[[#MCINST5:]] SW
-; M32R2-SF-NEXT: # <MCOperand Reg:RA>
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
+; M32R2-SF-NEXT: # <MCOperand Reg:R31>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
; M32R2-SF-NEXT: .cfi_offset 31, -4
; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #[[#MCINST6:]] JAL
; M32R2-SF-NEXT: # <MCOperand Expr:__fixsfsi>>
; M32R2-SF-NEXT: nop # <MCInst #[[#MCINST7:]] SLL
-; M32R2-SF-NEXT: # <MCOperand Reg:ZERO>
-; M32R2-SF-NEXT: # <MCOperand Reg:ZERO>
+; M32R2-SF-NEXT: # <MCOperand Reg:R0>
+; M32R2-SF-NEXT: # <MCOperand Reg:R0>
; M32R2-SF-NEXT: # <MCOperand Imm:0>>
; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; M32R2-SF-NEXT: # <MCInst #[[#MCINST8:]] LW
-; M32R2-SF-NEXT: # <MCOperand Reg:RA>
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
+; M32R2-SF-NEXT: # <MCOperand Reg:R31>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
; M32R2-SF-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; M32R2-SF-NEXT: # <MCOperand Reg:RA>>
+; M32R2-SF-NEXT: # <MCOperand Reg:R31>>
; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
; M32R2-SF-NEXT: # <MCOperand Imm:24>>
;
; M32R3R5-LABEL: test1:
@@ -95,7 +95,7 @@ define i32 @test1(float %t) {
; M32R3R5-NEXT: # <MCOperand Reg:F0>
; M32R3R5-NEXT: # <MCOperand Reg:F12>>
; M32R3R5-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; M32R3R5-NEXT: # <MCOperand Reg:RA>>
+; M32R3R5-NEXT: # <MCOperand Reg:R31>>
; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
; M32R3R5-NEXT: # <MCOperand Reg:R2>
; M32R3R5-NEXT: # <MCOperand Reg:F0>>
@@ -106,8 +106,8 @@ define i32 @test1(float %t) {
; M32R6-NEXT: # <MCOperand Reg:F0>
; M32R6-NEXT: # <MCOperand Reg:F12>>
; M32R6-NEXT: jr $ra # <MCInst #[[#MCINST9:]] JALR
-; M32R6-NEXT: # <MCOperand Reg:ZERO>
-; M32R6-NEXT: # <MCOperand Reg:RA>>
+; M32R6-NEXT: # <MCOperand Reg:R0>
+; M32R6-NEXT: # <MCOperand Reg:R31>>
; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
; M32R6-NEXT: # <MCOperand Reg:R2>
; M32R6-NEXT: # <MCOperand Reg:F0>>
@@ -121,14 +121,14 @@ define i32 @test1(float %t) {
; M3-NEXT: # <MCOperand Reg:R2>
; M3-NEXT: # <MCOperand Reg:F0>>
; M3-NEXT: nop # <MCInst #[[#MCINST7:]] SLL
-; M3-NEXT: # <MCOperand Reg:ZERO>
-; M3-NEXT: # <MCOperand Reg:ZERO>
+; M3-NEXT: # <MCOperand Reg:R0>
+; M3-NEXT: # <MCOperand Reg:R0>
; M3-NEXT: # <MCOperand Imm:0>>
; M3-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; M3-NEXT: # <MCOperand Reg:RA_64>>
+; M3-NEXT: # <MCOperand Reg:R31_64>>
; M3-NEXT: nop # <MCInst #[[#MCINST7]] SLL
-; M3-NEXT: # <MCOperand Reg:ZERO>
-; M3-NEXT: # <MCOperand Reg:ZERO>
+; M3-NEXT: # <MCOperand Reg:R0>
+; M3-NEXT: # <MCOperand Reg:R0>
; M3-NEXT: # <MCOperand Imm:0>>
;
; M64-LABEL: test1:
@@ -137,7 +137,7 @@ define i32 @test1(float %t) {
; M64-NEXT: # <MCOperand Reg:F0>
; M64-NEXT: # <MCOperand Reg:F12>>
; M64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; M64-NEXT: # <MCOperand Reg:RA_64>>
+; M64-NEXT: # <MCOperand Reg:R31_64>>
; M64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
; M64-NEXT: # <MCOperand Reg:R2>
; M64-NEXT: # <MCOperand Reg:F0>>
@@ -148,8 +148,8 @@ define i32 @test1(float %t) {
; M64R6-NEXT: # <MCOperand Reg:F0>
; M64R6-NEXT: # <MCOperand Reg:F12>>
; M64R6-NEXT: jr $ra # <MCInst #[[#MCINST10:]] JALR64
-; M64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; M64R6-NEXT: # <MCOperand Reg:RA_64>>
+; M64R6-NEXT: # <MCOperand Reg:R0_64>
+; M64R6-NEXT: # <MCOperand Reg:R31_64>>
; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
; M64R6-NEXT: # <MCOperand Reg:R2>
; M64R6-NEXT: # <MCOperand Reg:F0>>
@@ -160,7 +160,7 @@ define i32 @test1(float %t) {
; MMR2-FP32-NEXT: # <MCOperand Reg:F0>
; MMR2-FP32-NEXT: # <MCOperand Reg:F12>>
; MMR2-FP32-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM
-; MMR2-FP32-NEXT: # <MCOperand Reg:RA>>
+; MMR2-FP32-NEXT: # <MCOperand Reg:R31>>
; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
; MMR2-FP32-NEXT: # <MCOperand Reg:R2>
; MMR2-FP32-NEXT: # <MCOperand Reg:F0>>
@@ -171,7 +171,7 @@ define i32 @test1(float %t) {
; MMR2-FP64-NEXT: # <MCOperand Reg:F0>
; MMR2-FP64-NEXT: # <MCOperand Reg:F12>>
; MMR2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM
-; MMR2-FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR2-FP64-NEXT: # <MCOperand Reg:R31>>
; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
; MMR2-FP64-NEXT: # <MCOperand Reg:R2>
; MMR2-FP64-NEXT: # <MCOperand Reg:F0>>
@@ -183,25 +183,25 @@ define i32 @test1(float %t) {
; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MMR2-SF-NEXT: # <MCInst #[[#MCINST15:]] SWSP_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:RA>
-; MMR2-SF-NEXT: # <MCOperand Reg:SP>
+; MMR2-SF-NEXT: # <MCOperand Reg:R31>
+; MMR2-SF-NEXT: # <MCOperand Reg:R29>
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
; MMR2-SF-NEXT: .cfi_offset 31, -4
; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #[[#MCINST16:]] JAL_MM
; MMR2-SF-NEXT: # <MCOperand Expr:__fixsfsi>>
; MMR2-SF-NEXT: nop # <MCInst #[[#MCINST17:]] SLL_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:ZERO>
-; MMR2-SF-NEXT: # <MCOperand Reg:ZERO>
+; MMR2-SF-NEXT: # <MCOperand Reg:R0>
+; MMR2-SF-NEXT: # <MCOperand Reg:R0>
; MMR2-SF-NEXT: # <MCOperand Imm:0>>
; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MMR2-SF-NEXT: # <MCInst #[[#MCINST18:]] LWSP_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:RA>
-; MMR2-SF-NEXT: # <MCOperand Reg:SP>
+; MMR2-SF-NEXT: # <MCOperand Reg:R31>
+; MMR2-SF-NEXT: # <MCOperand Reg:R29>
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
; MMR2-SF-NEXT: addiusp 24 # <MCInst #[[#MCINST14]] ADDIUSP_MM
; MMR2-SF-NEXT: # <MCOperand Imm:24>>
; MMR2-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:RA>>
+; MMR2-SF-NEXT: # <MCOperand Reg:R31>>
;
; MMR6-LABEL: test1:
; MMR6: # %bb.0: # %entry
@@ -212,34 +212,34 @@ define i32 @test1(float %t) {
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:F0>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MMR6-SF-LABEL: test1:
; MMR6-SF: # %bb.0: # %entry
; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4:]] ADDiu
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MMR6-SF-NEXT: # <MCInst #[[#MCINST5:]] SW
-; MMR6-SF-NEXT: # <MCOperand Reg:RA>
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
+; MMR6-SF-NEXT: # <MCOperand Reg:R31>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: .cfi_offset 31, -4
; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #[[#MCINST21:]] BALC_MMR6
; MMR6-SF-NEXT: # <MCOperand Expr:__fixsfsi>>
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MMR6-SF-NEXT: # <MCInst #[[#MCINST8:]] LW
-; MMR6-SF-NEXT: # <MCOperand Reg:RA>
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
+; MMR6-SF-NEXT: # <MCOperand Reg:R31>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
; MMR6-SF-NEXT: # <MCOperand Imm:24>>
; MMR6-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
-; MMR6-SF-NEXT: # <MCOperand Reg:RA>>
+; MMR6-SF-NEXT: # <MCOperand Reg:R31>>
entry:
%conv = fptosi float %t to i32
ret i32 %conv
@@ -252,7 +252,7 @@ define i32 @test2(double %t) {
; M32-NEXT: # <MCOperand Reg:F0>
; M32-NEXT: # <MCOperand Reg:D6>>
; M32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; M32-NEXT: # <MCOperand Reg:RA>>
+; M32-NEXT: # <MCOperand Reg:R31>>
; M32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
; M32-NEXT: # <MCOperand Reg:R2>
; M32-NEXT: # <MCOperand Reg:F0>>
@@ -263,7 +263,7 @@ define i32 @test2(double %t) {
; M32R2-FP64-NEXT: # <MCOperand Reg:F0>
; M32R2-FP64-NEXT: # <MCOperand Reg:D12_64>>
; M32R2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; M32R2-FP64-NEXT: # <MCOperand Reg:RA>>
+; M32R2-FP64-NEXT: # <MCOperand Reg:R31>>
; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
; M32R2-FP64-NEXT: # <MCOperand Reg:R2>
; M32R2-FP64-NEXT: # <MCOperand Reg:F0>>
@@ -271,32 +271,32 @@ define i32 @test2(double %t) {
; M32R2-SF-LABEL: test2:
; M32R2-SF: # %bb.0: # %entry
; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4]] ADDiu
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; M32R2-SF-NEXT: # <MCInst #[[#MCINST5]] SW
-; M32R2-SF-NEXT: # <MCOperand Reg:RA>
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
+; M32R2-SF-NEXT: # <MCOperand Reg:R31>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
; M32R2-SF-NEXT: .cfi_offset 31, -4
; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #[[#MCINST6]] JAL
; M32R2-SF-NEXT: # <MCOperand Expr:__fixdfsi>>
; M32R2-SF-NEXT: nop # <MCInst #[[#MCINST7]] SLL
-; M32R2-SF-NEXT: # <MCOperand Reg:ZERO>
-; M32R2-SF-NEXT: # <MCOperand Reg:ZERO>
+; M32R2-SF-NEXT: # <MCOperand Reg:R0>
+; M32R2-SF-NEXT: # <MCOperand Reg:R0>
; M32R2-SF-NEXT: # <MCOperand Imm:0>>
; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; M32R2-SF-NEXT: # <MCInst #[[#MCINST8]] LW
-; M32R2-SF-NEXT: # <MCOperand Reg:RA>
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
+; M32R2-SF-NEXT: # <MCOperand Reg:R31>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
; M32R2-SF-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; M32R2-SF-NEXT: # <MCOperand Reg:RA>>
+; M32R2-SF-NEXT: # <MCOperand Reg:R31>>
; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
-; M32R2-SF-NEXT: # <MCOperand Reg:SP>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
+; M32R2-SF-NEXT: # <MCOperand Reg:R29>
; M32R2-SF-NEXT: # <MCOperand Imm:24>>
;
; M32R3R5-LABEL: test2:
@@ -305,7 +305,7 @@ define i32 @test2(double %t) {
; M32R3R5-NEXT: # <MCOperand Reg:F0>
; M32R3R5-NEXT: # <MCOperand Reg:D6>>
; M32R3R5-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; M32R3R5-NEXT: # <MCOperand Reg:RA>>
+; M32R3R5-NEXT: # <MCOperand Reg:R31>>
; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
; M32R3R5-NEXT: # <MCOperand Reg:R2>
; M32R3R5-NEXT: # <MCOperand Reg:F0>>
@@ -316,8 +316,8 @@ define i32 @test2(double %t) {
; M32R6-NEXT: # <MCOperand Reg:F0>
; M32R6-NEXT: # <MCOperand Reg:D12_64>>
; M32R6-NEXT: jr $ra # <MCInst #[[#MCINST9]] JALR
-; M32R6-NEXT: # <MCOperand Reg:ZERO>
-; M32R6-NEXT: # <MCOperand Reg:RA>>
+; M32R6-NEXT: # <MCOperand Reg:R0>
+; M32R6-NEXT: # <MCOperand Reg:R31>>
; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
; M32R6-NEXT: # <MCOperand Reg:R2>
; M32R6-NEXT: # <MCOperand Reg:F0>>
@@ -331,14 +331,14 @@ define i32 @test2(double %t) {
; M3-NEXT: # <MCOperand Reg:R2>
; M3-NEXT: # <MCOperand Reg:F0>>
; M3-NEXT: nop # <MCInst #[[#MCINST7]] SLL
-; M3-NEXT: # <MCOperand Reg:ZERO>
-; M3-NEXT: # <MCOperand Reg:ZERO>
+; M3-NEXT: # <MCOperand Reg:R0>
+; M3-NEXT: # <MCOperand Reg:R0>
; M3-NEXT: # <MCOperand Imm:0>>
; M3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; M3-NEXT: # <MCOperand Reg:RA_64>>
+; M3-NEXT: # <MCOperand Reg:R31_64>>
; M3-NEXT: nop # <MCInst #[[#MCINST7]] SLL
-; M3-NEXT: # <MCOperand Reg:ZERO>
-; M3-NEXT: # <MCOperand Reg:ZERO>
+; M3-NEXT: # <MCOperand Reg:R0>
+; M3-NEXT: # <MCOperand Reg:R0>
; M3-NEXT: # <MCOperand Imm:0>>
;
; M64-LABEL: test2:
@@ -347,7 +347,7 @@ define i32 @test2(double %t) {
; M64-NEXT: # <MCOperand Reg:F0>
; M64-NEXT: # <MCOperand Reg:D12_64>>
; M64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; M64-NEXT: # <MCOperand Reg:RA_64>>
+; M64-NEXT: # <MCOperand Reg:R31_64>>
; M64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
; M64-NEXT: # <MCOperand Reg:R2>
; M64-NEXT: # <MCOperand Reg:F0>>
@@ -358,8 +358,8 @@ define i32 @test2(double %t) {
; M64R6-NEXT: # <MCOperand Reg:F0>
; M64R6-NEXT: # <MCOperand Reg:D12_64>>
; M64R6-NEXT: jr $ra # <MCInst #[[#MCINST10]] JALR64
-; M64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; M64R6-NEXT: # <MCOperand Reg:RA_64>>
+; M64R6-NEXT: # <MCOperand Reg:R0_64>
+; M64R6-NEXT: # <MCOperand Reg:R31_64>>
; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
; M64R6-NEXT: # <MCOperand Reg:R2>
; M64R6-NEXT: # <MCOperand Reg:F0>>
@@ -370,7 +370,7 @@ define i32 @test2(double %t) {
; MMR2-FP32-NEXT: # <MCOperand Reg:F0>
; MMR2-FP32-NEXT: # <MCOperand Reg:D6>>
; MMR2-FP32-NEXT: jr $ra # <MCInst #[[#MCINST12]] JR_MM
-; MMR2-FP32-NEXT: # <MCOperand Reg:RA>>
+; MMR2-FP32-NEXT: # <MCOperand Reg:R31>>
; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
; MMR2-FP32-NEXT: # <MCOperand Reg:R2>
; MMR2-FP32-NEXT: # <MCOperand Reg:F0>>
@@ -381,7 +381,7 @@ define i32 @test2(double %t) {
; MMR2-FP64-NEXT: # <MCOperand Reg:F0>
; MMR2-FP64-NEXT: # <MCOperand Reg:D12_64>>
; MMR2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST12]] JR_MM
-; MMR2-FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR2-FP64-NEXT: # <MCOperand Reg:R31>>
; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
; MMR2-FP64-NEXT: # <MCOperand Reg:R2>
; MMR2-FP64-NEXT: # <MCOperand Reg:F0>>
@@ -393,25 +393,25 @@ define i32 @test2(double %t) {
; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MMR2-SF-NEXT: # <MCInst #[[#MCINST15]] SWSP_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:RA>
-; MMR2-SF-NEXT: # <MCOperand Reg:SP>
+; MMR2-SF-NEXT: # <MCOperand Reg:R31>
+; MMR2-SF-NEXT: # <MCOperand Reg:R29>
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
; MMR2-SF-NEXT: .cfi_offset 31, -4
; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #[[#MCINST16]] JAL_MM
; MMR2-SF-NEXT: # <MCOperand Expr:__fixdfsi>>
; MMR2-SF-NEXT: nop # <MCInst #[[#MCINST17]] SLL_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:ZERO>
-; MMR2-SF-NEXT: # <MCOperand Reg:ZERO>
+; MMR2-SF-NEXT: # <MCOperand Reg:R0>
+; MMR2-SF-NEXT: # <MCOperand Reg:R0>
; MMR2-SF-NEXT: # <MCOperand Imm:0>>
; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MMR2-SF-NEXT: # <MCInst #[[#MCINST18]] LWSP_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:RA>
-; MMR2-SF-NEXT: # <MCOperand Reg:SP>
+; MMR2-SF-NEXT: # <MCOperand Reg:R31>
+; MMR2-SF-NEXT: # <MCOperand Reg:R29>
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
; MMR2-SF-NEXT: addiusp 24 # <MCInst #[[#MCINST14]] ADDIUSP_MM
; MMR2-SF-NEXT: # <MCOperand Imm:24>>
; MMR2-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:RA>>
+; MMR2-SF-NEXT: # <MCOperand Reg:R31>>
;
; MMR6-LABEL: test2:
; MMR6: # %bb.0: # %entry
@@ -422,34 +422,34 @@ define i32 @test2(double %t) {
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:F0>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MMR6-SF-LABEL: test2:
; MMR6-SF: # %bb.0: # %entry
; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4]] ADDiu
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MMR6-SF-NEXT: # <MCInst #[[#MCINST5]] SW
-; MMR6-SF-NEXT: # <MCOperand Reg:RA>
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
+; MMR6-SF-NEXT: # <MCOperand Reg:R31>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: .cfi_offset 31, -4
; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #[[#MCINST21]] BALC_MMR6
; MMR6-SF-NEXT: # <MCOperand Expr:__fixdfsi>>
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MMR6-SF-NEXT: # <MCInst #[[#MCINST8]] LW
-; MMR6-SF-NEXT: # <MCOperand Reg:RA>
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
+; MMR6-SF-NEXT: # <MCOperand Reg:R31>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
-; MMR6-SF-NEXT: # <MCOperand Reg:SP>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
+; MMR6-SF-NEXT: # <MCOperand Reg:R29>
; MMR6-SF-NEXT: # <MCOperand Imm:24>>
; MMR6-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM
-; MMR6-SF-NEXT: # <MCOperand Reg:RA>>
+; MMR6-SF-NEXT: # <MCOperand Reg:R31>>
entry:
%conv = fptosi double %t to i32
ret i32 %conv
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/load.ll b/llvm/test/CodeGen/Mips/llvm-ir/load.ll
index d97016bf43321..1dbe384fc037c 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/load.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/load.ll
@@ -27,175 +27,175 @@ define i8 @f1() {
; MIPS32-LABEL: f1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
; MIPS32-NEXT: # <MCOperand Reg:R2>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MMR3-LABEL: f1:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM
; MMR3-NEXT: # <MCOperand Reg:R2>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS32R6-LABEL: f1:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7:]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
; MIPS32R6-NEXT: # <MCOperand Reg:R2>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MMR6-LABEL: f1:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(a)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS3-LABEL: f1:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%highest(a)>>
; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%higher(a)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS3-NEXT: # <MCOperand Reg:R31_64>>
; MIPS3-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
; MIPS3-NEXT: # <MCOperand Reg:R2>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS64-LABEL: f1:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%highest(a)>>
; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%higher(a)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
; MIPS64-NEXT: # <MCOperand Reg:R2>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS64R6-LABEL: f1:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(a)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(a)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
; MIPS64R6-NEXT: # <MCOperand Reg:R2>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MMR5FP64-LABEL: f1:
; MMR5FP64: # %bb.0: # %entry
; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM
; MMR5FP64-NEXT: # <MCOperand Reg:R2>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS32R5FP643-LABEL: f1:
; MIPS32R5FP643: # %bb.0: # %entry
; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS1-PSX-LABEL: f1:
; MIPS1-PSX: # %bb.0: # %entry
; MIPS1-PSX-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS1-PSX-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(a)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R31>>
; MIPS1-PSX-NEXT: nop # <MCInst #[[#MCINST13:]] SLL
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
; MIPS1-PSX-NEXT: # <MCOperand Imm:0>>
entry:
%0 = load i8, ptr @a
@@ -206,175 +206,175 @@ define i32 @f2() {
; MIPS32-LABEL: f2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
; MIPS32-NEXT: # <MCOperand Reg:R2>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MMR3-LABEL: f2:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST15:]] LB_MM
; MMR3-NEXT: # <MCOperand Reg:R2>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS32R6-LABEL: f2:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
; MIPS32R6-NEXT: # <MCOperand Reg:R2>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MMR6-LABEL: f2:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST15:]] LB_MM
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(a)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS3-LABEL: f2:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9]] LUi64
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%highest(a)>>
; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%higher(a)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS3-NEXT: # <MCOperand Reg:R31_64>>
; MIPS3-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
; MIPS3-NEXT: # <MCOperand Reg:R2>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS64-LABEL: f2:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%highest(a)>>
; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%higher(a)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
; MIPS64-NEXT: # <MCOperand Reg:R2>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS64R6-LABEL: f2:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(a)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(a)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
; MIPS64R6-NEXT: # <MCOperand Reg:R2>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MMR5FP64-LABEL: f2:
; MMR5FP64: # %bb.0: # %entry
; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST15:]] LB_MM
; MMR5FP64-NEXT: # <MCOperand Reg:R2>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS32R5FP643-LABEL: f2:
; MIPS32R5FP643: # %bb.0: # %entry
; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS1-PSX-LABEL: f2:
; MIPS1-PSX: # %bb.0: # %entry
; MIPS1-PSX-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1]] LUi
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS1-PSX-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB
; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(a)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R31>>
; MIPS1-PSX-NEXT: nop # <MCInst #[[#MCINST13]] SLL
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
; MIPS1-PSX-NEXT: # <MCOperand Imm:0>>
entry:
%0 = load i8, ptr @a
@@ -386,175 +386,175 @@ define i16 @f3() {
; MIPS32-LABEL: f3:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
; MIPS32-NEXT: # <MCOperand Reg:R2>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MMR3-LABEL: f3:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LHu_MM
; MMR3-NEXT: # <MCOperand Reg:R2>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS32R6-LABEL: f3:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
; MIPS32R6-NEXT: # <MCOperand Reg:R2>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MMR6-LABEL: f3:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LHu_MM
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(b)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS3-LABEL: f3:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%highest(b)>>
; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%higher(b)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS3-NEXT: # <MCOperand Reg:R31_64>>
; MIPS3-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
; MIPS3-NEXT: # <MCOperand Reg:R2>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS64-LABEL: f3:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%highest(b)>>
; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%higher(b)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
; MIPS64-NEXT: # <MCOperand Reg:R2>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS64R6-LABEL: f3:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(b)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(b)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
; MIPS64R6-NEXT: # <MCOperand Reg:R2>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MMR5FP64-LABEL: f3:
; MMR5FP64: # %bb.0: # %entry
; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LHu_MM
; MMR5FP64-NEXT: # <MCOperand Reg:R2>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS32R5FP643-LABEL: f3:
; MIPS32R5FP643: # %bb.0: # %entry
; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS1-PSX-LABEL: f3:
; MIPS1-PSX: # %bb.0: # %entry
; MIPS1-PSX-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS1-PSX-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu
; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(b)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R31>>
; MIPS1-PSX-NEXT: nop # <MCInst #[[#MCINST13]] SLL
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
; MIPS1-PSX-NEXT: # <MCOperand Imm:0>>
entry:
%0 = load i16, ptr @b
@@ -565,175 +565,175 @@ define i32 @f4() {
; MIPS32-LABEL: f4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
; MIPS32-NEXT: # <MCOperand Reg:R2>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MMR3-LABEL: f4:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST19:]] LH_MM
; MMR3-NEXT: # <MCOperand Reg:R2>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS32R6-LABEL: f4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
; MIPS32R6-NEXT: # <MCOperand Reg:R2>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MMR6-LABEL: f4:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST19:]] LH_MM
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(b)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS3-LABEL: f4:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%highest(b)>>
; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%higher(b)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS3-NEXT: # <MCOperand Reg:R31_64>>
; MIPS3-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
; MIPS3-NEXT: # <MCOperand Reg:R2>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS64-LABEL: f4:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%highest(b)>>
; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%higher(b)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
; MIPS64-NEXT: # <MCOperand Reg:R2>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS64R6-LABEL: f4:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(b)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(b)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
; MIPS64R6-NEXT: # <MCOperand Reg:R2>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MMR5FP64-LABEL: f4:
; MMR5FP64: # %bb.0: # %entry
; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST19:]] LH_MM
; MMR5FP64-NEXT: # <MCOperand Reg:R2>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS32R5FP643-LABEL: f4:
; MIPS32R5FP643: # %bb.0: # %entry
; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS1-PSX-LABEL: f4:
; MIPS1-PSX: # %bb.0: # %entry
; MIPS1-PSX-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS1-PSX-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH
; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(b)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R31>>
; MIPS1-PSX-NEXT: nop # <MCInst #[[#MCINST13]] SLL
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
; MIPS1-PSX-NEXT: # <MCOperand Imm:0>>
entry:
%0 = load i16, ptr @b
@@ -745,175 +745,175 @@ define i32 @f5() {
; MIPS32-LABEL: f5:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
; MIPS32-NEXT: # <MCOperand Reg:R2>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MMR3-LABEL: f5:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST21:]] LW_MM
; MMR3-NEXT: # <MCOperand Reg:R2>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS32R6-LABEL: f5:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
; MIPS32R6-NEXT: # <MCOperand Reg:R2>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MMR6-LABEL: f5:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST21:]] LW_MM
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS3-LABEL: f5:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS3-NEXT: # <MCOperand Reg:R31_64>>
; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
; MIPS3-NEXT: # <MCOperand Reg:R2>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS64-LABEL: f5:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
; MIPS64-NEXT: # <MCOperand Reg:R2>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS64R6-LABEL: f5:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
; MIPS64R6-NEXT: # <MCOperand Reg:R2>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MMR5FP64-LABEL: f5:
; MMR5FP64: # %bb.0: # %entry
; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST21:]] LW_MM
; MMR5FP64-NEXT: # <MCOperand Reg:R2>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS32R5FP643-LABEL: f5:
; MIPS32R5FP643: # %bb.0: # %entry
; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS1-PSX-LABEL: f5:
; MIPS1-PSX: # %bb.0: # %entry
; MIPS1-PSX-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS1-PSX-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW
; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R31>>
; MIPS1-PSX-NEXT: nop # <MCInst #[[#MCINST13]] SLL
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
; MIPS1-PSX-NEXT: # <MCOperand Imm:0>>
entry:
%0 = load i32, ptr @c
@@ -924,196 +924,196 @@ define i64 @f6() {
; MIPS32-LABEL: f6:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
; MIPS32-NEXT: # <MCOperand Reg:R3>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST22:]] ADDiu
; MIPS32-NEXT: # <MCOperand Reg:R2>
-; MIPS32-NEXT: # <MCOperand Reg:ZERO>
+; MIPS32-NEXT: # <MCOperand Reg:R0>
; MIPS32-NEXT: # <MCOperand Imm:0>>
;
; MMR3-LABEL: f6:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR3-NEXT: li16 $2, 0 # <MCInst #[[#MCINST23:]] LI16_MM
; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Imm:0>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
; MMR3-NEXT: # <MCOperand Reg:R3>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS32R6-LABEL: f6:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
; MIPS32R6-NEXT: # <MCOperand Reg:R3>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST22:]] ADDiu
; MIPS32R6-NEXT: # <MCOperand Reg:R2>
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
; MIPS32R6-NEXT: # <MCOperand Imm:0>>
;
; MMR6-LABEL: f6:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
; MMR6-NEXT: # <MCOperand Reg:R3>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR6-NEXT: li16 $2, 0 # <MCInst #[[#MCINST23:]] LI16_MM
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS3-LABEL: f6:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS3-NEXT: # <MCOperand Reg:R31_64>>
; MIPS3-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST24:]] LWu
; MIPS3-NEXT: # <MCOperand Reg:R2_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS64-LABEL: f6:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST24:]] LWu
; MIPS64-NEXT: # <MCOperand Reg:R2_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS64R6-LABEL: f6:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST24:]] LWu
; MIPS64R6-NEXT: # <MCOperand Reg:R2_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MMR5FP64-LABEL: f6:
; MMR5FP64: # %bb.0: # %entry
; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR5FP64-NEXT: li16 $2, 0 # <MCInst #[[#MCINST23:]] LI16_MM
; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Imm:0>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
; MMR5FP64-NEXT: # <MCOperand Reg:R3>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS32R5FP643-LABEL: f6:
; MIPS32R5FP643: # %bb.0: # %entry
; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
; MIPS32R5FP643-NEXT: # <MCOperand Reg:R3>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST22:]] ADDiu
; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:ZERO>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R0>
; MIPS32R5FP643-NEXT: # <MCOperand Imm:0>>
;
; MIPS1-PSX-LABEL: f6:
; MIPS1-PSX: # %bb.0: # %entry
; MIPS1-PSX-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS1-PSX-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R31>>
; MIPS1-PSX-NEXT: addiu $3, $zero, 0 # <MCInst #[[#MCINST22:]] ADDiu
; MIPS1-PSX-NEXT: # <MCOperand Reg:R3>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
; MIPS1-PSX-NEXT: # <MCOperand Imm:0>>
entry:
%0 = load i32, ptr @c
@@ -1125,14 +1125,14 @@ define i64 @f7() {
; MIPS32-LABEL: f7:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
; MIPS32-NEXT: # <MCOperand Reg:R3>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA
; MIPS32-NEXT: # <MCOperand Reg:R2>
; MIPS32-NEXT: # <MCOperand Reg:R3>
@@ -1141,14 +1141,14 @@ define i64 @f7() {
; MMR3-LABEL: f7:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
; MMR3-NEXT: # <MCOperand Reg:R3>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST26:]] SRA_MM
; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Reg:R3>
@@ -1157,15 +1157,15 @@ define i64 @f7() {
; MIPS32R6-LABEL: f7:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
; MIPS32R6-NEXT: # <MCOperand Reg:R3>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA
; MIPS32R6-NEXT: # <MCOperand Reg:R2>
; MIPS32R6-NEXT: # <MCOperand Reg:R3>
@@ -1174,115 +1174,115 @@ define i64 @f7() {
; MMR6-LABEL: f7:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
; MMR6-NEXT: # <MCOperand Reg:R3>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR6-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST26:]] SRA_MM
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:R3>
; MMR6-NEXT: # <MCOperand Imm:31>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS3-LABEL: f7:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS3-NEXT: # <MCOperand Reg:R31_64>>
; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST27:]] LW64
; MIPS3-NEXT: # <MCOperand Reg:R2_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS64-LABEL: f7:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST27:]] LW64
; MIPS64-NEXT: # <MCOperand Reg:R2_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS64R6-LABEL: f7:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST27:]] LW64
; MIPS64R6-NEXT: # <MCOperand Reg:R2_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MMR5FP64-LABEL: f7:
; MMR5FP64: # %bb.0: # %entry
; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST21]] LW_MM
; MMR5FP64-NEXT: # <MCOperand Reg:R3>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST26:]] SRA_MM
; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Reg:R3>
@@ -1291,14 +1291,14 @@ define i64 @f7() {
; MIPS32R5FP643-LABEL: f7:
; MIPS32R5FP643: # %bb.0: # %entry
; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
; MIPS32R5FP643-NEXT: # <MCOperand Reg:R3>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA
; MIPS32R5FP643-NEXT: # <MCOperand Reg:R2>
; MIPS32R5FP643-NEXT: # <MCOperand Reg:R3>
@@ -1307,14 +1307,14 @@ define i64 @f7() {
; MIPS1-PSX-LABEL: f7:
; MIPS1-PSX: # %bb.0: # %entry
; MIPS1-PSX-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS1-PSX-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20]] LW
; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(c)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R31>>
; MIPS1-PSX-NEXT: sra $3, $2, 31 # <MCInst #[[#MCINST25:]] SRA
; MIPS1-PSX-NEXT: # <MCOperand Reg:R3>
; MIPS1-PSX-NEXT: # <MCOperand Reg:R2>
@@ -1329,175 +1329,175 @@ define float @f8() {
; MIPS32-LABEL: f8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1
; MIPS32-NEXT: # <MCOperand Reg:F0>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MMR3-LABEL: f8:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(e)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST29:]] LWC1_MM
; MMR3-NEXT: # <MCOperand Reg:F0>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MIPS32R6-LABEL: f8:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1
; MIPS32R6-NEXT: # <MCOperand Reg:F0>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MMR6-LABEL: f8:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(e)>>
; MMR6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST29:]] LWC1_MM
; MMR6-NEXT: # <MCOperand Reg:F0>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(e)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS3-LABEL: f8:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%highest(e)>>
; MIPS3-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%higher(e)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS3-NEXT: # <MCOperand Reg:R31_64>>
; MIPS3-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1
; MIPS3-NEXT: # <MCOperand Reg:F0>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MIPS64-LABEL: f8:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%highest(e)>>
; MIPS64-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%higher(e)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1
; MIPS64-NEXT: # <MCOperand Reg:F0>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MIPS64R6-LABEL: f8:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(e)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(e)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1
; MIPS64R6-NEXT: # <MCOperand Reg:F0>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MMR5FP64-LABEL: f8:
; MMR5FP64: # %bb.0: # %entry
; MMR5FP64-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(e)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST29:]] LWC1_MM
; MMR5FP64-NEXT: # <MCOperand Reg:F0>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MIPS32R5FP643-LABEL: f8:
; MIPS32R5FP643: # %bb.0: # %entry
; MIPS32R5FP643-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1
; MIPS32R5FP643-NEXT: # <MCOperand Reg:F0>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MIPS1-PSX-LABEL: f8:
; MIPS1-PSX: # %bb.0: # %entry
; MIPS1-PSX-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS1-PSX-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1
; MIPS1-PSX-NEXT: # <MCOperand Reg:F0>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(e)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R31>>
; MIPS1-PSX-NEXT: nop # <MCInst #[[#MCINST13]] SLL
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
; MIPS1-PSX-NEXT: # <MCOperand Imm:0>>
entry:
%0 = load float, ptr @e
@@ -1508,179 +1508,179 @@ define double @f9() {
; MIPS32-LABEL: f9:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST30:]] LDC1
; MIPS32-NEXT: # <MCOperand Reg:D0>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MMR3-LABEL: f9:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(f)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC1_MM_D32
; MMR3-NEXT: # <MCOperand Reg:D0>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MIPS32R6-LABEL: f9:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST32:]] LDC164
; MIPS32R6-NEXT: # <MCOperand Reg:D0_64>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MMR6-LABEL: f9:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(f)>>
; MMR6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST33:]] LDC1_D64_MMR6
; MMR6-NEXT: # <MCOperand Reg:D0_64>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(f)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS3-LABEL: f9:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%highest(f)>>
; MIPS3-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%higher(f)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS3-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS3-NEXT: # <MCOperand Reg:R31_64>>
; MIPS3-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST32:]] LDC164
; MIPS3-NEXT: # <MCOperand Reg:D0_64>
-; MIPS3-NEXT: # <MCOperand Reg:AT_64>
+; MIPS3-NEXT: # <MCOperand Reg:R1_64>
; MIPS3-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MIPS64-LABEL: f9:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%highest(f)>>
; MIPS64-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%higher(f)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS64-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST32:]] LDC164
; MIPS64-NEXT: # <MCOperand Reg:D0_64>
-; MIPS64-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64-NEXT: # <MCOperand Reg:R1_64>
; MIPS64-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MIPS64R6-LABEL: f9:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(f)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(f)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST32:]] LDC164
; MIPS64R6-NEXT: # <MCOperand Reg:D0_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MMR5FP64-LABEL: f9:
; MMR5FP64: # %bb.0: # %entry
; MMR5FP64-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(f)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST34:]] LDC1_MM_D64
; MMR5FP64-NEXT: # <MCOperand Reg:D0_64>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MIPS32R5FP643-LABEL: f9:
; MIPS32R5FP643: # %bb.0: # %entry
; MIPS32R5FP643-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST32:]] LDC164
; MIPS32R5FP643-NEXT: # <MCOperand Reg:D0_64>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MIPS1-PSX-LABEL: f9:
; MIPS1-PSX: # %bb.0: # %entry
; MIPS1-PSX-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS1-PSX-NEXT: lwc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST28:]] LWC1
; MIPS1-PSX-NEXT: # <MCOperand Reg:F0>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(f)>>
; MIPS1-PSX-NEXT: lwc1 $f1, %lo(f+4)($1) # <MCInst #[[#MCINST28:]] LWC1
; MIPS1-PSX-NEXT: # <MCOperand Reg:F1>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:AT>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R1>
; MIPS1-PSX-NEXT: # <MCOperand Expr:%lo(f+4)>>
; MIPS1-PSX-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS1-PSX-NEXT: # <MCOperand Reg:RA>>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R31>>
; MIPS1-PSX-NEXT: nop # <MCInst #[[#MCINST13]] SLL
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
-; MIPS1-PSX-NEXT: # <MCOperand Reg:ZERO>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
+; MIPS1-PSX-NEXT: # <MCOperand Reg:R0>
; MIPS1-PSX-NEXT: # <MCOperand Imm:0>>
entry:
%0 = load double, ptr @f
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
index 345180995c948..aab0b12bd238d 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
@@ -105,21 +105,21 @@ define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mtc1 $7, $f2 # <MCInst #[[#MCINST1:]] MTC1
; MM32R3-NEXT: # <MCOperand Reg:F2>
-; MM32R3-NEXT: # <MCOperand Reg:A3>>
+; MM32R3-NEXT: # <MCOperand Reg:R7>>
; MM32R3-NEXT: mthc1 $6, $f2 # <MCInst #[[#MCINST2:]] MTHC1_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D1>
; MM32R3-NEXT: # <MCOperand Reg:D1>
-; MM32R3-NEXT: # <MCOperand Reg:A2>>
+; MM32R3-NEXT: # <MCOperand Reg:R6>>
; MM32R3-NEXT: andi16 $2, $4, 1 # <MCInst #[[#MCINST3:]] ANDI16_MM
; MM32R3-NEXT: # <MCOperand Reg:R2>
-; MM32R3-NEXT: # <MCOperand Reg:A0>
+; MM32R3-NEXT: # <MCOperand Reg:R4>
; MM32R3-NEXT: # <MCOperand Imm:1>>
; MM32R3-NEXT: ldc1 $f0, 16($sp) # <MCInst #[[#MCINST4:]] LDC1_MM_D32
; MM32R3-NEXT: # <MCOperand Reg:D0>
-; MM32R3-NEXT: # <MCOperand Reg:SP>
+; MM32R3-NEXT: # <MCOperand Reg:R29>
; MM32R3-NEXT: # <MCOperand Imm:16>>
; MM32R3-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
-; MM32R3-NEXT: # <MCOperand Reg:RA>>
+; MM32R3-NEXT: # <MCOperand Reg:R31>>
; MM32R3-NEXT: movn.d $f0, $f2, $2 # <MCInst #[[#MCINST6:]] MOVN_I_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D1>
@@ -223,14 +223,14 @@ define double @tst_select_i1_double_reordered(double %x, double %y,
; MM32R3-NEXT: # <MCOperand Reg:D7>>
; MM32R3-NEXT: lw $2, 16($sp) # <MCInst #[[#MCINST8:]] LWSP_MM
; MM32R3-NEXT: # <MCOperand Reg:R2>
-; MM32R3-NEXT: # <MCOperand Reg:SP>
+; MM32R3-NEXT: # <MCOperand Reg:R29>
; MM32R3-NEXT: # <MCOperand Imm:16>>
; MM32R3-NEXT: andi16 $2, $2, 1 # <MCInst #[[#MCINST3]] ANDI16_MM
; MM32R3-NEXT: # <MCOperand Reg:R2>
; MM32R3-NEXT: # <MCOperand Reg:R2>
; MM32R3-NEXT: # <MCOperand Imm:1>>
; MM32R3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MM32R3-NEXT: # <MCOperand Reg:RA>>
+; MM32R3-NEXT: # <MCOperand Reg:R31>>
; MM32R3-NEXT: movn.d $f0, $f12, $2 # <MCInst #[[#MCINST6]] MOVN_I_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D6>
@@ -330,7 +330,7 @@ define double @tst_select_fcmp_olt_double(double %x, double %y) {
; MM32R3-NEXT: # <MCOperand Reg:D7>
; MM32R3-NEXT: # <MCOperand Imm:4>>
; MM32R3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MM32R3-NEXT: # <MCOperand Reg:RA>>
+; MM32R3-NEXT: # <MCOperand Reg:R31>>
; MM32R3-NEXT: movt.d $f0, $f12, $fcc0 # <MCInst #[[#MCINST10:]] MOVT_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D6>
@@ -428,7 +428,7 @@ define double @tst_select_fcmp_ole_double(double %x, double %y) {
; MM32R3-NEXT: # <MCOperand Reg:D7>
; MM32R3-NEXT: # <MCOperand Imm:6>>
; MM32R3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MM32R3-NEXT: # <MCOperand Reg:RA>>
+; MM32R3-NEXT: # <MCOperand Reg:R31>>
; MM32R3-NEXT: movt.d $f0, $f12, $fcc0 # <MCInst #[[#MCINST10]] MOVT_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D6>
@@ -526,7 +526,7 @@ define double @tst_select_fcmp_ogt_double(double %x, double %y) {
; MM32R3-NEXT: # <MCOperand Reg:D7>
; MM32R3-NEXT: # <MCOperand Imm:23>>
; MM32R3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MM32R3-NEXT: # <MCOperand Reg:RA>>
+; MM32R3-NEXT: # <MCOperand Reg:R31>>
; MM32R3-NEXT: movf.d $f0, $f12, $fcc0 # <MCInst #[[#MCINST11:]] MOVF_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D6>
@@ -624,7 +624,7 @@ define double @tst_select_fcmp_oge_double(double %x, double %y) {
; MM32R3-NEXT: # <MCOperand Reg:D7>
; MM32R3-NEXT: # <MCOperand Imm:21>>
; MM32R3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MM32R3-NEXT: # <MCOperand Reg:RA>>
+; MM32R3-NEXT: # <MCOperand Reg:R31>>
; MM32R3-NEXT: movf.d $f0, $f12, $fcc0 # <MCInst #[[#MCINST11]] MOVF_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D6>
@@ -722,7 +722,7 @@ define double @tst_select_fcmp_oeq_double(double %x, double %y) {
; MM32R3-NEXT: # <MCOperand Reg:D7>
; MM32R3-NEXT: # <MCOperand Imm:2>>
; MM32R3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MM32R3-NEXT: # <MCOperand Reg:RA>>
+; MM32R3-NEXT: # <MCOperand Reg:R31>>
; MM32R3-NEXT: movt.d $f0, $f12, $fcc0 # <MCInst #[[#MCINST10]] MOVT_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D6>
@@ -820,7 +820,7 @@ define double @tst_select_fcmp_one_double(double %x, double %y) {
; MM32R3-NEXT: # <MCOperand Reg:D7>
; MM32R3-NEXT: # <MCOperand Imm:19>>
; MM32R3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MM32R3-NEXT: # <MCOperand Reg:RA>>
+; MM32R3-NEXT: # <MCOperand Reg:R31>>
; MM32R3-NEXT: movf.d $f0, $f12, $fcc0 # <MCInst #[[#MCINST11]] MOVF_D32_MM
; MM32R3-NEXT: # <MCOperand Reg:D0>
; MM32R3-NEXT: # <MCOperand Reg:D6>
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/store.ll b/llvm/test/CodeGen/Mips/llvm-ir/store.ll
index b5a930569da71..b79ebc83465b5 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/store.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/store.ll
@@ -25,131 +25,131 @@ define void @f1(i8 %a) {
; MIPS32-LABEL: f1:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST3:]] SB
-; MIPS32-NEXT: # <MCOperand Reg:A0>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R4>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MMR3-LABEL: f1:
; MMR3: # %bb.0:
; MMR3-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST6:]] SB_MM
-; MMR3-NEXT: # <MCOperand Reg:A0>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R4>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS32R6-LABEL: f1:
; MIPS32R6: # %bb.0:
; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7:]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST3:]] SB
-; MIPS32R6-NEXT: # <MCOperand Reg:A0>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R4>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MMR6-LABEL: f1:
; MMR6: # %bb.0:
; MMR6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR6-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST6:]] SB_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R4>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(a)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS4-LABEL: f1:
; MIPS4: # %bb.0:
; MIPS4-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%highest(a)>>
; MIPS4-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%higher(a)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; MIPS4-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS4-NEXT: # <MCOperand Reg:R31_64>>
; MIPS4-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST12:]] SB64
-; MIPS4-NEXT: # <MCOperand Reg:A0_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R4_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS64R6-LABEL: f1:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(a)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(a)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13:]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST12:]] SB64
-; MIPS64R6-NEXT: # <MCOperand Reg:A0_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R4_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MMR5FP64-LABEL: f1:
; MMR5FP64: # %bb.0:
; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(a)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST6:]] SB_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:A0>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R4>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(a)>>
;
; MIPS32R5FP643-LABEL: f1:
; MIPS32R5FP643: # %bb.0:
; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(a)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST3:]] SB
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:A0>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R4>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(a)>>
store i8 %a, ptr @a
ret void
@@ -159,131 +159,131 @@ define void @f2(i16 %a) {
; MIPS32-LABEL: f2:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST14:]] SH
-; MIPS32-NEXT: # <MCOperand Reg:A0>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R4>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MMR3-LABEL: f2:
; MMR3: # %bb.0:
; MMR3-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST15:]] SH_MM
-; MMR3-NEXT: # <MCOperand Reg:A0>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R4>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS32R6-LABEL: f2:
; MIPS32R6: # %bb.0:
; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST14:]] SH
-; MIPS32R6-NEXT: # <MCOperand Reg:A0>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R4>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MMR6-LABEL: f2:
; MMR6: # %bb.0:
; MMR6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR6-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST15:]] SH_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R4>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(b)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS4-LABEL: f2:
; MIPS4: # %bb.0:
; MIPS4-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%highest(b)>>
; MIPS4-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%higher(b)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS4-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS4-NEXT: # <MCOperand Reg:R31_64>>
; MIPS4-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST16:]] SH64
-; MIPS4-NEXT: # <MCOperand Reg:A0_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R4_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS64R6-LABEL: f2:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(b)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(b)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST16:]] SH64
-; MIPS64R6-NEXT: # <MCOperand Reg:A0_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R4_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MMR5FP64-LABEL: f2:
; MMR5FP64: # %bb.0:
; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(b)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST15:]] SH_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:A0>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R4>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(b)>>
;
; MIPS32R5FP643-LABEL: f2:
; MIPS32R5FP643: # %bb.0:
; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(b)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST14:]] SH
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:A0>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R4>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(b)>>
store i16 %a, ptr @b
ret void
@@ -293,131 +293,131 @@ define void @f3(i32 %a) {
; MIPS32-LABEL: f3:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST17:]] SW
-; MIPS32-NEXT: # <MCOperand Reg:A0>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R4>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MMR3-LABEL: f3:
; MMR3: # %bb.0:
; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST18:]] SW_MM
-; MMR3-NEXT: # <MCOperand Reg:A0>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R4>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS32R6-LABEL: f3:
; MIPS32R6: # %bb.0:
; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST17:]] SW
-; MIPS32R6-NEXT: # <MCOperand Reg:A0>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R4>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MMR6-LABEL: f3:
; MMR6: # %bb.0:
; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR6-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST18:]] SW_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R4>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(c)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS4-LABEL: f3:
; MIPS4: # %bb.0:
; MIPS4-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS4-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS4-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS4-NEXT: # <MCOperand Reg:R31_64>>
; MIPS4-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST19:]] SW64
-; MIPS4-NEXT: # <MCOperand Reg:A0_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R4_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS64R6-LABEL: f3:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(c)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(c)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST19:]] SW64
-; MIPS64R6-NEXT: # <MCOperand Reg:A0_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R4_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MMR5FP64-LABEL: f3:
; MMR5FP64: # %bb.0:
; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(c)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST18:]] SW_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:A0>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R4>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(c)>>
;
; MIPS32R5FP643-LABEL: f3:
; MIPS32R5FP643: # %bb.0:
; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(c)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST17:]] SW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:A0>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R4>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(c)>>
store i32 %a, ptr @c
ret void
@@ -427,179 +427,179 @@ define void @f4(i64 %a) {
; MIPS32-LABEL: f4:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(d)>>
; MIPS32-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST17]] SW
-; MIPS32-NEXT: # <MCOperand Reg:A0>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R4>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(d)>>
; MIPS32-NEXT: addiu $1, $1, %lo(d) # <MCInst #[[#MCINST20:]] ADDiu
-; MIPS32-NEXT: # <MCOperand Reg:AT>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(d)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: sw $5, 4($1) # <MCInst #[[#MCINST17]] SW
-; MIPS32-NEXT: # <MCOperand Reg:A1>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R5>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Imm:4>>
;
; MMR3-LABEL: f4:
; MMR3: # %bb.0:
; MMR3-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(d)>>
; MMR3-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST18]] SW_MM
-; MMR3-NEXT: # <MCOperand Reg:A0>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R4>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR3-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM
; MMR3-NEXT: # <MCOperand Reg:R2>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR3-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM
-; MMR3-NEXT: # <MCOperand Reg:A1>
+; MMR3-NEXT: # <MCOperand Reg:R5>
; MMR3-NEXT: # <MCOperand Reg:R2>
; MMR3-NEXT: # <MCOperand Imm:4>>
; MMR3-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
;
; MIPS32R6-LABEL: f4:
; MIPS32R6: # %bb.0:
; MIPS32R6-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(d)>>
; MIPS32R6-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST17]] SW
-; MIPS32R6-NEXT: # <MCOperand Reg:A0>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R4>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(d)>>
; MIPS32R6-NEXT: addiu $1, $1, %lo(d) # <MCInst #[[#MCINST20:]] ADDiu
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(d)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: sw $5, 4($1) # <MCInst #[[#MCINST17]] SW
-; MIPS32R6-NEXT: # <MCOperand Reg:A1>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R5>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Imm:4>>
;
; MMR6-LABEL: f4:
; MMR6: # %bb.0:
; MMR6-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(d)>>
; MMR6-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST18]] SW_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R4>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR6-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR6-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM
-; MMR6-NEXT: # <MCOperand Reg:A1>
+; MMR6-NEXT: # <MCOperand Reg:R5>
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:4>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS4-LABEL: f4:
; MIPS4: # %bb.0:
; MIPS4-NEXT: lui $1, %highest(d) # <MCInst #[[#MCINST9]] LUi64
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%highest(d)>>
; MIPS4-NEXT: daddiu $1, $1, %higher(d) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%higher(d)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: daddiu $1, $1, %hi(d) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%hi(d)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS4-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS4-NEXT: # <MCOperand Reg:R31_64>>
; MIPS4-NEXT: sd $4, %lo(d)($1) # <MCInst #[[#MCINST23:]] SD
-; MIPS4-NEXT: # <MCOperand Reg:A0_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R4_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%lo(d)>>
;
; MIPS64R6-LABEL: f4:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: lui $1, %highest(d) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(d)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(d) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(d)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(d) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(d)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: sd $4, %lo(d)($1) # <MCInst #[[#MCINST23:]] SD
-; MIPS64R6-NEXT: # <MCOperand Reg:A0_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R4_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(d)>>
;
; MMR5FP64-LABEL: f4:
; MMR5FP64: # %bb.0:
; MMR5FP64-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(d)>>
; MMR5FP64-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST18]] SW_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:A0>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R4>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR5FP64-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM
; MMR5FP64-NEXT: # <MCOperand Reg:R2>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(d)>>
; MMR5FP64-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:A1>
+; MMR5FP64-NEXT: # <MCOperand Reg:R5>
; MMR5FP64-NEXT: # <MCOperand Reg:R2>
; MMR5FP64-NEXT: # <MCOperand Imm:4>>
; MMR5FP64-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
;
; MIPS32R5FP643-LABEL: f4:
; MIPS32R5FP643: # %bb.0:
; MIPS32R5FP643-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(d)>>
; MIPS32R5FP643-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST17]] SW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:A0>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R4>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(d)>>
; MIPS32R5FP643-NEXT: addiu $1, $1, %lo(d) # <MCInst #[[#MCINST20:]] ADDiu
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(d)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: sw $5, 4($1) # <MCInst #[[#MCINST17]] SW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:A1>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R5>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Imm:4>>
store i64 %a, ptr @d
ret void
@@ -609,131 +609,131 @@ define void @f5(float %e) {
; MIPS32-LABEL: f5:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1
; MIPS32-NEXT: # <MCOperand Reg:F12>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MMR3-LABEL: f5:
; MMR3: # %bb.0:
; MMR3-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(e)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST25:]] SWC1_MM
; MMR3-NEXT: # <MCOperand Reg:F12>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MIPS32R6-LABEL: f5:
; MIPS32R6: # %bb.0:
; MIPS32R6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1
; MIPS32R6-NEXT: # <MCOperand Reg:F12>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MMR6-LABEL: f5:
; MMR6: # %bb.0:
; MMR6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(e)>>
; MMR6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST25:]] SWC1_MM
; MMR6-NEXT: # <MCOperand Reg:F12>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(e)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS4-LABEL: f5:
; MIPS4: # %bb.0:
; MIPS4-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%highest(e)>>
; MIPS4-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%higher(e)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS4-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS4-NEXT: # <MCOperand Reg:R31_64>>
; MIPS4-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1
; MIPS4-NEXT: # <MCOperand Reg:F12>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MIPS64R6-LABEL: f5:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(e)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(e)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1
; MIPS64R6-NEXT: # <MCOperand Reg:F12>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MMR5FP64-LABEL: f5:
; MMR5FP64: # %bb.0:
; MMR5FP64-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(e)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST25:]] SWC1_MM
; MMR5FP64-NEXT: # <MCOperand Reg:F12>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(e)>>
;
; MIPS32R5FP643-LABEL: f5:
; MIPS32R5FP643: # %bb.0:
; MIPS32R5FP643-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(e)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1
; MIPS32R5FP643-NEXT: # <MCOperand Reg:F12>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(e)>>
store float %e, ptr @e
ret void
@@ -743,131 +743,131 @@ define void @f6(double %f) {
; MIPS32-LABEL: f6:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32-NEXT: # <MCOperand Reg:RA>>
+; MIPS32-NEXT: # <MCOperand Reg:R31>>
; MIPS32-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST26:]] SDC1
; MIPS32-NEXT: # <MCOperand Reg:D6>
-; MIPS32-NEXT: # <MCOperand Reg:AT>
+; MIPS32-NEXT: # <MCOperand Reg:R1>
; MIPS32-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MMR3-LABEL: f6:
; MMR3: # %bb.0:
; MMR3-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%hi(f)>>
; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR3-NEXT: # <MCOperand Reg:RA>>
+; MMR3-NEXT: # <MCOperand Reg:R31>>
; MMR3-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST27:]] SDC1_MM_D32
; MMR3-NEXT: # <MCOperand Reg:D6>
-; MMR3-NEXT: # <MCOperand Reg:AT>
+; MMR3-NEXT: # <MCOperand Reg:R1>
; MMR3-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MIPS32R6-LABEL: f6:
; MIPS32R6: # %bb.0:
; MIPS32R6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:ZERO>
-; MIPS32R6-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R6-NEXT: # <MCOperand Reg:R0>
+; MIPS32R6-NEXT: # <MCOperand Reg:R31>>
; MIPS32R6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164
; MIPS32R6-NEXT: # <MCOperand Reg:D12_64>
-; MIPS32R6-NEXT: # <MCOperand Reg:AT>
+; MIPS32R6-NEXT: # <MCOperand Reg:R1>
; MIPS32R6-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MMR6-LABEL: f6:
; MMR6: # %bb.0:
; MMR6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%hi(f)>>
; MMR6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST29:]] SDC1_D64_MMR6
; MMR6-NEXT: # <MCOperand Reg:D12_64>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:%lo(f)>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
;
; MIPS4-LABEL: f6:
; MIPS4: # %bb.0:
; MIPS4-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%highest(f)>>
; MIPS4-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%higher(f)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS4-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS4-NEXT: # <MCOperand Reg:R31_64>>
; MIPS4-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164
; MIPS4-NEXT: # <MCOperand Reg:D12_64>
-; MIPS4-NEXT: # <MCOperand Reg:AT_64>
+; MIPS4-NEXT: # <MCOperand Reg:R1_64>
; MIPS4-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MIPS64R6-LABEL: f6:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%highest(f)>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%higher(f)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:ZERO_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:RA_64>>
+; MIPS64R6-NEXT: # <MCOperand Reg:R0_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R31_64>>
; MIPS64R6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164
; MIPS64R6-NEXT: # <MCOperand Reg:D12_64>
-; MIPS64R6-NEXT: # <MCOperand Reg:AT_64>
+; MIPS64R6-NEXT: # <MCOperand Reg:R1_64>
; MIPS64R6-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MMR5FP64-LABEL: f6:
; MMR5FP64: # %bb.0:
; MMR5FP64-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%hi(f)>>
; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:RA>>
+; MMR5FP64-NEXT: # <MCOperand Reg:R31>>
; MMR5FP64-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST30:]] SDC1_MM_D64
; MMR5FP64-NEXT: # <MCOperand Reg:D12_64>
-; MMR5FP64-NEXT: # <MCOperand Reg:AT>
+; MMR5FP64-NEXT: # <MCOperand Reg:R1>
; MMR5FP64-NEXT: # <MCOperand Expr:%lo(f)>>
;
; MIPS32R5FP643-LABEL: f6:
; MIPS32R5FP643: # %bb.0:
; MIPS32R5FP643-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%hi(f)>>
; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:RA>>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R31>>
; MIPS32R5FP643-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164
; MIPS32R5FP643-NEXT: # <MCOperand Reg:D12_64>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:AT>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:R1>
; MIPS32R5FP643-NEXT: # <MCOperand Expr:%lo(f)>>
store double %f, ptr @f
ret void
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
index 6eaa4d16614c5..b8299fe659100 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
@@ -72,65 +72,65 @@ body: |
; MM: bb.0.entry:
; MM: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
- ; MM: BC1F_MM $fcc0, %bb.2, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: BC1F_MM $fcc0, %bb.2, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.1.entry:
; MM: successors: %bb.3(0x80000000)
- ; MM: J %bb.3, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: J %bb.3, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.2.if.then:
- ; MM: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
+ ; MM: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
; MM: $r2 = LI16_MM 0
- ; MM: JRC16_MM undef $ra, implicit killed $r2
+ ; MM: JRC16_MM undef $r31, implicit killed $r2
; MM: bb.3.return:
; MM: $r2 = LI16_MM 1
- ; MM: JRC16_MM undef $ra, implicit killed $r2
+ ; MM: JRC16_MM undef $r31, implicit killed $r2
; PIC-LABEL: name: a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
- ; PIC: BC1F_MM $fcc0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL_MM $zero, 0
+ ; PIC: BC1F_MM $fcc0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL_MM $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
; PIC: $r2 = LI16_MM 0
- ; PIC: JRC16_MM undef $ra, implicit killed $r2
+ ; PIC: JRC16_MM undef $r31, implicit killed $r2
; PIC: bb.4.return:
; PIC: $r2 = LI16_MM 1
- ; PIC: JRC16_MM undef $ra, implicit killed $r2
+ ; PIC: JRC16_MM undef $r31, implicit killed $r2
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d6, $d7
FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
- BC1T_MM killed $fcc0, %bb.2, implicit-def dead $at
+ BC1T_MM killed $fcc0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $r1
$r2 = LI16_MM 0
- PseudoReturn undef $ra, implicit killed $r2
+ PseudoReturn undef $r31, implicit killed $r2
bb.2.return:
$r2 = LI16_MM 1
- PseudoReturn undef $ra, implicit killed $r2
+ PseudoReturn undef $r31, implicit killed $r2
...
---
@@ -172,44 +172,44 @@ body: |
; MM: bb.0.entry:
; MM: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
- ; MM: BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: BC1F_MM killed $fcc0, %bb.1, implicit-def dead $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.1.return:
; MM: $r2 = LI16_MM 1
- ; MM: JRC16_MM undef $ra, implicit killed $r2
+ ; MM: JRC16_MM undef $r31, implicit killed $r2
; MM: bb.2.if.then:
- ; MM: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
+ ; MM: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
; MM: $r2 = LI16_MM 0
- ; MM: JRC16_MM undef $ra, implicit killed $r2
+ ; MM: JRC16_MM undef $r31, implicit killed $r2
; PIC-LABEL: name: b
; PIC: bb.0.entry:
; PIC: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
- ; PIC: BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
- ; PIC: $zero = SLL_MM $zero, 0
+ ; PIC: BC1F_MM killed $fcc0, %bb.1, implicit-def dead $r1 {
+ ; PIC: $r0 = SLL_MM $r0, 0
; PIC: }
; PIC: bb.1.return:
; PIC: $r2 = LI16_MM 1
- ; PIC: JRC16_MM undef $ra, implicit killed $r2
+ ; PIC: JRC16_MM undef $r31, implicit killed $r2
; PIC: bb.2.if.then:
- ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
; PIC: $r2 = LI16_MM 0
- ; PIC: JRC16_MM undef $ra, implicit killed $r2
+ ; PIC: JRC16_MM undef $r31, implicit killed $r2
bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $d6, $d7
FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
- BC1F_MM killed $fcc0, %bb.2, implicit-def dead $at
+ BC1F_MM killed $fcc0, %bb.2, implicit-def dead $r1
bb.2.return:
$r2 = LI16_MM 1
- PseudoReturn undef $ra, implicit killed $r2
+ PseudoReturn undef $r31, implicit killed $r2
bb.1.if.then:
- INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $r1
$r2 = LI16_MM 0
- PseudoReturn undef $ra, implicit killed $r2
+ PseudoReturn undef $r31, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
index fe4258cf1fedf..bbe7f6972fc73 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
@@ -72,57 +72,57 @@ body: |
; MM: bb.0.entry:
; MM: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; MM: $d0_64 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
- ; MM: BC1EQZC_MMR6 $d0_64, %bb.2, implicit-def $at
+ ; MM: BC1EQZC_MMR6 $d0_64, %bb.2, implicit-def $r1
; MM: bb.1.entry:
; MM: successors: %bb.3(0x80000000)
; MM: BC_MMR6 %bb.3
; MM: bb.2.if.then:
- ; MM: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
+ ; MM: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
; MM: $r2 = LI16_MM 0
- ; MM: JRC16_MM undef $ra, implicit $r2
+ ; MM: JRC16_MM undef $r31, implicit $r2
; MM: bb.3.return:
; MM: $r2 = LI16_MM 1
- ; MM: JRC16_MM undef $ra, implicit $r2
+ ; MM: JRC16_MM undef $r31, implicit $r2
; PIC-LABEL: name: a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: $d0_64 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
- ; PIC: BC1EQZC_MMR6 $d0_64, %bb.3, implicit-def $at
+ ; PIC: BC1EQZC_MMR6 $d0_64, %bb.3, implicit-def $r1
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
; PIC: $r2 = LI16_MM 0
- ; PIC: JRC16_MM undef $ra, implicit $r2
+ ; PIC: JRC16_MM undef $r31, implicit $r2
; PIC: bb.4.return:
; PIC: $r2 = LI16_MM 1
- ; PIC: JRC16_MM undef $ra, implicit $r2
+ ; PIC: JRC16_MM undef $r31, implicit $r2
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d12_64, $d14_64
$d0_64 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
- BC1NEZC_MMR6 killed $d0_64, %bb.2, implicit-def $at
+ BC1NEZC_MMR6 killed $d0_64, %bb.2, implicit-def $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
$r2 = LI16_MM 0
- PseudoReturn undef $ra, implicit $r2
+ PseudoReturn undef $r31, implicit $r2
bb.2.return:
$r2 = LI16_MM 1
- PseudoReturn undef $ra, implicit $r2
+ PseudoReturn undef $r31, implicit $r2
...
---
@@ -164,56 +164,56 @@ body: |
; MM: bb.0.entry:
; MM: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; MM: $d0_64 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
- ; MM: BC1NEZC_MMR6 $d0_64, %bb.2, implicit-def $at
+ ; MM: BC1NEZC_MMR6 $d0_64, %bb.2, implicit-def $r1
; MM: bb.1.entry:
; MM: successors: %bb.3(0x80000000)
; MM: BC_MMR6 %bb.3
; MM: bb.2.if.then:
- ; MM: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
+ ; MM: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
; MM: $r2 = LI16_MM 0
- ; MM: JRC16_MM undef $ra, implicit $r2
+ ; MM: JRC16_MM undef $r31, implicit $r2
; MM: bb.3.return:
; MM: $r2 = LI16_MM 1
- ; MM: JRC16_MM undef $ra, implicit $r2
+ ; MM: JRC16_MM undef $r31, implicit $r2
; PIC-LABEL: name: b
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; PIC: $d0_64 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
- ; PIC: BC1NEZC_MMR6 $d0_64, %bb.3, implicit-def $at
+ ; PIC: BC1NEZC_MMR6 $d0_64, %bb.3, implicit-def $r1
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
; PIC: $r2 = LI16_MM 0
- ; PIC: JRC16_MM undef $ra, implicit $r2
+ ; PIC: JRC16_MM undef $r31, implicit $r2
; PIC: bb.4.return:
; PIC: $r2 = LI16_MM 1
- ; PIC: JRC16_MM undef $ra, implicit $r2
+ ; PIC: JRC16_MM undef $r31, implicit $r2
bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $d12_64, $d14_64
$d0_64 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
- BC1EQZC_MMR6 killed $d0_64, %bb.2, implicit-def $at
+ BC1EQZC_MMR6 killed $d0_64, %bb.2, implicit-def $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
$r2 = LI16_MM 0
- PseudoReturn undef $ra, implicit $r2
+ PseudoReturn undef $r31, implicit $r2
bb.2.return:
$r2 = LI16_MM 1
- PseudoReturn undef $ra, implicit $r2
+ PseudoReturn undef $r31, implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
index 0ca457ae56350..3d1574ba89bea 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
@@ -71,69 +71,69 @@ body: |
; MIPS: bb.0.entry:
; MIPS: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
- ; MIPS: BC1F $fcc0, %bb.2, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: BC1F $fcc0, %bb.2, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.1.entry:
; MIPS: successors: %bb.3(0x80000000)
- ; MIPS: J %bb.3, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: J %bb.3, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.2.if.then:
- ; MIPS: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MIPS: PseudoReturn undef $ra, implicit killed $r2 {
- ; MIPS: $r2 = ADDiu $zero, 0
+ ; MIPS: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MIPS: PseudoReturn undef $r31, implicit killed $r2 {
+ ; MIPS: $r2 = ADDiu $r0, 0
; MIPS: }
; MIPS: bb.3.return:
- ; MIPS: PseudoReturn undef $ra, implicit killed $r2 {
- ; MIPS: $r2 = ADDiu $zero, 1
+ ; MIPS: PseudoReturn undef $r31, implicit killed $r2 {
+ ; MIPS: $r2 = ADDiu $r0, 1
; MIPS: }
; PIC-LABEL: name: a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
- ; PIC: BC1F $fcc0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BC1F $fcc0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
- ; PIC: $r2 = ADDiu $zero, 0
+ ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn undef $r31, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $r0, 0
; PIC: }
; PIC: bb.4.return:
- ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
- ; PIC: $r2 = ADDiu $zero, 1
+ ; PIC: PseudoReturn undef $r31, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $r0, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d6, $d7
FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
- BC1T killed $fcc0, %bb.2, implicit-def $at
+ BC1T killed $fcc0, %bb.2, implicit-def $r1
bb.1.if.then:
- INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
- $r2 = ADDiu $zero, 0
- PseudoReturn undef $ra, implicit killed $r2
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $r1
+ $r2 = ADDiu $r0, 0
+ PseudoReturn undef $r31, implicit killed $r2
bb.2.return:
- $r2 = ADDiu $zero, 1
- PseudoReturn undef $ra, implicit killed $r2
+ $r2 = ADDiu $r0, 1
+ PseudoReturn undef $r31, implicit killed $r2
...
---
@@ -175,68 +175,68 @@ body: |
; MIPS: bb.0.entry:
; MIPS: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
- ; MIPS: BC1T $fcc0, %bb.2, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: BC1T $fcc0, %bb.2, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.1.entry:
; MIPS: successors: %bb.3(0x80000000)
- ; MIPS: J %bb.3, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: J %bb.3, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.2.if.then:
- ; MIPS: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MIPS: PseudoReturn undef $ra, implicit killed $r2 {
- ; MIPS: $r2 = ADDiu $zero, 0
+ ; MIPS: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MIPS: PseudoReturn undef $r31, implicit killed $r2 {
+ ; MIPS: $r2 = ADDiu $r0, 0
; MIPS: }
; MIPS: bb.3.return:
- ; MIPS: PseudoReturn undef $ra, implicit killed $r2 {
- ; MIPS: $r2 = ADDiu $zero, 1
+ ; MIPS: PseudoReturn undef $r31, implicit killed $r2 {
+ ; MIPS: $r2 = ADDiu $r0, 1
; MIPS: }
; PIC-LABEL: name: b
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
- ; PIC: BC1T $fcc0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BC1T $fcc0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
- ; PIC: $r2 = ADDiu $zero, 0
+ ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn undef $r31, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $r0, 0
; PIC: }
; PIC: bb.4.return:
- ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
- ; PIC: $r2 = ADDiu $zero, 1
+ ; PIC: PseudoReturn undef $r31, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $r0, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d6, $d7
FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
- BC1F killed $fcc0, %bb.2, implicit-def $at
+ BC1F killed $fcc0, %bb.2, implicit-def $r1
bb.1.if.then:
- INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
- $r2 = ADDiu $zero, 0
- PseudoReturn undef $ra, implicit killed $r2
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $r1
+ $r2 = ADDiu $r0, 0
+ PseudoReturn undef $r31, implicit killed $r2
bb.2.return:
- $r2 = ADDiu $zero, 1
- PseudoReturn undef $ra, implicit killed $r2
+ $r2 = ADDiu $r0, 1
+ PseudoReturn undef $r31, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
index a6250ba6f50b1..5d28ebfab5c54 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
@@ -74,64 +74,64 @@ body: |
; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; R6: $d0_64 = CMP_EQ_D killed $d12_64, killed $d14_64
; R6: BC1NEZ $d0_64, %bb.2 {
- ; R6: $zero = SLL $zero, 0
+ ; R6: $r0 = SLL $r0, 0
; R6: }
; R6: bb.1.entry:
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
; R6: bb.2.if.then:
- ; R6: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; R6: PseudoReturn undef $ra, implicit killed $r2 {
- ; R6: $r2 = ADDiu $zero, 0
+ ; R6: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; R6: PseudoReturn undef $r31, implicit killed $r2 {
+ ; R6: $r2 = ADDiu $r0, 0
; R6: }
; R6: bb.3.return:
- ; R6: PseudoReturn undef $ra, implicit killed $r2 {
- ; R6: $r2 = ADDiu $zero, 1
+ ; R6: PseudoReturn undef $r31, implicit killed $r2 {
+ ; R6: $r2 = ADDiu $r0, 1
; R6: }
; PIC-LABEL: name: a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: $d0_64 = CMP_EQ_D killed $d12_64, killed $d14_64
; PIC: BC1NEZ $d0_64, %bb.3 {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
- ; PIC: $r2 = ADDiu $zero, 0
+ ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn undef $r31, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $r0, 0
; PIC: }
; PIC: bb.4.return:
- ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
- ; PIC: $r2 = ADDiu $zero, 1
+ ; PIC: PseudoReturn undef $r31, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $r0, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d12_64, $d14_64
$d0_64 = CMP_EQ_D killed $d12_64, killed $d14_64
- BC1EQZ killed $d0_64, %bb.2, implicit-def $at
+ BC1EQZ killed $d0_64, %bb.2, implicit-def $r1
bb.1.if.then:
- INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
- $r2 = ADDiu $zero, 0
- PseudoReturn undef $ra, implicit killed $r2
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $r1
+ $r2 = ADDiu $r0, 0
+ PseudoReturn undef $r31, implicit killed $r2
bb.2.return:
- $r2 = ADDiu $zero, 1
- PseudoReturn undef $ra, implicit killed $r2
+ $r2 = ADDiu $r0, 1
+ PseudoReturn undef $r31, implicit killed $r2
...
---
@@ -174,63 +174,63 @@ body: |
; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; R6: $d0_64 = CMP_EQ_D killed $d12_64, killed $d14_64
; R6: BC1EQZ $d0_64, %bb.2 {
- ; R6: $zero = SLL $zero, 0
+ ; R6: $r0 = SLL $r0, 0
; R6: }
; R6: bb.1.entry:
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
; R6: bb.2.if.then:
- ; R6: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; R6: PseudoReturn undef $ra, implicit killed $r2 {
- ; R6: $r2 = ADDiu $zero, 0
+ ; R6: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; R6: PseudoReturn undef $r31, implicit killed $r2 {
+ ; R6: $r2 = ADDiu $r0, 0
; R6: }
; R6: bb.3.return:
- ; R6: PseudoReturn undef $ra, implicit killed $r2 {
- ; R6: $r2 = ADDiu $zero, 1
+ ; R6: PseudoReturn undef $r31, implicit killed $r2 {
+ ; R6: $r2 = ADDiu $r0, 1
; R6: }
; PIC-LABEL: name: b
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: $d0_64 = CMP_EQ_D killed $d12_64, killed $d14_64
; PIC: BC1EQZ $d0_64, %bb.3 {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
- ; PIC: $r2 = ADDiu $zero, 0
+ ; PIC: INLINEASM &".space 310680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn undef $r31, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $r0, 0
; PIC: }
; PIC: bb.4.return:
- ; PIC: PseudoReturn undef $ra, implicit killed $r2 {
- ; PIC: $r2 = ADDiu $zero, 1
+ ; PIC: PseudoReturn undef $r31, implicit killed $r2 {
+ ; PIC: $r2 = ADDiu $r0, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d12_64, $d14_64
$d0_64 = CMP_EQ_D killed $d12_64, killed $d14_64
- BC1NEZ killed $d0_64, %bb.2, implicit-def $at
+ BC1NEZ killed $d0_64, %bb.2, implicit-def $r1
bb.1.if.then:
- INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
- $r2 = ADDiu $zero, 0
- PseudoReturn undef $ra, implicit killed $r2
+ INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $r1
+ $r2 = ADDiu $r0, 0
+ PseudoReturn undef $r31, implicit killed $r2
bb.2.return:
- $r2 = ADDiu $zero, 1
- PseudoReturn undef $ra, implicit killed $r2
+ $r2 = ADDiu $r0, 1
+ PseudoReturn undef $r31, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
index bebb66dfe29bd..68b6062500f05 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
@@ -106,7 +106,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -132,49 +132,49 @@ body: |
; MM-LABEL: name: expand_BEQ_MM
; MM: bb.0 (%ir-block.0):
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MM: renamable $at = ANDi killed renamable $a0, 1
- ; MM: BNEZC_MM $at, %bb.2, implicit-def $at
+ ; MM: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MM: BNEZC_MM $r1, %bb.2, implicit-def $r1
; MM: bb.1 (%ir-block.0):
; MM: successors: %bb.3(0x80000000)
- ; MM: J %bb.3, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: J %bb.3, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.2.iftrue:
; MM: successors: %bb.3(0x80000000)
; MM: INLINEASM &".space 131068", sideeffect attdialect
; MM: bb.3.tail:
- ; MM: JRC16_MM undef $ra
+ ; MM: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BEQ_MM
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BNEZC_MM $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BNEZC_MM $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BEQ_MM killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BEQ_MM killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -182,7 +182,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -197,7 +197,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -223,53 +223,53 @@ body: |
; MM-LABEL: name: expand_BGEZ_MM
; MM: bb.0 (%ir-block.0):
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MM: renamable $at = ANDi killed renamable $a0, 1
- ; MM: BLTZ_MM $at, %bb.2, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MM: BLTZ_MM $r1, %bb.2, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.1 (%ir-block.0):
; MM: successors: %bb.3(0x80000000)
- ; MM: J %bb.3, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: J %bb.3, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.2.iftrue:
; MM: successors: %bb.3(0x80000000)
; MM: INLINEASM &".space 131068", sideeffect attdialect
; MM: bb.3.tail:
- ; MM: JRC16_MM undef $ra
+ ; MM: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BGEZ_MM
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLTZ_MM $at, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL_MM $zero, 0
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLTZ_MM $r1, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL_MM $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGEZ_MM killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGEZ_MM killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -277,7 +277,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -292,7 +292,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -318,53 +318,53 @@ body: |
; MM-LABEL: name: expand_BGTZ_MM
; MM: bb.0 (%ir-block.0):
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MM: renamable $at = ANDi killed renamable $a0, 1
- ; MM: BLEZ_MM $at, %bb.2, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MM: BLEZ_MM $r1, %bb.2, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.1 (%ir-block.0):
; MM: successors: %bb.3(0x80000000)
- ; MM: J %bb.3, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: J %bb.3, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.2.iftrue:
; MM: successors: %bb.3(0x80000000)
; MM: INLINEASM &".space 131068", sideeffect attdialect
; MM: bb.3.tail:
- ; MM: JRC16_MM undef $ra
+ ; MM: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BGTZ_MM
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLEZ_MM $at, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL_MM $zero, 0
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLEZ_MM $r1, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL_MM $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGTZ_MM killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGTZ_MM killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -372,7 +372,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -387,7 +387,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -413,53 +413,53 @@ body: |
; MM-LABEL: name: expand_BLEZ_MM
; MM: bb.0 (%ir-block.0):
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MM: renamable $at = ANDi killed renamable $a0, 1
- ; MM: BGTZ_MM $at, %bb.2, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MM: BGTZ_MM $r1, %bb.2, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.1 (%ir-block.0):
; MM: successors: %bb.3(0x80000000)
- ; MM: J %bb.3, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: J %bb.3, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.2.iftrue:
; MM: successors: %bb.3(0x80000000)
; MM: INLINEASM &".space 131068", sideeffect attdialect
; MM: bb.3.tail:
- ; MM: JRC16_MM undef $ra
+ ; MM: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BLEZ_MM
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGTZ_MM $at, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL_MM $zero, 0
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGTZ_MM $r1, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL_MM $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLEZ_MM killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLEZ_MM killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -467,7 +467,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -482,7 +482,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -508,53 +508,53 @@ body: |
; MM-LABEL: name: expand_BLTZ_MM
; MM: bb.0 (%ir-block.0):
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MM: renamable $at = ANDi killed renamable $a0, 1
- ; MM: BGEZ_MM $at, %bb.2, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MM: BGEZ_MM $r1, %bb.2, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.1 (%ir-block.0):
; MM: successors: %bb.3(0x80000000)
- ; MM: J %bb.3, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: J %bb.3, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.2.iftrue:
; MM: successors: %bb.3(0x80000000)
; MM: INLINEASM &".space 131068", sideeffect attdialect
; MM: bb.3.tail:
- ; MM: JRC16_MM undef $ra
+ ; MM: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BLTZ_MM
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGEZ_MM $at, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL_MM $zero, 0
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGEZ_MM $r1, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL_MM $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLTZ_MM killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLTZ_MM killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -562,7 +562,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -577,7 +577,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -603,49 +603,49 @@ body: |
; MM-LABEL: name: expand_BNE_MM
; MM: bb.0 (%ir-block.0):
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MM: renamable $at = ANDi killed renamable $a0, 1
- ; MM: BEQZC_MM $at, %bb.2, implicit-def $at
+ ; MM: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MM: BEQZC_MM $r1, %bb.2, implicit-def $r1
; MM: bb.1 (%ir-block.0):
; MM: successors: %bb.3(0x80000000)
- ; MM: J %bb.3, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: J %bb.3, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.2.iftrue:
; MM: successors: %bb.3(0x80000000)
; MM: INLINEASM &".space 131068", sideeffect attdialect
; MM: bb.3.tail:
- ; MM: JRC16_MM undef $ra
+ ; MM: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BNE_MM
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BEQZC_MM $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BEQZC_MM $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BNE_MM killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BNE_MM killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -653,7 +653,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -668,7 +668,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -694,53 +694,53 @@ body: |
; MM-LABEL: name: expand_BEQZ16_MM
; MM: bb.0 (%ir-block.0):
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MM: renamable $r2 = ANDi killed renamable $a0, 1
- ; MM: BNEZ16_MM $r2, %bb.2, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: renamable $r2 = ANDi killed renamable $r4, 1
+ ; MM: BNEZ16_MM $r2, %bb.2, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.1 (%ir-block.0):
; MM: successors: %bb.3(0x80000000)
- ; MM: J %bb.3, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: J %bb.3, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.2.iftrue:
; MM: successors: %bb.3(0x80000000)
; MM: INLINEASM &".space 131068", sideeffect attdialect
; MM: bb.3.tail:
- ; MM: JRC16_MM undef $ra
+ ; MM: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BEQZ16_MM
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $r2 = ANDi killed renamable $a0, 1
- ; PIC: BNEZ16_MM $r2, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL_MM $zero, 0
+ ; PIC: renamable $r2 = ANDi killed renamable $r4, 1
+ ; PIC: BNEZ16_MM $r2, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL_MM $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $r2 = ANDi killed renamable $a0, 1
- BEQZ16_MM killed renamable $r2, %bb.2, implicit-def $at
+ renamable $r2 = ANDi killed renamable $r4, 1
+ BEQZ16_MM killed renamable $r2, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -748,7 +748,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -763,7 +763,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -789,53 +789,53 @@ body: |
; MM-LABEL: name: expand_BNEZ16_MM
; MM: bb.0 (%ir-block.0):
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MM: renamable $r2 = ANDi killed renamable $a0, 1
- ; MM: BEQZ16_MM $r2, %bb.2, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: renamable $r2 = ANDi killed renamable $r4, 1
+ ; MM: BEQZ16_MM $r2, %bb.2, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.1 (%ir-block.0):
; MM: successors: %bb.3(0x80000000)
- ; MM: J %bb.3, implicit-def $at {
- ; MM: $zero = SLL_MM $zero, 0
+ ; MM: J %bb.3, implicit-def $r1 {
+ ; MM: $r0 = SLL_MM $r0, 0
; MM: }
; MM: bb.2.iftrue:
; MM: successors: %bb.3(0x80000000)
; MM: INLINEASM &".space 131068", sideeffect attdialect
; MM: bb.3.tail:
- ; MM: JRC16_MM undef $ra
+ ; MM: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BNEZ16_MM
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $r2 = ANDi killed renamable $a0, 1
- ; PIC: BEQZ16_MM $r2, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL_MM $zero, 0
+ ; PIC: renamable $r2 = ANDi killed renamable $r4, 1
+ ; PIC: BEQZ16_MM $r2, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL_MM $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR_MM %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $r2 = ANDi killed renamable $a0, 1
- BNEZ16_MM killed renamable $r2, %bb.2, implicit-def $at
+ renamable $r2 = ANDi killed renamable $r4, 1
+ BNEZ16_MM killed renamable $r2, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -843,6 +843,6 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
index 644f98a51016a..d9c73e3cda070 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
@@ -150,7 +150,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -176,8 +176,8 @@ body: |
; MMR6-LABEL: name: expand_BEQC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BNEC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BNEC_MMR6 $r1, $r0, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -185,36 +185,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 131068", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BEQC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BNEC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BNEC_MMR6 $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BEQC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BEQC_MMR6 killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -222,7 +222,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -237,7 +237,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -263,8 +263,8 @@ body: |
; MMR6-LABEL: name: expand_BNEC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BEQC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BEQC_MMR6 $r1, $r0, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -272,36 +272,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 131068", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BNEC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BEQC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BEQC_MMR6 $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BNEC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BNEC_MMR6 killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -309,7 +309,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -324,7 +324,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -350,8 +350,8 @@ body: |
; MMR6-LABEL: name: expand_BGEC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BLTC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BLTC_MMR6 $r1, $r0, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -359,36 +359,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 131068", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BGEC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLTC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLTC_MMR6 $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGEC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGEC_MMR6 killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -396,7 +396,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -411,7 +411,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -437,8 +437,8 @@ body: |
; MMR6-LABEL: name: expand_BGEUC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BLTUC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BLTUC_MMR6 $r1, $r0, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -446,36 +446,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 131068", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BGEUC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLTUC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLTUC_MMR6 $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGEUC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGEUC_MMR6 killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -483,7 +483,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -498,7 +498,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -524,8 +524,8 @@ body: |
; MMR6-LABEL: name: expand_BGEZC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BLTZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BLTZC_MMR6 $r1, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -533,36 +533,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 131068", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BGEZC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLTZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLTZC_MMR6 $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGEZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGEZC_MMR6 killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -570,7 +570,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -585,7 +585,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -611,8 +611,8 @@ body: |
; MMR6-LABEL: name: expand_BGTZC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BLEZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BLEZC_MMR6 $r1, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -620,36 +620,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 131068", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BGTZC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLEZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLEZC_MMR6 $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGTZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGTZC_MMR6 killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -657,7 +657,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -672,7 +672,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -698,8 +698,8 @@ body: |
; MMR6-LABEL: name: expand_BLEZC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BGTZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BGTZC_MMR6 $r1, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -707,36 +707,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 131068", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BLEZC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGTZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGTZC_MMR6 $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLEZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLEZC_MMR6 killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -744,7 +744,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -759,7 +759,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -785,8 +785,8 @@ body: |
; MMR6-LABEL: name: expand_BLTC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BGEC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BGEC_MMR6 $r1, $r0, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -794,36 +794,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 131068", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BLTC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGEC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGEC_MMR6 $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLTC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLTC_MMR6 killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -831,7 +831,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -846,7 +846,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -872,8 +872,8 @@ body: |
; MMR6-LABEL: name: expand_BLTUC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BGEUC_MMR6 $at, $zero, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BGEUC_MMR6 $r1, $r0, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -881,36 +881,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 131068", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BLTUC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGEUC_MMR6 $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGEUC_MMR6 $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLTUC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLTUC_MMR6 killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -918,7 +918,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -933,7 +933,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -959,8 +959,8 @@ body: |
; MMR6-LABEL: name: expand_BLTZC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BGEZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BGEZC_MMR6 $r1, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -968,36 +968,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 131068", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BLTZC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGEZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGEZC_MMR6 $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLTZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLTZC_MMR6 killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -1005,7 +1005,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -1020,7 +1020,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1046,8 +1046,8 @@ body: |
; MMR6-LABEL: name: expand_BEQZC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BNEZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BNEZC_MMR6 $r1, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -1055,36 +1055,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 8388608", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BEQZC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BNEZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BNEZC_MMR6 $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 8388608", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BEQZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BEQZC_MMR6 killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -1092,7 +1092,7 @@ body: |
INLINEASM &".space 8388608", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -1107,7 +1107,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1133,8 +1133,8 @@ body: |
; MMR6-LABEL: name: expand_BNEZC_MMR6
; MMR6: bb.0 (%ir-block.0):
; MMR6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MMR6: renamable $at = ANDi killed renamable $a0, 1
- ; MMR6: BEQZC_MMR6 $at, %bb.2, implicit-def $at
+ ; MMR6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MMR6: BEQZC_MMR6 $r1, %bb.2, implicit-def $r1
; MMR6: bb.1 (%ir-block.0):
; MMR6: successors: %bb.3(0x80000000)
; MMR6: BC_MMR6 %bb.3
@@ -1142,36 +1142,36 @@ body: |
; MMR6: successors: %bb.3(0x80000000)
; MMR6: INLINEASM &".space 8388608", sideeffect attdialect
; MMR6: bb.3.tail:
- ; MMR6: JRC16_MM undef $ra
+ ; MMR6: JRC16_MM undef $r31
; PIC-LABEL: name: expand_BNEZC_MMR6
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BEQZC_MMR6 $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BEQZC_MMR6 $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC_MMR6 %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC_MMR6 $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC_MMR6 $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 8388608", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JRC16_MM undef $ra
+ ; PIC: JRC16_MM undef $r31
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BNEZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BNEZC_MMR6 killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -1179,6 +1179,6 @@ body: |
INLINEASM &".space 8388608", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
index 94c97f5c0d05d..b205dcacbc9f4 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
@@ -90,7 +90,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -116,68 +116,68 @@ body: |
; MIPS64-LABEL: name: expand_BEQ64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BNE64 $a0_64, $zero_64, %bb.2, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: BNE64 $r4_64, $r0_64, %bb.2, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BEQ64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BNE64 $a0_64, $zero_64, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BNE64 $r4_64, $r0_64, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BEQ64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+ BEQ64 killed renamable $r4_64, $r0_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -192,7 +192,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -218,68 +218,68 @@ body: |
; MIPS64-LABEL: name: expand_BNE64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BEQ64 $a0_64, $zero_64, %bb.2, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: BEQ64 $r4_64, $r0_64, %bb.2, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BNE64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BEQ64 $a0_64, $zero_64, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BEQ64 $r4_64, $r0_64, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BNE64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+ BNE64 killed renamable $r4_64, $r0_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -294,7 +294,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -320,68 +320,68 @@ body: |
; MIPS64-LABEL: name: expand_BGEZ64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BLTZ64 $a0_64, %bb.2, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: BLTZ64 $r4_64, %bb.2, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEZ64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BLTZ64 $a0_64, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BLTZ64 $r4_64, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BGEZ64 killed renamable $a0_64, %bb.2, implicit-def $at
+ BGEZ64 killed renamable $r4_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -396,7 +396,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -422,68 +422,68 @@ body: |
; MIPS64-LABEL: name: expand_BGTZ64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BLEZ64 $a0_64, %bb.2, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: BLEZ64 $r4_64, %bb.2, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGTZ64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BLEZ64 $a0_64, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BLEZ64 $r4_64, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BGTZ64 killed renamable $a0_64, %bb.2, implicit-def $at
+ BGTZ64 killed renamable $r4_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -498,7 +498,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -524,68 +524,68 @@ body: |
; MIPS64-LABEL: name: expand_BLEZ64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BGTZ64 $a0_64, %bb.2, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: BGTZ64 $r4_64, %bb.2, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLEZ64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BGTZ64 $a0_64, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BGTZ64 $r4_64, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BLEZ64 killed renamable $a0_64, %bb.2, implicit-def $at
+ BLEZ64 killed renamable $r4_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -600,7 +600,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -626,67 +626,67 @@ body: |
; MIPS64-LABEL: name: expand_BLTZ64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BGEZ64 $a0_64, %bb.2, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: BGEZ64 $r4_64, %bb.2, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 131068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTZ64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BGEZ64 $a0_64, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BGEZ64 $r4_64, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 131068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BLTZ64 killed renamable $a0_64, %bb.2, implicit-def $at
+ BLTZ64 killed renamable $r4_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 131068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
index 67ad61d45636a..387961037483a 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
@@ -162,7 +162,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -188,43 +188,43 @@ body: |
; MIPS64-LABEL: name: expand_BNEZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS64: BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: BNEZC64 killed renamable $r4_64, %bb.2, implicit-def $r1
; MIPS64: bb.1.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.2.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BNEZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; PIC: BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ ; PIC: BNEZC64 killed renamable $r4_64, %bb.2, implicit-def $r1
; PIC: bb.1.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.2.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ BNEZC64 killed renamable $r4_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -239,7 +239,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -265,43 +265,43 @@ body: |
; MIPS64-LABEL: name: expand_BEQZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; MIPS64: BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: BEQZC64 killed renamable $r4_64, %bb.2, implicit-def $r1
; MIPS64: bb.1.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.2.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BEQZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; PIC: BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ ; PIC: BEQZC64 killed renamable $r4_64, %bb.2, implicit-def $r1
; PIC: bb.1.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.2.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ BEQZC64 killed renamable $r4_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -316,7 +316,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -342,64 +342,64 @@ body: |
; MIPS64-LABEL: name: expand_BNEC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BEQC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: BEQC64 $r4_64, $r0_64, %bb.2, implicit-def $r1
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BNEC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BEQC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: BEQC64 $r4_64, $r0_64, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BNEC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+ BNEC64 killed renamable $r4_64, $r0_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -414,7 +414,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -440,64 +440,64 @@ body: |
; MIPS64-LABEL: name: expand_BEQC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BNEC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: BNEC64 $r4_64, $r0_64, %bb.2, implicit-def $r1
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BEQC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BNEC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: BNEC64 $r4_64, $r0_64, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BEQC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+ BEQC64 killed renamable $r4_64, $r0_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -512,7 +512,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -538,64 +538,64 @@ body: |
; MIPS64-LABEL: name: expand_BLTC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BGEC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: BGEC64 $r4_64, $r0_64, %bb.2, implicit-def $r1
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BGEC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: BGEC64 $r4_64, $r0_64, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BLTC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+ BLTC64 killed renamable $r4_64, $r0_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -610,7 +610,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -636,64 +636,64 @@ body: |
; MIPS64-LABEL: name: expand_BLTUC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BGEUC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: BGEUC64 $r4_64, $r0_64, %bb.2, implicit-def $r1
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTUC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BGEUC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: BGEUC64 $r4_64, $r0_64, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BLTUC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+ BLTUC64 killed renamable $r4_64, $r0_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -708,7 +708,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -734,64 +734,64 @@ body: |
; MIPS64-LABEL: name: expand_BGEC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BLTC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: BLTC64 $r4_64, $r0_64, %bb.2, implicit-def $r1
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BLTC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: BLTC64 $r4_64, $r0_64, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BGEC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+ BGEC64 killed renamable $r4_64, $r0_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -806,7 +806,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -832,64 +832,64 @@ body: |
; MIPS64-LABEL: name: expand_BGEUC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BLTUC64 $a0_64, $zero_64, %bb.2, implicit-def $at
+ ; MIPS64: BLTUC64 $r4_64, $r0_64, %bb.2, implicit-def $r1
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEUC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BLTUC64 $a0_64, $zero_64, %bb.3, implicit-def $at
+ ; PIC: BLTUC64 $r4_64, $r0_64, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BGEUC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
+ BGEUC64 killed renamable $r4_64, $r0_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -904,7 +904,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -930,64 +930,64 @@ body: |
; MIPS64-LABEL: name: expand_BLEZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BGTZC64 $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: BGTZC64 $r4_64, %bb.2, implicit-def $r1
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLEZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BGTZC64 $a0_64, %bb.3, implicit-def $at
+ ; PIC: BGTZC64 $r4_64, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BLEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ BLEZC64 killed renamable $r4_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -1002,7 +1002,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1028,64 +1028,64 @@ body: |
; MIPS64-LABEL: name: expand_BLTZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BGEZC64 $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: BGEZC64 $r4_64, %bb.2, implicit-def $r1
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BGEZC64 $a0_64, %bb.3, implicit-def $at
+ ; PIC: BGEZC64 $r4_64, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BLTZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ BLTZC64 killed renamable $r4_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -1100,7 +1100,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1126,64 +1126,64 @@ body: |
; MIPS64-LABEL: name: expand_BGEZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BLTZC64 $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: BLTZC64 $r4_64, %bb.2, implicit-def $r1
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BLTZC64 $a0_64, %bb.3, implicit-def $at
+ ; PIC: BLTZC64 $r4_64, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BGEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ BGEZC64 killed renamable $r4_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
---
@@ -1198,7 +1198,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1224,63 +1224,63 @@ body: |
; MIPS64-LABEL: name: expand_BGTZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS64: BLEZC64 $a0_64, %bb.2, implicit-def $at
+ ; MIPS64: BLEZC64 $r4_64, %bb.2, implicit-def $r1
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
- ; MIPS64: J %bb.3, implicit-def $at {
- ; MIPS64: $zero = SLL $zero, 0
+ ; MIPS64: J %bb.3, implicit-def $r1 {
+ ; MIPS64: $r0 = SLL $r0, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", sideeffect attdialect
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 1
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
- ; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; MIPS64: $r2_64 = DADDiu $zero_64, 0
+ ; MIPS64: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; MIPS64: $r2_64 = DADDiu $r0_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGTZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: BLEZC64 $a0_64, %bb.3, implicit-def $at
+ ; PIC: BLEZC64 $r4_64, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", sideeffect attdialect
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 1
; PIC: }
; PIC: bb.4.tail:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2_64 {
- ; PIC: $r2_64 = DADDiu $zero_64, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2_64 {
+ ; PIC: $r2_64 = DADDiu $r0_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64
+ liveins: $r4_64
- BGTZC64 killed renamable $a0_64, %bb.2, implicit-def $at
+ BGTZC64 killed renamable $r4_64, %bb.2, implicit-def $r1
bb.1.iftrue:
INLINEASM &".space 831068", sideeffect attdialect
- $r2_64 = DADDiu $zero_64, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
bb.2.tail:
- $r2_64 = DADDiu $zero_64, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2_64
+ $r2_64 = DADDiu $r0_64, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2_64
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
index 48aa43b280b62..ec8d20268b4fb 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
@@ -150,7 +150,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -176,8 +176,8 @@ body: |
; R6-LABEL: name: expand_BEQC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BNEC $at, $zero, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BNEC $r1, $r0, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -185,36 +185,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 131068", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BEQC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BNEC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BNEC $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BEQC killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BEQC killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -222,7 +222,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -237,7 +237,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -263,8 +263,8 @@ body: |
; R6-LABEL: name: expand_BNEC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BEQC $at, $zero, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BEQC $r1, $r0, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -272,36 +272,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 131068", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BNEC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BEQC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BEQC $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BNEC killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BNEC killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -309,7 +309,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -324,7 +324,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -350,8 +350,8 @@ body: |
; R6-LABEL: name: expand_BGEC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BLTC $at, $zero, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BLTC $r1, $r0, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -359,36 +359,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 131068", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BGEC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLTC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLTC $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGEC killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGEC killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -396,7 +396,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -411,7 +411,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -437,8 +437,8 @@ body: |
; R6-LABEL: name: expand_BGEUC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BLTUC $at, $zero, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BLTUC $r1, $r0, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -446,36 +446,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 131068", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BGEUC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLTUC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLTUC $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGEUC killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGEUC killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -483,7 +483,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -498,7 +498,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -524,8 +524,8 @@ body: |
; R6-LABEL: name: expand_BGEZC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BLTZC $at, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BLTZC $r1, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -533,36 +533,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 131068", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BGEZC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLTZC $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLTZC $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGEZC killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGEZC killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -570,7 +570,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -585,7 +585,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -611,8 +611,8 @@ body: |
; R6-LABEL: name: expand_BGTZC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BLEZC $at, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BLEZC $r1, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -620,36 +620,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 131068", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BGTZC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLEZC $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLEZC $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGTZC killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGTZC killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -657,7 +657,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -672,7 +672,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -698,8 +698,8 @@ body: |
; R6-LABEL: name: expand_BLEZC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BGTZC $at, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BGTZC $r1, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -707,36 +707,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 131068", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BLEZC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGTZC $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGTZC $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLEZC killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLEZC killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -744,7 +744,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -759,7 +759,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -785,8 +785,8 @@ body: |
; R6-LABEL: name: expand_BLTC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BGEC $at, $zero, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BGEC $r1, $r0, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -794,36 +794,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 131068", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BLTC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGEC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGEC $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLTC killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLTC killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -831,7 +831,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -846,7 +846,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -872,8 +872,8 @@ body: |
; R6-LABEL: name: expand_BLTUC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BGEUC $at, $zero, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BGEUC $r1, $r0, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -881,36 +881,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 131068", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BLTUC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGEUC $at, $zero, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGEUC $r1, $r0, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLTUC killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLTUC killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -918,7 +918,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -933,7 +933,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -959,8 +959,8 @@ body: |
; R6-LABEL: name: expand_BLTZC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BGEZC $at, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BGEZC $r1, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -968,36 +968,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 131068", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BLTZC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGEZC $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGEZC $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLTZC killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLTZC killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -1005,7 +1005,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -1020,7 +1020,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1046,8 +1046,8 @@ body: |
; R6-LABEL: name: expand_BEQZC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BNEZC $at, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BNEZC $r1, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -1055,36 +1055,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 8388608", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BEQZC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BNEZC $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BNEZC $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 8388608", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BEQZC killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BEQZC killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -1092,7 +1092,7 @@ body: |
INLINEASM &".space 8388608", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -1107,7 +1107,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1133,8 +1133,8 @@ body: |
; R6-LABEL: name: expand_BNEZC
; R6: bb.0 (%ir-block.0):
; R6: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; R6: renamable $at = ANDi killed renamable $a0, 1
- ; R6: BEQZC $at, %bb.2, implicit-def $at
+ ; R6: renamable $r1 = ANDi killed renamable $r4, 1
+ ; R6: BEQZC $r1, %bb.2, implicit-def $r1
; R6: bb.1 (%ir-block.0):
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
@@ -1142,36 +1142,36 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: INLINEASM &".space 8388608", sideeffect attdialect
; R6: bb.3.tail:
- ; R6: JIC undef $ra, 0, implicit-def $at
+ ; R6: JIC undef $r31, 0, implicit-def $r1
; PIC-LABEL: name: expand_BNEZC
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BEQZC $at, %bb.3, implicit-def $at
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BEQZC $r1, %bb.3, implicit-def $r1
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
- ; PIC: BALC %bb.2, implicit-def $ra
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: BALC %bb.2, implicit-def $r31
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: $sp = ADDiu $sp, 8
- ; PIC: JIC $at, 0, implicit-def $at
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: $r29 = ADDiu $r29, 8
+ ; PIC: JIC $r1, 0, implicit-def $r1
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 8388608", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: JIC undef $ra, 0, implicit-def $at
+ ; PIC: JIC undef $r31, 0, implicit-def $r1
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BNEZC killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BNEZC killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -1179,6 +1179,6 @@ body: |
INLINEASM &".space 8388608", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
index 9490802a9ff14..7d1ef5a9c675e 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
@@ -84,7 +84,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -110,57 +110,57 @@ body: |
; MIPS-LABEL: name: expand_BEQ
; MIPS: bb.0 (%ir-block.0):
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS: renamable $at = ANDi killed renamable $a0, 1
- ; MIPS: BNE $at, $zero, %bb.2, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MIPS: BNE $r1, $r0, %bb.2, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.1 (%ir-block.0):
; MIPS: successors: %bb.3(0x80000000)
- ; MIPS: J %bb.3, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: J %bb.3, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.2.iftrue:
; MIPS: successors: %bb.3(0x80000000)
; MIPS: INLINEASM &".space 131068", sideeffect attdialect
; MIPS: bb.3.tail:
- ; MIPS: PseudoReturn undef $ra {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: PseudoReturn undef $r31 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; PIC-LABEL: name: expand_BEQ
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BNE $at, $zero, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BNE $r1, $r0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: PseudoReturn undef $ra {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: PseudoReturn undef $r31 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BEQ killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BEQ killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -168,7 +168,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -183,7 +183,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -209,57 +209,57 @@ body: |
; MIPS-LABEL: name: expand_BGEZ
; MIPS: bb.0 (%ir-block.0):
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS: renamable $at = ANDi killed renamable $a0, 1
- ; MIPS: BLTZ $at, %bb.2, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MIPS: BLTZ $r1, %bb.2, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.1 (%ir-block.0):
; MIPS: successors: %bb.3(0x80000000)
- ; MIPS: J %bb.3, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: J %bb.3, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.2.iftrue:
; MIPS: successors: %bb.3(0x80000000)
; MIPS: INLINEASM &".space 131068", sideeffect attdialect
; MIPS: bb.3.tail:
- ; MIPS: PseudoReturn undef $ra {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: PseudoReturn undef $r31 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; PIC-LABEL: name: expand_BGEZ
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLTZ $at, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLTZ $r1, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: PseudoReturn undef $ra {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: PseudoReturn undef $r31 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGEZ killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGEZ killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -267,7 +267,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -282,7 +282,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -308,57 +308,57 @@ body: |
; MIPS-LABEL: name: expand_BGTZ
; MIPS: bb.0 (%ir-block.0):
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS: renamable $at = ANDi killed renamable $a0, 1
- ; MIPS: BLEZ $at, %bb.2, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MIPS: BLEZ $r1, %bb.2, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.1 (%ir-block.0):
; MIPS: successors: %bb.3(0x80000000)
- ; MIPS: J %bb.3, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: J %bb.3, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.2.iftrue:
; MIPS: successors: %bb.3(0x80000000)
; MIPS: INLINEASM &".space 131068", sideeffect attdialect
; MIPS: bb.3.tail:
- ; MIPS: PseudoReturn undef $ra {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: PseudoReturn undef $r31 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; PIC-LABEL: name: expand_BGTZ
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BLEZ $at, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BLEZ $r1, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: PseudoReturn undef $ra {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: PseudoReturn undef $r31 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BGTZ killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BGTZ killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -366,7 +366,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -381,7 +381,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -407,57 +407,57 @@ body: |
; MIPS-LABEL: name: expand_BLEZ
; MIPS: bb.0 (%ir-block.0):
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS: renamable $at = ANDi killed renamable $a0, 1
- ; MIPS: BGTZ $at, %bb.2, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MIPS: BGTZ $r1, %bb.2, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.1 (%ir-block.0):
; MIPS: successors: %bb.3(0x80000000)
- ; MIPS: J %bb.3, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: J %bb.3, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.2.iftrue:
; MIPS: successors: %bb.3(0x80000000)
; MIPS: INLINEASM &".space 131068", sideeffect attdialect
; MIPS: bb.3.tail:
- ; MIPS: PseudoReturn undef $ra {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: PseudoReturn undef $r31 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; PIC-LABEL: name: expand_BLEZ
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGTZ $at, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGTZ $r1, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: PseudoReturn undef $ra {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: PseudoReturn undef $r31 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLEZ killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLEZ killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -465,7 +465,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -480,7 +480,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -506,57 +506,57 @@ body: |
; MIPS-LABEL: name: expand_BLTZ
; MIPS: bb.0 (%ir-block.0):
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS: renamable $at = ANDi killed renamable $a0, 1
- ; MIPS: BGEZ $at, %bb.2, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MIPS: BGEZ $r1, %bb.2, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.1 (%ir-block.0):
; MIPS: successors: %bb.3(0x80000000)
- ; MIPS: J %bb.3, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: J %bb.3, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.2.iftrue:
; MIPS: successors: %bb.3(0x80000000)
; MIPS: INLINEASM &".space 131068", sideeffect attdialect
; MIPS: bb.3.tail:
- ; MIPS: PseudoReturn undef $ra {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: PseudoReturn undef $r31 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; PIC-LABEL: name: expand_BLTZ
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BGEZ $at, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BGEZ $r1, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: PseudoReturn undef $ra {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: PseudoReturn undef $r31 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BLTZ killed renamable $at, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BLTZ killed renamable $r1, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -564,7 +564,7 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
---
@@ -579,7 +579,7 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -605,57 +605,57 @@ body: |
; MIPS-LABEL: name: expand_BNE
; MIPS: bb.0 (%ir-block.0):
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; MIPS: renamable $at = ANDi killed renamable $a0, 1
- ; MIPS: BEQ $at, $zero, %bb.2, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: renamable $r1 = ANDi killed renamable $r4, 1
+ ; MIPS: BEQ $r1, $r0, %bb.2, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.1 (%ir-block.0):
; MIPS: successors: %bb.3(0x80000000)
- ; MIPS: J %bb.3, implicit-def $at {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: J %bb.3, implicit-def $r1 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; MIPS: bb.2.iftrue:
; MIPS: successors: %bb.3(0x80000000)
; MIPS: INLINEASM &".space 131068", sideeffect attdialect
; MIPS: bb.3.tail:
- ; MIPS: PseudoReturn undef $ra {
- ; MIPS: $zero = SLL $zero, 0
+ ; MIPS: PseudoReturn undef $r31 {
+ ; MIPS: $r0 = SLL $r0, 0
; MIPS: }
; PIC-LABEL: name: expand_BNE
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; PIC: renamable $at = ANDi killed renamable $a0, 1
- ; PIC: BEQ $at, $zero, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: renamable $r1 = ANDi killed renamable $r4, 1
+ ; PIC: BEQ $r1, $r0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp = ADDiu $sp, -8
- ; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29 = ADDiu $r29, -8
+ ; PIC: SW $r31, $r29, 0
+ ; PIC: $r1 = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1 = LONG_BRANCH_ADDiu $r1, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at = ADDu $ra, $at
- ; PIC: $ra = LW $sp, 0
- ; PIC: JR $at {
- ; PIC: $sp = ADDiu $sp, 8
+ ; PIC: $r1 = ADDu $r31, $r1
+ ; PIC: $r31 = LW $r29, 0
+ ; PIC: JR $r1 {
+ ; PIC: $r29 = ADDiu $r29, 8
; PIC: }
; PIC: bb.3.iftrue:
; PIC: successors: %bb.4(0x80000000)
; PIC: INLINEASM &".space 131068", sideeffect attdialect
; PIC: bb.4.tail:
- ; PIC: PseudoReturn undef $ra {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: PseudoReturn undef $r31 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0
+ liveins: $r4
- renamable $at = ANDi killed renamable $a0, 1
- BNE killed renamable $at, $zero, %bb.2, implicit-def $at
+ renamable $r1 = ANDi killed renamable $r4, 1
+ BNE killed renamable $r1, $r0, %bb.2, implicit-def $r1
bb.1.iftrue:
successors: %bb.2(0x80000000)
@@ -663,6 +663,6 @@ body: |
INLINEASM &".space 131068", sideeffect attdialect
bb.2.tail:
- PseudoReturn undef $ra
+ PseudoReturn undef $r31
...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
index 2b010d7d89e91..26205f7804c61 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
@@ -230,8 +230,8 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -258,82 +258,82 @@ body: |
; MSA: bb.0.entry:
; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MSA: renamable $w0 = LDI_B 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; MSA: renamable $w0 = SHF_B killed renamable $w0, 27
; MSA: renamable $w0 = SHF_W killed renamable $w0, 177
- ; MSA: BNZ_B $w0, %bb.2, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: BNZ_B $w0, %bb.2, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.1.entry:
; MSA: successors: %bb.3(0x80000000)
- ; MSA: J %bb.3, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: J %bb.3, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 1
+ ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 0
; MSA: }
; PIC-LABEL: name: _Z4bz_8Dv16_a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $w0 = LDI_B 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; PIC: renamable $w0 = SHF_B killed renamable $w0, 27
; PIC: renamable $w0 = SHF_W killed renamable $w0, 177
- ; PIC: BNZ_B $w0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BNZ_B $w0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 1
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64, $a1_64
+ liveins: $r4_64, $r5_64
renamable $w0 = LDI_B 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
renamable $w0 = SHF_B killed renamable $w0, 27
renamable $w0 = SHF_W killed renamable $w0, 177
- BZ_B killed renamable $w0, %bb.2, implicit-def dead $at
+ BZ_B killed renamable $w0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $r2 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
+ renamable $r2 = ADDiu $r0, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2
bb.2:
- renamable $r2 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ renamable $r2 = ADDiu $r0, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2
...
---
@@ -347,8 +347,8 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -375,79 +375,79 @@ body: |
; MSA: bb.0.entry:
; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MSA: renamable $w0 = LDI_B 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; MSA: renamable $w0 = SHF_H killed renamable $w0, 27
- ; MSA: BNZ_H $w0, %bb.2, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: BNZ_H $w0, %bb.2, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.1.entry:
; MSA: successors: %bb.3(0x80000000)
- ; MSA: J %bb.3, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: J %bb.3, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 1
+ ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 0
; MSA: }
; PIC-LABEL: name: _Z5bz_16Dv8_s
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $w0 = LDI_B 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; PIC: renamable $w0 = SHF_H killed renamable $w0, 27
- ; PIC: BNZ_H $w0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BNZ_H $w0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 1
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64, $a1_64
+ liveins: $r4_64, $r5_64
renamable $w0 = LDI_B 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
renamable $w0 = SHF_H killed renamable $w0, 27
- BZ_H killed renamable $w0, %bb.2, implicit-def dead $at
+ BZ_H killed renamable $w0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $r2 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
+ renamable $r2 = ADDiu $r0, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2
bb.2:
- renamable $r2 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ renamable $r2 = ADDiu $r0, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2
...
---
@@ -461,8 +461,8 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -489,79 +489,79 @@ body: |
; MSA: bb.0.entry:
; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MSA: renamable $w0 = LDI_B 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; MSA: renamable $w0 = SHF_W killed renamable $w0, 177
- ; MSA: BNZ_W $w0, %bb.2, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: BNZ_W $w0, %bb.2, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.1.entry:
; MSA: successors: %bb.3(0x80000000)
- ; MSA: J %bb.3, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: J %bb.3, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 1
+ ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 0
; MSA: }
; PIC-LABEL: name: _Z5bz_32Dv4_i
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $w0 = LDI_B 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; PIC: renamable $w0 = SHF_W killed renamable $w0, 177
- ; PIC: BNZ_W $w0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BNZ_W $w0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 1
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64, $a1_64
+ liveins: $r4_64, $r5_64
renamable $w0 = LDI_B 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
renamable $w0 = SHF_W killed renamable $w0, 177
- BZ_W killed renamable $w0, %bb.2, implicit-def dead $at
+ BZ_W killed renamable $w0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $r2 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
+ renamable $r2 = ADDiu $r0, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2
bb.2:
- renamable $r2 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ renamable $r2 = ADDiu $r0, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2
...
---
@@ -575,8 +575,8 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -603,76 +603,76 @@ body: |
; MSA: bb.0.entry:
; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MSA: renamable $w0 = LDI_B 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- ; MSA: BNZ_D $w0, %bb.2, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ ; MSA: BNZ_D $w0, %bb.2, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.1.entry:
; MSA: successors: %bb.3(0x80000000)
- ; MSA: J %bb.3, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: J %bb.3, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 1
+ ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 0
; MSA: }
; PIC-LABEL: name: _Z5bz_64Dv2_x
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $w0 = LDI_B 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- ; PIC: BNZ_D $w0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ ; PIC: BNZ_D $w0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 1
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64, $a1_64
+ liveins: $r4_64, $r5_64
renamable $w0 = LDI_B 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- BZ_D killed renamable $w0, %bb.2, implicit-def dead $at
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ BZ_D killed renamable $w0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $r2 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
+ renamable $r2 = ADDiu $r0, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2
bb.2:
- renamable $r2 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ renamable $r2 = ADDiu $r0, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2
...
---
@@ -686,8 +686,8 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -714,76 +714,76 @@ body: |
; MSA: bb.0.entry:
; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MSA: renamable $w0 = LDI_B 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- ; MSA: BNZ_V $w0, %bb.2, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ ; MSA: BNZ_V $w0, %bb.2, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.1.entry:
; MSA: successors: %bb.3(0x80000000)
- ; MSA: J %bb.3, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: J %bb.3, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 1
+ ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 0
; MSA: }
; PIC-LABEL: name: _Z5bz_64_vDv2_x
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $w0 = LDI_B 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- ; PIC: BNZ_V $w0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ ; PIC: BNZ_V $w0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 1
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64, $a1_64
+ liveins: $r4_64, $r5_64
renamable $w0 = LDI_B 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- BZ_V killed renamable $w0, %bb.2, implicit-def dead $at
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ BZ_V killed renamable $w0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $r2 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
+ renamable $r2 = ADDiu $r0, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2
bb.2:
- renamable $r2 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ renamable $r2 = ADDiu $r0, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2
...
---
@@ -797,8 +797,8 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -825,82 +825,82 @@ body: |
; MSA: bb.0.entry:
; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MSA: renamable $w0 = LDI_B 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; MSA: renamable $w0 = SHF_B killed renamable $w0, 27
; MSA: renamable $w0 = SHF_W killed renamable $w0, 177
- ; MSA: BZ_B $w0, %bb.2, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: BZ_B $w0, %bb.2, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.1.entry:
; MSA: successors: %bb.3(0x80000000)
- ; MSA: J %bb.3, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: J %bb.3, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 1
+ ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 0
; MSA: }
; PIC-LABEL: name: _Z5bnz_8Dv16_a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $w0 = LDI_B 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; PIC: renamable $w0 = SHF_B killed renamable $w0, 27
; PIC: renamable $w0 = SHF_W killed renamable $w0, 177
- ; PIC: BZ_B $w0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BZ_B $w0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 1
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64, $a1_64
+ liveins: $r4_64, $r5_64
renamable $w0 = LDI_B 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
renamable $w0 = SHF_B killed renamable $w0, 27
renamable $w0 = SHF_W killed renamable $w0, 177
- BNZ_B killed renamable $w0, %bb.2, implicit-def dead $at
+ BNZ_B killed renamable $w0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $r2 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
+ renamable $r2 = ADDiu $r0, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2
bb.2:
- renamable $r2 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ renamable $r2 = ADDiu $r0, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2
...
---
@@ -914,8 +914,8 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -942,79 +942,79 @@ body: |
; MSA: bb.0.entry:
; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MSA: renamable $w0 = LDI_B 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; MSA: renamable $w0 = SHF_H killed renamable $w0, 27
- ; MSA: BZ_H $w0, %bb.2, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: BZ_H $w0, %bb.2, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.1.entry:
; MSA: successors: %bb.3(0x80000000)
- ; MSA: J %bb.3, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: J %bb.3, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 1
+ ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 0
; MSA: }
; PIC-LABEL: name: _Z6bnz_16Dv8_s
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $w0 = LDI_B 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; PIC: renamable $w0 = SHF_H killed renamable $w0, 27
- ; PIC: BZ_H $w0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BZ_H $w0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 1
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64, $a1_64
+ liveins: $r4_64, $r5_64
renamable $w0 = LDI_B 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
renamable $w0 = SHF_H killed renamable $w0, 27
- BNZ_H killed renamable $w0, %bb.2, implicit-def dead $at
+ BNZ_H killed renamable $w0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $r2 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
+ renamable $r2 = ADDiu $r0, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2
bb.2:
- renamable $r2 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ renamable $r2 = ADDiu $r0, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2
...
---
@@ -1028,8 +1028,8 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1056,79 +1056,79 @@ body: |
; MSA: bb.0.entry:
; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MSA: renamable $w0 = LDI_B 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; MSA: renamable $w0 = SHF_W killed renamable $w0, 177
- ; MSA: BZ_W $w0, %bb.2, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: BZ_W $w0, %bb.2, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.1.entry:
; MSA: successors: %bb.3(0x80000000)
- ; MSA: J %bb.3, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: J %bb.3, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 1
+ ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 0
; MSA: }
; PIC-LABEL: name: _Z6bnz_32Dv4_i
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $w0 = LDI_B 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
; PIC: renamable $w0 = SHF_W killed renamable $w0, 177
- ; PIC: BZ_W $w0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: BZ_W $w0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 1
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64, $a1_64
+ liveins: $r4_64, $r5_64
renamable $w0 = LDI_B 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
renamable $w0 = SHF_W killed renamable $w0, 177
- BNZ_W killed renamable $w0, %bb.2, implicit-def dead $at
+ BNZ_W killed renamable $w0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $r2 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
+ renamable $r2 = ADDiu $r0, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2
bb.2:
- renamable $r2 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ renamable $r2 = ADDiu $r0, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2
...
---
@@ -1142,8 +1142,8 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1170,76 +1170,76 @@ body: |
; MSA: bb.0.entry:
; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MSA: renamable $w0 = LDI_B 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- ; MSA: BZ_D $w0, %bb.2, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ ; MSA: BZ_D $w0, %bb.2, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.1.entry:
; MSA: successors: %bb.3(0x80000000)
- ; MSA: J %bb.3, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: J %bb.3, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 1
+ ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 0
; MSA: }
; PIC-LABEL: name: _Z6bnz_64Dv2_x
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $w0 = LDI_B 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- ; PIC: BZ_D $w0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ ; PIC: BZ_D $w0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 1
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64, $a1_64
+ liveins: $r4_64, $r5_64
renamable $w0 = LDI_B 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- BNZ_D killed renamable $w0, %bb.2, implicit-def dead $at
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ BNZ_D killed renamable $w0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $r2 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
+ renamable $r2 = ADDiu $r0, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2
bb.2:
- renamable $r2 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ renamable $r2 = ADDiu $r0, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2
...
---
@@ -1253,8 +1253,8 @@ failedISel: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1281,75 +1281,75 @@ body: |
; MSA: bb.0.entry:
; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MSA: renamable $w0 = LDI_B 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- ; MSA: BZ_V $w0, %bb.2, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ ; MSA: BZ_V $w0, %bb.2, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.1.entry:
; MSA: successors: %bb.3(0x80000000)
- ; MSA: J %bb.3, implicit-def $at {
- ; MSA: $zero = SLL $zero, 0
+ ; MSA: J %bb.3, implicit-def $r1 {
+ ; MSA: $r0 = SLL $r0, 0
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 1
+ ; MSA: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 1
; MSA: }
; MSA: bb.3:
- ; MSA: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; MSA: renamable $r2 = ADDiu $zero, 0
+ ; MSA: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; MSA: renamable $r2 = ADDiu $r0, 0
; MSA: }
; PIC-LABEL: name: _Z6bnz_64_vDv2_x
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $w0 = LDI_B 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- ; PIC: BZ_V $w0, %bb.3, implicit-def $at {
- ; PIC: $zero = SLL $zero, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ ; PIC: BZ_V $w0, %bb.3, implicit-def $r1 {
+ ; PIC: $r0 = SLL $r0, 0
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
- ; PIC: $sp_64 = DADDiu $sp_64, -16
- ; PIC: SD $ra_64, $sp_64, 0
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
- ; PIC: $at_64 = DSLL $at_64, 16
- ; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
+ ; PIC: $r29_64 = DADDiu $r29_64, -16
+ ; PIC: SD $r31_64, $r29_64, 0
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r0_64, target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $r1_64 = DSLL $r1_64, 16
+ ; PIC: BAL_BR %bb.2, implicit-def $r31 {
+ ; PIC: $r1_64 = LONG_BRANCH_DADDiu $r1_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
- ; PIC: $at_64 = DADDu $ra_64, $at_64
- ; PIC: $ra_64 = LD $sp_64, 0
- ; PIC: JR64 $at_64 {
- ; PIC: $sp_64 = DADDiu $sp_64, 16
+ ; PIC: $r1_64 = DADDu $r31_64, $r1_64
+ ; PIC: $r31_64 = LD $r29_64, 0
+ ; PIC: JR64 $r1_64 {
+ ; PIC: $r29_64 = DADDiu $r29_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $at
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 1
+ ; PIC: INLINEASM &".space 810680", sideeffect attdialect, clobber, implicit-def dead early-clobber $r1
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 1
; PIC: }
; PIC: bb.4:
- ; PIC: PseudoReturn64 undef $ra_64, implicit killed $r2 {
- ; PIC: renamable $r2 = ADDiu $zero, 0
+ ; PIC: PseudoReturn64 undef $r31_64, implicit killed $r2 {
+ ; PIC: renamable $r2 = ADDiu $r0, 0
; PIC: }
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $a0_64, $a1_64
+ liveins: $r4_64, $r5_64
renamable $w0 = LDI_B 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
- renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
- BNZ_V killed renamable $w0, %bb.2, implicit-def dead $at
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r4_64, 0
+ renamable $w0 = INSERT_D killed renamable $w0, killed renamable $r5_64, 1
+ BNZ_V killed renamable $w0, %bb.2, implicit-def dead $r1
bb.1.if.then:
- INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
- renamable $r2 = ADDiu $zero, 1
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $r1
+ renamable $r2 = ADDiu $r0, 1
+ PseudoReturn64 undef $r31_64, implicit killed $r2
bb.2:
- renamable $r2 = ADDiu $zero, 0
- PseudoReturn64 undef $ra_64, implicit killed $r2
+ renamable $r2 = ADDiu $r0, 0
+ PseudoReturn64 undef $r31_64, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/micromips-eva.mir b/llvm/test/CodeGen/Mips/micromips-eva.mir
index f3a58ef94c3c0..10fd02e21e641 100644
--- a/llvm/test/CodeGen/Mips/micromips-eva.mir
+++ b/llvm/test/CodeGen/Mips/micromips-eva.mir
@@ -141,7 +141,7 @@ registers:
- { id: 7, class: gpr32, preferred-register: '' }
- { id: 8, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$r4', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -169,14 +169,14 @@ constants:
body: |
bb.0.entry:
successors: %bb.1(0x80000000)
- liveins: $a0
+ liveins: $r4
- %0:gpr32 = COPY $a0
+ %0:gpr32 = COPY $r4
%1:gpr32 = COPY %0
SW %0, %stack.0.z.addr, 0 :: (store (s32) into %ir.z.addr)
%2:gpr32 = LW %stack.0.z.addr, 0 :: (dereferenceable load (s32) from %ir.z.addr)
SYNC 0
- %3:gpr32 = ADDiu $zero, 42
+ %3:gpr32 = ADDiu $r0, 42
bb.1.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -184,7 +184,7 @@ body: |
%4:gpr32 = LLE %2, 0
%6:gpr32 = ADDu %4, %3
%8:gpr32 = SCE %6, %2, 0
- BEQ %8, $zero, %bb.1, implicit-def $at
+ BEQ %8, $r0, %bb.1, implicit-def $r1
bb.2.entry:
SYNC 0
diff --git a/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll b/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
index 85262983c0a27..b640494759b17 100644
--- a/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
+++ b/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
@@ -18,14 +18,14 @@ define i64 @test(i32 signext %a, i32 signext %b) {
; MMR2-NEXT: mthi $2 # <MCInst #[[#MCINST3:]] MTHI_MM
; MMR2-NEXT: # <MCOperand Reg:R2>>
; MMR2-NEXT: madd $4, $5 # <MCInst #[[#MCINST4:]] MADD
-; MMR2-NEXT: # <MCOperand Reg:A0>
-; MMR2-NEXT: # <MCOperand Reg:A1>>
+; MMR2-NEXT: # <MCOperand Reg:R4>
+; MMR2-NEXT: # <MCOperand Reg:R5>>
; MMR2-NEXT: mflo16 $2 # <MCInst #[[#MCINST5:]] MFLO16_MM
; MMR2-NEXT: # <MCOperand Reg:R2>>
; MMR2-NEXT: mfhi16 $3 # <MCInst #[[#MCINST6:]] MFHI16_MM
; MMR2-NEXT: # <MCOperand Reg:R3>>
; MMR2-NEXT: jrc $ra # <MCInst #[[#MCINST7:]] JRC16_MM
-; MMR2-NEXT: # <MCOperand Reg:RA>>
+; MMR2-NEXT: # <MCOperand Reg:R31>>
;
; MMR2-DSP-LABEL: test:
; MMR2-DSP: # %bb.0: # %entry
@@ -43,14 +43,14 @@ define i64 @test(i32 signext %a, i32 signext %b) {
; MMR2-DSP-NEXT: # <MCOperand Reg:R2>>
; MMR2-DSP-NEXT: madd $ac0, $4, $5 # <MCInst #[[#MCINST10:]] MADD_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:AC0>
-; MMR2-DSP-NEXT: # <MCOperand Reg:A0>
-; MMR2-DSP-NEXT: # <MCOperand Reg:A1>
+; MMR2-DSP-NEXT: # <MCOperand Reg:R4>
+; MMR2-DSP-NEXT: # <MCOperand Reg:R5>
; MMR2-DSP-NEXT: # <MCOperand Reg:AC0>>
; MMR2-DSP-NEXT: mflo $2, $ac0 # <MCInst #[[#MCINST11:]] MFLO_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:R2>
; MMR2-DSP-NEXT: # <MCOperand Reg:AC0>>
; MMR2-DSP-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM
-; MMR2-DSP-NEXT: # <MCOperand Reg:RA>>
+; MMR2-DSP-NEXT: # <MCOperand Reg:R31>>
; MMR2-DSP-NEXT: mfhi $3, $ac0 # <MCInst #[[#MCINST13:]] MFHI_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:R3>
; MMR2-DSP-NEXT: # <MCOperand Reg:AC0>>
diff --git a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
index 37a20acf7f991..38b5aa5efa885 100644
--- a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
+++ b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
@@ -48,24 +48,24 @@ frameInfo:
fixedStack:
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
constants:
body: |
bb.0.entry:
- liveins: $ra
+ liveins: $r31
- $sp = ADDiu $sp, -24
+ $r29 = ADDiu $r29, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- CFI_INSTRUCTION offset $ra_64, -4
- $a0 = LI16_MM 1
- $a1 = LI16_MM 2
- JAL_MM @callee13, csr_o32, implicit-def dead $ra, implicit killed $a0, implicit killed $a1, implicit-def $sp, implicit-def $r2
- $ra = LW $sp, 20 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit $r2
+ SW killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ CFI_INSTRUCTION offset $r31_64, -4
+ $r4 = LI16_MM 1
+ $r5 = LI16_MM 2
+ JAL_MM @callee13, csr_o32, implicit-def dead $r31, implicit killed $r4, implicit killed $r5, implicit-def $r29, implicit-def $r2
+ $r31 = LW $r29, 20 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 24
+ PseudoReturn undef $r31, implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
index b2b057259d584..174adf5973e03 100644
--- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
@@ -27,8 +27,8 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
- - { reg: '$a1', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
+ - { reg: '$r5', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -49,37 +49,37 @@ frameInfo:
fixedStack:
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s1', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r17', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
body: |
bb.0:
- liveins: $a0, $a1, $ra, $s1, $s0
+ liveins: $r4, $r5, $r31, $r17, $r16
- $sp = ADDiu $sp, -32
+ $r29 = ADDiu $r29, -32
CFI_INSTRUCTION def_cfa_offset 32
- SW killed $ra, $sp, 28 :: (store (s32) into %stack.0)
- SW killed $s1, $sp, 24 :: (store (s32) into %stack.1)
- SW killed $s0, $sp, 20 :: (store (s32) into %stack.2)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s1_64, -8
- CFI_INSTRUCTION offset $s0_64, -12
- $s1 = MOVE16_MM $a1
- $s0 = MOVE16_MM $a0
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
- SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store (s32) into %ir.adr)
+ SW killed $r31, $r29, 28 :: (store (s32) into %stack.0)
+ SW killed $r17, $r29, 24 :: (store (s32) into %stack.1)
+ SW killed $r16, $r29, 20 :: (store (s32) into %stack.2)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r17_64, -8
+ CFI_INSTRUCTION offset $r16_64, -12
+ $r17 = MOVE16_MM $r5
+ $r16 = MOVE16_MM $r4
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def dead $r2
+ SW16_MM killed renamable $r17, killed renamable $r16, 0 :: (store (s32) into %ir.adr)
$r2 = LI16_MM 0
- $s0 = LW $sp, 20 :: (load (s32) from %stack.2)
- $s1 = LW $sp, 24 :: (load (s32) from %stack.1)
- $ra = LW $sp, 28 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 32
- PseudoReturn undef $ra, implicit killed $r2
+ $r16 = LW $r29, 20 :: (load (s32) from %stack.2)
+ $r17 = LW $r29, 24 :: (load (s32) from %stack.1)
+ $r31 = LW $r29, 28 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 32
+ PseudoReturn undef $r31, implicit killed $r2
...
---
@@ -95,8 +95,8 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
- - { reg: '$a1', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
+ - { reg: '$r5', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -117,37 +117,37 @@ frameInfo:
fixedStack:
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s1', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r17', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
body: |
bb.0:
- liveins: $a0, $a1, $ra, $s1, $s0
+ liveins: $r4, $r5, $r31, $r17, $r16
- $sp = ADDiu $sp, -32
+ $r29 = ADDiu $r29, -32
CFI_INSTRUCTION def_cfa_offset 32
- SW killed $ra, $sp, 28 :: (store (s32) into %stack.0)
- SW_MM killed $s1, $sp, 24 :: (store (s32) into %stack.1)
- SW_MM killed $s0, $sp, 20 :: (store (s32) into %stack.2)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s1_64, -8
- CFI_INSTRUCTION offset $s0_64, -12
- $s1 = MOVE16_MM $a1
- $s0 = MOVE16_MM $a0
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
- SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store (s32) into %ir.adr)
+ SW killed $r31, $r29, 28 :: (store (s32) into %stack.0)
+ SW_MM killed $r17, $r29, 24 :: (store (s32) into %stack.1)
+ SW_MM killed $r16, $r29, 20 :: (store (s32) into %stack.2)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r17_64, -8
+ CFI_INSTRUCTION offset $r16_64, -12
+ $r17 = MOVE16_MM $r5
+ $r16 = MOVE16_MM $r4
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def dead $r2
+ SW16_MM killed renamable $r17, killed renamable $r16, 0 :: (store (s32) into %ir.adr)
$r2 = LI16_MM 0
- $s0 = LW_MM $sp, 20 :: (load (s32) from %stack.2)
- $s1 = LW_MM $sp, 24 :: (load (s32) from %stack.1)
- $ra = LW $sp, 28 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 32
- PseudoReturn undef $ra, implicit killed $r2
+ $r16 = LW_MM $r29, 20 :: (load (s32) from %stack.2)
+ $r17 = LW_MM $r29, 24 :: (load (s32) from %stack.1)
+ $r31 = LW $r29, 28 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 32
+ PseudoReturn undef $r31, implicit killed $r2
...
---
@@ -163,8 +163,8 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
- - { reg: '$a1', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
+ - { reg: '$r5', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -185,37 +185,37 @@ frameInfo:
fixedStack:
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s1', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r17', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
body: |
bb.0:
- liveins: $a0, $a1, $ra, $s1, $s0
+ liveins: $r4, $r5, $r31, $r17, $r16
- $sp = ADDiu $sp, -32
+ $r29 = ADDiu $r29, -32
CFI_INSTRUCTION def_cfa_offset 32
- SW killed $ra, $sp, 28 :: (store (s32) into %stack.0)
- SW_MM killed $s1, $sp, 24 :: (store (s32) into %stack.1)
- SW killed $s0, $sp, 20 :: (store (s32) into %stack.2)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s1_64, -8
- CFI_INSTRUCTION offset $s0_64, -12
- $s1 = MOVE16_MM $a1
- $s0 = MOVE16_MM $a0
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
- SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store (s32) into %ir.adr)
+ SW killed $r31, $r29, 28 :: (store (s32) into %stack.0)
+ SW_MM killed $r17, $r29, 24 :: (store (s32) into %stack.1)
+ SW killed $r16, $r29, 20 :: (store (s32) into %stack.2)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r17_64, -8
+ CFI_INSTRUCTION offset $r16_64, -12
+ $r17 = MOVE16_MM $r5
+ $r16 = MOVE16_MM $r4
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def dead $r2
+ SW16_MM killed renamable $r17, killed renamable $r16, 0 :: (store (s32) into %ir.adr)
$r2 = LI16_MM 0
- $s0 = LW_MM $sp, 20 :: (load (s32) from %stack.2)
- $s1 = LW $sp, 24 :: (load (s32) from %stack.1)
- $ra = LW $sp, 28 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 32
- PseudoReturn undef $ra, implicit killed $r2
+ $r16 = LW_MM $r29, 20 :: (load (s32) from %stack.2)
+ $r17 = LW $r29, 24 :: (load (s32) from %stack.1)
+ $r31 = LW $r29, 28 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 32
+ PseudoReturn undef $r31, implicit killed $r2
...
---
@@ -231,8 +231,8 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
- - { reg: '$a1', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
+ - { reg: '$r5', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -253,37 +253,37 @@ frameInfo:
fixedStack:
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s1', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r17', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
body: |
bb.0:
- liveins: $a0, $a1, $ra, $s1, $s0
+ liveins: $r4, $r5, $r31, $r17, $r16
- $sp = ADDiu $sp, -32
+ $r29 = ADDiu $r29, -32
CFI_INSTRUCTION def_cfa_offset 32
- SW killed $ra, $sp, 28 :: (store (s32) into %stack.0)
- SW killed $s1, $sp, 24 :: (store (s32) into %stack.1)
- SW_MM killed $s0, $sp, 20 :: (store (s32) into %stack.2)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s1_64, -8
- CFI_INSTRUCTION offset $s0_64, -12
- $s1 = MOVE16_MM $a1
- $s0 = MOVE16_MM $a0
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
- SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store (s32) into %ir.adr)
+ SW killed $r31, $r29, 28 :: (store (s32) into %stack.0)
+ SW killed $r17, $r29, 24 :: (store (s32) into %stack.1)
+ SW_MM killed $r16, $r29, 20 :: (store (s32) into %stack.2)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r17_64, -8
+ CFI_INSTRUCTION offset $r16_64, -12
+ $r17 = MOVE16_MM $r5
+ $r16 = MOVE16_MM $r4
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def dead $r2
+ SW16_MM killed renamable $r17, killed renamable $r16, 0 :: (store (s32) into %ir.adr)
$r2 = LI16_MM 0
- $s0 = LW $sp, 20 :: (load (s32) from %stack.2)
- $s1 = LW_MM $sp, 24 :: (load (s32) from %stack.1)
- $ra = LW $sp, 28 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 32
- PseudoReturn undef $ra, implicit killed $r2
+ $r16 = LW $r29, 20 :: (load (s32) from %stack.2)
+ $r17 = LW_MM $r29, 24 :: (load (s32) from %stack.1)
+ $r31 = LW $r29, 28 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 32
+ PseudoReturn undef $r31, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-movep.mir b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-movep.mir
index e46352c169ee9..b674f2b988f19 100644
--- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-movep.mir
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-movep.mir
@@ -15,70 +15,70 @@
name: move1
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
body: |
bb.0:
- liveins: $ra
+ liveins: $r31
; CHECK-LABEL: name: move1
; CHECK: ADDIUSP_MM -24
; CHECK: CFI_INSTRUCTION def_cfa_offset 24
- ; CHECK: SWSP_MM killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- ; CHECK: CFI_INSTRUCTION offset $ra_64, -4
- ; CHECK: JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $r2, implicit-def $r3
- ; CHECK: $a0, $a1 = MOVEP_MM $r2, $r3
- ; CHECK: JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $r2, implicit-def $r3
- ; CHECK: $ra = LWSP_MM $sp, 20 :: (load (s32) from %stack.0)
+ ; CHECK: SWSP_MM killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ ; CHECK: CFI_INSTRUCTION offset $r31_64, -4
+ ; CHECK: JAL_MM @g, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def $r2, implicit-def $r3
+ ; CHECK: $r4, $r5 = MOVEP_MM $r2, $r3
+ ; CHECK: JAL_MM @f, csr_o32, implicit-def dead $r31, implicit $r4, implicit $r5, implicit-def $r29, implicit-def $r2, implicit-def $r3
+ ; CHECK: $r31 = LWSP_MM $r29, 20 :: (load (s32) from %stack.0)
; CHECK: ADDIUSP_MM 24
- ; CHECK: PseudoReturn undef $ra, implicit $r2, implicit $r3
- $sp = ADDiu $sp, -24
+ ; CHECK: PseudoReturn undef $r31, implicit $r2, implicit $r3
+ $r29 = ADDiu $r29, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- CFI_INSTRUCTION offset $ra_64, -4
- JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $r2, implicit-def $r3
- $a0 = MOVE16_MM $r2
- $a1 = MOVE16_MM $r3
- JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $r2, implicit-def $r3
- $ra = LW $sp, 20 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit $r2, implicit $r3
+ SW killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ CFI_INSTRUCTION offset $r31_64, -4
+ JAL_MM @g, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def $r2, implicit-def $r3
+ $r4 = MOVE16_MM $r2
+ $r5 = MOVE16_MM $r3
+ JAL_MM @f, csr_o32, implicit-def dead $r31, implicit $r4, implicit $r5, implicit-def $r29, implicit-def $r2, implicit-def $r3
+ $r31 = LW $r29, 20 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 24
+ PseudoReturn undef $r31, implicit $r2, implicit $r3
...
---
name: move2
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
body: |
bb.0:
- liveins: $ra
+ liveins: $r31
; CHECK-LABEL: name: move2
; CHECK: ADDIUSP_MM -24
; CHECK: CFI_INSTRUCTION def_cfa_offset 24
- ; CHECK: SWSP_MM killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- ; CHECK: CFI_INSTRUCTION offset $ra_64, -4
- ; CHECK: JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $r2, implicit-def $r3
- ; CHECK: $a0, $a1 = MOVEP_MM $r2, $r3
- ; CHECK: JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $r2, implicit-def $r3
- ; CHECK: $ra = LWSP_MM $sp, 20 :: (load (s32) from %stack.0)
+ ; CHECK: SWSP_MM killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ ; CHECK: CFI_INSTRUCTION offset $r31_64, -4
+ ; CHECK: JAL_MM @g, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def $r2, implicit-def $r3
+ ; CHECK: $r4, $r5 = MOVEP_MM $r2, $r3
+ ; CHECK: JAL_MM @f, csr_o32, implicit-def dead $r31, implicit $r4, implicit $r5, implicit-def $r29, implicit-def $r2, implicit-def $r3
+ ; CHECK: $r31 = LWSP_MM $r29, 20 :: (load (s32) from %stack.0)
; CHECK: ADDIUSP_MM 24
- ; CHECK: PseudoReturn undef $ra, implicit $r2, implicit $r3
- $sp = ADDiu $sp, -24
+ ; CHECK: PseudoReturn undef $r31, implicit $r2, implicit $r3
+ $r29 = ADDiu $r29, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- CFI_INSTRUCTION offset $ra_64, -4
- JAL_MM @g, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def $r2, implicit-def $r3
- $a1 = MOVE16_MM $r3
- $a0 = MOVE16_MM $r2
- JAL_MM @f, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $r2, implicit-def $r3
- $ra = LW $sp, 20 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit $r2, implicit $r3
+ SW killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ CFI_INSTRUCTION offset $r31_64, -4
+ JAL_MM @g, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def $r2, implicit-def $r3
+ $r5 = MOVE16_MM $r3
+ $r4 = MOVE16_MM $r2
+ JAL_MM @f, csr_o32, implicit-def dead $r31, implicit $r4, implicit $r5, implicit-def $r29, implicit-def $r2, implicit-def $r3
+ $r31 = LW $r29, 20 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 24
+ PseudoReturn undef $r31, implicit $r2, implicit $r3
...
---
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
index 70d7fdcd2690c..831462ada5a97 100644
--- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
@@ -26,7 +26,7 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a1', virtual-reg: '' }
+ - { reg: '$r5', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -47,29 +47,29 @@ frameInfo:
fixedStack:
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
body: |
bb.0:
- liveins: $a1, $ra, $s0
+ liveins: $r5, $r31, $r16
- $sp = ADDiu $sp, -24
+ $r29 = ADDiu $r29, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- SW killed $s0, $sp, 16 :: (store (s32) into %stack.1)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s0_64, -8
- $s0 = MOVE16_MM $a1
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
- $r2 = MOVE16_MM killed $s0
- $s0 = LW $sp, 16 :: (load (s32) from %stack.1)
- $ra = LW $sp, 20 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit killed $r2
+ SW killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ SW killed $r16, $r29, 16 :: (store (s32) into %stack.1)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r16_64, -8
+ $r16 = MOVE16_MM $r5
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def dead $r2
+ $r2 = MOVE16_MM killed $r16
+ $r16 = LW $r29, 16 :: (load (s32) from %stack.1)
+ $r31 = LW $r29, 20 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 24
+ PseudoReturn undef $r31, implicit killed $r2
...
---
@@ -85,7 +85,7 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a1', virtual-reg: '' }
+ - { reg: '$r5', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -106,29 +106,29 @@ frameInfo:
fixedStack:
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
body: |
bb.0:
- liveins: $a1, $ra, $s0
+ liveins: $r5, $r31, $r16
- $sp = ADDiu $sp, -24
+ $r29 = ADDiu $r29, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW_MM killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- SW_MM killed $s0, $sp, 16 :: (store (s32) into %stack.1)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s0_64, -8
- $s0 = MOVE16_MM $a1
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
- $r2 = MOVE16_MM killed $s0
- $s0 = LW_MM $sp, 16 :: (load (s32) from %stack.1)
- $ra = LW_MM $sp, 20 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit killed $r2
+ SW_MM killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ SW_MM killed $r16, $r29, 16 :: (store (s32) into %stack.1)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r16_64, -8
+ $r16 = MOVE16_MM $r5
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def dead $r2
+ $r2 = MOVE16_MM killed $r16
+ $r16 = LW_MM $r29, 16 :: (load (s32) from %stack.1)
+ $r31 = LW_MM $r29, 20 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 24
+ PseudoReturn undef $r31, implicit killed $r2
...
---
@@ -144,7 +144,7 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a1', virtual-reg: '' }
+ - { reg: '$r5', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -165,29 +165,29 @@ frameInfo:
fixedStack:
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
body: |
bb.0:
- liveins: $a1, $ra, $s0
+ liveins: $r5, $r31, $r16
- $sp = ADDiu $sp, -24
+ $r29 = ADDiu $r29, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW_MM killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- SW killed $s0, $sp, 16 :: (store (s32) into %stack.1)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s0_64, -8
- $s0 = MOVE16_MM $a1
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
- $r2 = MOVE16_MM killed $s0
- $s0 = LW_MM $sp, 16 :: (load (s32) from %stack.1)
- $ra = LW $sp, 20 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit killed $r2
+ SW_MM killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ SW killed $r16, $r29, 16 :: (store (s32) into %stack.1)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r16_64, -8
+ $r16 = MOVE16_MM $r5
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def dead $r2
+ $r2 = MOVE16_MM killed $r16
+ $r16 = LW_MM $r29, 16 :: (load (s32) from %stack.1)
+ $r31 = LW $r29, 20 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 24
+ PseudoReturn undef $r31, implicit killed $r2
...
---
@@ -203,7 +203,7 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a1', virtual-reg: '' }
+ - { reg: '$r5', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -224,29 +224,29 @@ frameInfo:
fixedStack:
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
body: |
bb.0:
- liveins: $a1, $ra, $s0
+ liveins: $r5, $r31, $r16
- $sp = ADDiu $sp, -24
+ $r29 = ADDiu $r29, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- SW_MM killed $s0, $sp, 16 :: (store (s32) into %stack.1)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s0_64, -8
- $s0 = MOVE16_MM $a1
- JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2
- $r2 = MOVE16_MM killed $s0
- $s0 = LW $sp, 16 :: (load (s32) from %stack.1)
- $ra = LW_MM $sp, 20 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit killed $r2
+ SW killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ SW_MM killed $r16, $r29, 16 :: (store (s32) into %stack.1)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r16_64, -8
+ $r16 = MOVE16_MM $r5
+ JAL @f, csr_o32, implicit-def dead $r31, implicit-def $r29, implicit-def dead $r2
+ $r2 = MOVE16_MM killed $r16
+ $r16 = LW $r29, 16 :: (load (s32) from %stack.1)
+ $r31 = LW_MM $r29, 20 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 24
+ PseudoReturn undef $r31, implicit killed $r2
...
diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll
index 0cf6e7198c5e2..fb150094d5678 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128.ll
@@ -2780,9 +2780,9 @@ entry:
define fp128 @select_LD(i32 signext %a, i64, fp128 %b, fp128 %c) {
; C_CC_FMT-LABEL: select_LD:
; C_CC_FMT: # %bb.0: # %entry
-; C_CC_FMT-NEXT: move $2, $8
-; C_CC_FMT-NEXT: movn $2, $6, $4
+; C_CC_FMT-NEXT: movn $8, $6, $4
; C_CC_FMT-NEXT: movn $9, $7, $4
+; C_CC_FMT-NEXT: move $2, $8
; C_CC_FMT-NEXT: move $4, $9
; C_CC_FMT-NEXT: jr $ra
; C_CC_FMT-NEXT: nop
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
index 2a1e5abb15d6a..115aa54f8722c 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
@@ -119,8 +119,8 @@ registers:
- { id: 57, class: gpr64, preferred-register: '' }
- { id: 58, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%5' }
- - { reg: '$t9_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '%5' }
+ - { reg: '$r25_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -144,20 +144,20 @@ constants:
body: |
bb.0.entry:
successors: %bb.1.entry._ZTW1k.exit_crit_edge(0x7fe00000), %bb.2.init.i.i(0x00200000)
- liveins: $a0_64, $t9_64
+ liveins: $r4_64, $r25_64
%57 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
- %58 = DADDu %57, $t9_64
+ %58 = DADDu %57, $r25_64
%6 = DADDiu %58, target-flags(mips-gpoff-lo) @_Z2k1i
- %5 = COPY $a0_64
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ %5 = COPY $r4_64
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
%7 = LUi64 target-flags(mips-call-hi16) @_Z1gi
%8 = DADDu killed %7, %6
%9 = LD killed %8, target-flags(mips-call-lo16) @_Z1gi :: (load (s64) from call-entry @_Z1gi)
- $a0_64 = COPY %5
- $gp_64 = COPY %6
- JALR64Pseudo killed %9, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $r4_64 = COPY %5
+ $r28_64 = COPY %6
+ JALR64Pseudo killed %9, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
%10 = COPY $r2
%11 = COPY %5.sub_32
%12 = ADDu %10, killed %11
@@ -166,70 +166,70 @@ body: |
%15 = LD killed %14, target-flags(mips-got-lo16) @v :: (load (s64) from got)
%16 = LW killed %15, 0 :: (dereferenceable load (s32) from @v)
%0 = ADDu killed %12, killed %16
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
%17 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%18 = DADDu killed %17, %6
%19 = LD killed %18, target-flags(mips-call-lo16) &__tls_get_addr :: (load (s64) from call-entry &__tls_get_addr)
%20 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
- $a0_64 = COPY %20
- $gp_64 = COPY %6
- JALR64Pseudo killed %19, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $r4_64 = COPY %20
+ $r28_64 = COPY %6
+ JALR64Pseudo killed %19, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
%21 = COPY $r2_64
%22 = DADDiu %21, target-flags(mips-dtprel-hi) @__tls_guard
%23 = LBu killed %22, target-flags(mips-dtprel-lo) @__tls_guard :: (dereferenceable load (s8) from @__tls_guard)
- BEQ killed %23, $zero, %bb.2.init.i.i, implicit-def dead $at
- B %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead $at
+ BEQ killed %23, $r0, %bb.2.init.i.i, implicit-def dead $r1
+ B %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead $r1
bb.1.entry._ZTW1k.exit_crit_edge:
successors: %bb.3._ZTW1k.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
%39 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%40 = DADDu killed %39, %6
%41 = LD killed %40, target-flags(mips-call-lo16) &__tls_get_addr :: (load (s64) from call-entry &__tls_get_addr)
%42 = DADDiu %6, target-flags(mips-tlsgd) @k
- $a0_64 = COPY %42
- $gp_64 = COPY %6
- JALR64Pseudo killed %41, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $r4_64 = COPY %42
+ $r28_64 = COPY %6
+ JALR64Pseudo killed %41, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
%43 = COPY $r2_64
%1 = LW %43, 0 :: (dereferenceable load (s32) from @k)
- B %bb.3._ZTW1k.exit, implicit-def dead $at
+ B %bb.3._ZTW1k.exit, implicit-def dead $r1
bb.2.init.i.i:
successors: %bb.3._ZTW1k.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
%24 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%25 = DADDu killed %24, %6
%26 = LD %25, target-flags(mips-call-lo16) &__tls_get_addr :: (load (s64) from call-entry &__tls_get_addr)
%27 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
- $a0_64 = COPY %27
- $gp_64 = COPY %6
- JALR64Pseudo killed %26, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $r4_64 = COPY %27
+ $r28_64 = COPY %6
+ JALR64Pseudo killed %26, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
%28 = COPY $r2_64
%29 = DADDiu %28, target-flags(mips-dtprel-hi) @__tls_guard
- %30 = ADDiu $zero, 1
+ %30 = ADDiu $r0, 1
SB killed %30, killed %29, target-flags(mips-dtprel-lo) @__tls_guard :: (store (s8) into @__tls_guard)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
%31 = LUi64 target-flags(mips-call-hi16) @_Z1gi
%32 = DADDu killed %31, %6
- %33 = DADDiu $zero_64, 3
+ %33 = DADDiu $r0_64, 3
%34 = LD killed %32, target-flags(mips-call-lo16) @_Z1gi :: (load (s64) from call-entry @_Z1gi)
- $a0_64 = COPY %33
- $gp_64 = COPY %6
- JALR64Pseudo killed %34, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $r4_64 = COPY %33
+ $r28_64 = COPY %6
+ JALR64Pseudo killed %34, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
%35 = COPY $r2
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
%36 = LD %25, target-flags(mips-call-lo16) &__tls_get_addr :: (load (s64) from call-entry &__tls_get_addr)
%37 = DADDiu %6, target-flags(mips-tlsgd) @k
- $a0_64 = COPY %37
- $gp_64 = COPY %6
- JALR64Pseudo killed %36, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $r4_64 = COPY %37
+ $r28_64 = COPY %6
+ JALR64Pseudo killed %36, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
%38 = COPY $r2_64
SW %35, %38, 0 :: (store (s32) into @k)
%2 = COPY %35
@@ -242,30 +242,30 @@ body: |
%44 = LUi64 target-flags(mips-got-hi16) @_ZTH1j
%45 = DADDu killed %44, %6
%46 = LD killed %45, target-flags(mips-got-lo16) @_ZTH1j :: (load (s64) from got)
- BEQ64 killed %46, $zero_64, %bb.5._ZTW1j.exit, implicit-def dead $at
- B %bb.4, implicit-def dead $at
+ BEQ64 killed %46, $r0_64, %bb.5._ZTW1j.exit, implicit-def dead $r1
+ B %bb.4, implicit-def dead $r1
bb.4 (%ir-block.2):
successors: %bb.5._ZTW1j.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
%47 = LUi64 target-flags(mips-call-hi16) @_ZTH1j
%48 = DADDu killed %47, %6
%49 = LD killed %48, target-flags(mips-call-lo16) @_ZTH1j :: (load (s64) from call-entry @_ZTH1j)
- $gp_64 = COPY %6
- JALR64Pseudo killed %49, csr_n64, implicit-def dead $ra, implicit $gp_64, implicit-def $sp
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $r28_64 = COPY %6
+ JALR64Pseudo killed %49, csr_n64, implicit-def dead $r31, implicit $r28_64, implicit-def $r29
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
bb.5._ZTW1j.exit:
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
%50 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%51 = DADDu killed %50, %6
%52 = LD killed %51, target-flags(mips-call-lo16) &__tls_get_addr :: (load (s64) from call-entry &__tls_get_addr)
%53 = DADDiu %6, target-flags(mips-tlsgd) @j
- $a0_64 = COPY %53
- $gp_64 = COPY %6
- JALR64Pseudo killed %52, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $r4_64 = COPY %53
+ $r28_64 = COPY %6
+ JALR64Pseudo killed %52, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
%54 = COPY $r2_64
%55 = LW %54, 0 :: (dereferenceable load (s32) from @j)
%56 = ADDu %4, killed %55
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
index c2b158dd7fb19..15188aaa1ae71 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
@@ -45,8 +45,8 @@ registers:
- { id: 11, class: gpr32, preferred-register: '' }
- { id: 12, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
- - { reg: '$t9', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '%0' }
+ - { reg: '$r25', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
@@ -70,16 +70,16 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0, $t9, $r2
+ liveins: $r4, $r25, $r2
- %1 = ADDu $r2, $t9
- %0 = COPY $a0
- ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp
+ %1 = ADDu $r2, $r25
+ %0 = COPY $r4
+ ADJCALLSTACKDOWN 16, 0, implicit-def dead $r29, implicit $r29
%2 = LW %1, target-flags(mips-got-call) @_Z1gi :: (load (s32) from call-entry @_Z1gi)
- $a0 = COPY %0
- $gp = COPY %1
- JALRPseudo killed %2, csr_o32_fpxx, implicit-def dead $ra, implicit $a0, implicit $gp, implicit-def $sp, implicit-def $r2
- ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp
+ $r4 = COPY %0
+ $r28 = COPY %1
+ JALRPseudo killed %2, csr_o32_fpxx, implicit-def dead $r31, implicit $r4, implicit $r28, implicit-def $r29, implicit-def $r2
+ ADJCALLSTACKUP 16, 0, implicit-def dead $r29, implicit $r29
%3 = COPY $r2
%4 = ADDu %3, %0
%5 = LW %1, target-flags(mips-got) @v :: (load (s32) from got)
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
index 0b312c5b2da73..3e855eaa8bd66 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
@@ -46,8 +46,8 @@ registers:
- { id: 12, class: gpr64, preferred-register: '' }
- { id: 13, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%0' }
- - { reg: '$t9_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '%0' }
+ - { reg: '$r25_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -70,18 +70,18 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64, $t9_64
+ liveins: $r4_64, $r25_64
%12 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
- %13 = DADDu %12, $t9_64
+ %13 = DADDu %12, $r25_64
%1 = DADDiu %13, target-flags(mips-gpoff-lo) @_Z2k1i
- %0 = COPY $a0_64
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ %0 = COPY $r4_64
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
%2 = LD %1, target-flags(mips-got-call) @_Z1gi :: (load (s64) from call-entry @_Z1gi)
- $a0_64 = COPY %0
- $gp_64 = COPY %1
- JALR64Pseudo killed %2, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $r4_64 = COPY %0
+ $r28_64 = COPY %1
+ JALR64Pseudo killed %2, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
%3 = COPY $r2
%4 = COPY %0.sub_32
%5 = ADDu %3, killed %4
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
index 45598990e4c19..18781c47c951b 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
@@ -111,8 +111,8 @@ registers:
- { id: 50, class: gpr64, preferred-register: '' }
- { id: 51, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '$a0_64', virtual-reg: '%5' }
- - { reg: '$t9_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '%5' }
+ - { reg: '$r25_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -136,17 +136,17 @@ constants:
body: |
bb.0.entry:
successors: %bb.1.entry._ZTW1k.exit_crit_edge(0x7fe00000), %bb.2.init.i.i(0x00200000)
- liveins: $a0_64, $t9_64
+ liveins: $r4_64, $r25_64
%50 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
- %51 = DADDu %50, $t9_64
+ %51 = DADDu %50, $r25_64
%43 = DADDiu %51, target-flags(mips-gpoff-lo) @_Z2k1i
- %5 = COPY $a0_64
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ %5 = COPY $r4_64
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
%6 = COPY %5.sub_32
- $a0_64 = COPY %5
- JAL @_Z1gi, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $r4_64 = COPY %5
+ JAL @_Z1gi, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit-def $r29, implicit-def $r2
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
%7 = COPY $r2
%8 = ADDu %7, killed %6
%9 = LUi64 target-flags(mips-highest) @v
@@ -163,8 +163,8 @@ body: |
%18 = COPY $r3_64
%19 = DADDu %18, killed %16
%20 = LBu killed %19, 0 :: (dereferenceable load (s8) from @__tls_guard)
- BEQ killed %20, $zero, %bb.2.init.i.i, implicit-def dead $at
- J %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead $at
+ BEQ killed %20, $r0, %bb.2.init.i.i, implicit-def dead $r1
+ J %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead $r1
bb.1.entry._ZTW1k.exit_crit_edge:
successors: %bb.3._ZTW1k.exit(0x80000000)
@@ -176,7 +176,7 @@ body: |
%35 = COPY $r3_64
%36 = DADDu %35, killed %33
%1 = LW killed %36, 0 :: (dereferenceable load (s32) from @k)
- J %bb.3._ZTW1k.exit, implicit-def dead $at
+ J %bb.3._ZTW1k.exit, implicit-def dead $r1
bb.2.init.i.i:
successors: %bb.3._ZTW1k.exit(0x80000000)
@@ -187,16 +187,16 @@ body: |
$r3_64 = COPY %23
%24 = COPY $r3_64
%25 = DADDu %24, killed %22
- %26 = ADDiu $zero, 1
+ %26 = ADDiu $r0, 1
SB killed %26, killed %25, 0 :: (store (s8) into @__tls_guard)
%27 = LUi64 target-flags(mips-tprel-hi) @k
%28 = DADDiu killed %27, target-flags(mips-tprel-lo) @k
%29 = DADDu %24, killed %28
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- %30 = DADDiu $zero_64, 3
- $a0_64 = COPY %30
- JAL @_Z1gi, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
+ %30 = DADDiu $r0_64, 3
+ $r4_64 = COPY %30
+ JAL @_Z1gi, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit-def $r29, implicit-def $r2
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
%31 = COPY $r2
SW %31, killed %29, 0 :: (store (s32) into @k)
%2 = COPY %31
@@ -212,15 +212,15 @@ body: |
%40 = DADDiu killed %39, target-flags(mips-abs-hi) @_ZTH1j
%41 = DSLL killed %40, 16
%42 = DADDiu killed %41, target-flags(mips-abs-lo) @_ZTH1j
- BEQ64 killed %42, $zero_64, %bb.5._ZTW1j.exit, implicit-def dead $at
- J %bb.4, implicit-def dead $at
+ BEQ64 killed %42, $r0_64, %bb.5._ZTW1j.exit, implicit-def dead $r1
+ J %bb.4, implicit-def dead $r1
bb.4 (%ir-block.2):
successors: %bb.5._ZTW1j.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- JAL @_ZTH1j, csr_n64, implicit-def dead $ra, implicit-def $sp
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
+ JAL @_ZTH1j, csr_n64, implicit-def dead $r31, implicit-def $r29
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
bb.5._ZTW1j.exit:
%44 = RDHWR64 $hwr29, 0
diff --git a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
index 63bb2d2eef4ed..4af41df6ee139 100644
--- a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
+++ b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
@@ -77,10 +77,10 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
- - { reg: '$a2_64', virtual-reg: '' }
- - { reg: '$a3_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
+ - { reg: '$r6_64', virtual-reg: '' }
+ - { reg: '$r7_64', virtual-reg: '' }
- { reg: '$r8_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
@@ -131,31 +131,31 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0_64, $a1_64, $a2_64, $a3_64, $r8_64
+ liveins: $r4_64, $r5_64, $r6_64, $r7_64, $r8_64
- SD killed $a0_64, %stack.1.a, 0 :: (store (s64) into %ir.1, align 16)
- SD killed $a1_64, %stack.1.a, 8 :: (store (s64) into %ir.2)
+ SD killed $r4_64, %stack.1.a, 0 :: (store (s64) into %ir.1, align 16)
+ SD killed $r5_64, %stack.1.a, 8 :: (store (s64) into %ir.2)
$w0 = LD_B %stack.1.a, 0 :: (dereferenceable load (s128) from %ir.a)
- SD killed $a2_64, %stack.2.b, 0 :: (store (s64) into %ir.4, align 16)
- SD killed $a3_64, %stack.2.b, 8 :: (store (s64) into %ir.5)
+ SD killed $r6_64, %stack.2.b, 0 :: (store (s64) into %ir.4, align 16)
+ SD killed $r7_64, %stack.2.b, 8 :: (store (s64) into %ir.5)
$w1 = LD_B %stack.2.b, 0 :: (dereferenceable load (s128) from %ir.b)
ST_B killed $w0, %stack.3.a.addr, 0 :: (store (s128) into %ir.a.addr)
ST_B killed $w1, %stack.4.b.addr, 0 :: (store (s128) into %ir.b.addr)
SW $r8, %stack.5.c.addr, 0, implicit killed $r8_64 :: (store (s32) into %ir.c.addr)
- $at_64 = LEA_ADDiu64 %stack.8, 0
- SD killed $at_64, %stack.6.g, 0 :: (store (s64) into %ir.g)
- $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- $a0_64 = LEA_ADDiu64 %stack.4.b.addr, 0
- JAL @h, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1_64, implicit-def $sp
- ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- $at_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r1_64 = LEA_ADDiu64 %stack.8, 0
+ SD killed $r1_64, %stack.6.g, 0 :: (store (s64) into %ir.g)
+ $r5_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
+ $r4_64 = LEA_ADDiu64 %stack.4.b.addr, 0
+ JAL @h, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r5_64, implicit-def $r29
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
+ $r1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$r2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$r3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $a0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $a2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $a3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r4_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r5_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r6_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r7_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$r8_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$r9_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$r10_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
@@ -164,25 +164,25 @@ body: |
$r13_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$r14_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$r15_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $s0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $s1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $s2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $s3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $s4_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $s5_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $s6_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $s7_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $t8_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $t9_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
- $ra_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r16_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r17_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r18_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r19_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r20_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r21_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r22_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r23_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r24_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r25_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
+ $r31_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
$w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load (s128) from %ir.a.addr)
- SD $at_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $r2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $r3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $a0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $a1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $a2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $a3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r4_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r5_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r6_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r7_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $r8_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $r9_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $r10_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
@@ -191,23 +191,23 @@ body: |
SD $r13_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $r14_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
SD $r15_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $s0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $s1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $s2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $s3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $s4_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $s5_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $s6_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $s7_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $t8_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $t9_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- SD $ra_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
- $at_64 = LD %stack.7.d, 0 :: (dereferenceable load (s64) from %ir.d)
- $r2 = LB $at_64, 0 :: (load (s8) from %ir.arrayidx)
+ SD $r16_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r17_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r18_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r19_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r20_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r21_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r22_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r23_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r24_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r25_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ SD $r31_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
+ $r1_64 = LD %stack.7.d, 0 :: (dereferenceable load (s64) from %ir.d)
+ $r2 = LB $r1_64, 0 :: (load (s8) from %ir.arrayidx)
$w1 = FILL_B killed $r2
$w0 = ADDV_B killed $w0, killed $w1
- $at = LB killed $at_64, 1 :: (load (s8) from %ir.arrayidx3)
- $w1 = FILL_B killed $at
+ $r1 = LB killed $r1_64, 1 :: (load (s8) from %ir.arrayidx3)
+ $w1 = FILL_B killed $r1
$w0 = ADDV_B killed $w0, killed $w1
$w1 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load (s128) from %ir.b.addr)
$w0 = ADDV_B killed $w1, killed $w0
diff --git a/llvm/test/CodeGen/Mips/msa/ldr_str.ll b/llvm/test/CodeGen/Mips/msa/ldr_str.ll
index a029b39b06d27..d399621d25cdc 100644
--- a/llvm/test/CodeGen/Mips/msa/ldr_str.ll
+++ b/llvm/test/CodeGen/Mips/msa/ldr_str.ll
@@ -14,7 +14,7 @@ define void @llvm_mips_ldr_d_test(ptr %val, ptr %ptr) nounwind {
; MIPS32R5-EB-NEXT: # implicit-def: $r2
; MIPS32R5-EB-NEXT: lwr $2, 23($5)
; MIPS32R5-EB-NEXT: lwl $2, 20($5)
-; MIPS32R5-EB-NEXT: # implicit-def: $at
+; MIPS32R5-EB-NEXT: # implicit-def: $r1
; MIPS32R5-EB-NEXT: lwr $1, 19($5)
; MIPS32R5-EB-NEXT: lwl $1, 16($5)
; MIPS32R5-EB-NEXT: fill.w $w0, $2
@@ -28,7 +28,7 @@ define void @llvm_mips_ldr_d_test(ptr %val, ptr %ptr) nounwind {
; MIPS32R5-EL-NEXT: # implicit-def: $r2
; MIPS32R5-EL-NEXT: lwr $2, 16($5)
; MIPS32R5-EL-NEXT: lwl $2, 19($5)
-; MIPS32R5-EL-NEXT: # implicit-def: $at
+; MIPS32R5-EL-NEXT: # implicit-def: $r1
; MIPS32R5-EL-NEXT: lwr $1, 20($5)
; MIPS32R5-EL-NEXT: lwl $1, 23($5)
; MIPS32R5-EL-NEXT: fill.w $w0, $2
@@ -72,7 +72,7 @@ declare <2 x i64> @llvm.mips.ldr.d(ptr, i32) nounwind
define void @llvm_mips_ldr_w_test(ptr %val, ptr %ptr) nounwind {
; MIPS32R5-EB-LABEL: llvm_mips_ldr_w_test:
; MIPS32R5-EB: # %bb.0: # %entry
-; MIPS32R5-EB-NEXT: # implicit-def: $at
+; MIPS32R5-EB-NEXT: # implicit-def: $r1
; MIPS32R5-EB-NEXT: lwr $1, 19($5)
; MIPS32R5-EB-NEXT: lwl $1, 16($5)
; MIPS32R5-EB-NEXT: fill.w $w0, $1
@@ -82,7 +82,7 @@ define void @llvm_mips_ldr_w_test(ptr %val, ptr %ptr) nounwind {
;
; MIPS32R5-EL-LABEL: llvm_mips_ldr_w_test:
; MIPS32R5-EL: # %bb.0: # %entry
-; MIPS32R5-EL-NEXT: # implicit-def: $at
+; MIPS32R5-EL-NEXT: # implicit-def: $r1
; MIPS32R5-EL-NEXT: lwr $1, 16($5)
; MIPS32R5-EL-NEXT: lwl $1, 19($5)
; MIPS32R5-EL-NEXT: fill.w $w0, $1
diff --git a/llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll b/llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll
index 027e1ee1cfe6a..6cc22c92733f4 100644
--- a/llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll
+++ b/llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -O0 -stop-before=regallocfast < %s | FileCheck -check-prefix=MIPS32 %s
; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=pic -O0 -stop-before=regallocfast < %s | FileCheck -check-prefix=MIPS64 %s
-; The second call does not need $gp, so the copy setting it up is dead.
+; The second call does not need $r28, so the copy setting it up is dead.
@tls_gd = external thread_local global i32
@tls_ld = external thread_local(localdynamic) global i32
@@ -10,27 +10,27 @@
define i32 @two_tls_calls() {
; MIPS32-LABEL: name: two_tls_calls
; MIPS32: bb.0 (%ir-block.0):
- ; MIPS32-NEXT: liveins: $t9, $r2
+ ; MIPS32-NEXT: liveins: $r25, $r2
; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $t9
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp
+ ; MIPS32-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def dead $r29, implicit $r29
; MIPS32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[ADDu]], target-flags(mips-tlsgd) @tls_gd
; MIPS32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got-call) &__tls_get_addr :: (load (s32) from call-entry &__tls_get_addr)
- ; MIPS32-NEXT: $a0 = COPY [[ADDiu]]
- ; MIPS32-NEXT: $gp = COPY [[ADDu]]
- ; MIPS32-NEXT: $t9 = COPY [[LW]]
- ; MIPS32-NEXT: JALRPseudo $t9, csr_o32, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0, implicit $gp, implicit-def $sp, implicit-def $r2
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp
+ ; MIPS32-NEXT: $r4 = COPY [[ADDiu]]
+ ; MIPS32-NEXT: $r28 = COPY [[ADDu]]
+ ; MIPS32-NEXT: $r25 = COPY [[LW]]
+ ; MIPS32-NEXT: JALRPseudo $r25, csr_o32, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $r31, implicit $r4, implicit $r28, implicit-def $r29, implicit-def $r2
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def dead $r29, implicit $r29
; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $r2
; MIPS32-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (dereferenceable load (s32) from @tls_gd)
- ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp
+ ; MIPS32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def dead $r29, implicit $r29
; MIPS32-NEXT: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu [[ADDu]], target-flags(mips-tlsldm) @tls_ld
; MIPS32-NEXT: [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got-call) &__tls_get_addr :: (load (s32) from call-entry &__tls_get_addr)
- ; MIPS32-NEXT: $a0 = COPY [[ADDiu1]]
- ; MIPS32-NEXT: dead $gp = COPY [[ADDu]]
- ; MIPS32-NEXT: $t9 = COPY [[LW2]]
- ; MIPS32-NEXT: JALRPseudo $t9, csr_o32, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0, implicit-def $sp, implicit-def $r2
- ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp
+ ; MIPS32-NEXT: $r4 = COPY [[ADDiu1]]
+ ; MIPS32-NEXT: dead $r28 = COPY [[ADDu]]
+ ; MIPS32-NEXT: $r25 = COPY [[LW2]]
+ ; MIPS32-NEXT: JALRPseudo $r25, csr_o32, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $r31, implicit $r4, implicit-def $r29, implicit-def $r2
+ ; MIPS32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def dead $r29, implicit $r29
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $r2
; MIPS32-NEXT: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-dtprel-hi) @tls_ld
; MIPS32-NEXT: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[COPY1]]
@@ -41,29 +41,29 @@ define i32 @two_tls_calls() {
;
; MIPS64-LABEL: name: two_tls_calls
; MIPS64: bb.0 (%ir-block.0):
- ; MIPS64-NEXT: liveins: $t9_64
+ ; MIPS64-NEXT: liveins: $r25_64
; MIPS64-NEXT: {{ $}}
; MIPS64-NEXT: [[LUi64_:%[0-9]+]]:gpr64 = LUi64 target-flags(mips-gpoff-hi) @two_tls_calls
- ; MIPS64-NEXT: [[DADDu:%[0-9]+]]:gpr64 = DADDu [[LUi64_]], $t9_64
+ ; MIPS64-NEXT: [[DADDu:%[0-9]+]]:gpr64 = DADDu [[LUi64_]], $r25_64
; MIPS64-NEXT: [[DADDiu:%[0-9]+]]:gpr64 = DADDiu [[DADDu]], target-flags(mips-gpoff-lo) @two_tls_calls
- ; MIPS64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; MIPS64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
; MIPS64-NEXT: [[DADDiu1:%[0-9]+]]:gpr64 = DADDiu [[DADDiu]], target-flags(mips-tlsgd) @tls_gd
; MIPS64-NEXT: [[LD:%[0-9]+]]:gpr64 = LD [[DADDiu]], target-flags(mips-got-call) &__tls_get_addr :: (load (s64) from call-entry &__tls_get_addr)
- ; MIPS64-NEXT: $a0_64 = COPY [[DADDiu1]]
- ; MIPS64-NEXT: $gp_64 = COPY [[DADDiu]]
- ; MIPS64-NEXT: $t9_64 = COPY [[LD]]
- ; MIPS64-NEXT: JALR64Pseudo $t9_64, csr_n64, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $r2_64
- ; MIPS64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; MIPS64-NEXT: $r4_64 = COPY [[DADDiu1]]
+ ; MIPS64-NEXT: $r28_64 = COPY [[DADDiu]]
+ ; MIPS64-NEXT: $r25_64 = COPY [[LD]]
+ ; MIPS64-NEXT: JALR64Pseudo $r25_64, csr_n64, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $r31, implicit $r4_64, implicit $r28_64, implicit-def $r29, implicit-def $r2_64
+ ; MIPS64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
; MIPS64-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $r2_64
; MIPS64-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (dereferenceable load (s32) from @tls_gd)
- ; MIPS64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; MIPS64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit $r29
; MIPS64-NEXT: [[DADDiu2:%[0-9]+]]:gpr64 = DADDiu [[DADDiu]], target-flags(mips-tlsldm) @tls_ld
; MIPS64-NEXT: [[LD1:%[0-9]+]]:gpr64 = LD [[DADDiu]], target-flags(mips-got-call) &__tls_get_addr :: (load (s64) from call-entry &__tls_get_addr)
- ; MIPS64-NEXT: $a0_64 = COPY [[DADDiu2]]
- ; MIPS64-NEXT: dead $gp_64 = COPY [[DADDiu]]
- ; MIPS64-NEXT: $t9_64 = COPY [[LD1]]
- ; MIPS64-NEXT: JALR64Pseudo $t9_64, csr_n64, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2_64
- ; MIPS64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; MIPS64-NEXT: $r4_64 = COPY [[DADDiu2]]
+ ; MIPS64-NEXT: dead $r28_64 = COPY [[DADDiu]]
+ ; MIPS64-NEXT: $r25_64 = COPY [[LD1]]
+ ; MIPS64-NEXT: JALR64Pseudo $r25_64, csr_n64, target-flags(mips-jalr) <mcsymbol __tls_get_addr>, implicit-def dead $r31, implicit $r4_64, implicit-def $r29, implicit-def $r2_64
+ ; MIPS64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit $r29
; MIPS64-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $r2_64
; MIPS64-NEXT: [[LUi64_1:%[0-9]+]]:gpr64 = LUi64 target-flags(mips-dtprel-hi) @tls_ld
; MIPS64-NEXT: [[DADDu1:%[0-9]+]]:gpr64 = DADDu [[LUi64_1]], [[COPY1]]
diff --git a/llvm/test/CodeGen/Mips/setcc-se.ll b/llvm/test/CodeGen/Mips/setcc-se.ll
index 2ddce7855ecc2..6b93538fa603d 100644
--- a/llvm/test/CodeGen/Mips/setcc-se.ll
+++ b/llvm/test/CodeGen/Mips/setcc-se.ll
@@ -14,10 +14,10 @@ define i32 @seteq0(i32 %a) {
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: sltiu $2, $4, 1 # <MCInst #[[#MCINST1:]] SLTiu_MM
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Imm:1>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2:]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -34,10 +34,10 @@ define i32 @setne0(i32 %a) {
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: sltu $2, $zero, $4 # <MCInst #[[#MCINST3:]] SLTu_MM
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:ZERO>
-; MMR6-NEXT: # <MCOperand Reg:A0>>
+; MMR6-NEXT: # <MCOperand Reg:R0>
+; MMR6-NEXT: # <MCOperand Reg:R4>>
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -69,13 +69,13 @@ define void @slti_beq0(i32 %a) {
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6:]] ADDu
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:T9>>
+; MMR6-NEXT: # <MCOperand Reg:R25>>
; MMR6-NEXT: slti $1, $4, -32768 # <MCInst #[[#MCINST7:]] SLTi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Imm:-32768>>
; MMR6-NEXT: beqzc $1, $BB2_2 # <MCInst #[[#MCINST8:]] BEQZC_MMR6
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:$BB2_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9:]] LW_MM
@@ -83,12 +83,12 @@ define void @slti_beq0(i32 %a) {
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10:]] SW16_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB2_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
entry:
%cmp = icmp slt i32 %a, -32768
br i1 %cmp, label %if.then, label %if.end
@@ -128,20 +128,20 @@ define void @slti_beq1(i32 %a) {
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:T9>>
+; MMR6-NEXT: # <MCOperand Reg:R25>>
; MMR6-NEXT: lui $1, 65535 # <MCInst #[[#MCINST11:]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Imm:65535>>
; MMR6-NEXT: ori $1, $1, 32766 # <MCInst #[[#MCINST12:]] ORi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Imm:32766>>
; MMR6-NEXT: slt $1, $1, $4 # <MCInst #[[#MCINST13:]] SLT_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:A0>>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R4>>
; MMR6-NEXT: bnezc $1, $BB3_2 # <MCInst #[[#MCINST14:]] BNEZC_MMR6
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:$BB3_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
@@ -149,12 +149,12 @@ define void @slti_beq1(i32 %a) {
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB3_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
entry:
%cmp = icmp slt i32 %a, -32769
br i1 %cmp, label %if.then, label %if.end
@@ -192,13 +192,13 @@ define void @slti_beq2(i32 %a) {
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:T9>>
+; MMR6-NEXT: # <MCOperand Reg:R25>>
; MMR6-NEXT: slti $1, $4, 32767 # <MCInst #[[#MCINST7]] SLTi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Imm:32767>>
; MMR6-NEXT: beqzc $1, $BB4_2 # <MCInst #[[#MCINST8]] BEQZC_MMR6
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:$BB4_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
@@ -206,12 +206,12 @@ define void @slti_beq2(i32 %a) {
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB4_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
entry:
%cmp = icmp slt i32 %a, 32767
br i1 %cmp, label %if.then, label %if.end
@@ -250,17 +250,17 @@ define void @slti_beq3(i32 %a) {
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:T9>>
+; MMR6-NEXT: # <MCOperand Reg:R25>>
; MMR6-NEXT: addiu $1, $zero, 32767 # <MCInst #[[#MCINST15:]] ADDiu_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:ZERO>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R0>
; MMR6-NEXT: # <MCOperand Imm:32767>>
; MMR6-NEXT: slt $1, $1, $4 # <MCInst #[[#MCINST13]] SLT_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:A0>>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R4>>
; MMR6-NEXT: bnezc $1, $BB5_2 # <MCInst #[[#MCINST14]] BNEZC_MMR6
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:$BB5_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
@@ -268,12 +268,12 @@ define void @slti_beq3(i32 %a) {
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB5_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
entry:
%cmp = icmp slt i32 %a, 32768
br i1 %cmp, label %if.then, label %if.end
@@ -311,13 +311,13 @@ define void @sltiu_beq0(i32 %a) {
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:T9>>
+; MMR6-NEXT: # <MCOperand Reg:R25>>
; MMR6-NEXT: sltiu $1, $4, 32767 # <MCInst #[[#MCINST1]] SLTiu_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Imm:32767>>
; MMR6-NEXT: beqzc $1, $BB6_2 # <MCInst #[[#MCINST8]] BEQZC_MMR6
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:$BB6_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
@@ -325,12 +325,12 @@ define void @sltiu_beq0(i32 %a) {
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB6_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
entry:
%cmp = icmp ult i32 %a, 32767
br i1 %cmp, label %if.then, label %if.end
@@ -369,17 +369,17 @@ define void @sltiu_beq1(i32 %a) {
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:T9>>
+; MMR6-NEXT: # <MCOperand Reg:R25>>
; MMR6-NEXT: addiu $1, $zero, 32767 # <MCInst #[[#MCINST15]] ADDiu_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:ZERO>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R0>
; MMR6-NEXT: # <MCOperand Imm:32767>>
; MMR6-NEXT: sltu $1, $1, $4 # <MCInst #[[#MCINST3]] SLTu_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:A0>>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R4>>
; MMR6-NEXT: bnezc $1, $BB7_2 # <MCInst #[[#MCINST14]] BNEZC_MMR6
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:$BB7_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
@@ -387,12 +387,12 @@ define void @sltiu_beq1(i32 %a) {
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB7_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
entry:
%cmp = icmp ult i32 %a, 32768
br i1 %cmp, label %if.then, label %if.end
@@ -430,13 +430,13 @@ define void @sltiu_beq2(i32 %a) {
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:T9>>
+; MMR6-NEXT: # <MCOperand Reg:R25>>
; MMR6-NEXT: sltiu $1, $4, -32768 # <MCInst #[[#MCINST1]] SLTiu_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Imm:-32768>>
; MMR6-NEXT: beqzc $1, $BB8_2 # <MCInst #[[#MCINST8]] BEQZC_MMR6
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:$BB8_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
@@ -444,12 +444,12 @@ define void @sltiu_beq2(i32 %a) {
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB8_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
entry:
%cmp = icmp ult i32 %a, -32768
br i1 %cmp, label %if.then, label %if.end
@@ -489,20 +489,20 @@ define void @sltiu_beq3(i32 %a) {
; MMR6-NEXT: addu $2, $2, $25 # <MCInst #[[#MCINST6]] ADDu
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Reg:R2>
-; MMR6-NEXT: # <MCOperand Reg:T9>>
+; MMR6-NEXT: # <MCOperand Reg:R25>>
; MMR6-NEXT: lui $1, 65535 # <MCInst #[[#MCINST11]] LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Imm:65535>>
; MMR6-NEXT: ori $1, $1, 32766 # <MCInst #[[#MCINST12]] ORi_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Imm:32766>>
; MMR6-NEXT: sltu $1, $1, $4 # <MCInst #[[#MCINST3]] SLTu_MM
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:AT>
-; MMR6-NEXT: # <MCOperand Reg:A0>>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R1>
+; MMR6-NEXT: # <MCOperand Reg:R4>>
; MMR6-NEXT: bnezc $1, $BB9_2 # <MCInst #[[#MCINST14]] BNEZC_MMR6
-; MMR6-NEXT: # <MCOperand Reg:AT>
+; MMR6-NEXT: # <MCOperand Reg:R1>
; MMR6-NEXT: # <MCOperand Expr:$BB9_2>>
; MMR6-NEXT: # %bb.1: # %if.then
; MMR6-NEXT: lw $2, %got(g1)($2) # <MCInst #[[#MCINST9]] LW_MM
@@ -510,12 +510,12 @@ define void @sltiu_beq3(i32 %a) {
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Expr:%got(g1)>>
; MMR6-NEXT: sw16 $4, 0($2) # <MCInst #[[#MCINST10]] SW16_MM
-; MMR6-NEXT: # <MCOperand Reg:A0>
+; MMR6-NEXT: # <MCOperand Reg:R4>
; MMR6-NEXT: # <MCOperand Reg:R2>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: $BB9_2: # %if.end
; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST2]] JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:RA>>
+; MMR6-NEXT: # <MCOperand Reg:R31>>
entry:
%cmp = icmp ult i32 %a, -32769
br i1 %cmp, label %if.then, label %if.end
diff --git a/llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir b/llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
index d56524a604396..198e802db9b05 100644
--- a/llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
+++ b/llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
@@ -39,9 +39,9 @@ name: testBuildPairF64
# CHECK-NEXT: BuildPairF64
body: |
bb.0:
- $d0 = BuildPairF64 $zero, $zero
+ $d0 = BuildPairF64 $r0, $r0
bb.1:
- JAL @foo, implicit-def $ra
+ JAL @foo, implicit-def $r31
bb.2:
RetRA
...
@@ -55,9 +55,9 @@ name: testBuildPairF64_64
# CHECK-NEXT: BuildPairF64_64
body: |
bb.0:
- $d0_64 = BuildPairF64_64 $zero, $zero
+ $d0_64 = BuildPairF64_64 $r0, $r0
bb.1:
- JAL @foo, implicit-def $ra
+ JAL @foo, implicit-def $r31
bb.2:
RetRA
...
@@ -68,12 +68,12 @@ name: testBuildPairF64implicitSp
# CHECK-NEXT: successors
# CHECK-NEXT: liveins:
# CHECK-NEXT: {{[[:space:]]$}}
-# CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
+# CHECK-NEXT: $r29 = ADDiu $r29, -{{[0-9]+}}
body: |
bb.0:
- $d0 = BuildPairF64 $zero, $zero, implicit $sp
+ $d0 = BuildPairF64 $r0, $r0, implicit $r29
bb.1:
- JAL @foo, implicit-def $ra
+ JAL @foo, implicit-def $r31
bb.2:
RetRA
...
@@ -84,12 +84,12 @@ name: testBuildPairF64_64implicitSp
# CHECK-NEXT: successors
# CHECK-NEXT: liveins:
# CHECK-NEXT: {{[[:space:]]$}}
-# CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
+# CHECK-NEXT: $r29 = ADDiu $r29, -{{[0-9]+}}
body: |
bb.0:
- $d0_64 = BuildPairF64_64 $zero, $zero, implicit $sp
+ $d0_64 = BuildPairF64_64 $r0, $r0, implicit $r29
bb.1:
- JAL @foo, implicit-def $ra
+ JAL @foo, implicit-def $r31
bb.2:
RetRA
...
@@ -103,9 +103,9 @@ name: testExtractElementF64
# CHECK-NEXT: ExtractElementF64
body: |
bb.0:
- $at = ExtractElementF64 $d6, 1
+ $r1 = ExtractElementF64 $d6, 1
bb.1:
- JAL @foo, implicit-def $ra
+ JAL @foo, implicit-def $r31
bb.2:
RetRA
...
@@ -119,9 +119,9 @@ name: testExtractElementF64_64
# CHECK-NEXT: ExtractElementF64_64
body: |
bb.0:
- $at = ExtractElementF64_64 $d12_64, 1
+ $r1 = ExtractElementF64_64 $d12_64, 1
bb.1:
- JAL @foo, implicit-def $ra
+ JAL @foo, implicit-def $r31
bb.2:
RetRA
...
@@ -132,12 +132,12 @@ name: testExtractElementF64implicitSp
# CHECK-NEXT: successors
# CHECK-NEXT: liveins:
# CHECK-NEXT: {{[[:space:]]$}}
-# CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
+# CHECK-NEXT: $r29 = ADDiu $r29, -{{[0-9]+}}
body: |
bb.0:
- $at = ExtractElementF64 $d6, 1, implicit $sp
+ $r1 = ExtractElementF64 $d6, 1, implicit $r29
bb.1:
- JAL @foo, implicit-def $ra
+ JAL @foo, implicit-def $r31
bb.2:
RetRA
...
@@ -148,12 +148,12 @@ name: testExtractElementF64_64implicitSp
# CHECK-NEXT: successors
# CHECK-NEXT: liveins:
# CHECK-NEXT: {{[[:space:]]$}}
-# CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
+# CHECK-NEXT: $r29 = ADDiu $r29, -{{[0-9]+}}
body: |
bb.0:
- $at = ExtractElementF64_64 $d12_64, 1, implicit $sp
+ $r1 = ExtractElementF64_64 $d12_64, 1, implicit $r29
bb.1:
- JAL @foo, implicit-def $ra
+ JAL @foo, implicit-def $r31
bb.2:
RetRA
...
diff --git a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
index 53bf8302300a7..2313214b7ab75 100644
--- a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
+++ b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
@@ -17,7 +17,7 @@ selected: false
tracksRegLiveness: false
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -40,7 +40,7 @@ stack:
constants:
body: |
bb.0.entry:
- $zero = SLL_MMR6 killed $zero, 0
- JRC16_MMR6 undef $ra, implicit $r2
+ $r0 = SLL_MMR6 killed $r0, 0
+ JRC16_MMR6 undef $r31, implicit $r2
...
diff --git a/llvm/test/CodeGen/Mips/sll64_64-is-not-a-copy.mir b/llvm/test/CodeGen/Mips/sll64_64-is-not-a-copy.mir
index aa7ac7fc7b441..5efa21fef60ec 100644
--- a/llvm/test/CodeGen/Mips/sll64_64-is-not-a-copy.mir
+++ b/llvm/test/CodeGen/Mips/sll64_64-is-not-a-copy.mir
@@ -21,11 +21,11 @@ name: test
tracksRegLiveness: true
body: |
bb.0:
- liveins: $a0_64, $a1_64, $a2_64, $a3_64
- %109:gpr64 = COPY $a3_64
- %108:gpr64 = COPY $a2_64
- %107:gpr64 = COPY $a1_64
- %106:gpr64 = COPY $a0_64
+ liveins: $r4_64, $r5_64, $r6_64, $r7_64
+ %109:gpr64 = COPY $r7_64
+ %108:gpr64 = COPY $r6_64
+ %107:gpr64 = COPY $r5_64
+ %106:gpr64 = COPY $r4_64
%111:gpr32 = LUi 1023
%112:gpr32 = ORi %111, 65535
%3:gpr64 = LD %106, 16
@@ -39,34 +39,34 @@ body: |
%2:gpr64 = LD %106, 8
%0:gpr64 = LD %106, 0
%121:gpr32 = SLL %119, 1
- %271:gpr64 = DADDiu $zero_64, 0
+ %271:gpr64 = DADDiu $r0_64, 0
%6:gpr32 = ADDiu %121, 2
- %136:gpr64 = DADDiu $zero_64, 3
+ %136:gpr64 = DADDiu $r0_64, 3
%137:gpr64 = DSLL %136, 52
%138:gpr64 = AND64 %0, %137
- %139:gpr64 = DADDiu $zero_64, 13107
+ %139:gpr64 = DADDiu $r0_64, 13107
%140:gpr64 = DSLL %139, 18
%141:gpr64 = DADDiu %140, 768
%142:gpr64 = AND64 %0, %141
- %143:gpr64 = DADDiu $zero_64, 8211
+ %143:gpr64 = DADDiu $r0_64, 8211
%144:gpr64 = DSLL %143, 18
%145:gpr64 = DADDiu %144, 512
%146:gpr64 = DSRL %3, 51
%148:gpr32 = nuw nsw SLL %146.sub_32, 0
- %153:gpr64 = DADDiu $zero_64, 1
+ %153:gpr64 = DADDiu $r0_64, 1
%154:gpr64 = DSLL %153, 55
- %155:gpr64 = DADDiu $zero_64, -4
+ %155:gpr64 = DADDiu $r0_64, -4
%215:gpr64 = LUi64 3
%216:gpr64 = ORi64 %215, 65535
- J %bb.2, implicit-def dead $at
+ J %bb.2, implicit-def dead $r1
bb.1:
RetRA
bb.2:
%124:gpr64 = nuw nsw DSLL %271, 3
%11:gpr64 = nuw DADDu %107, %124
%12:gpr64 = LD %11, 0
- BNE64 %138, $zero_64, %bb.97, implicit-def dead $at
- BNE64 %142, %145, %bb.96, implicit-def dead $at
+ BNE64 %138, $r0_64, %bb.97, implicit-def dead $r1
+ BNE64 %142, %145, %bb.96, implicit-def dead $r1
bb.11:
%149:gpr32 = ANDi %148, 2
%151:gpr32 = SLL %12.sub_32, 0
@@ -104,7 +104,7 @@ body: |
%256:gpr32 = ADDu %7, %255
%258:gpr32 = SLL %283.sub_32, 1
%24:gpr64 = DADDu %24, %38
- BNE %56, %35, %bb.40, implicit-def $at
+ BNE %56, %35, %bb.40, implicit-def $r1
bb.40:
%59:gpr32 = exact SRA %56, 2
%290:gpr64 = COPY %58
@@ -120,15 +120,15 @@ body: |
%311:gpr64 = COPY %58
%312:gpr64 = COPY %57
%180:gpr32 = SLT64 %312, %311
- BEQ %180, $zero, %bb.87, implicit-def dead $at
+ BEQ %180, $r0, %bb.87, implicit-def dead $r1
bb.86:
%58:gpr64 = DADDu %58, %33
%57:gpr64 = DADDu %57, %26
- BNE %56, %34, %bb.58, implicit-def $at
+ BNE %56, %34, %bb.58, implicit-def $r1
bb.87:
%313:gpr64 = COPY %30
bb.96:
bb.97:
%267:gpr32 = samesign SLTu64 %271, %108
- BNE %267, $zero, %bb.2, implicit-def dead $at
- J %bb.1, implicit-def dead $at
\ No newline at end of file
+ BNE %267, $r0, %bb.2, implicit-def dead $r1
+ J %bb.1, implicit-def dead $r1
\ No newline at end of file
diff --git a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
index b198ced3fb225..bab32ee7a6686 100644
--- a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
+++ b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
@@ -28,8 +28,8 @@ selected: false
failedISel: false
tracksRegLiveness: true
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
- - { reg: '$a1', virtual-reg: '%1' }
+ - { reg: '$r4', virtual-reg: '%0' }
+ - { reg: '$r5', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -52,10 +52,10 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
- %1:gpr32 = COPY $a1
- %0:gpr32 = COPY $a0
+ %1:gpr32 = COPY $r5
+ %0:gpr32 = COPY $r4
%3:gpr32 = IMPLICIT_DEF
%2:gpr32 = LWL %0, 0, %3 :: (load (s32) from %ir.a, align 1)
%4:gpr32 = LWR %0, 3, %2 :: (load (s32) from %ir.a, align 1)
@@ -74,8 +74,8 @@ selected: false
failedISel: false
tracksRegLiveness: true
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
- - { reg: '$a1', virtual-reg: '%1' }
+ - { reg: '$r4', virtual-reg: '%0' }
+ - { reg: '$r5', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -98,10 +98,10 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: $a0, $a1
+ liveins: $r4, $r5
- %1:gpr32 = COPY $a1
- %0:gpr32 = COPY $a0
+ %1:gpr32 = COPY $r5
+ %0:gpr32 = COPY $r4
%3:gpr32 = IMPLICIT_DEF
%2:gpr32 = LWLE %0, 0, %3 :: (load (s32) from %ir.a, align 1)
%4:gpr32 = LWRE %0, 3, %2 :: (load (s32) from %ir.a, align 1)
diff --git a/llvm/test/CodeGen/Mips/unaligned-memops.ll b/llvm/test/CodeGen/Mips/unaligned-memops.ll
index caaa212a40cd5..ad96a4079eb30 100644
--- a/llvm/test/CodeGen/Mips/unaligned-memops.ll
+++ b/llvm/test/CodeGen/Mips/unaligned-memops.ll
@@ -8,9 +8,9 @@
define void @g2(ptr %a, ptr %b) {
; MIPS-LABEL: name: g2
; MIPS: bb.0.entry:
- ; MIPS: liveins: $a0, $a1
- ; MIPS: [[COPY:%[0-9]+]]:gpr32 = COPY $a1
- ; MIPS: [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS: liveins: $r4, $r5
+ ; MIPS: [[COPY:%[0-9]+]]:gpr32 = COPY $r5
+ ; MIPS: [[COPY1:%[0-9]+]]:gpr32 = COPY $r4
; MIPS: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; MIPS: [[LWL:%[0-9]+]]:gpr32 = LWL [[COPY1]], 0, [[DEF]] :: (load (s32) from %ir.a, align 1)
; MIPS: [[LWR:%[0-9]+]]:gpr32 = LWR [[COPY1]], 3, [[LWL]] :: (load (s32) from %ir.a, align 1)
@@ -19,9 +19,9 @@ define void @g2(ptr %a, ptr %b) {
; MIPS: RetRA
; MICROMIPS-LABEL: name: g2
; MICROMIPS: bb.0.entry:
- ; MICROMIPS: liveins: $a0, $a1
- ; MICROMIPS: [[COPY:%[0-9]+]]:gpr32 = COPY $a1
- ; MICROMIPS: [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
+ ; MICROMIPS: liveins: $r4, $r5
+ ; MICROMIPS: [[COPY:%[0-9]+]]:gpr32 = COPY $r5
+ ; MICROMIPS: [[COPY1:%[0-9]+]]:gpr32 = COPY $r4
; MICROMIPS: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; MICROMIPS: [[LWL_MM:%[0-9]+]]:gpr32 = LWL_MM [[COPY1]], 0, [[DEF]] :: (load (s32) from %ir.a, align 1)
; MICROMIPS: [[LWR_MM:%[0-9]+]]:gpr32 = LWR_MM [[COPY1]], 3, [[LWL_MM]] :: (load (s32) from %ir.a, align 1)
diff --git a/llvm/test/DebugInfo/MIR/Mips/call-site-info-update-delay-slot-filler.mir b/llvm/test/DebugInfo/MIR/Mips/call-site-info-update-delay-slot-filler.mir
index d450ee8428464..141fd9f726664 100644
--- a/llvm/test/DebugInfo/MIR/Mips/call-site-info-update-delay-slot-filler.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/call-site-info-update-delay-slot-filler.mir
@@ -61,23 +61,23 @@ name: machine_power_off
alignment: 4
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:
- { bb: 0, offset: 6, fwdArgRegs: [] }
body: |
bb.0.entry:
- liveins: $ra
+ liveins: $r31
- $sp = ADDiu $sp, -24
+ $r29 = ADDiu $r29, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- CFI_INSTRUCTION offset $ra_64, -4
- renamable $at = LUi target-flags(mips-abs-hi) @pm_power_off, debug-location !17
- renamable $t9 = LW killed renamable $at, target-flags(mips-abs-lo) @pm_power_off, debug-location !17 :: (dereferenceable load (s32) from `i32 ()** bitcast (i32 (...)** @pm_power_off to i32 ()**)`)
- JALRPseudo $t9, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit-def dead $r2, debug-location !17
- $ra = LW $sp, 20, debug-location !17 :: (load (s32) from %stack.0)
- $sp = ADDiu $sp, 24
- PseudoReturn undef $ra, implicit undef $r2, debug-location !17
+ SW killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ CFI_INSTRUCTION offset $r31_64, -4
+ renamable $r1 = LUi target-flags(mips-abs-hi) @pm_power_off, debug-location !17
+ renamable $r25 = LW killed renamable $r1, target-flags(mips-abs-lo) @pm_power_off, debug-location !17 :: (dereferenceable load (s32) from `i32 ()** bitcast (i32 (...)** @pm_power_off to i32 ()**)`)
+ JALRPseudo $r25, csr_o32_fp64, implicit-def dead $r31, implicit-def $r29, implicit-def dead $r2, debug-location !17
+ $r31 = LW $r29, 20, debug-location !17 :: (load (s32) from %stack.0)
+ $r29 = ADDiu $r29, 24
+ PseudoReturn undef $r31, implicit undef $r2, debug-location !17
...
diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir
index 42dfa5901cbdc..145793a7908d9 100644
--- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir
@@ -12,17 +12,17 @@
#CHECK-NEXT: DW_AT_abstract_origin {{.*}} "foo"
#CHECK: DW_TAG_GNU_call_site_parameter
-#CHECK-NEXT: DW_AT_location (DW_OP_reg6 A2_64)
+#CHECK-NEXT: DW_AT_location (DW_OP_reg6 R6_64)
#CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_lit0)
#CHECK-EMPTY:
#CHECK-NEXT: DW_TAG_GNU_call_site_parameter
-#CHECK-NEXT: DW_AT_location (DW_OP_reg4 A0_64)
-#CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg5 A1_64))
+#CHECK-NEXT: DW_AT_location (DW_OP_reg4 R4_64)
+#CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg5 R5_64))
#CHECK-EMPTY:
## The parameter, which value is loaded by COPY instr using sub-register, should be omitted.
#CHECK-NOT: DW_TAG_GNU_call_site_parameter
-#CHECK-NOT: DW_AT_location (DW_OP_reg5 A1_64)
-#CHECK-NOT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg4 A0_64))
+#CHECK-NOT: DW_AT_location (DW_OP_reg5 R5_64)
+#CHECK-NOT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg4 R4_64))
--- |
; ModuleID = 'm.ll'
source_filename = "m.c"
@@ -76,34 +76,34 @@ name: f1
alignment: 8
stack:
- { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '$ra_64', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:
- { bb: 0, offset: 12, fwdArgRegs:
- - { arg: 0, reg: '$a0_64' }
- - { arg: 1, reg: '$a1' }
- - { arg: 2, reg: '$a2' } }
+ - { arg: 0, reg: '$r4_64' }
+ - { arg: 1, reg: '$r5' }
+ - { arg: 2, reg: '$r6' } }
body: |
bb.0.entry:
- DBG_VALUE $a0_64, $noreg, !16, !DIExpression(), debug-location !18
- DBG_VALUE $a1_64, $noreg, !17, !DIExpression(), debug-location !18
- $sp_64 = DADDiu $sp_64, -16
+ DBG_VALUE $r4_64, $noreg, !16, !DIExpression(), debug-location !18
+ DBG_VALUE $r5_64, $noreg, !17, !DIExpression(), debug-location !18
+ $r29_64 = DADDiu $r29_64, -16
CFI_INSTRUCTION def_cfa_offset 16
- SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
- CFI_INSTRUCTION offset $ra_64, -8
- $at_64 = OR64 $a0_64, $zero_64
- DBG_VALUE $a1_64, $noreg, !17, !DIExpression(), debug-location !18
- DBG_VALUE $at_64, $noreg, !16, !DIExpression(), debug-location !18
- $a0_64 = OR64 killed $a1_64, $zero_64, debug-location !18
- DBG_VALUE $a0_64, $noreg, !17, !DIExpression(), debug-location !18
- $a1 = OR $at, $zero, implicit killed $at_64, debug-location !18
- JAL @foo, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1, implicit killed $a2, implicit-def $sp, implicit-def $r2, debug-location !18 {
- $a2 = ADDiu $zero, 0, debug-location !18
+ SD killed $r31_64, $r29_64, 8 :: (store (s64) into %stack.0)
+ CFI_INSTRUCTION offset $r31_64, -8
+ $r1_64 = OR64 $r4_64, $r0_64
+ DBG_VALUE $r5_64, $noreg, !17, !DIExpression(), debug-location !18
+ DBG_VALUE $r1_64, $noreg, !16, !DIExpression(), debug-location !18
+ $r4_64 = OR64 killed $r5_64, $r0_64, debug-location !18
+ DBG_VALUE $r4_64, $noreg, !17, !DIExpression(), debug-location !18
+ $r5 = OR $r1, $r0, implicit killed $r1_64, debug-location !18
+ JAL @foo, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r5, implicit killed $r6, implicit-def $r29, implicit-def $r2, debug-location !18 {
+ $r6 = ADDiu $r0, 0, debug-location !18
}
renamable $r2_64 = SLL64_32 killed renamable $r2, debug-location !18
- $ra_64 = LD $sp_64, 8, debug-location !18 :: (load (s64) from %stack.0)
- PseudoReturn64 undef $ra_64, implicit $r2_64, debug-location !18 {
- $sp_64 = DADDiu $sp_64, 16
+ $r31_64 = LD $r29_64, 8, debug-location !18 :: (load (s64) from %stack.0)
+ PseudoReturn64 undef $r31_64, implicit $r2_64, debug-location !18 {
+ $r29_64 = DADDiu $r29_64, 16
}
...
diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir
index 085935b589c98..89db8ba4be180 100644
--- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir
@@ -21,12 +21,12 @@
# CHECK-EMPTY:
## Parameter forwarding register A1_64 is set in call delay slot.
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT: DW_AT_location (DW_OP_reg5 A1_64)
-# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg17 S1_64+0)
+# CHECK-NEXT: DW_AT_location (DW_OP_reg5 R5_64)
+# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg17 R17_64+0)
# CHECK-EMPTY:
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT: DW_AT_location (DW_OP_reg4 A0_64)
-# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg17 S1_64+0)
+# CHECK-NEXT: DW_AT_location (DW_OP_reg4 R4_64)
+# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg17 R17_64+0)
--- |
; ModuleID = 'm.ll'
@@ -83,47 +83,47 @@ name: set
alignment: 8
stack:
- { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '$ra_64', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '$s1_64', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r17_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '$s0_64', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:
- { bb: 0, offset: 17, fwdArgRegs:
- - { arg: 0, reg: '$a0_64' }
- - { arg: 1, reg: '$a1_64' } }
+ - { arg: 0, reg: '$r4_64' }
+ - { arg: 1, reg: '$r5_64' } }
body: |
bb.0.entry:
- DBG_VALUE $a0_64, $noreg, !18, !DIExpression(), debug-location !20
- DBG_VALUE $a1_64, $noreg, !19, !DIExpression(), debug-location !20
- DBG_VALUE $a1_64, $noreg, !19, !DIExpression(), debug-location !20
- $sp_64 = DADDiu $sp_64, -32
+ DBG_VALUE $r4_64, $noreg, !18, !DIExpression(), debug-location !20
+ DBG_VALUE $r5_64, $noreg, !19, !DIExpression(), debug-location !20
+ DBG_VALUE $r5_64, $noreg, !19, !DIExpression(), debug-location !20
+ $r29_64 = DADDiu $r29_64, -32
CFI_INSTRUCTION def_cfa_offset 32
- SD killed $ra_64, $sp_64, 24 :: (store (s64) into %stack.0)
- SD killed $s1_64, $sp_64, 16 :: (store (s64) into %stack.1)
- SD killed $s0_64, $sp_64, 8 :: (store (s64) into %stack.2)
- CFI_INSTRUCTION offset $ra_64, -8
- CFI_INSTRUCTION offset $s1_64, -16
- CFI_INSTRUCTION offset $s0_64, -24
- $s0_64 = OR64 $a0_64, $zero_64
- DBG_VALUE $a1, $noreg, !19, !DIExpression(), debug-location !20
- DBG_VALUE $s0_64, $noreg, !18, !DIExpression(), debug-location !20
- renamable $s1 = ADDiu renamable $a1, 1, implicit killed $a1_64, implicit-def $s1_64, debug-location !20
- DBG_VALUE $s1, $noreg, !19, !DIExpression(), debug-location !20
- $a0_64 = OR64 $s1_64, $zero_64, debug-location !20
- JAL @sum, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1_64, implicit-def $sp, implicit-def $r2, debug-location !20 {
- $a1_64 = OR64 $s1_64, $zero_64, debug-location !20
+ SD killed $r31_64, $r29_64, 24 :: (store (s64) into %stack.0)
+ SD killed $r17_64, $r29_64, 16 :: (store (s64) into %stack.1)
+ SD killed $r16_64, $r29_64, 8 :: (store (s64) into %stack.2)
+ CFI_INSTRUCTION offset $r31_64, -8
+ CFI_INSTRUCTION offset $r17_64, -16
+ CFI_INSTRUCTION offset $r16_64, -24
+ $r16_64 = OR64 $r4_64, $r0_64
+ DBG_VALUE $r5, $noreg, !19, !DIExpression(), debug-location !20
+ DBG_VALUE $r16_64, $noreg, !18, !DIExpression(), debug-location !20
+ renamable $r17 = ADDiu renamable $r5, 1, implicit killed $r5_64, implicit-def $r17_64, debug-location !20
+ DBG_VALUE $r17, $noreg, !19, !DIExpression(), debug-location !20
+ $r4_64 = OR64 $r17_64, $r0_64, debug-location !20
+ JAL @sum, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit $r5_64, implicit-def $r29, implicit-def $r2, debug-location !20 {
+ $r5_64 = OR64 $r17_64, $r0_64, debug-location !20
}
- renamable $at = nsw ADDu killed renamable $r2, renamable $s1, implicit killed $s1_64, debug-location !20
- SW killed renamable $at, killed renamable $s0_64, 0
- $s0_64 = LD $sp_64, 8
- $s1_64 = LD $sp_64, 16
- $ra_64 = LD $sp_64, 24
- PseudoReturn64 undef $ra_64 {
- $sp_64 = DADDiu $sp_64, 32
+ renamable $r1 = nsw ADDu killed renamable $r2, renamable $r17, implicit killed $r17_64, debug-location !20
+ SW killed renamable $r1, killed renamable $r16_64, 0
+ $r16_64 = LD $r29_64, 8
+ $r17_64 = LD $r29_64, 16
+ $r31_64 = LD $r29_64, 24
+ PseudoReturn64 undef $r31_64 {
+ $r29_64 = DADDiu $r29_64, 32
}
...
diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir
index ed2e8c6c96c31..996c7982835b4 100644
--- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir
@@ -21,12 +21,12 @@
# CHECK-EMPTY:
## Parameter forwarding register A1_64 is set in call delay slot.
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT: DW_AT_location (DW_OP_reg5 A1_64)
-# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg17 S1_64+0)
+# CHECK-NEXT: DW_AT_location (DW_OP_reg5 R5_64)
+# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg17 R17_64+0)
# CHECK-EMPTY:
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT: DW_AT_location (DW_OP_reg4 A0_64)
-# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg17 S1_64+0)
+# CHECK-NEXT: DW_AT_location (DW_OP_reg4 R4_64)
+# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg17 R17_64+0)
--- |
; ModuleID = 'm.ll'
@@ -80,47 +80,47 @@ name: set
alignment: 4
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s1', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r17', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:
- { bb: 0, offset: 16, fwdArgRegs:
- - { arg: 0, reg: '$a0' }
- - { arg: 1, reg: '$a1' } }
+ - { arg: 0, reg: '$r4' }
+ - { arg: 1, reg: '$r5' } }
body: |
bb.0.entry:
- DBG_VALUE $a0, $noreg, !17, !DIExpression(), debug-location !19
- DBG_VALUE $a1, $noreg, !18, !DIExpression(), debug-location !19
- DBG_VALUE $a1, $noreg, !18, !DIExpression(), debug-location !19
- $sp = ADDiu $sp, -32
+ DBG_VALUE $r4, $noreg, !17, !DIExpression(), debug-location !19
+ DBG_VALUE $r5, $noreg, !18, !DIExpression(), debug-location !19
+ DBG_VALUE $r5, $noreg, !18, !DIExpression(), debug-location !19
+ $r29 = ADDiu $r29, -32
CFI_INSTRUCTION def_cfa_offset 32
- SW killed $ra, $sp, 28 :: (store (s32) into %stack.0)
- SW killed $s1, $sp, 24 :: (store (s32) into %stack.1)
- SW killed $s0, $sp, 20 :: (store (s32) into %stack.2)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s1_64, -8
- CFI_INSTRUCTION offset $s0_64, -12
- $s0 = OR $a0, $zero
- DBG_VALUE $s0, $noreg, !17, !DIExpression(), debug-location !19
- renamable $s1 = nsw ADDiu killed renamable $a1, 1, debug-location !19
- DBG_VALUE $s1, $noreg, !18, !DIExpression(), debug-location !19
- $a0 = OR $s1, $zero, debug-location !19
- JAL @sum, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, implicit-def $r2, debug-location !19 {
- $a1 = OR $s1, $zero, debug-location !19
+ SW killed $r31, $r29, 28 :: (store (s32) into %stack.0)
+ SW killed $r17, $r29, 24 :: (store (s32) into %stack.1)
+ SW killed $r16, $r29, 20 :: (store (s32) into %stack.2)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r17_64, -8
+ CFI_INSTRUCTION offset $r16_64, -12
+ $r16 = OR $r4, $r0
+ DBG_VALUE $r16, $noreg, !17, !DIExpression(), debug-location !19
+ renamable $r17 = nsw ADDiu killed renamable $r5, 1, debug-location !19
+ DBG_VALUE $r17, $noreg, !18, !DIExpression(), debug-location !19
+ $r4 = OR $r17, $r0, debug-location !19
+ JAL @sum, csr_o32, implicit-def dead $r31, implicit $r4, implicit $r5, implicit-def $r29, implicit-def $r2, debug-location !19 {
+ $r5 = OR $r17, $r0, debug-location !19
}
- renamable $at = nsw ADDu killed renamable $r2, killed renamable $s1, debug-location !19
- SW killed renamable $at, killed renamable $s0, 0, debug-location !19 :: (store (s32) into %ir.adr)
- $s0 = LW $sp, 20
- DBG_VALUE $a0, $noreg, !17, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !19
- $s1 = LW $sp, 24
- $ra = LW $sp, 28
- PseudoReturn undef $ra {
- $sp = ADDiu $sp, 32
+ renamable $r1 = nsw ADDu killed renamable $r2, killed renamable $r17, debug-location !19
+ SW killed renamable $r1, killed renamable $r16, 0, debug-location !19 :: (store (s32) into %ir.adr)
+ $r16 = LW $r29, 20
+ DBG_VALUE $r4, $noreg, !17, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !19
+ $r17 = LW $r29, 24
+ $r31 = LW $r29, 28
+ PseudoReturn undef $r31 {
+ $r29 = ADDiu $r29, 32
}
...
diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir
index a3936d715b04f..d991a8c6125de 100644
--- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir
@@ -21,16 +21,16 @@
# CHECK: DW_TAG_GNU_call_site
# CHECK-NEXT: DW_AT_abstract_origin {{.*}} "fn1"
# CHECK: DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT: DW_AT_location (DW_OP_reg5 A1_64)
-# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg16 S0_64+0)
+# CHECK-NEXT: DW_AT_location (DW_OP_reg5 R5_64)
+# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg16 R16_64+0)
# CHECK-EMPTY:
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT: DW_AT_location (DW_OP_reg4 A0_64)
+# CHECK-NEXT: DW_AT_location (DW_OP_reg4 R4_64)
# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_constu 0x2c)
# CHECK-EMPTY:
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT: DW_AT_location (DW_OP_reg6 A2_64)
-# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg16 S0_64+10)
+# CHECK-NEXT: DW_AT_location (DW_OP_reg6 R6_64)
+# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg16 R16_64+10)
--- |
; ModuleID = 'mips64.ll'
source_filename = "m64.c"
@@ -91,45 +91,45 @@
name: fn2
alignment: 8
liveins:
- - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$r4_64', virtual-reg: '' }
stack:
- { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '$ra_64', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '$s0_64', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:
- { bb: 0, offset: 8, fwdArgRegs: [] }
- { bb: 0, offset: 12, fwdArgRegs:
- - { arg: 0, reg: '$a0_64' }
- - { arg: 1, reg: '$a1_64' }
- - { arg: 2, reg: '$a2_64' } }
+ - { arg: 0, reg: '$r4_64' }
+ - { arg: 1, reg: '$r5_64' }
+ - { arg: 2, reg: '$r6_64' } }
body: |
bb.0.entry:
- DBG_VALUE $a0_64, $noreg, !18, !DIExpression(), debug-location !20
- $sp_64 = DADDiu $sp_64, -16
+ DBG_VALUE $r4_64, $noreg, !18, !DIExpression(), debug-location !20
+ $r29_64 = DADDiu $r29_64, -16
CFI_INSTRUCTION def_cfa_offset 16
- SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
- SD killed $s0_64, $sp_64, 0 :: (store (s64) into %stack.1)
- CFI_INSTRUCTION offset $ra_64, -8
- CFI_INSTRUCTION offset $s0_64, -16
- DBG_VALUE $s0_64, $noreg, !18, !DIExpression(), debug-location !20
- JAL @clobber, csr_n64, implicit-def dead $ra, implicit-def $sp, debug-location !20 {
- $s0_64 = OR64 $a0_64, $zero_64
+ SD killed $r31_64, $r29_64, 8 :: (store (s64) into %stack.0)
+ SD killed $r16_64, $r29_64, 0 :: (store (s64) into %stack.1)
+ CFI_INSTRUCTION offset $r31_64, -8
+ CFI_INSTRUCTION offset $r16_64, -16
+ DBG_VALUE $r16_64, $noreg, !18, !DIExpression(), debug-location !20
+ JAL @clobber, csr_n64, implicit-def dead $r31, implicit-def $r29, debug-location !20 {
+ $r16_64 = OR64 $r4_64, $r0_64
}
- renamable $a2_64 = nsw DADDiu renamable $s0_64, 10, debug-location !20
- $a0_64 = DADDiu $zero_64, 44, debug-location !20
- JAL @fn1, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit killed $a1_64, implicit $a2_64, implicit-def $sp, implicit-def $r2, debug-location !20 {
- $a1_64 = OR64 killed $s0_64, $zero_64, debug-location !20
+ renamable $r6_64 = nsw DADDiu renamable $r16_64, 10, debug-location !20
+ $r4_64 = DADDiu $r0_64, 44, debug-location !20
+ JAL @fn1, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit killed $r5_64, implicit $r6_64, implicit-def $r29, implicit-def $r2, debug-location !20 {
+ $r5_64 = OR64 killed $r16_64, $r0_64, debug-location !20
}
DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !20
- renamable $at = SLTi renamable $r2, 11, debug-location !20
+ renamable $r1 = SLTi renamable $r2, 11, debug-location !20
renamable $r3 = nsw ADDiu renamable $r2, 10, debug-location !20
- renamable $r2 = MOVZ_I_I killed renamable $r3, killed renamable $at, killed renamable $r2, debug-location !20
+ renamable $r2 = MOVZ_I_I killed renamable $r3, killed renamable $r1, killed renamable $r2, debug-location !20
renamable $r2_64 = SLL64_32 killed renamable $r2, debug-location !20
- $s0_64 = LD $sp_64, 0, debug-location !20 :: (load (s64) from %stack.1)
- $ra_64 = LD $sp_64, 8, debug-location !20 :: (load (s64) from %stack.0)
- PseudoReturn64 undef $ra_64, implicit $r2_64, debug-location !20 {
- $sp_64 = DADDiu $sp_64, 16
+ $r16_64 = LD $r29_64, 0, debug-location !20 :: (load (s64) from %stack.1)
+ $r31_64 = LD $r29_64, 8, debug-location !20 :: (load (s64) from %stack.0)
+ PseudoReturn64 undef $r31_64, implicit $r2_64, debug-location !20 {
+ $r29_64 = DADDiu $r29_64, 16
}
diff --git a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir
index 624538489704c..5b3f7c7c16a67 100644
--- a/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir
@@ -21,16 +21,16 @@
# CHECK: DW_TAG_GNU_call_site
# CHECK-NEXT: DW_AT_abstract_origin {{.*}} "fn1"
# CHECK: DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT: DW_AT_location (DW_OP_reg5 A1_64)
-# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg16 S0_64+0)
+# CHECK-NEXT: DW_AT_location (DW_OP_reg5 R5_64)
+# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg16 R16_64+0)
# CHECK-EMPTY:
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT: DW_AT_location (DW_OP_reg4 A0_64)
+# CHECK-NEXT: DW_AT_location (DW_OP_reg4 R4_64)
# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_constu 0x2c)
# CHECK-EMPTY:
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT: DW_AT_location (DW_OP_reg6 A2_64)
-# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg16 S0_64+10)
+# CHECK-NEXT: DW_AT_location (DW_OP_reg6 R6_64)
+# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg16 R16_64+10)
--- |
; ModuleID = 'm.ll'
source_filename = "m.c"
@@ -89,44 +89,44 @@
name: fn2
alignment: 4
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:
- { bb: 0, offset: 8, fwdArgRegs: [] }
- { bb: 0, offset: 12, fwdArgRegs:
- - { arg: 0, reg: '$a0' }
- - { arg: 1, reg: '$a1' }
- - { arg: 2, reg: '$a2' } }
+ - { arg: 0, reg: '$r4' }
+ - { arg: 1, reg: '$r5' }
+ - { arg: 2, reg: '$r6' } }
body: |
bb.0.entry:
- DBG_VALUE $a0, $noreg, !16, !DIExpression(), debug-location !18
- $sp = ADDiu $sp, -24
+ DBG_VALUE $r4, $noreg, !16, !DIExpression(), debug-location !18
+ $r29 = ADDiu $r29, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
- SW killed $s0, $sp, 16 :: (store (s32) into %stack.1)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s0_64, -8
- DBG_VALUE $s0, $noreg, !16, !DIExpression(), debug-location !18
- JAL @clobber, csr_o32, implicit-def dead $ra, implicit-def $sp, debug-location !18 {
- $s0 = OR $a0, $zero
+ SW killed $r31, $r29, 20 :: (store (s32) into %stack.0)
+ SW killed $r16, $r29, 16 :: (store (s32) into %stack.1)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r16_64, -8
+ DBG_VALUE $r16, $noreg, !16, !DIExpression(), debug-location !18
+ JAL @clobber, csr_o32, implicit-def dead $r31, implicit-def $r29, debug-location !18 {
+ $r16 = OR $r4, $r0
}
- renamable $a2 = nsw ADDiu renamable $s0, 10, debug-location !18
- $a0 = ADDiu $zero, 44, debug-location !18
- JAL @fn1, csr_o32, implicit-def dead $ra, implicit $a0, implicit killed $a1, implicit $a2, implicit-def $sp, implicit-def $r2, debug-location !18 {
- $a1 = OR killed $s0, $zero, debug-location !18
+ renamable $r6 = nsw ADDiu renamable $r16, 10, debug-location !18
+ $r4 = ADDiu $r0, 44, debug-location !18
+ JAL @fn1, csr_o32, implicit-def dead $r31, implicit $r4, implicit killed $r5, implicit $r6, implicit-def $r29, implicit-def $r2, debug-location !18 {
+ $r5 = OR killed $r16, $r0, debug-location !18
}
DBG_VALUE $r2, $noreg, !17, !DIExpression(), debug-location !18
- renamable $at = SLTi renamable $r2, 11, debug-location !18
+ renamable $r1 = SLTi renamable $r2, 11, debug-location !18
renamable $r3 = nsw ADDiu renamable $r2, 10, debug-location !18
- renamable $r2 = MOVZ_I_I killed renamable $r3, killed renamable $at, killed renamable $r2, debug-location !18
- $s0 = LW $sp, 16, debug-location !18 :: (load (s32) from %stack.1)
- $ra = LW $sp, 20, debug-location !18 :: (load (s32) from %stack.0)
- PseudoReturn undef $ra, implicit $r2, debug-location !18 {
- $sp = ADDiu $sp, 24
+ renamable $r2 = MOVZ_I_I killed renamable $r3, killed renamable $r1, killed renamable $r2, debug-location !18
+ $r16 = LW $r29, 16, debug-location !18 :: (load (s32) from %stack.1)
+ $r31 = LW $r29, 20, debug-location !18 :: (load (s32) from %stack.0)
+ PseudoReturn undef $r31, implicit $r2, debug-location !18 {
+ $r29 = ADDiu $r29, 24
}
diff --git a/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir b/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
index b721443263723..84b734d4b3a97 100644
--- a/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
@@ -21,7 +21,7 @@
#
# Check that last bundled instruction of block gets recognized as end of basic block.
# CHECK: bb.2.if.end
-# CHECK-NEXT: DBG_VALUE $s0, $noreg, !12, !DIExpression()
+# CHECK-NEXT: DBG_VALUE $r16, $noreg, !12, !DIExpression()
--- |
; ModuleID = '<stdin>'
@@ -118,7 +118,7 @@ selected: false
tracksRegLiveness: false
registers:
liveins:
- - { reg: '$a0', virtual-reg: '' }
+ - { reg: '$r4', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -143,11 +143,11 @@ stack:
debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
constants:
@@ -155,37 +155,37 @@ body: |
bb.0.entry:
successors: %bb.2(0x30000000), %bb.1(0x50000000)
- $sp = ADDiu $sp, -32
+ $r29 = ADDiu $r29, -32
CFI_INSTRUCTION def_cfa_offset 32
- SW killed $ra, $sp, 28 :: (store (s32) into %stack.1)
- SW killed $s0, $sp, 24 :: (store (s32) into %stack.2)
- CFI_INSTRUCTION offset $ra_64, -4
- CFI_INSTRUCTION offset $s0_64, -8
- DBG_VALUE $a0, $noreg, !12, !DIExpression(), debug-location !17
- $s0 = OR $a0, $zero
- DBG_VALUE $s0, $noreg, !12, !DIExpression(), debug-location !17
- DBG_VALUE $sp, 0, !13, !DIExpression(DW_OP_plus_uconst, 20), debug-location !19
- JAL @set_cond, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit-def $sp, debug-location !20 {
- renamable $a1 = LEA_ADDiu $sp, 20
+ SW killed $r31, $r29, 28 :: (store (s32) into %stack.1)
+ SW killed $r16, $r29, 24 :: (store (s32) into %stack.2)
+ CFI_INSTRUCTION offset $r31_64, -4
+ CFI_INSTRUCTION offset $r16_64, -8
+ DBG_VALUE $r4, $noreg, !12, !DIExpression(), debug-location !17
+ $r16 = OR $r4, $r0
+ DBG_VALUE $r16, $noreg, !12, !DIExpression(), debug-location !17
+ DBG_VALUE $r29, 0, !13, !DIExpression(DW_OP_plus_uconst, 20), debug-location !19
+ JAL @set_cond, csr_o32, implicit-def dead $r31, implicit $r4, implicit $r5, implicit-def $r29, debug-location !20 {
+ renamable $r5 = LEA_ADDiu $r29, 20
}
- renamable $at = LW $sp, 20, debug-location !21 :: (dereferenceable load (s32) from %ir.condition, !tbaa !23)
- DBG_VALUE $at, $noreg, !13, !DIExpression(), debug-location !19
- BEQ killed renamable $at, $zero, %bb.2, implicit-def $at, debug-location !27 {
+ renamable $r1 = LW $r29, 20, debug-location !21 :: (dereferenceable load (s32) from %ir.condition, !tbaa !23)
+ DBG_VALUE $r1, $noreg, !13, !DIExpression(), debug-location !19
+ BEQ killed renamable $r1, $r0, %bb.2, implicit-def $r1, debug-location !27 {
NOP debug-location !27
}
bb.1.if.then:
successors: %bb.2(0x80000000)
- JAL @do_something, csr_o32, implicit-def dead $ra, implicit undef $a0, implicit $a1, implicit-def $sp, debug-location !28 {
- $a1 = OR killed $s0, $zero, debug-location !28
+ JAL @do_something, csr_o32, implicit-def dead $r31, implicit undef $r4, implicit $r5, implicit-def $r29, debug-location !28 {
+ $r5 = OR killed $r16, $r0, debug-location !28
}
bb.2.if.end:
- $s0 = LW $sp, 24, debug-location !29 :: (load (s32) from %stack.2)
- $ra = LW $sp, 28, debug-location !29 :: (load (s32) from %stack.1)
- PseudoReturn undef $ra, debug-location !29 {
- $sp = ADDiu $sp, 32
+ $r16 = LW $r29, 24, debug-location !29 :: (load (s32) from %stack.2)
+ $r31 = LW $r29, 28, debug-location !29 :: (load (s32) from %stack.1)
+ PseudoReturn undef $r31, debug-location !29 {
+ $r29 = ADDiu $r29, 32
}
...
diff --git a/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir b/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir
index 5cba34e9731f4..bc0d122726223 100644
--- a/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir
@@ -6,9 +6,9 @@
#
# CHECK: ![[ARG1:.*]] = !DILocalVariable(name: "arg1"
# CHECK: ![[ARG2:.*]] = !DILocalVariable(name: "arg2"
-# CHECK: DBG_VALUE $s0_64, $noreg, ![[ARG2]], !DIExpression(), debug-location
-# CHECK: $s1_64 = OR64 killed $s0_64, $zero_64, debug-location
-# CHECK-NEXT: DBG_VALUE $s1_64, $noreg, ![[ARG2]], !DIExpression(), debug-location
+# CHECK: DBG_VALUE $r16_64, $noreg, ![[ARG2]], !DIExpression(), debug-location
+# CHECK: $r17_64 = OR64 killed $r16_64, $r0_64, debug-location
+# CHECK-NEXT: DBG_VALUE $r17_64, $noreg, ![[ARG2]], !DIExpression(), debug-location
# CHECK: DBG_VALUE $f24, $noreg, ![[ARG1]], !DIExpression(), debug-location
# CHECK: $f26 = FMOV_S killed $f24, debug-location
# CHECK-NEXT: DBG_VALUE $f26, $noreg, ![[ARG1]], !DIExpression(), debug-location
@@ -100,7 +100,7 @@ tracksRegLiveness: false
registers:
liveins:
- { reg: '$f12', virtual-reg: '' }
- - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$r5_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -132,13 +132,13 @@ stack:
stack-id: default, callee-saved-register: '$d24_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, name: '', type: spill-slot, offset: -32, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '$ra_64', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r31_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 4, name: '', type: spill-slot, offset: -40, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '$s1_64', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r17_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 5, name: '', type: spill-slot, offset: -48, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '$s0_64', callee-saved-restored: true,
+ stack-id: default, callee-saved-register: '$r16_64', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
constants:
@@ -157,82 +157,82 @@ constants:
body: |
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $f12, $a1_64, $s1_64, $f26, $d26_64, $d25_64, $d24_64, $ra_64, $s1_64, $s0_64
+ liveins: $f12, $r5_64, $r17_64, $f26, $d26_64, $d25_64, $d24_64, $r31_64, $r17_64, $r16_64
DBG_VALUE $f12, $noreg, !14, !DIExpression(), debug-location !19
- DBG_VALUE $a1_64, $noreg, !15, !DIExpression(), debug-location !19
- $sp_64 = DADDiu $sp_64, -48
+ DBG_VALUE $r5_64, $noreg, !15, !DIExpression(), debug-location !19
+ $r29_64 = DADDiu $r29_64, -48
CFI_INSTRUCTION def_cfa_offset 48
- SDC164 killed $d26_64, $sp_64, 40 :: (store (s64) into %stack.0)
- SDC164 killed $d25_64, $sp_64, 32 :: (store (s64) into %stack.1)
- SDC164 killed $d24_64, $sp_64, 24 :: (store (s64) into %stack.2)
- SD killed $ra_64, $sp_64, 16 :: (store (s64) into %stack.3)
- SD killed $s1_64, $sp_64, 8 :: (store (s64) into %stack.4)
- SD killed $s0_64, $sp_64, 0 :: (store (s64) into %stack.5)
+ SDC164 killed $d26_64, $r29_64, 40 :: (store (s64) into %stack.0)
+ SDC164 killed $d25_64, $r29_64, 32 :: (store (s64) into %stack.1)
+ SDC164 killed $d24_64, $r29_64, 24 :: (store (s64) into %stack.2)
+ SD killed $r31_64, $r29_64, 16 :: (store (s64) into %stack.3)
+ SD killed $r17_64, $r29_64, 8 :: (store (s64) into %stack.4)
+ SD killed $r16_64, $r29_64, 0 :: (store (s64) into %stack.5)
CFI_INSTRUCTION offset $d27_64, -8
CFI_INSTRUCTION offset $d26_64, -4
CFI_INSTRUCTION offset $d26_64, -16
CFI_INSTRUCTION offset $d25_64, -12
CFI_INSTRUCTION offset $d25_64, -24
CFI_INSTRUCTION offset $d24_64, -20
- CFI_INSTRUCTION offset $ra_64, -32
- CFI_INSTRUCTION offset $s1_64, -40
- CFI_INSTRUCTION offset $s0_64, -48
- renamable $s0_64 = COPY $a1_64
- DBG_VALUE $s0, $noreg, !15, !DIExpression(), debug-location !19
- DBG_VALUE $s0_64, $noreg, !15, !DIExpression(), debug-location !19
+ CFI_INSTRUCTION offset $r31_64, -32
+ CFI_INSTRUCTION offset $r17_64, -40
+ CFI_INSTRUCTION offset $r16_64, -48
+ renamable $r16_64 = COPY $r5_64
+ DBG_VALUE $r16, $noreg, !15, !DIExpression(), debug-location !19
+ DBG_VALUE $r16_64, $noreg, !15, !DIExpression(), debug-location !19
DBG_VALUE $f12, $noreg, !14, !DIExpression(), debug-location !19
renamable $d0_64 = CVT_D64_S renamable $f12, implicit $fcr31, debug-location !19
- renamable $at_64 = LUi64 target-flags(mips-highest) %const.0
- renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-higher) %const.0
- renamable $at_64 = DSLL killed renamable $at_64, 16
- renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-abs-hi) %const.0
- renamable $at_64 = DSLL killed renamable $at_64, 16
- renamable $d1_64 = LDC164 killed renamable $at_64, target-flags(mips-abs-lo) %const.0 :: (load (s64) from constant-pool)
+ renamable $r1_64 = LUi64 target-flags(mips-highest) %const.0
+ renamable $r1_64 = DADDiu killed renamable $r1_64, target-flags(mips-higher) %const.0
+ renamable $r1_64 = DSLL killed renamable $r1_64, 16
+ renamable $r1_64 = DADDiu killed renamable $r1_64, target-flags(mips-abs-hi) %const.0
+ renamable $r1_64 = DSLL killed renamable $r1_64, 16
+ renamable $d1_64 = LDC164 killed renamable $r1_64, target-flags(mips-abs-lo) %const.0 :: (load (s64) from constant-pool)
FCMP_D64 killed renamable $d0_64, killed renamable $d1_64, 7, implicit-def $fcc0, debug-location !19
- BC1T killed $fcc0, %bb.2, implicit-def dead $at, debug-location !19
- J %bb.1, implicit-def dead $at, debug-location !19
+ BC1T killed $fcc0, %bb.2, implicit-def dead $r1, debug-location !19
+ J %bb.1, implicit-def dead $r1, debug-location !19
bb.1.if.then:
successors: %bb.3(0x80000000)
- liveins: $f12, $s0_64
+ liveins: $f12, $r16_64
- JAL @externFunc, csr_n64, implicit-def dead $ra, implicit $f12, implicit-def $sp, implicit-def dead $f0, debug-location !19
- renamable $a0_64 = SLL64_32 renamable $s0, implicit $s0_64, debug-location !19
- JAL @externFunc3, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2, debug-location !19
+ JAL @externFunc, csr_n64, implicit-def dead $r31, implicit $f12, implicit-def $r29, implicit-def dead $f0, debug-location !19
+ renamable $r4_64 = SLL64_32 renamable $r16, implicit $r16_64, debug-location !19
+ JAL @externFunc3, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit-def $r29, implicit-def $r2, debug-location !19
renamable $f0 = PseudoCVT_S_W killed renamable $r2, debug-location !19
; This instruction is inserted additionally in order to test moving from one register to another
- $s1_64 = OR64 killed $s0_64, $zero_64, debug-location !19
- renamable $at_64 = LUi64 target-flags(mips-highest) %const.2
- renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-higher) %const.2
- renamable $at_64 = DSLL killed renamable $at_64, 16
- renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-abs-hi) %const.2
- renamable $at_64 = DSLL killed renamable $at_64, 16
- renamable $f1 = LWC1 killed renamable $at_64, target-flags(mips-abs-lo) %const.2 :: (load (s32) from constant-pool)
+ $r17_64 = OR64 killed $r16_64, $r0_64, debug-location !19
+ renamable $r1_64 = LUi64 target-flags(mips-highest) %const.2
+ renamable $r1_64 = DADDiu killed renamable $r1_64, target-flags(mips-higher) %const.2
+ renamable $r1_64 = DSLL killed renamable $r1_64, 16
+ renamable $r1_64 = DADDiu killed renamable $r1_64, target-flags(mips-abs-hi) %const.2
+ renamable $r1_64 = DSLL killed renamable $r1_64, 16
+ renamable $f1 = LWC1 killed renamable $r1_64, target-flags(mips-abs-lo) %const.2 :: (load (s32) from constant-pool)
renamable $f0 = FADD_S killed renamable $f0, killed renamable $f1, implicit $fcr31, debug-location !19
- J %bb.3, implicit-def dead $at, debug-location !19
+ J %bb.3, implicit-def dead $r1, debug-location !19
bb.2.if.else:
successors: %bb.3(0x80000000)
- liveins: $f12, $s0_64
-
- renamable $at_64 = LUi64 target-flags(mips-highest) %const.1
- renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-higher) %const.1
- renamable $at_64 = DSLL killed renamable $at_64, 16
- renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-abs-hi) %const.1
- renamable $at_64 = DSLL killed renamable $at_64, 16
- renamable $f0 = LWC1 killed renamable $at_64, target-flags(mips-abs-lo) %const.1 :: (load (s32) from constant-pool)
+ liveins: $f12, $r16_64
+
+ renamable $r1_64 = LUi64 target-flags(mips-highest) %const.1
+ renamable $r1_64 = DADDiu killed renamable $r1_64, target-flags(mips-higher) %const.1
+ renamable $r1_64 = DSLL killed renamable $r1_64, 16
+ renamable $r1_64 = DADDiu killed renamable $r1_64, target-flags(mips-abs-hi) %const.1
+ renamable $r1_64 = DSLL killed renamable $r1_64, 16
+ renamable $f0 = LWC1 killed renamable $r1_64, target-flags(mips-abs-lo) %const.1 :: (load (s32) from constant-pool)
renamable $f24 = FADD_S killed renamable $f12, killed renamable $f0, implicit $fcr31, debug-location !19
DBG_VALUE $f24, $noreg, !14, !DIExpression(), debug-location !19
$f12 = COPY renamable $f24, debug-location !19
- JAL @externFunc2, csr_n64, implicit-def dead $ra, implicit $f12, implicit-def $sp, implicit-def $f0, debug-location !19
+ JAL @externFunc2, csr_n64, implicit-def dead $r31, implicit $f12, implicit-def $r29, implicit-def $f0, debug-location !19
renamable $f25 = COPY $f0, debug-location !19
- renamable $a0_64 = SLL64_32 renamable $s0, implicit killed $s0_64, debug-location !19
- JAL @externFunc4, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $r2, debug-location !19
- renamable $s0 = COPY $r2, debug-location !19
+ renamable $r4_64 = SLL64_32 renamable $r16, implicit killed $r16_64, debug-location !19
+ JAL @externFunc4, csr_n64, implicit-def dead $r31, implicit $r4_64, implicit-def $r29, implicit-def $r2, debug-location !19
+ renamable $r16 = COPY $r2, debug-location !19
$f12 = COPY renamable $f24, debug-location !19
- JAL @externFunc, csr_n64, implicit-def dead $ra, implicit $f12, implicit-def $sp, implicit-def dead $f0, debug-location !19
- renamable $f0 = PseudoCVT_S_W killed renamable $s0, debug-location !19
+ JAL @externFunc, csr_n64, implicit-def dead $r31, implicit $f12, implicit-def $r29, implicit-def dead $f0, debug-location !19
+ renamable $f0 = PseudoCVT_S_W killed renamable $r16, debug-location !19
renamable $f0 = FADD_S killed renamable $f25, killed renamable $f0, implicit $fcr31, debug-location !19
; This instruction is inserted additionally in order to test moving variable's value from one float register to another.
$f26 = FMOV_S killed $f24, debug-location !19
@@ -240,13 +240,13 @@ body: |
bb.3.if.end:
liveins: $f0
- $s0_64 = LD $sp_64, 0, debug-location !19 :: (load (s64) from %stack.5)
- $s1_64 = LD $sp_64, 8, debug-location !19 :: (load (s64) from %stack.4)
- $ra_64 = LD $sp_64, 16, debug-location !19 :: (load (s64) from %stack.3)
- $d24_64 = LDC164 $sp_64, 24, debug-location !19 :: (load (s64) from %stack.2)
- $d25_64 = LDC164 $sp_64, 32, debug-location !19 :: (load (s64) from %stack.1)
- $d26_64 = LDC164 $sp_64, 40, debug-location !19 :: (load (s64) from %stack.0)
- $sp_64 = DADDiu $sp_64, 48
+ $r16_64 = LD $r29_64, 0, debug-location !19 :: (load (s64) from %stack.5)
+ $r17_64 = LD $r29_64, 8, debug-location !19 :: (load (s64) from %stack.4)
+ $r31_64 = LD $r29_64, 16, debug-location !19 :: (load (s64) from %stack.3)
+ $d24_64 = LDC164 $r29_64, 24, debug-location !19 :: (load (s64) from %stack.2)
+ $d25_64 = LDC164 $r29_64, 32, debug-location !19 :: (load (s64) from %stack.1)
+ $d26_64 = LDC164 $r29_64, 40, debug-location !19 :: (load (s64) from %stack.0)
+ $r29_64 = DADDiu $r29_64, 48
RetRA implicit $f0, debug-location !19
...
diff --git a/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir b/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
index fa45845b72aec..7b074d8ae8e66 100644
--- a/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
@@ -6,11 +6,11 @@
# CHECK: ![[VARA:.*]] = !DILocalVariable(name: "a"
# CHECK: ![[VARB:.*]] = !DILocalVariable(name: "b"
# CHECK: ![[VARC:.*]] = !DILocalVariable(name: "c"
-# CHECK: $at = COPY $a2
-# CHECK-NEXT: DBG_VALUE $at, $noreg, ![[VARC]], !DIExpression(), debug-location
-# CHECK: $s0 = COPY $a1
-# CHECK-NEXT: DBG_VALUE $a0, $noreg, ![[VARA]], !DIExpression(), debug-location
-# CHECK-NEXT: DBG_VALUE $s0, $noreg, ![[VARB]], !DIExpression(), debug-location
+# CHECK: $r1 = COPY $r6
+# CHECK-NEXT: DBG_VALUE $r1, $noreg, ![[VARC]], !DIExpression(), debug-location
+# CHECK: $r16 = COPY $r5
+# CHECK-NEXT: DBG_VALUE $r4, $noreg, ![[VARA]], !DIExpression(), debug-location
+# CHECK-NEXT: DBG_VALUE $r16, $noreg, ![[VARB]], !DIExpression(), debug-location
--- |
; ModuleID = 'test.c'
@@ -87,31 +87,31 @@ registers:
- { id: 7, class: gpr32, preferred-register: '' }
- { id: 8, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '$a0', virtual-reg: '%0' }
- - { reg: '$a1', virtual-reg: '%1' }
- - { reg: '$a2', virtual-reg: '%2' }
+ - { reg: '$r4', virtual-reg: '%0' }
+ - { reg: '$r5', virtual-reg: '%1' }
+ - { reg: '$r6', virtual-reg: '%2' }
body: |
bb.0.entry:
- liveins: $a0, $a1, $a2
+ liveins: $r4, $r5, $r6
- DBG_VALUE $a0, $noreg, !12, !DIExpression(), debug-location !16
- DBG_VALUE $a1, $noreg, !13, !DIExpression(), debug-location !16
- DBG_VALUE $a2, $noreg, !14, !DIExpression(), debug-location !16
- %2:gpr32 = COPY $a2
+ DBG_VALUE $r4, $noreg, !12, !DIExpression(), debug-location !16
+ DBG_VALUE $r5, $noreg, !13, !DIExpression(), debug-location !16
+ DBG_VALUE $r6, $noreg, !14, !DIExpression(), debug-location !16
+ %2:gpr32 = COPY $r6
DBG_VALUE %2, $noreg, !14, !DIExpression(), debug-location !16
- %8:gpr32 = COPY $a1
+ %8:gpr32 = COPY $r5
DBG_VALUE %8, $noreg, !13, !DIExpression(), debug-location !16
- %0:gpr32 = COPY $a0
+ %0:gpr32 = COPY $r4
DBG_VALUE %0, $noreg, !12, !DIExpression(), debug-location !16
%3:gpr32 = nsw ADDu %8, %0, debug-location !17
- ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp, debug-location !19
+ ADJCALLSTACKDOWN 16, 0, implicit-def dead $r29, implicit $r29, debug-location !19
%4:gpr32 = nsw ADDiu %8, 10, debug-location !18
- $a0 = COPY %3, debug-location !19
- $a1 = COPY %2, debug-location !19
- DBG_VALUE $a1, $noreg, !14, !DIExpression(), debug-location !16
- $a2 = COPY %4, debug-location !19
- JAL @fn1, csr_o32, implicit-def dead $ra, implicit $a0, implicit $a1, implicit $a2, implicit-def $sp, implicit-def $r2, debug-location !19
- ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp, debug-location !19
+ $r4 = COPY %3, debug-location !19
+ $r5 = COPY %2, debug-location !19
+ DBG_VALUE $r5, $noreg, !14, !DIExpression(), debug-location !16
+ $r6 = COPY %4, debug-location !19
+ JAL @fn1, csr_o32, implicit-def dead $r31, implicit $r4, implicit $r5, implicit $r6, implicit-def $r29, implicit-def $r2, debug-location !19
+ ADJCALLSTACKUP 16, 0, implicit-def dead $r29, implicit $r29, debug-location !19
%5:gpr32 = COPY killed $r2, debug-location !19
DBG_VALUE %5, $noreg, !15, !DIExpression(), debug-location !16
%6:gpr32 = SLTi %5, 11, debug-location !22
diff --git a/llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll b/llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll
index 2feeaf5780059..e76159f17cfcf 100644
--- a/llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll
+++ b/llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll
@@ -24,8 +24,8 @@ declare void @foo(ptr)
; CHECK: DW_AT_name {{.*}}"e"
; CHECK: DW_TAG_variable
; CHECK-NEXT: DW_AT_location [DW_FORM_sec_offset] (
-; CHECK-NEXT: [0x00000028, 0x0000002c) ".text": DW_OP_reg1 AT_64
-; CHECK-NEXT: [0x0000002c, 0x00000048) ".text": DW_OP_breg29 SP_64+16)
+; CHECK-NEXT: [0x00000028, 0x0000002c) ".text": DW_OP_reg1 R1_64
+; CHECK-NEXT: [0x0000002c, 0x00000048) ".text": DW_OP_breg29 R29_64+16)
; CHECK-NEXT: DW_AT_name [DW_FORM_strp] ( .debug_str[0x0000006b] = "x")
define i32 @f0(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !4 {
@@ -54,8 +54,8 @@ entry:
; CHECK: DW_TAG_variable
; CHECK-NEXT: DW_AT_location [DW_FORM_sec_offset] (
-; CHECK-NEXT: [0x00000080, 0x00000084) ".text": DW_OP_reg1 AT_64
-; CHECK-NEXT: [0x00000084, 0x00000098) ".text": DW_OP_breg29 SP_64+16)
+; CHECK-NEXT: [0x00000080, 0x00000084) ".text": DW_OP_reg1 R1_64
+; CHECK-NEXT: [0x00000084, 0x00000098) ".text": DW_OP_breg29 R29_64+16)
; CHECK-NEXT: DW_AT_name [DW_FORM_strp] ( .debug_str[0x0000006b] = "x")
define i32 @f1(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !15 {
diff --git a/llvm/test/DebugInfo/Mips/dsr-non-fixed-objects.ll b/llvm/test/DebugInfo/Mips/dsr-non-fixed-objects.ll
index 67bd22abd6766..9a5a1ca71a9b5 100644
--- a/llvm/test/DebugInfo/Mips/dsr-non-fixed-objects.ll
+++ b/llvm/test/DebugInfo/Mips/dsr-non-fixed-objects.ll
@@ -21,7 +21,7 @@ declare void @foo(ptr)
; }
; CHECK: DW_TAG_subprogram
-; CHECK: DW_AT_location [DW_FORM_exprloc] (DW_OP_breg29 SP_64+36)
+; CHECK: DW_AT_location [DW_FORM_exprloc] (DW_OP_breg29 R29_64+36)
; CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000065] = "c")
; Function Attrs: nounwind
@@ -45,7 +45,7 @@ entry:
}
; CHECK: DW_TAG_subprogram
-; CHECK: DW_AT_location [DW_FORM_exprloc] (DW_OP_breg23 S7_64+32)
+; CHECK: DW_AT_location [DW_FORM_exprloc] (DW_OP_breg23 R23_64+32)
; CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000065] = "c")
define ptr @f3(i32 signext %a, i32 signext %b) !dbg !8 {
diff --git a/llvm/test/DebugInfo/Mips/dw_op_entry_value_32bit.ll b/llvm/test/DebugInfo/Mips/dw_op_entry_value_32bit.ll
index 0d884d37d86a3..9f516d4546d19 100644
--- a/llvm/test/DebugInfo/Mips/dw_op_entry_value_32bit.ll
+++ b/llvm/test/DebugInfo/Mips/dw_op_entry_value_32bit.ll
@@ -18,12 +18,12 @@
;; Confirm that info from callSites attribute is used as entry_value in DIExpression.
;; Test mips32:
-; CHECK: $a0 = nsw ADDu $a1, killed renamable $a0,
-; CHECK-NEXT: DBG_VALUE $a0, $noreg, !14, !DIExpression(DW_OP_LLVM_entry_value, 1)
+; CHECK: $r4 = nsw ADDu $r5, killed renamable $r4,
+; CHECK-NEXT: DBG_VALUE $r4, $noreg, !14, !DIExpression(DW_OP_LLVM_entry_value, 1)
;; Test mipsel:
-; CHECKel: $a0 = nsw ADDu $a1, killed renamable $a0,
-; CHECKel-NEXT: DBG_VALUE $a0, $noreg, !14, !DIExpression(DW_OP_LLVM_entry_value, 1)
+; CHECKel: $r4 = nsw ADDu $r5, killed renamable $r4,
+; CHECKel-NEXT: DBG_VALUE $r4, $noreg, !14, !DIExpression(DW_OP_LLVM_entry_value, 1)
; ModuleID = 'm.c'
source_filename = "m.c"
diff --git a/llvm/test/DebugInfo/Mips/dw_op_entry_value_64bit.ll b/llvm/test/DebugInfo/Mips/dw_op_entry_value_64bit.ll
index bfbadf46c96fd..b635906d9465d 100644
--- a/llvm/test/DebugInfo/Mips/dw_op_entry_value_64bit.ll
+++ b/llvm/test/DebugInfo/Mips/dw_op_entry_value_64bit.ll
@@ -18,12 +18,12 @@
;; Confirm that info from callSites attribute is used as entry_value in DIExpression.
;; Test mips64:
-; CHECK64: $a0_64 = nsw DADDu $a1_64, killed renamable $a0_64,
-; CHECK64-NEXT: DBG_VALUE $a0_64, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1)
+; CHECK64: $r4_64 = nsw DADDu $r5_64, killed renamable $r4_64,
+; CHECK64-NEXT: DBG_VALUE $r4_64, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1)
;; Test mips64el:
-; CHECK64el: $a0_64 = nsw DADDu $a1_64, killed renamable $a0_64,
-; CHECK64el-NEXT: DBG_VALUE $a0_64, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1)
+; CHECK64el: $r4_64 = nsw DADDu $r5_64, killed renamable $r4_64,
+; CHECK64el-NEXT: DBG_VALUE $r4_64, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1)
; ModuleID = 'm.c'
source_filename = "m.c"
diff --git a/llvm/test/DebugInfo/Mips/livedebugvariables-reorder.mir b/llvm/test/DebugInfo/Mips/livedebugvariables-reorder.mir
index 3108537f569f0..fac6807a41666 100644
--- a/llvm/test/DebugInfo/Mips/livedebugvariables-reorder.mir
+++ b/llvm/test/DebugInfo/Mips/livedebugvariables-reorder.mir
@@ -67,9 +67,9 @@ callSites:
machineFunctionInfo: {}
body: |
bb.0.entry:
- ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp, debug-location !12
- JAL @foo, csr_o32_fpxx, implicit-def dead $ra, implicit-def $sp, implicit-def $r2, debug-location !12
- ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp, debug-location !12
+ ADJCALLSTACKDOWN 16, 0, implicit-def dead $r29, implicit $r29, debug-location !12
+ JAL @foo, csr_o32_fpxx, implicit-def dead $r31, implicit-def $r29, implicit-def $r2, debug-location !12
+ ADJCALLSTACKUP 16, 0, implicit-def dead $r29, implicit $r29, debug-location !12
%0:gpr32 = COPY killed $r2, debug-location !12
DBG_VALUE 1001, $noreg, !8, !DIExpression(DW_OP_LLVM_fragment, 0, 16), debug-location !12
DBG_VALUE 1002, $noreg, !8, !DIExpression(DW_OP_LLVM_fragment, 16, 16), debug-location !12
@@ -77,7 +77,7 @@ body: |
DBG_VALUE 333, $noreg, !10, !DIExpression(), debug-location !12
DBG_VALUE 444, $noreg, !11, !DIExpression(), debug-location !12
DBG_VALUE %0, $noreg, !8, !DIExpression(), debug-location !12
- INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $r2, 12 /* clobber */, implicit-def dead early-clobber $r3, 12 /* clobber */, implicit-def dead early-clobber $a0, 12 /* clobber */, implicit-def dead early-clobber $a1, 12 /* clobber */, implicit-def dead early-clobber $a2, 12 /* clobber */, implicit-def dead early-clobber $a3, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15, 12 /* clobber */, implicit-def dead early-clobber $t8, 12 /* clobber */, implicit-def dead early-clobber $t9, 12 /* clobber */, implicit-def dead early-clobber $gp, 12 /* clobber */, implicit-def dead early-clobber $ra, 12 /* clobber */, implicit-def dead early-clobber $s0, 12 /* clobber */, implicit-def dead early-clobber $s1, 12 /* clobber */, implicit-def dead early-clobber $s2, 12 /* clobber */, implicit-def dead early-clobber $s3, 12 /* clobber */, implicit-def dead early-clobber $s4, 12 /* clobber */, implicit-def dead early-clobber $s5, 12 /* clobber */, implicit-def dead early-clobber $s6, 12 /* clobber */, implicit-def dead early-clobber $s7, 12 /* clobber */, implicit-def dead early-clobber $at, !13, debug-location !12
+ INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $r2, 12 /* clobber */, implicit-def dead early-clobber $r3, 12 /* clobber */, implicit-def dead early-clobber $r4, 12 /* clobber */, implicit-def dead early-clobber $r5, 12 /* clobber */, implicit-def dead early-clobber $r6, 12 /* clobber */, implicit-def dead early-clobber $r7, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15, 12 /* clobber */, implicit-def dead early-clobber $r24, 12 /* clobber */, implicit-def dead early-clobber $r25, 12 /* clobber */, implicit-def dead early-clobber $r28, 12 /* clobber */, implicit-def dead early-clobber $r31, 12 /* clobber */, implicit-def dead early-clobber $r16, 12 /* clobber */, implicit-def dead early-clobber $r17, 12 /* clobber */, implicit-def dead early-clobber $r18, 12 /* clobber */, implicit-def dead early-clobber $r19, 12 /* clobber */, implicit-def dead early-clobber $r20, 12 /* clobber */, implicit-def dead early-clobber $r21, 12 /* clobber */, implicit-def dead early-clobber $r22, 12 /* clobber */, implicit-def dead early-clobber $r23, 12 /* clobber */, implicit-def dead early-clobber $r1, !13, debug-location !12
$r2 = COPY killed %0, debug-location !12
RetRA implicit killed $r2, debug-location !12
diff --git a/llvm/test/MC/Mips/eh-frame.s b/llvm/test/MC/Mips/eh-frame.s
index dac142325f9fd..1313a005c1ffa 100644
--- a/llvm/test/MC/Mips/eh-frame.s
+++ b/llvm/test/MC/Mips/eh-frame.s
@@ -65,7 +65,7 @@ func:
// DWARF32_PIC-NEXT: Augmentation data: 1B
// ^^ fde pointer encoding: DW_EH_PE_pcrel | DW_EH_PE_sdata4
// DWARF32-EMPTY:
-// DWARF32-NEXT: DW_CFA_def_cfa_register: SP_64
+// DWARF32-NEXT: DW_CFA_def_cfa_register: R29_64
//
// DWARF32_ABS: 00000014 00000010 00000018 FDE cie=00000000 pc=00000000...00000000
// DWARF32_PIC: 00000014 00000010 00000018 FDE cie=00000000 pc=0000001c...0000001c
@@ -89,7 +89,7 @@ func:
// DWARF64_PIC: Augmentation data: 1B
// ^^ fde pointer encoding: DW_EH_PE_pcrel | DW_EH_PE_sdata4
// DWARF64-EMPTY:
-// DWARF64-NEXT: DW_CFA_def_cfa_register: SP_64
+// DWARF64-NEXT: DW_CFA_def_cfa_register: R29_64
// DWARF64_PIC-NEXT: DW_CFA_nop:
//
// DWARF64_ABS: 00000014 00000018 00000018 FDE cie=00000000 pc=00000000...00000000
diff --git a/llvm/test/tools/llvm-exegesis/Mips/print-assembled-snippet.s b/llvm/test/tools/llvm-exegesis/Mips/print-assembled-snippet.s
index f0844c4145a2b..90266daefd959 100644
--- a/llvm/test/tools/llvm-exegesis/Mips/print-assembled-snippet.s
+++ b/llvm/test/tools/llvm-exegesis/Mips/print-assembled-snippet.s
@@ -10,8 +10,8 @@
# RUN: --snippets-file=%s --mode=latency --repetition-mode=duplicate \
# RUN: | FileCheck %s --check-prefix=CHECK-LINUX-64
-# LLVM-EXEGESIS-DEFREG A0 0
-# LLVM-EXEGESIS-DEFREG A1 0
+# LLVM-EXEGESIS-DEFREG R4 0
+# LLVM-EXEGESIS-DEFREG R5 0
add $2, $5, $4
# CHECK-LINUX: cpu_name: generic
>From d8b3fd713f9683d0d527ab0ce652f4ddea3f726f Mon Sep 17 00:00:00 2001
From: Anton Rapetov <anton.rapetov at mediatek.com>
Date: Thu, 8 Oct 2026 11:14:14 -0400
Subject: [PATCH 5/7] [Mips][test] Update test expectations for new register
allocation
Renaming the GPR records changed the MCRegister enum ID ordering and thus
the register allocator's tie-breaking. Update the test expectations that
depend on it:
- the delay slot filler now fills delay slots with different instructions
(e.g. CodeGen/Mips/mips64-sret.ll, CodeGen/Mips/eh-return32.ll);
- the register allocator picks different (but equivalent) registers for
virtual registers, which also changes the order of some instructions and
the encoding in the DebugInfo/exception table tests;
- liveins lists are printed in the new enum order in the GlobalISel MIR
tests.
Autogenerated tests were regenerated with the update_*_test_checks.py
scripts; the rest were edited by hand.
Co-Authored-By: Claude Sonnet <noreply at anthropic.com>
---
llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll | 24 +-
.../Mips/GlobalISel/irtranslator/call.ll | 6 +-
.../irtranslator/global_address_pic.ll | 4 +-
.../CodeGen/Mips/cconv/illegal-vectors.ll | 4 +-
llvm/test/CodeGen/Mips/cconv/o32-mips64.ll | 16 +-
llvm/test/CodeGen/Mips/eh-return32.ll | 2 +-
llvm/test/CodeGen/Mips/eh-return64.ll | 2 +-
llvm/test/CodeGen/Mips/fmuladd-soft-float.ll | 72 +++---
llvm/test/CodeGen/Mips/funnel-shift-rot.ll | 4 +-
llvm/test/CodeGen/Mips/funnel-shift.ll | 2 +-
llvm/test/CodeGen/Mips/ins.ll | 33 +--
llvm/test/CodeGen/Mips/llvm-ir/add.ll | 4 +-
llvm/test/CodeGen/Mips/llvm-ir/and.ll | 26 +-
llvm/test/CodeGen/Mips/llvm-ir/ashr.ll | 4 +
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 5 +
llvm/test/CodeGen/Mips/llvm-ir/mul.ll | 2 +-
llvm/test/CodeGen/Mips/llvm-ir/or.ll | 205 ++++++++--------
llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll | 3 +
llvm/test/CodeGen/Mips/llvm-ir/select-int.ll | 106 +++++---
llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 5 +
llvm/test/CodeGen/Mips/llvm-ir/udiv.ll | 3 +
llvm/test/CodeGen/Mips/llvm-ir/xor.ll | 78 +++---
.../Mips/micromips-gcc-except-table.ll | 2 +-
llvm/test/CodeGen/Mips/mips64-f128.ll | 4 +-
llvm/test/CodeGen/Mips/mips64-sret.ll | 9 +-
llvm/test/CodeGen/Mips/o32_cc_vararg.ll | 6 +-
llvm/test/CodeGen/Mips/select.ll | 230 ++++++++++--------
llvm/test/DebugInfo/Mips/eh_frame.ll | 4 +-
28 files changed, 465 insertions(+), 400 deletions(-)
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll
index 90446ed339a17..341bb9042a6ba 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll
@@ -6,11 +6,11 @@
define i1 @sel_i1(i1 %j, i1 %k, i1 %l) {
; CHECK-LABEL: sel_i1:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: move $2, $6
; CHECK-NEXT: xor $1, $4, $zero
; CHECK-NEXT: andi $1, $1, 1
-; CHECK-NEXT: movn $6, $5, $1
; CHECK-NEXT: jr $ra
-; CHECK-NEXT: move $2, $6
+; CHECK-NEXT: movn $2, $5, $1
entry:
%cond = xor i1 %j, false
%res = select i1 %cond, i1 %k, i1 %l
@@ -21,14 +21,14 @@ entry:
define i8 @sel_i8(i8 %j, i8 %k, i8 %l) {
; CHECK-LABEL: sel_i8:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: move $2, $6
; CHECK-NEXT: seb $1, $4
-; CHECK-NEXT: seb $2, $zero
-; CHECK-NEXT: xor $1, $1, $2
+; CHECK-NEXT: seb $3, $zero
+; CHECK-NEXT: xor $1, $1, $3
; CHECK-NEXT: sltu $1, $zero, $1
; CHECK-NEXT: andi $1, $1, 1
-; CHECK-NEXT: movn $6, $5, $1
; CHECK-NEXT: jr $ra
-; CHECK-NEXT: move $2, $6
+; CHECK-NEXT: movn $2, $5, $1
entry:
%cond = icmp ne i8 %j, 0
%res = select i1 %cond, i8 %k, i8 %l
@@ -39,14 +39,14 @@ entry:
define i16 @sel_i16(i16 %j, i16 %k, i16 %l) {
; CHECK-LABEL: sel_i16:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: move $2, $6
; CHECK-NEXT: seh $1, $4
-; CHECK-NEXT: seh $2, $zero
-; CHECK-NEXT: xor $1, $1, $2
+; CHECK-NEXT: seh $3, $zero
+; CHECK-NEXT: xor $1, $1, $3
; CHECK-NEXT: sltu $1, $zero, $1
; CHECK-NEXT: andi $1, $1, 1
-; CHECK-NEXT: movn $6, $5, $1
; CHECK-NEXT: jr $ra
-; CHECK-NEXT: move $2, $6
+; CHECK-NEXT: movn $2, $5, $1
entry:
%cond = icmp ne i16 %j, 0
%res = select i1 %cond, i16 %k, i16 %l
@@ -57,12 +57,12 @@ entry:
define i32 @sel_i32(i32 %j, i32 %k, i32 %l) {
; CHECK-LABEL: sel_i32:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: move $2, $6
; CHECK-NEXT: xor $1, $4, $zero
; CHECK-NEXT: sltu $1, $zero, $1
; CHECK-NEXT: andi $1, $1, 1
-; CHECK-NEXT: movn $6, $5, $1
; CHECK-NEXT: jr $ra
-; CHECK-NEXT: move $2, $6
+; CHECK-NEXT: movn $2, $5, $1
entry:
%cond = icmp ne i32 %j, 0
%res = select i1 %cond, i32 %k, i32 %l
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
index 1016e6f0ec7df..89f90b193df5c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
@@ -23,7 +23,7 @@ define i32 @call_global(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32: RetRA implicit $r2
; MIPS32_PIC-LABEL: name: call_global
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $r4, $r5, $r6, $r7, $r25, $r2
+ ; MIPS32_PIC: liveins: $r2, $r4, $r5, $r6, $r7, $r25
; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
@@ -87,7 +87,7 @@ define i32 @call_global_with_local_linkage(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32: RetRA implicit $r2
; MIPS32_PIC-LABEL: name: call_global_with_local_linkage
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $r4, $r5, $r6, $r7, $r25, $r2
+ ; MIPS32_PIC: liveins: $r2, $r4, $r5, $r6, $r7, $r25
; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
@@ -179,7 +179,7 @@ define void @call_f_with_void_ret() {
; MIPS32: RetRA
; MIPS32_PIC-LABEL: name: call_f_with_void_ret
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $r25, $r2
+ ; MIPS32_PIC: liveins: $r2, $r25
; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
; MIPS32_PIC: ADJCALLSTACKDOWN 16, 0, implicit-def $r29, implicit $r29
; MIPS32_PIC: [[GV:%[0-9]+]]:gpr32(p0) = G_GLOBAL_VALUE target-flags(mips-got-call) @f_with_void_ret
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
index 483f4aff874f0..cb882b92d482e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
@@ -20,7 +20,7 @@ entry:
define i32 @call_global(i32 %a, i32 %b) {
; MIPS32_PIC-LABEL: name: call_global
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $r4, $r5, $r25, $r2
+ ; MIPS32_PIC: liveins: $r2, $r4, $r5, $r25
; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
@@ -42,7 +42,7 @@ entry:
define i32 @call_global_with_local_linkage(i32 %a, i32 %b) {
; MIPS32_PIC-LABEL: name: call_global_with_local_linkage
; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: liveins: $r4, $r5, $r25, $r2
+ ; MIPS32_PIC: liveins: $r2, $r4, $r5, $r25
; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $r2, $r25
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(s32) = COPY $r4
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(s32) = COPY $r5
diff --git a/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll b/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
index d605079371afe..9803302eeef5b 100644
--- a/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
+++ b/llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
@@ -282,11 +282,11 @@ define <3 x i32> @arg_v3i32(<3 x i32> %vec, ptr %p) {
;
; MIPS32-LABEL: arg_v3i32:
; MIPS32: # %bb.0:
+; MIPS32-NEXT: move $3, $5
+; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: sw $6, 8($7)
; MIPS32-NEXT: sw $5, 4($7)
; MIPS32-NEXT: sw $4, 0($7)
-; MIPS32-NEXT: move $2, $4
-; MIPS32-NEXT: move $3, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: move $4, $6
store <3 x i32> %vec, ptr %p
diff --git a/llvm/test/CodeGen/Mips/cconv/o32-mips64.ll b/llvm/test/CodeGen/Mips/cconv/o32-mips64.ll
index be4b0f914cc2e..347187291b892 100644
--- a/llvm/test/CodeGen/Mips/cconv/o32-mips64.ll
+++ b/llvm/test/CodeGen/Mips/cconv/o32-mips64.ll
@@ -53,15 +53,15 @@ define i64 @increment(i64 %value) {
define i64 @identity_i64(i64 %value) {
; BE-LABEL: identity_i64:
; BE: # %bb.0:
-; BE-NEXT: move $2, $4
-; BE-NEXT: jr $ra
; BE-NEXT: move $3, $5
+; BE-NEXT: jr $ra
+; BE-NEXT: move $2, $4
;
; LE-LABEL: identity_i64:
; LE: # %bb.0:
-; LE-NEXT: move $2, $4
-; LE-NEXT: jr $ra
; LE-NEXT: move $3, $5
+; LE-NEXT: jr $ra
+; LE-NEXT: move $2, $4
ret i64 %value
}
@@ -111,14 +111,14 @@ define double @identity_double(double %value) {
;
; SOFT-BE-LABEL: identity_double:
; SOFT-BE: # %bb.0:
-; SOFT-BE-NEXT: move $2, $4
-; SOFT-BE-NEXT: jr $ra
; SOFT-BE-NEXT: move $3, $5
+; SOFT-BE-NEXT: jr $ra
+; SOFT-BE-NEXT: move $2, $4
;
; SOFT-LE-LABEL: identity_double:
; SOFT-LE: # %bb.0:
-; SOFT-LE-NEXT: move $2, $4
-; SOFT-LE-NEXT: jr $ra
; SOFT-LE-NEXT: move $3, $5
+; SOFT-LE-NEXT: jr $ra
+; SOFT-LE-NEXT: move $2, $4
ret double %value
}
diff --git a/llvm/test/CodeGen/Mips/eh-return32.ll b/llvm/test/CodeGen/Mips/eh-return32.ll
index 0c60c47310952..5be90db04c167 100644
--- a/llvm/test/CodeGen/Mips/eh-return32.ll
+++ b/llvm/test/CodeGen/Mips/eh-return32.ll
@@ -69,8 +69,8 @@ entry:
; CHECK: .cfi_offset 7,
; check that stack adjustment and handler are put in $v1 and $v0.
-; CHECK: move $3, $4
; CHECK: move $2, $5
+; CHECK: move $3, $4
; check that $a0-$a3 are restored from stack.
; CHECK: lw $4, [[offset0]]($sp)
diff --git a/llvm/test/CodeGen/Mips/eh-return64.ll b/llvm/test/CodeGen/Mips/eh-return64.ll
index f5a547a3b608c..b99b4a566a004 100644
--- a/llvm/test/CodeGen/Mips/eh-return64.ll
+++ b/llvm/test/CodeGen/Mips/eh-return64.ll
@@ -72,8 +72,8 @@ entry:
; CHECK: .cfi_offset 7, -32
; check that stack adjustment and handler are put in $v1 and $v0.
-; CHECK: move $3, $4
; CHECK: move $2, $5
+; CHECK: move $3, $4
; check that $a0-$a3 are restored from stack.
; CHECK: ld $4, [[offset0]]($sp)
diff --git a/llvm/test/CodeGen/Mips/fmuladd-soft-float.ll b/llvm/test/CodeGen/Mips/fmuladd-soft-float.ll
index 4fa1085274457..c66ac7bd86899 100644
--- a/llvm/test/CodeGen/Mips/fmuladd-soft-float.ll
+++ b/llvm/test/CodeGen/Mips/fmuladd-soft-float.ll
@@ -89,9 +89,9 @@ define double @fmuladd_intrinsic_f64(double %a, double %b, double %c) #0 {
; SOFT-FLOAT-32-NEXT: .cfi_offset 31, -4
; SOFT-FLOAT-32-NEXT: jal __muldf3
; SOFT-FLOAT-32-NEXT: nop
-; SOFT-FLOAT-32-NEXT: move $4, $2
; SOFT-FLOAT-32-NEXT: lw $6, 40($sp)
; SOFT-FLOAT-32-NEXT: lw $7, 44($sp)
+; SOFT-FLOAT-32-NEXT: move $4, $2
; SOFT-FLOAT-32-NEXT: jal __adddf3
; SOFT-FLOAT-32-NEXT: move $5, $3
; SOFT-FLOAT-32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
@@ -106,9 +106,9 @@ define double @fmuladd_intrinsic_f64(double %a, double %b, double %c) #0 {
; SOFT-FLOAT-32R2-NEXT: .cfi_offset 31, -4
; SOFT-FLOAT-32R2-NEXT: jal __muldf3
; SOFT-FLOAT-32R2-NEXT: nop
-; SOFT-FLOAT-32R2-NEXT: move $4, $2
; SOFT-FLOAT-32R2-NEXT: lw $6, 40($sp)
; SOFT-FLOAT-32R2-NEXT: lw $7, 44($sp)
+; SOFT-FLOAT-32R2-NEXT: move $4, $2
; SOFT-FLOAT-32R2-NEXT: jal __adddf3
; SOFT-FLOAT-32R2-NEXT: move $5, $3
; SOFT-FLOAT-32R2-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
@@ -240,9 +240,9 @@ define double @fmuladd_contract_f64(double %a, double %b, double %c) #0 {
; SOFT-FLOAT-32-NEXT: .cfi_offset 31, -4
; SOFT-FLOAT-32-NEXT: jal __muldf3
; SOFT-FLOAT-32-NEXT: nop
-; SOFT-FLOAT-32-NEXT: move $4, $2
; SOFT-FLOAT-32-NEXT: lw $6, 40($sp)
; SOFT-FLOAT-32-NEXT: lw $7, 44($sp)
+; SOFT-FLOAT-32-NEXT: move $4, $2
; SOFT-FLOAT-32-NEXT: jal __adddf3
; SOFT-FLOAT-32-NEXT: move $5, $3
; SOFT-FLOAT-32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
@@ -257,9 +257,9 @@ define double @fmuladd_contract_f64(double %a, double %b, double %c) #0 {
; SOFT-FLOAT-32R2-NEXT: .cfi_offset 31, -4
; SOFT-FLOAT-32R2-NEXT: jal __muldf3
; SOFT-FLOAT-32R2-NEXT: nop
-; SOFT-FLOAT-32R2-NEXT: move $4, $2
; SOFT-FLOAT-32R2-NEXT: lw $6, 40($sp)
; SOFT-FLOAT-32R2-NEXT: lw $7, 44($sp)
+; SOFT-FLOAT-32R2-NEXT: move $4, $2
; SOFT-FLOAT-32R2-NEXT: jal __adddf3
; SOFT-FLOAT-32R2-NEXT: move $5, $3
; SOFT-FLOAT-32R2-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
@@ -345,13 +345,13 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-32-NEXT: lw $5, 76($sp)
; SOFT-FLOAT-32-NEXT: jal __mulsf3
; SOFT-FLOAT-32-NEXT: move $4, $17
-; SOFT-FLOAT-32-NEXT: move $4, $2
; SOFT-FLOAT-32-NEXT: lw $17, 88($sp)
; SOFT-FLOAT-32-NEXT: lw $21, 72($sp)
; SOFT-FLOAT-32-NEXT: lw $5, 92($sp)
; SOFT-FLOAT-32-NEXT: sw $20, 12($16)
-; SOFT-FLOAT-32-NEXT: jal __addsf3
; SOFT-FLOAT-32-NEXT: sw $19, 8($16)
+; SOFT-FLOAT-32-NEXT: jal __addsf3
+; SOFT-FLOAT-32-NEXT: move $4, $2
; SOFT-FLOAT-32-NEXT: sw $2, 4($16)
; SOFT-FLOAT-32-NEXT: move $4, $18
; SOFT-FLOAT-32-NEXT: jal __mulsf3
@@ -408,13 +408,13 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-32R2-NEXT: lw $5, 76($sp)
; SOFT-FLOAT-32R2-NEXT: jal __mulsf3
; SOFT-FLOAT-32R2-NEXT: move $4, $17
-; SOFT-FLOAT-32R2-NEXT: move $4, $2
; SOFT-FLOAT-32R2-NEXT: lw $17, 88($sp)
; SOFT-FLOAT-32R2-NEXT: lw $21, 72($sp)
; SOFT-FLOAT-32R2-NEXT: lw $5, 92($sp)
; SOFT-FLOAT-32R2-NEXT: sw $20, 12($16)
-; SOFT-FLOAT-32R2-NEXT: jal __addsf3
; SOFT-FLOAT-32R2-NEXT: sw $19, 8($16)
+; SOFT-FLOAT-32R2-NEXT: jal __addsf3
+; SOFT-FLOAT-32R2-NEXT: move $4, $2
; SOFT-FLOAT-32R2-NEXT: sw $2, 4($16)
; SOFT-FLOAT-32R2-NEXT: move $4, $18
; SOFT-FLOAT-32R2-NEXT: jal __mulsf3
@@ -464,9 +464,9 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-64-NEXT: sll $4, $21, 0
; SOFT-FLOAT-64-NEXT: jal __mulsf3
; SOFT-FLOAT-64-NEXT: sll $5, $20, 0
-; SOFT-FLOAT-64-NEXT: move $4, $2
-; SOFT-FLOAT-64-NEXT: jal __addsf3
; SOFT-FLOAT-64-NEXT: sll $5, $19, 0
+; SOFT-FLOAT-64-NEXT: jal __addsf3
+; SOFT-FLOAT-64-NEXT: move $4, $2
; SOFT-FLOAT-64-NEXT: move $22, $2
; SOFT-FLOAT-64-NEXT: sll $4, $18, 0
; SOFT-FLOAT-64-NEXT: jal __mulsf3
@@ -477,12 +477,12 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-64-NEXT: dsrl $1, $20, 32
; SOFT-FLOAT-64-NEXT: jal __mulsf3
; SOFT-FLOAT-64-NEXT: sll $5, $1, 0
-; SOFT-FLOAT-64-NEXT: move $4, $2
; SOFT-FLOAT-64-NEXT: dsll $1, $22, 32
-; SOFT-FLOAT-64-NEXT: dsrl $2, $19, 32
-; SOFT-FLOAT-64-NEXT: sll $5, $2, 0
-; SOFT-FLOAT-64-NEXT: jal __addsf3
+; SOFT-FLOAT-64-NEXT: dsrl $3, $19, 32
+; SOFT-FLOAT-64-NEXT: sll $5, $3, 0
; SOFT-FLOAT-64-NEXT: dsrl $19, $1, 32
+; SOFT-FLOAT-64-NEXT: jal __addsf3
+; SOFT-FLOAT-64-NEXT: move $4, $2
; SOFT-FLOAT-64-NEXT: # kill: def $r2 killed $r2 def $r2_64
; SOFT-FLOAT-64-NEXT: dsll $1, $2, 32
; SOFT-FLOAT-64-NEXT: sll $5, $16, 0
@@ -495,12 +495,12 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-64-NEXT: dsrl $1, $17, 32
; SOFT-FLOAT-64-NEXT: jal __mulsf3
; SOFT-FLOAT-64-NEXT: sll $5, $1, 0
-; SOFT-FLOAT-64-NEXT: move $4, $2
; SOFT-FLOAT-64-NEXT: dsll $1, $20, 32
; SOFT-FLOAT-64-NEXT: dsrl $17, $1, 32
; SOFT-FLOAT-64-NEXT: dsrl $1, $16, 32
-; SOFT-FLOAT-64-NEXT: jal __addsf3
; SOFT-FLOAT-64-NEXT: sll $5, $1, 0
+; SOFT-FLOAT-64-NEXT: jal __addsf3
+; SOFT-FLOAT-64-NEXT: move $4, $2
; SOFT-FLOAT-64-NEXT: # kill: def $r2 killed $r2 def $r2_64
; SOFT-FLOAT-64-NEXT: dsll $1, $2, 32
; SOFT-FLOAT-64-NEXT: or $3, $17, $1
@@ -548,9 +548,9 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-64R2-NEXT: sll $4, $21, 0
; SOFT-FLOAT-64R2-NEXT: jal __mulsf3
; SOFT-FLOAT-64R2-NEXT: sll $5, $20, 0
-; SOFT-FLOAT-64R2-NEXT: move $4, $2
-; SOFT-FLOAT-64R2-NEXT: jal __addsf3
; SOFT-FLOAT-64R2-NEXT: sll $5, $19, 0
+; SOFT-FLOAT-64R2-NEXT: jal __addsf3
+; SOFT-FLOAT-64R2-NEXT: move $4, $2
; SOFT-FLOAT-64R2-NEXT: move $22, $2
; SOFT-FLOAT-64R2-NEXT: sll $4, $18, 0
; SOFT-FLOAT-64R2-NEXT: jal __mulsf3
@@ -561,11 +561,11 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-64R2-NEXT: dsrl $1, $20, 32
; SOFT-FLOAT-64R2-NEXT: jal __mulsf3
; SOFT-FLOAT-64R2-NEXT: sll $5, $1, 0
-; SOFT-FLOAT-64R2-NEXT: move $4, $2
; SOFT-FLOAT-64R2-NEXT: dsrl $1, $19, 32
; SOFT-FLOAT-64R2-NEXT: sll $5, $1, 0
-; SOFT-FLOAT-64R2-NEXT: jal __addsf3
; SOFT-FLOAT-64R2-NEXT: dext $19, $22, 0, 32
+; SOFT-FLOAT-64R2-NEXT: jal __addsf3
+; SOFT-FLOAT-64R2-NEXT: move $4, $2
; SOFT-FLOAT-64R2-NEXT: # kill: def $r2 killed $r2 def $r2_64
; SOFT-FLOAT-64R2-NEXT: dsll $1, $2, 32
; SOFT-FLOAT-64R2-NEXT: sll $5, $16, 0
@@ -578,11 +578,11 @@ define <4 x float> @fmuladd_contract_v4f32(<4 x float> %a, <4 x float> %b, <4 x
; SOFT-FLOAT-64R2-NEXT: dsrl $1, $17, 32
; SOFT-FLOAT-64R2-NEXT: jal __mulsf3
; SOFT-FLOAT-64R2-NEXT: sll $5, $1, 0
-; SOFT-FLOAT-64R2-NEXT: move $4, $2
; SOFT-FLOAT-64R2-NEXT: dext $17, $20, 0, 32
; SOFT-FLOAT-64R2-NEXT: dsrl $1, $16, 32
-; SOFT-FLOAT-64R2-NEXT: jal __addsf3
; SOFT-FLOAT-64R2-NEXT: sll $5, $1, 0
+; SOFT-FLOAT-64R2-NEXT: jal __addsf3
+; SOFT-FLOAT-64R2-NEXT: move $4, $2
; SOFT-FLOAT-64R2-NEXT: # kill: def $r2 killed $r2 def $r2_64
; SOFT-FLOAT-64R2-NEXT: dsll $1, $2, 32
; SOFT-FLOAT-64R2-NEXT: or $3, $17, $1
@@ -637,9 +637,9 @@ define <4 x double> @fmuladd_contract_v4f64(<4 x double> %a, <4 x double> %b, <4
; SOFT-FLOAT-32-NEXT: lw $7, 124($sp)
; SOFT-FLOAT-32-NEXT: jal __muldf3
; SOFT-FLOAT-32-NEXT: nop
-; SOFT-FLOAT-32-NEXT: move $4, $2
; SOFT-FLOAT-32-NEXT: lw $6, 152($sp)
; SOFT-FLOAT-32-NEXT: lw $7, 156($sp)
+; SOFT-FLOAT-32-NEXT: move $4, $2
; SOFT-FLOAT-32-NEXT: jal __adddf3
; SOFT-FLOAT-32-NEXT: move $5, $3
; SOFT-FLOAT-32-NEXT: move $19, $2
@@ -649,9 +649,9 @@ define <4 x double> @fmuladd_contract_v4f64(<4 x double> %a, <4 x double> %b, <4
; SOFT-FLOAT-32-NEXT: lw $7, 132($sp)
; SOFT-FLOAT-32-NEXT: jal __muldf3
; SOFT-FLOAT-32-NEXT: move $20, $3
-; SOFT-FLOAT-32-NEXT: move $4, $2
; SOFT-FLOAT-32-NEXT: lw $6, 160($sp)
; SOFT-FLOAT-32-NEXT: lw $7, 164($sp)
+; SOFT-FLOAT-32-NEXT: move $4, $2
; SOFT-FLOAT-32-NEXT: jal __adddf3
; SOFT-FLOAT-32-NEXT: move $5, $3
; SOFT-FLOAT-32-NEXT: move $21, $2
@@ -661,8 +661,6 @@ define <4 x double> @fmuladd_contract_v4f64(<4 x double> %a, <4 x double> %b, <4
; SOFT-FLOAT-32-NEXT: lw $7, 116($sp)
; SOFT-FLOAT-32-NEXT: jal __muldf3
; SOFT-FLOAT-32-NEXT: move $22, $3
-; SOFT-FLOAT-32-NEXT: move $4, $2
-; SOFT-FLOAT-32-NEXT: move $5, $3
; SOFT-FLOAT-32-NEXT: lw $23, 140($sp)
; SOFT-FLOAT-32-NEXT: lw $fp, 136($sp)
; SOFT-FLOAT-32-NEXT: lw $17, 108($sp)
@@ -672,8 +670,10 @@ define <4 x double> @fmuladd_contract_v4f64(<4 x double> %a, <4 x double> %b, <4
; SOFT-FLOAT-32-NEXT: sw $22, 28($16)
; SOFT-FLOAT-32-NEXT: sw $21, 24($16)
; SOFT-FLOAT-32-NEXT: sw $20, 20($16)
-; SOFT-FLOAT-32-NEXT: jal __adddf3
; SOFT-FLOAT-32-NEXT: sw $19, 16($16)
+; SOFT-FLOAT-32-NEXT: move $4, $2
+; SOFT-FLOAT-32-NEXT: jal __adddf3
+; SOFT-FLOAT-32-NEXT: move $5, $3
; SOFT-FLOAT-32-NEXT: sw $3, 12($16)
; SOFT-FLOAT-32-NEXT: sw $2, 8($16)
; SOFT-FLOAT-32-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
@@ -734,9 +734,9 @@ define <4 x double> @fmuladd_contract_v4f64(<4 x double> %a, <4 x double> %b, <4
; SOFT-FLOAT-32R2-NEXT: lw $7, 124($sp)
; SOFT-FLOAT-32R2-NEXT: jal __muldf3
; SOFT-FLOAT-32R2-NEXT: nop
-; SOFT-FLOAT-32R2-NEXT: move $4, $2
; SOFT-FLOAT-32R2-NEXT: lw $6, 152($sp)
; SOFT-FLOAT-32R2-NEXT: lw $7, 156($sp)
+; SOFT-FLOAT-32R2-NEXT: move $4, $2
; SOFT-FLOAT-32R2-NEXT: jal __adddf3
; SOFT-FLOAT-32R2-NEXT: move $5, $3
; SOFT-FLOAT-32R2-NEXT: move $19, $2
@@ -746,9 +746,9 @@ define <4 x double> @fmuladd_contract_v4f64(<4 x double> %a, <4 x double> %b, <4
; SOFT-FLOAT-32R2-NEXT: lw $7, 132($sp)
; SOFT-FLOAT-32R2-NEXT: jal __muldf3
; SOFT-FLOAT-32R2-NEXT: move $20, $3
-; SOFT-FLOAT-32R2-NEXT: move $4, $2
; SOFT-FLOAT-32R2-NEXT: lw $6, 160($sp)
; SOFT-FLOAT-32R2-NEXT: lw $7, 164($sp)
+; SOFT-FLOAT-32R2-NEXT: move $4, $2
; SOFT-FLOAT-32R2-NEXT: jal __adddf3
; SOFT-FLOAT-32R2-NEXT: move $5, $3
; SOFT-FLOAT-32R2-NEXT: move $21, $2
@@ -758,8 +758,6 @@ define <4 x double> @fmuladd_contract_v4f64(<4 x double> %a, <4 x double> %b, <4
; SOFT-FLOAT-32R2-NEXT: lw $7, 116($sp)
; SOFT-FLOAT-32R2-NEXT: jal __muldf3
; SOFT-FLOAT-32R2-NEXT: move $22, $3
-; SOFT-FLOAT-32R2-NEXT: move $4, $2
-; SOFT-FLOAT-32R2-NEXT: move $5, $3
; SOFT-FLOAT-32R2-NEXT: lw $23, 140($sp)
; SOFT-FLOAT-32R2-NEXT: lw $fp, 136($sp)
; SOFT-FLOAT-32R2-NEXT: lw $17, 108($sp)
@@ -769,8 +767,10 @@ define <4 x double> @fmuladd_contract_v4f64(<4 x double> %a, <4 x double> %b, <4
; SOFT-FLOAT-32R2-NEXT: sw $22, 28($16)
; SOFT-FLOAT-32R2-NEXT: sw $21, 24($16)
; SOFT-FLOAT-32R2-NEXT: sw $20, 20($16)
-; SOFT-FLOAT-32R2-NEXT: jal __adddf3
; SOFT-FLOAT-32R2-NEXT: sw $19, 16($16)
+; SOFT-FLOAT-32R2-NEXT: move $4, $2
+; SOFT-FLOAT-32R2-NEXT: jal __adddf3
+; SOFT-FLOAT-32R2-NEXT: move $5, $3
; SOFT-FLOAT-32R2-NEXT: sw $3, 12($16)
; SOFT-FLOAT-32R2-NEXT: sw $2, 8($16)
; SOFT-FLOAT-32R2-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
@@ -841,12 +841,12 @@ define <4 x double> @fmuladd_contract_v4f64(<4 x double> %a, <4 x double> %b, <4
; SOFT-FLOAT-64-NEXT: move $4, $20
; SOFT-FLOAT-64-NEXT: jal __muldf3
; SOFT-FLOAT-64-NEXT: move $5, $17
-; SOFT-FLOAT-64-NEXT: move $4, $2
; SOFT-FLOAT-64-NEXT: ld $17, 72($sp)
; SOFT-FLOAT-64-NEXT: ld $5, 80($sp)
; SOFT-FLOAT-64-NEXT: sd $19, 24($16)
-; SOFT-FLOAT-64-NEXT: jal __adddf3
; SOFT-FLOAT-64-NEXT: sd $22, 16($16)
+; SOFT-FLOAT-64-NEXT: jal __adddf3
+; SOFT-FLOAT-64-NEXT: move $4, $2
; SOFT-FLOAT-64-NEXT: sd $2, 8($16)
; SOFT-FLOAT-64-NEXT: move $4, $21
; SOFT-FLOAT-64-NEXT: jal __muldf3
@@ -909,12 +909,12 @@ define <4 x double> @fmuladd_contract_v4f64(<4 x double> %a, <4 x double> %b, <4
; SOFT-FLOAT-64R2-NEXT: move $4, $20
; SOFT-FLOAT-64R2-NEXT: jal __muldf3
; SOFT-FLOAT-64R2-NEXT: move $5, $17
-; SOFT-FLOAT-64R2-NEXT: move $4, $2
; SOFT-FLOAT-64R2-NEXT: ld $17, 72($sp)
; SOFT-FLOAT-64R2-NEXT: ld $5, 80($sp)
; SOFT-FLOAT-64R2-NEXT: sd $19, 24($16)
-; SOFT-FLOAT-64R2-NEXT: jal __adddf3
; SOFT-FLOAT-64R2-NEXT: sd $22, 16($16)
+; SOFT-FLOAT-64R2-NEXT: jal __adddf3
+; SOFT-FLOAT-64R2-NEXT: move $4, $2
; SOFT-FLOAT-64R2-NEXT: sd $2, 8($16)
; SOFT-FLOAT-64R2-NEXT: move $4, $21
; SOFT-FLOAT-64R2-NEXT: jal __muldf3
diff --git a/llvm/test/CodeGen/Mips/funnel-shift-rot.ll b/llvm/test/CodeGen/Mips/funnel-shift-rot.ll
index 0522a06ff0429..09d596f56c265 100644
--- a/llvm/test/CodeGen/Mips/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/Mips/funnel-shift-rot.ll
@@ -327,8 +327,8 @@ define i32 @rotr_i32_shift_by_bitwidth(i32 %x) {
define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) {
; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth:
; CHECK: # %bb.0:
-; CHECK-NEXT: move $2, $4
; CHECK-NEXT: move $3, $5
+; CHECK-NEXT: move $2, $4
; CHECK-NEXT: move $4, $6
; CHECK-NEXT: jr $ra
; CHECK-NEXT: move $5, $7
@@ -339,8 +339,8 @@ define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) {
define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) {
; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth:
; CHECK: # %bb.0:
-; CHECK-NEXT: move $2, $4
; CHECK-NEXT: move $3, $5
+; CHECK-NEXT: move $2, $4
; CHECK-NEXT: move $4, $6
; CHECK-NEXT: jr $ra
; CHECK-NEXT: move $5, $7
diff --git a/llvm/test/CodeGen/Mips/funnel-shift.ll b/llvm/test/CodeGen/Mips/funnel-shift.ll
index da05ff845784f..ab3cfe609550d 100644
--- a/llvm/test/CodeGen/Mips/funnel-shift.ll
+++ b/llvm/test/CodeGen/Mips/funnel-shift.ll
@@ -518,8 +518,8 @@ define i32 @fshr_i32_shift_by_bitwidth(i32 %x, i32 %y) {
define <4 x i32> @fshl_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: fshl_v4i32_shift_by_bitwidth:
; CHECK: # %bb.0:
-; CHECK-NEXT: move $2, $4
; CHECK-NEXT: move $3, $5
+; CHECK-NEXT: move $2, $4
; CHECK-NEXT: move $4, $6
; CHECK-NEXT: jr $ra
; CHECK-NEXT: move $5, $7
diff --git a/llvm/test/CodeGen/Mips/ins.ll b/llvm/test/CodeGen/Mips/ins.ll
index 0492a5d1a9e75..1f7ec4023d3aa 100644
--- a/llvm/test/CodeGen/Mips/ins.ll
+++ b/llvm/test/CodeGen/Mips/ins.ll
@@ -7,9 +7,10 @@
define i32 @or_and_shl(i32 %a, i32 %b) {
; MIPS32R2-LABEL: or_and_shl:
; MIPS32R2: # %bb.0: # %entry
-; MIPS32R2-NEXT: ins $4, $5, 31, 1
-; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: ins $2, $5, 31, 1
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: nop
;
; MIPS64R2-LABEL: or_and_shl:
; MIPS64R2: # %bb.0: # %entry
@@ -28,9 +29,10 @@ entry:
define i32 @or_shl_and(i32 %a, i32 %b) {
; MIPS32R2-LABEL: or_shl_and:
; MIPS32R2: # %bb.0: # %entry
-; MIPS32R2-NEXT: ins $4, $5, 31, 1
-; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: ins $2, $5, 31, 1
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: nop
;
; MIPS64R2-LABEL: or_shl_and:
; MIPS64R2: # %bb.0: # %entry
@@ -49,18 +51,19 @@ entry:
define i64 @dinsm(i64 %a, i64 %b) {
; MIPS32R2-LABEL: dinsm:
; MIPS32R2: # %bb.0: # %entry
-; MIPS32R2-NEXT: ins $4, $6, 17, 15
+; MIPS32R2-NEXT: move $2, $4
; MIPS32R2-NEXT: srl $1, $6, 15
-; MIPS32R2-NEXT: sll $2, $7, 17
-; MIPS32R2-NEXT: or $3, $2, $1
+; MIPS32R2-NEXT: sll $3, $7, 17
+; MIPS32R2-NEXT: ins $2, $6, 17, 15
; MIPS32R2-NEXT: jr $ra
-; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: or $3, $3, $1
;
; MIPS64R2-LABEL: dinsm:
; MIPS64R2: # %bb.0: # %entry
-; MIPS64R2-NEXT: dinsm $4, $5, 17, 47
-; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
+; MIPS64R2-NEXT: dinsm $2, $5, 17, 47
+; MIPS64R2-NEXT: jr $ra
+; MIPS64R2-NEXT: nop
entry:
%shl = shl i64 %b, 17
%and = and i64 %a, 131071
@@ -71,16 +74,18 @@ entry:
define i64 @dinsu(i64 %a, i64 %b) {
; MIPS32R2-LABEL: dinsu:
; MIPS32R2: # %bb.0: # %entry
-; MIPS32R2-NEXT: ins $5, $6, 3, 29
+; MIPS32R2-NEXT: move $3, $5
; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: ins $3, $6, 3, 29
; MIPS32R2-NEXT: jr $ra
-; MIPS32R2-NEXT: move $3, $5
+; MIPS32R2-NEXT: nop
;
; MIPS64R2-LABEL: dinsu:
; MIPS64R2: # %bb.0: # %entry
-; MIPS64R2-NEXT: dinsu $4, $5, 35, 29
-; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
+; MIPS64R2-NEXT: dinsu $2, $5, 35, 29
+; MIPS64R2-NEXT: jr $ra
+; MIPS64R2-NEXT: nop
entry:
%shl = shl i64 %b, 35
%and = and i64 %a, 34359738367
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
index a21477acd5341..f908641592686 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/add.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
@@ -414,8 +414,8 @@ define signext i32 @add_i32_3(i32 signext %a) {
; R2-R6: addiu $2, $4, 3
- ; MMR6: addius5 $[[T0:[0-9]+]], 3
- ; MMR6: move $2, $[[T0]]
+ ; MMR6: move $[[T0:[0-9]+]], $4
+ ; MMR6: addius5 $[[T0]], 3
%r = add i32 3, %a
ret i32 %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/and.ll b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
index 87f7edb2b7132..7efd98a2936b9 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/and.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
@@ -66,8 +66,8 @@ define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
;
; MM32R3-LABEL: and_i1:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: and16 $4, $5
; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: and16 $2, $5
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i1:
@@ -115,8 +115,8 @@ define signext i8 @and_i8(i8 signext %a, i8 signext %b) {
;
; MM32R3-LABEL: and_i8:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: and16 $4, $5
; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: and16 $2, $5
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i8:
@@ -164,8 +164,8 @@ define signext i16 @and_i16(i16 signext %a, i16 signext %b) {
;
; MM32R3-LABEL: and_i16:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: and16 $4, $5
; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: and16 $2, $5
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i16:
@@ -210,8 +210,8 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
;
; MM32R3-LABEL: and_i32:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: and16 $4, $5
; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: and16 $2, $5
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i32:
@@ -259,10 +259,10 @@ define signext i64 @and_i64(i64 signext %a, i64 signext %b) {
;
; MM32R3-LABEL: and_i64:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: and16 $4, $6
-; MM32R3-NEXT: and16 $5, $7
-; MM32R3-NEXT: move $2, $4
; MM32R3-NEXT: move $3, $5
+; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: and16 $2, $6
+; MM32R3-NEXT: and16 $3, $7
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: and_i64:
@@ -668,16 +668,19 @@ define signext i1 @and_i1_31(i1 signext %b) {
;
; MIPS64-LABEL: and_i1_31:
; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: move $2, $4
;
; MIPS64R2-LABEL: and_i1_31:
; MIPS64R2: # %bb.0: # %entry
+; MIPS64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
;
; MIPS64R6-LABEL: and_i1_31:
; MIPS64R6: # %bb.0: # %entry
+; MIPS64R6-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: move $2, $4
;
@@ -961,16 +964,19 @@ define signext i1 @and_i1_255(i1 signext %b) {
;
; MIPS64-LABEL: and_i1_255:
; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: move $2, $4
;
; MIPS64R2-LABEL: and_i1_255:
; MIPS64R2: # %bb.0: # %entry
+; MIPS64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
;
; MIPS64R6-LABEL: and_i1_255:
; MIPS64R6: # %bb.0: # %entry
+; MIPS64R6-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: move $2, $4
;
@@ -1006,16 +1012,19 @@ define signext i8 @and_i8_255(i8 signext %b) {
;
; MIPS64-LABEL: and_i8_255:
; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: move $2, $4
;
; MIPS64R2-LABEL: and_i8_255:
; MIPS64R2: # %bb.0: # %entry
+; MIPS64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
;
; MIPS64R6-LABEL: and_i8_255:
; MIPS64R6: # %bb.0: # %entry
+; MIPS64R6-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: move $2, $4
;
@@ -1556,16 +1565,19 @@ define signext i1 @and_i1_65(i1 signext %b) {
;
; MIPS64-LABEL: and_i1_65:
; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: move $2, $4
;
; MIPS64R2-LABEL: and_i1_65:
; MIPS64R2: # %bb.0: # %entry
+; MIPS64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
;
; MIPS64R6-LABEL: and_i1_65:
; MIPS64R6: # %bb.0: # %entry
+; MIPS64R6-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: move $2, $4
;
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
index 2b8129acb91fc..d295f78ede022 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -53,21 +53,25 @@ define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
;
; MIPS3-LABEL: ashr_i1:
; MIPS3: # %bb.0: # %entry
+; MIPS3-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: move $2, $4
;
; MIPS64-LABEL: ashr_i1:
; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: move $2, $4
;
; MIPS64R2-LABEL: ashr_i1:
; MIPS64R2: # %bb.0: # %entry
+; MIPS64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
;
; MIPS64R6-LABEL: ashr_i1:
; MIPS64R6: # %bb.0: # %entry
+; MIPS64R6-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: move $2, $4
;
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
index 69b842c73db1b..1457ee32cee03 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -53,26 +53,31 @@ define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
;
; MIPS3-LABEL: lshr_i1:
; MIPS3: # %bb.0: # %entry
+; MIPS3-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: move $2, $4
;
; MIPS4-LABEL: lshr_i1:
; MIPS4: # %bb.0: # %entry
+; MIPS4-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS4-NEXT: jr $ra
; MIPS4-NEXT: move $2, $4
;
; MIPS64-LABEL: lshr_i1:
; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: move $2, $4
;
; MIPS64R2-LABEL: lshr_i1:
; MIPS64R2: # %bb.0: # %entry
+; MIPS64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
;
; MIPS64R6-LABEL: lshr_i1:
; MIPS64R6: # %bb.0: # %entry
+; MIPS64R6-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: move $2, $4
;
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
index 2735d53f5fe06..8d7ca0e796973 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -43,8 +43,8 @@ entry:
; 64R6: and $[[T0:[0-9]+]], $4, $5
- ; MM32R3: and16 $4, $5
; MM32R3: move $2, $4
+ ; MM32R3: and16 $2, $5
; MM32R6: and $[[T0:[0-9]+]], $4, $5
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/or.ll b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
index c595ff42086b2..4c68745013179 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
@@ -31,8 +31,8 @@ define signext i1 @or_i1(i1 signext %a, i1 signext %b) {
;
; MM32-LABEL: or_i1:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: or16 $4, $5
; MM32-NEXT: move $2, $4
+; MM32-NEXT: or16 $2, $5
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i1:
@@ -58,8 +58,8 @@ define signext i8 @or_i8(i8 signext %a, i8 signext %b) {
;
; MM32-LABEL: or_i8:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: or16 $4, $5
; MM32-NEXT: move $2, $4
+; MM32-NEXT: or16 $2, $5
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i8:
@@ -85,8 +85,8 @@ define signext i16 @or_i16(i16 signext %a, i16 signext %b) {
;
; MM32-LABEL: or_i16:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: or16 $4, $5
; MM32-NEXT: move $2, $4
+; MM32-NEXT: or16 $2, $5
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i16:
@@ -111,8 +111,8 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
;
; MM32-LABEL: or_i32:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: or16 $4, $5
; MM32-NEXT: move $2, $4
+; MM32-NEXT: or16 $2, $5
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i32:
@@ -138,10 +138,10 @@ define signext i64 @or_i64(i64 signext %a, i64 signext %b) {
;
; MM32-LABEL: or_i64:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: or16 $4, $6
-; MM32-NEXT: or16 $5, $7
-; MM32-NEXT: move $2, $4
; MM32-NEXT: move $3, $5
+; MM32-NEXT: move $2, $4
+; MM32-NEXT: or16 $2, $6
+; MM32-NEXT: or16 $3, $7
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i64:
@@ -208,6 +208,7 @@ define signext i1 @or_i1_4(i1 signext %b) {
;
; GP64-LABEL: or_i1_4:
; GP64: # %bb.0: # %entry
+; GP64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
;
@@ -304,9 +305,9 @@ entry:
define signext i64 @or_i64_4(i64 signext %b) {
; GP32-LABEL: or_i64_4:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $3, $5, 4
-; GP32-NEXT: jr $ra
; GP32-NEXT: move $2, $4
+; GP32-NEXT: jr $ra
+; GP32-NEXT: ori $3, $5, 4
;
; GP64-LABEL: or_i64_4:
; GP64: # %bb.0: # %entry
@@ -315,14 +316,14 @@ define signext i64 @or_i64_4(i64 signext %b) {
;
; MM32-LABEL: or_i64_4:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $3, $5, 4
; MM32-NEXT: move $2, $4
-; MM32-NEXT: jrc $ra
+; MM32-NEXT: jr $ra
+; MM32-NEXT: ori $3, $5, 4
;
; MM32R6-LABEL: or_i64_4:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $3, $5, 4
; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $3, $5, 4
; MM32R6-NEXT: jrc $ra
entry:
%r = or i64 4, %b
@@ -332,35 +333,32 @@ entry:
define signext i128 @or_i128_4(i128 signext %b) {
; GP32-LABEL: or_i128_4:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $1, $7, 4
-; GP32-NEXT: move $2, $4
; GP32-NEXT: move $3, $5
-; GP32-NEXT: move $4, $6
+; GP32-NEXT: move $2, $4
+; GP32-NEXT: ori $5, $7, 4
; GP32-NEXT: jr $ra
-; GP32-NEXT: move $5, $1
+; GP32-NEXT: move $4, $6
;
; GP64-LABEL: or_i128_4:
; GP64: # %bb.0: # %entry
-; GP64-NEXT: ori $3, $5, 4
-; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
+; GP64-NEXT: jr $ra
+; GP64-NEXT: ori $3, $5, 4
;
; MM32-LABEL: or_i128_4:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $1, $7, 4
-; MM32-NEXT: move $2, $4
; MM32-NEXT: move $3, $5
+; MM32-NEXT: move $2, $4
+; MM32-NEXT: ori $5, $7, 4
; MM32-NEXT: move $4, $6
-; MM32-NEXT: move $5, $1
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i128_4:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $1, $7, 4
-; MM32R6-NEXT: move $2, $4
; MM32R6-NEXT: move $3, $5
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $5, $7, 4
; MM32R6-NEXT: move $4, $6
-; MM32R6-NEXT: move $5, $1
; MM32R6-NEXT: jrc $ra
entry:
%r = or i128 4, %b
@@ -471,9 +469,9 @@ entry:
define signext i64 @or_i64_31(i64 signext %b) {
; GP32-LABEL: or_i64_31:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $3, $5, 31
-; GP32-NEXT: jr $ra
; GP32-NEXT: move $2, $4
+; GP32-NEXT: jr $ra
+; GP32-NEXT: ori $3, $5, 31
;
; GP64-LABEL: or_i64_31:
; GP64: # %bb.0: # %entry
@@ -482,14 +480,14 @@ define signext i64 @or_i64_31(i64 signext %b) {
;
; MM32-LABEL: or_i64_31:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $3, $5, 31
; MM32-NEXT: move $2, $4
-; MM32-NEXT: jrc $ra
+; MM32-NEXT: jr $ra
+; MM32-NEXT: ori $3, $5, 31
;
; MM32R6-LABEL: or_i64_31:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $3, $5, 31
; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $3, $5, 31
; MM32R6-NEXT: jrc $ra
entry:
%r = or i64 31, %b
@@ -499,35 +497,32 @@ entry:
define signext i128 @or_i128_31(i128 signext %b) {
; GP32-LABEL: or_i128_31:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $1, $7, 31
-; GP32-NEXT: move $2, $4
; GP32-NEXT: move $3, $5
-; GP32-NEXT: move $4, $6
+; GP32-NEXT: move $2, $4
+; GP32-NEXT: ori $5, $7, 31
; GP32-NEXT: jr $ra
-; GP32-NEXT: move $5, $1
+; GP32-NEXT: move $4, $6
;
; GP64-LABEL: or_i128_31:
; GP64: # %bb.0: # %entry
-; GP64-NEXT: ori $3, $5, 31
-; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
+; GP64-NEXT: jr $ra
+; GP64-NEXT: ori $3, $5, 31
;
; MM32-LABEL: or_i128_31:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $1, $7, 31
-; MM32-NEXT: move $2, $4
; MM32-NEXT: move $3, $5
+; MM32-NEXT: move $2, $4
+; MM32-NEXT: ori $5, $7, 31
; MM32-NEXT: move $4, $6
-; MM32-NEXT: move $5, $1
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i128_31:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $1, $7, 31
-; MM32R6-NEXT: move $2, $4
; MM32R6-NEXT: move $3, $5
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $5, $7, 31
; MM32R6-NEXT: move $4, $6
-; MM32R6-NEXT: move $5, $1
; MM32R6-NEXT: jrc $ra
entry:
%r = or i128 31, %b
@@ -638,9 +633,9 @@ entry:
define signext i64 @or_i64_255(i64 signext %b) {
; GP32-LABEL: or_i64_255:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $3, $5, 255
-; GP32-NEXT: jr $ra
; GP32-NEXT: move $2, $4
+; GP32-NEXT: jr $ra
+; GP32-NEXT: ori $3, $5, 255
;
; GP64-LABEL: or_i64_255:
; GP64: # %bb.0: # %entry
@@ -649,14 +644,14 @@ define signext i64 @or_i64_255(i64 signext %b) {
;
; MM32-LABEL: or_i64_255:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $3, $5, 255
; MM32-NEXT: move $2, $4
-; MM32-NEXT: jrc $ra
+; MM32-NEXT: jr $ra
+; MM32-NEXT: ori $3, $5, 255
;
; MM32R6-LABEL: or_i64_255:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $3, $5, 255
; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $3, $5, 255
; MM32R6-NEXT: jrc $ra
entry:
%r = or i64 255, %b
@@ -666,35 +661,32 @@ entry:
define signext i128 @or_i128_255(i128 signext %b) {
; GP32-LABEL: or_i128_255:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $1, $7, 255
-; GP32-NEXT: move $2, $4
; GP32-NEXT: move $3, $5
-; GP32-NEXT: move $4, $6
+; GP32-NEXT: move $2, $4
+; GP32-NEXT: ori $5, $7, 255
; GP32-NEXT: jr $ra
-; GP32-NEXT: move $5, $1
+; GP32-NEXT: move $4, $6
;
; GP64-LABEL: or_i128_255:
; GP64: # %bb.0: # %entry
-; GP64-NEXT: ori $3, $5, 255
-; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
+; GP64-NEXT: jr $ra
+; GP64-NEXT: ori $3, $5, 255
;
; MM32-LABEL: or_i128_255:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $1, $7, 255
-; MM32-NEXT: move $2, $4
; MM32-NEXT: move $3, $5
+; MM32-NEXT: move $2, $4
+; MM32-NEXT: ori $5, $7, 255
; MM32-NEXT: move $4, $6
-; MM32-NEXT: move $5, $1
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i128_255:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $1, $7, 255
-; MM32R6-NEXT: move $2, $4
; MM32R6-NEXT: move $3, $5
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $5, $7, 255
; MM32R6-NEXT: move $4, $6
-; MM32R6-NEXT: move $5, $1
; MM32R6-NEXT: jrc $ra
entry:
%r = or i128 255, %b
@@ -709,6 +701,7 @@ define signext i1 @or_i1_32768(i1 signext %b) {
;
; GP64-LABEL: or_i1_32768:
; GP64: # %bb.0: # %entry
+; GP64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
;
@@ -734,6 +727,7 @@ define signext i8 @or_i8_32768(i8 signext %b) {
;
; GP64-LABEL: or_i8_32768:
; GP64: # %bb.0: # %entry
+; GP64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
;
@@ -809,9 +803,9 @@ entry:
define signext i64 @or_i64_32768(i64 signext %b) {
; GP32-LABEL: or_i64_32768:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $3, $5, 32768
-; GP32-NEXT: jr $ra
; GP32-NEXT: move $2, $4
+; GP32-NEXT: jr $ra
+; GP32-NEXT: ori $3, $5, 32768
;
; GP64-LABEL: or_i64_32768:
; GP64: # %bb.0: # %entry
@@ -820,14 +814,14 @@ define signext i64 @or_i64_32768(i64 signext %b) {
;
; MM32-LABEL: or_i64_32768:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $3, $5, 32768
; MM32-NEXT: move $2, $4
-; MM32-NEXT: jrc $ra
+; MM32-NEXT: jr $ra
+; MM32-NEXT: ori $3, $5, 32768
;
; MM32R6-LABEL: or_i64_32768:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $3, $5, 32768
; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $3, $5, 32768
; MM32R6-NEXT: jrc $ra
entry:
%r = or i64 32768, %b
@@ -837,35 +831,32 @@ entry:
define signext i128 @or_i128_32768(i128 signext %b) {
; GP32-LABEL: or_i128_32768:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $1, $7, 32768
-; GP32-NEXT: move $2, $4
; GP32-NEXT: move $3, $5
-; GP32-NEXT: move $4, $6
+; GP32-NEXT: move $2, $4
+; GP32-NEXT: ori $5, $7, 32768
; GP32-NEXT: jr $ra
-; GP32-NEXT: move $5, $1
+; GP32-NEXT: move $4, $6
;
; GP64-LABEL: or_i128_32768:
; GP64: # %bb.0: # %entry
-; GP64-NEXT: ori $3, $5, 32768
-; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
+; GP64-NEXT: jr $ra
+; GP64-NEXT: ori $3, $5, 32768
;
; MM32-LABEL: or_i128_32768:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $1, $7, 32768
-; MM32-NEXT: move $2, $4
; MM32-NEXT: move $3, $5
+; MM32-NEXT: move $2, $4
+; MM32-NEXT: ori $5, $7, 32768
; MM32-NEXT: move $4, $6
-; MM32-NEXT: move $5, $1
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i128_32768:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $1, $7, 32768
-; MM32R6-NEXT: move $2, $4
; MM32R6-NEXT: move $3, $5
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $5, $7, 32768
; MM32R6-NEXT: move $4, $6
-; MM32R6-NEXT: move $5, $1
; MM32R6-NEXT: jrc $ra
entry:
%r = or i128 32768, %b
@@ -976,9 +967,9 @@ entry:
define signext i64 @or_i64_65(i64 signext %b) {
; GP32-LABEL: or_i64_65:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $3, $5, 65
-; GP32-NEXT: jr $ra
; GP32-NEXT: move $2, $4
+; GP32-NEXT: jr $ra
+; GP32-NEXT: ori $3, $5, 65
;
; GP64-LABEL: or_i64_65:
; GP64: # %bb.0: # %entry
@@ -987,14 +978,14 @@ define signext i64 @or_i64_65(i64 signext %b) {
;
; MM32-LABEL: or_i64_65:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $3, $5, 65
; MM32-NEXT: move $2, $4
-; MM32-NEXT: jrc $ra
+; MM32-NEXT: jr $ra
+; MM32-NEXT: ori $3, $5, 65
;
; MM32R6-LABEL: or_i64_65:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $3, $5, 65
; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $3, $5, 65
; MM32R6-NEXT: jrc $ra
entry:
%r = or i64 65, %b
@@ -1004,35 +995,32 @@ entry:
define signext i128 @or_i128_65(i128 signext %b) {
; GP32-LABEL: or_i128_65:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $1, $7, 65
-; GP32-NEXT: move $2, $4
; GP32-NEXT: move $3, $5
-; GP32-NEXT: move $4, $6
+; GP32-NEXT: move $2, $4
+; GP32-NEXT: ori $5, $7, 65
; GP32-NEXT: jr $ra
-; GP32-NEXT: move $5, $1
+; GP32-NEXT: move $4, $6
;
; GP64-LABEL: or_i128_65:
; GP64: # %bb.0: # %entry
-; GP64-NEXT: ori $3, $5, 65
-; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
+; GP64-NEXT: jr $ra
+; GP64-NEXT: ori $3, $5, 65
;
; MM32-LABEL: or_i128_65:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $1, $7, 65
-; MM32-NEXT: move $2, $4
; MM32-NEXT: move $3, $5
+; MM32-NEXT: move $2, $4
+; MM32-NEXT: ori $5, $7, 65
; MM32-NEXT: move $4, $6
-; MM32-NEXT: move $5, $1
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i128_65:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $1, $7, 65
-; MM32R6-NEXT: move $2, $4
; MM32R6-NEXT: move $3, $5
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $5, $7, 65
; MM32R6-NEXT: move $4, $6
-; MM32R6-NEXT: move $5, $1
; MM32R6-NEXT: jrc $ra
entry:
%r = or i128 65, %b
@@ -1047,6 +1035,7 @@ define signext i1 @or_i1_256(i1 signext %b) {
;
; GP64-LABEL: or_i1_256:
; GP64: # %bb.0: # %entry
+; GP64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
;
@@ -1072,6 +1061,7 @@ define signext i8 @or_i8_256(i8 signext %b) {
;
; GP64-LABEL: or_i8_256:
; GP64: # %bb.0: # %entry
+; GP64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
;
@@ -1143,9 +1133,9 @@ entry:
define signext i64 @or_i64_256(i64 signext %b) {
; GP32-LABEL: or_i64_256:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $3, $5, 256
-; GP32-NEXT: jr $ra
; GP32-NEXT: move $2, $4
+; GP32-NEXT: jr $ra
+; GP32-NEXT: ori $3, $5, 256
;
; GP64-LABEL: or_i64_256:
; GP64: # %bb.0: # %entry
@@ -1154,14 +1144,14 @@ define signext i64 @or_i64_256(i64 signext %b) {
;
; MM32-LABEL: or_i64_256:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $3, $5, 256
; MM32-NEXT: move $2, $4
-; MM32-NEXT: jrc $ra
+; MM32-NEXT: jr $ra
+; MM32-NEXT: ori $3, $5, 256
;
; MM32R6-LABEL: or_i64_256:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $3, $5, 256
; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $3, $5, 256
; MM32R6-NEXT: jrc $ra
entry:
%r = or i64 256, %b
@@ -1171,35 +1161,32 @@ entry:
define signext i128 @or_i128_256(i128 signext %b) {
; GP32-LABEL: or_i128_256:
; GP32: # %bb.0: # %entry
-; GP32-NEXT: ori $1, $7, 256
-; GP32-NEXT: move $2, $4
; GP32-NEXT: move $3, $5
-; GP32-NEXT: move $4, $6
+; GP32-NEXT: move $2, $4
+; GP32-NEXT: ori $5, $7, 256
; GP32-NEXT: jr $ra
-; GP32-NEXT: move $5, $1
+; GP32-NEXT: move $4, $6
;
; GP64-LABEL: or_i128_256:
; GP64: # %bb.0: # %entry
-; GP64-NEXT: ori $3, $5, 256
-; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
+; GP64-NEXT: jr $ra
+; GP64-NEXT: ori $3, $5, 256
;
; MM32-LABEL: or_i128_256:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: ori $1, $7, 256
-; MM32-NEXT: move $2, $4
; MM32-NEXT: move $3, $5
+; MM32-NEXT: move $2, $4
+; MM32-NEXT: ori $5, $7, 256
; MM32-NEXT: move $4, $6
-; MM32-NEXT: move $5, $1
; MM32-NEXT: jrc $ra
;
; MM32R6-LABEL: or_i128_256:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: ori $1, $7, 256
-; MM32R6-NEXT: move $2, $4
; MM32R6-NEXT: move $3, $5
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: ori $5, $7, 256
; MM32R6-NEXT: move $4, $6
-; MM32R6-NEXT: move $5, $1
; MM32R6-NEXT: jrc $ra
entry:
%r = or i128 256, %b
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
index 91a45a88df90a..895307e5f8bb5 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
@@ -59,16 +59,19 @@ define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
;
; MIPS3-LABEL: sdiv_i1:
; MIPS3: # %bb.0: # %entry
+; MIPS3-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: move $2, $4
;
; GP64-LABEL: sdiv_i1:
; GP64: # %bb.0: # %entry
+; GP64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
;
; GP64R6-LABEL: sdiv_i1:
; GP64R6: # %bb.0: # %entry
+; GP64R6-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; GP64R6-NEXT: jr $ra
; GP64R6-NEXT: move $2, $4
;
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
index 20a06139a02b1..d710a2d089875 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
@@ -37,24 +37,30 @@ entry:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2-M3: move $5, $6
+ ; M2: move $2, $5
+ ; M2: move $2, $6
+ ; M3: nop
+ ; M3: jr $ra
+ ; M3: move $2, $6
; M2-M3: [[BB0]]:
; M2-M3: jr $ra
- ; M2-M3: move $2, $5
+ ; M2: nop
+ ; M3: move $2, $5
- ; CMOV: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV: movn $6, $5, $[[T0]]
; CMOV: move $2, $6
+ ; CMOV: andi $[[T0:[0-9]+]], $4, 1
+ ; CMOV: jr $ra
+ ; CMOV: movn $2, $5, $[[T0]]
; SEL: andi $[[T0:[0-9]+]], $4, 1
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
; SEL: or $2, $[[T2]], $[[T1]]
+ ; MM32R3: move $2, $6
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
- ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
- ; MM32R3: move $2, $[[T1]]
+ ; MM32R3: jr $ra
+ ; MM32R3: movn $2, $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
@@ -73,24 +79,30 @@ entry:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2-M3: move $5, $6
+ ; M2: move $2, $5
+ ; M2: move $2, $6
+ ; M3: nop
+ ; M3: jr $ra
+ ; M3: move $2, $6
; M2-M3: [[BB0]]:
; M2-M3: jr $ra
- ; M2-M3: move $2, $5
+ ; M2: nop
+ ; M3: move $2, $5
- ; CMOV: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV: movn $6, $5, $[[T0]]
; CMOV: move $2, $6
+ ; CMOV: andi $[[T0:[0-9]+]], $4, 1
+ ; CMOV: jr $ra
+ ; CMOV: movn $2, $5, $[[T0]]
; SEL: andi $[[T0:[0-9]+]], $4, 1
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
; SEL: or $2, $[[T2]], $[[T1]]
+ ; MM32R3: move $2, $6
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
- ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
- ; MM32R3: move $2, $[[T1]]
+ ; MM32R3: jr $ra
+ ; MM32R3: movn $2, $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
@@ -109,15 +121,22 @@ entry:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2-M3: move $5, $6
+ ; M2: move $2, $5
+ ; M2: move $2, $6
+ ; M3: nop
+ ; M3: move $5, $6
; M2-M3: [[BB0]]:
; M2-M3: jr $ra
+ ; M2: nop
; M3: sll $2, $5, 0
- ; CMOV: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV: movn $6, $5, $[[T0]]
- ; CMOV-64:sll $2, $6, 0
+ ; CMOV-32: move $2, $6
+ ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
+ ; CMOV-32: jr $ra
+ ; CMOV-32: movn $2, $5, $[[T0]]
+ ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
+ ; CMOV-64: movn $6, $5, $[[T0]]
+ ; CMOV-64: sll $2, $6, 0
; SEL: andi $[[T0:[0-9]+]], $4, 1
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
@@ -125,9 +144,10 @@ entry:
; SEL: or $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; SEL-64: sll $2, $[[T3]], 0
+ ; MM32R3: move $2, $6
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
- ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
- ; MM32R3: move $2, $[[T1]]
+ ; MM32R3: jr $ra
+ ; MM32R3: movn $2, $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
@@ -143,19 +163,24 @@ define signext i64 @tst_select_i1_i64(i1 signext %s,
entry:
; ALL-LABEL: tst_select_i1_i64:
+ ; M2: move $3, $7
; M2: andi $[[T0:[0-9]+]], $4, 1
- ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
+ ; M2: beqz $[[T0]], $[[BB0:BB[0-9_]+]]
+ ; M2: move $2, $6
+ ; FIXME: This branch is redundant
+ ; M2: beqz $[[T0]], $[[BB1:BB[0-9_]+]]
+ ; M2: nop
+ ; M2: $[[BB2:BB[0-9_]+]]:
+ ; M2: jr $ra
; M2: nop
- ; M2: lw $[[T1:[0-9]+]], 16($sp)
; M2: $[[BB0]]:
- ; FIXME: This branch is redundant
- ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
+ ; M2: lw $[[T1:[0-9]+]], 16($sp)
+ ; M2: bnez $[[T0]], $[[BB2]]
; M2: nop
- ; M2: lw $[[T2:[0-9]+]], 20($sp)
; M2: $[[BB1]]:
- ; M2: move $2, $[[T1]]
+ ; M2: lw $[[T2:[0-9]+]], 20($sp)
; M2: jr $ra
- ; M2: move $3, $[[T2]]
+ ; M2: nop
; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
; CMOV-32: lw $2, 16($sp)
@@ -175,15 +200,16 @@ entry:
; M3: andi $[[T0:[0-9]+]], $4, 1
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
- ; M3: nop
- ; M3: move $5, $6
+ ; M3: move $2, $5
+ ; M3: move $2, $6
; M3: [[BB0]]:
; M3: jr $ra
- ; M3: move $2, $5
+ ; M3: nop
- ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV-64: movn $6, $5, $[[T0]]
; CMOV-64: move $2, $6
+ ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
+ ; CMOV-64: jr $ra
+ ; CMOV-64: movn $2, $5, $[[T0]]
; SEL-64: andi $[[T0:[0-9]+]], $4, 1
; FIXME: This shift is redundant
@@ -233,11 +259,11 @@ define ptr @tst_select_word_cst(ptr %a, ptr %b) {
; M3: [[BB0]]:
; M3: jr $ra
+ ; CMOV-32: move $2, $4
; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1
; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
- ; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]]
; CMOV-32: jr $ra
- ; CMOV-32: move $2, $[[T2]]
+ ; CMOV-32: movn $2, $zero, $[[T1]]
; SEL-32: addiu $[[T0:[0-9]+]], $zero, -1
; SEL-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
@@ -245,10 +271,11 @@ define ptr @tst_select_word_cst(ptr %a, ptr %b) {
; SEL-32: jr $ra
; SEL-32: seleqz $2, $4, $[[T2]]
+ ; CMOV-64: move $2, $4
; CMOV-64: daddiu $[[T0:[0-9]+]], $zero, -1
; CMOV-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
- ; CMOV-64: movn $[[T2:[0-9]+]], $zero, $[[T1]]
- ; CMOV-64: move $2, $[[T2]]
+ ; CMOV-64: jr $ra
+ ; CMOV-64: movn $2, $zero, $[[T1]]
; SEL-64: daddiu $[[T0:[0-9]+]], $zero, -1
; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
@@ -257,11 +284,12 @@ define ptr @tst_select_word_cst(ptr %a, ptr %b) {
; SEL-64: sll $[[T2]], $[[T2]], 0
; SEL-64: seleqz $2, $4, $[[T2]]
+ ; MM32R3: move $2, $4
; MM32R3: li16 $[[T0:[0-9]+]], -1
; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]]
; MM32R3: li16 $[[T2:[0-9]+]], 0
- ; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]] # <MCInst #{{[0-9]+}} MOVN_I_MM
- ; MM32R3: move $2, $[[T3]]
+ ; MM32R3: jr $ra
+ ; MM32R3: movn $2, $[[T2]], $[[T1]] # <MCInst #{{[0-9]+}} MOVN_I_MM
; MM32R6: li16 $[[T0:[0-9]+]], -1
; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]]
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
index 394890a9dcc7c..ab5791500d54d 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -53,26 +53,31 @@ define signext i1 @shl_i1(i1 signext %a, i1 signext %b) {
;
; MIPS3-LABEL: shl_i1:
; MIPS3: # %bb.0: # %entry
+; MIPS3-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: move $2, $4
;
; MIPS4-LABEL: shl_i1:
; MIPS4: # %bb.0: # %entry
+; MIPS4-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS4-NEXT: jr $ra
; MIPS4-NEXT: move $2, $4
;
; MIPS64-LABEL: shl_i1:
; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: move $2, $4
;
; MIPS64R2-LABEL: shl_i1:
; MIPS64R2: # %bb.0: # %entry
+; MIPS64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
;
; MIPS64R6-LABEL: shl_i1:
; MIPS64R6: # %bb.0: # %entry
+; MIPS64R6-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: move $2, $4
;
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
index b15e5869f3584..6e44d6c5b3a43 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
@@ -59,16 +59,19 @@ define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
;
; MIPS3-LABEL: udiv_i1:
; MIPS3: # %bb.0: # %entry
+; MIPS3-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: move $2, $4
;
; GP64-LABEL: udiv_i1:
; GP64: # %bb.0: # %entry
+; GP64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; GP64-NEXT: jr $ra
; GP64-NEXT: move $2, $4
;
; GP64R6-LABEL: udiv_i1:
; GP64R6: # %bb.0: # %entry
+; GP64R6-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; GP64R6-NEXT: jr $ra
; GP64R6-NEXT: move $2, $4
;
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/xor.ll b/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
index ec9a204b2b431..ea13178a8b76a 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
@@ -63,8 +63,8 @@ define signext i1 @xor_i1(i1 signext %a, i1 signext %b) {
;
; MM32R3-LABEL: xor_i1:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: xor16 $4, $5
; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: xor16 $2, $5
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: xor_i1:
@@ -112,8 +112,8 @@ define signext i8 @xor_i8(i8 signext %a, i8 signext %b) {
;
; MM32R3-LABEL: xor_i8:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: xor16 $4, $5
; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: xor16 $2, $5
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: xor_i8:
@@ -161,8 +161,8 @@ define signext i16 @xor_i16(i16 signext %a, i16 signext %b) {
;
; MM32R3-LABEL: xor_i16:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: xor16 $4, $5
; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: xor16 $2, $5
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: xor_i16:
@@ -207,8 +207,8 @@ define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
;
; MM32R3-LABEL: xor_i32:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: xor16 $4, $5
; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: xor16 $2, $5
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: xor_i32:
@@ -256,10 +256,10 @@ define signext i64 @xor_i64(i64 signext %a, i64 signext %b) {
;
; MM32R3-LABEL: xor_i64:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: xor16 $4, $6
-; MM32R3-NEXT: xor16 $5, $7
-; MM32R3-NEXT: move $2, $4
; MM32R3-NEXT: move $3, $5
+; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: xor16 $2, $6
+; MM32R3-NEXT: xor16 $3, $7
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: xor_i64:
@@ -372,16 +372,19 @@ define signext i1 @xor_i1_4(i1 signext %b) {
;
; MIPS64-LABEL: xor_i1_4:
; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: move $2, $4
;
; MIPS64R2-LABEL: xor_i1_4:
; MIPS64R2: # %bb.0: # %entry
+; MIPS64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
;
; MIPS64R6-LABEL: xor_i1_4:
; MIPS64R6: # %bb.0: # %entry
+; MIPS64R6-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: move $2, $4
;
@@ -537,21 +540,21 @@ entry:
define signext i64 @xor_i64_4(i64 signext %b) {
; MIPS-LABEL: xor_i64_4:
; MIPS: # %bb.0: # %entry
-; MIPS-NEXT: xori $3, $5, 4
-; MIPS-NEXT: jr $ra
; MIPS-NEXT: move $2, $4
+; MIPS-NEXT: jr $ra
+; MIPS-NEXT: xori $3, $5, 4
;
; MIPS32R2-LABEL: xor_i64_4:
; MIPS32R2: # %bb.0: # %entry
-; MIPS32R2-NEXT: xori $3, $5, 4
-; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: xori $3, $5, 4
;
; MIPS32R6-LABEL: xor_i64_4:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: xori $3, $5, 4
-; MIPS32R6-NEXT: jr $ra
; MIPS32R6-NEXT: move $2, $4
+; MIPS32R6-NEXT: jr $ra
+; MIPS32R6-NEXT: xori $3, $5, 4
;
; MIPS64-LABEL: xor_i64_4:
; MIPS64: # %bb.0: # %entry
@@ -570,14 +573,14 @@ define signext i64 @xor_i64_4(i64 signext %b) {
;
; MM32R3-LABEL: xor_i64_4:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: xori $3, $5, 4
; MM32R3-NEXT: move $2, $4
-; MM32R3-NEXT: jrc $ra
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: xori $3, $5, 4
;
; MM32R6-LABEL: xor_i64_4:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: xori $3, $5, 4
; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: xori $3, $5, 4
; MM32R6-NEXT: jrc $ra
entry:
%r = xor i64 4, %b
@@ -587,65 +590,60 @@ entry:
define signext i128 @xor_i128_4(i128 signext %b) {
; MIPS-LABEL: xor_i128_4:
; MIPS: # %bb.0: # %entry
-; MIPS-NEXT: xori $1, $7, 4
-; MIPS-NEXT: move $2, $4
; MIPS-NEXT: move $3, $5
-; MIPS-NEXT: move $4, $6
+; MIPS-NEXT: move $2, $4
+; MIPS-NEXT: xori $5, $7, 4
; MIPS-NEXT: jr $ra
-; MIPS-NEXT: move $5, $1
+; MIPS-NEXT: move $4, $6
;
; MIPS32R2-LABEL: xor_i128_4:
; MIPS32R2: # %bb.0: # %entry
-; MIPS32R2-NEXT: xori $1, $7, 4
-; MIPS32R2-NEXT: move $2, $4
; MIPS32R2-NEXT: move $3, $5
-; MIPS32R2-NEXT: move $4, $6
+; MIPS32R2-NEXT: move $2, $4
+; MIPS32R2-NEXT: xori $5, $7, 4
; MIPS32R2-NEXT: jr $ra
-; MIPS32R2-NEXT: move $5, $1
+; MIPS32R2-NEXT: move $4, $6
;
; MIPS32R6-LABEL: xor_i128_4:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: xori $1, $7, 4
-; MIPS32R6-NEXT: move $2, $4
; MIPS32R6-NEXT: move $3, $5
-; MIPS32R6-NEXT: move $4, $6
+; MIPS32R6-NEXT: move $2, $4
+; MIPS32R6-NEXT: xori $5, $7, 4
; MIPS32R6-NEXT: jr $ra
-; MIPS32R6-NEXT: move $5, $1
+; MIPS32R6-NEXT: move $4, $6
;
; MIPS64-LABEL: xor_i128_4:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: xori $3, $5, 4
-; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: move $2, $4
+; MIPS64-NEXT: jr $ra
+; MIPS64-NEXT: xori $3, $5, 4
;
; MIPS64R2-LABEL: xor_i128_4:
; MIPS64R2: # %bb.0: # %entry
-; MIPS64R2-NEXT: xori $3, $5, 4
-; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
+; MIPS64R2-NEXT: jr $ra
+; MIPS64R2-NEXT: xori $3, $5, 4
;
; MIPS64R6-LABEL: xor_i128_4:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: xori $3, $5, 4
-; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: move $2, $4
+; MIPS64R6-NEXT: jr $ra
+; MIPS64R6-NEXT: xori $3, $5, 4
;
; MM32R3-LABEL: xor_i128_4:
; MM32R3: # %bb.0: # %entry
-; MM32R3-NEXT: xori $1, $7, 4
-; MM32R3-NEXT: move $2, $4
; MM32R3-NEXT: move $3, $5
+; MM32R3-NEXT: move $2, $4
+; MM32R3-NEXT: xori $5, $7, 4
; MM32R3-NEXT: move $4, $6
-; MM32R3-NEXT: move $5, $1
; MM32R3-NEXT: jrc $ra
;
; MM32R6-LABEL: xor_i128_4:
; MM32R6: # %bb.0: # %entry
-; MM32R6-NEXT: xori $1, $7, 4
-; MM32R6-NEXT: move $2, $4
; MM32R6-NEXT: move $3, $5
+; MM32R6-NEXT: move $2, $4
+; MM32R6-NEXT: xori $5, $7, 4
; MM32R6-NEXT: move $4, $6
-; MM32R6-NEXT: move $5, $1
; MM32R6-NEXT: jrc $ra
entry:
%r = xor i128 4, %b
diff --git a/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll b/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll
index 20d64fc216b79..e643c10630888 100644
--- a/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll
+++ b/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -O3 -filetype=obj < %s | llvm-objdump -s -j .gcc_except_table - | FileCheck %s
; CHECK: Contents of section .gcc_except_table:
-; CHECK-NEXT: 0000 ff9b1501 0c001000 00100e1e 011e1800
+; CHECK-NEXT: 0000 ff9b1501 0c000e00 000e101e 011e1800
; CHECK-NEXT: 0010 00010000 00000000
@_ZTIi = external constant ptr
diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll
index fb150094d5678..0cf6e7198c5e2 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128.ll
@@ -2780,9 +2780,9 @@ entry:
define fp128 @select_LD(i32 signext %a, i64, fp128 %b, fp128 %c) {
; C_CC_FMT-LABEL: select_LD:
; C_CC_FMT: # %bb.0: # %entry
-; C_CC_FMT-NEXT: movn $8, $6, $4
-; C_CC_FMT-NEXT: movn $9, $7, $4
; C_CC_FMT-NEXT: move $2, $8
+; C_CC_FMT-NEXT: movn $2, $6, $4
+; C_CC_FMT-NEXT: movn $9, $7, $4
; C_CC_FMT-NEXT: move $4, $9
; C_CC_FMT-NEXT: jr $ra
; C_CC_FMT-NEXT: nop
diff --git a/llvm/test/CodeGen/Mips/mips64-sret.ll b/llvm/test/CodeGen/Mips/mips64-sret.ll
index 4c05ec097b068..16f5e52757e10 100644
--- a/llvm/test/CodeGen/Mips/mips64-sret.ll
+++ b/llvm/test/CodeGen/Mips/mips64-sret.ll
@@ -3,9 +3,10 @@
define void @foo(ptr noalias sret(i32) %agg.result) nounwind {
entry:
; CHECK-LABEL: foo:
-; CHECK: sw {{.*}}, 0($4)
+; CHECK: move $2, $4
+; CHECK: addiu $1, $zero, 42
; CHECK: jr $ra
-; CHECK-NEXT: move $2, $4
+; CHECK: sw $1, 0($4)
store i32 42, ptr %agg.result
ret void
@@ -14,9 +15,9 @@ entry:
define void @bar(i32 signext %v, ptr noalias sret(i32) %agg.result) nounwind {
entry:
; CHECK-LABEL: bar:
-; CHECK: sw $4, 0($5)
+; CHECK: move $2, $5
; CHECK: jr $ra
-; CHECK-NEXT: move $2, $5
+; CHECK: sw $4, 0($5)
store i32 %v, ptr %agg.result
ret void
diff --git a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
index f509f49a341a9..464c3dff71d3c 100644
--- a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -27,10 +27,10 @@ entry:
; CHECK-LABEL: va1:
; CHECK: addiu $sp, $sp, -16
+; CHECK: move $2, $5
; CHECK: sw $7, 28($sp)
; CHECK: sw $6, 24($sp)
; CHECK: sw $5, 20($sp)
-; CHECK: move $2, $5
}
; check whether the variable double argument will be accessed from the 8-byte
@@ -77,9 +77,9 @@ entry:
; CHECK-LABEL: va3:
; CHECK: addiu $sp, $sp, -16
+; CHECK: move $2, $6
; CHECK: sw $7, 28($sp)
; CHECK: sw $6, 24($sp)
-; CHECK: move $2, $6
}
; double
@@ -124,8 +124,8 @@ entry:
; CHECK-LABEL: va5:
; CHECK: addiu $sp, $sp, -24
-; CHECK: sw $7, 36($sp)
; CHECK: move $2, $7
+; CHECK: sw $7, 36($sp)
}
; double
diff --git a/llvm/test/CodeGen/Mips/select.ll b/llvm/test/CodeGen/Mips/select.ll
index eee1921d1b894..588ea38d7890b 100644
--- a/llvm/test/CodeGen/Mips/select.ll
+++ b/llvm/test/CodeGen/Mips/select.ll
@@ -12,15 +12,15 @@
define i32 @i32_icmp_ne_i32_val(i32 signext %s, i32 signext %f0, i32 signext %f1) nounwind readnone {
; 32-LABEL: i32_icmp_ne_i32_val:
; 32: # %bb.0: # %entry
-; 32-NEXT: movn $5, $6, $4
-; 32-NEXT: jr $ra
; 32-NEXT: move $2, $5
+; 32-NEXT: jr $ra
+; 32-NEXT: movn $2, $6, $4
;
; 32R2-LABEL: i32_icmp_ne_i32_val:
; 32R2: # %bb.0: # %entry
-; 32R2-NEXT: movn $5, $6, $4
-; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $2, $5
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: movn $2, $6, $4
;
; 32R6-LABEL: i32_icmp_ne_i32_val:
; 32R6: # %bb.0: # %entry
@@ -31,15 +31,17 @@ define i32 @i32_icmp_ne_i32_val(i32 signext %s, i32 signext %f0, i32 signext %f1
;
; 64-LABEL: i32_icmp_ne_i32_val:
; 64: # %bb.0: # %entry
-; 64-NEXT: movn $5, $6, $4
-; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
+; 64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
+; 64-NEXT: jr $ra
+; 64-NEXT: movn $2, $6, $4
;
; 64R2-LABEL: i32_icmp_ne_i32_val:
; 64R2: # %bb.0: # %entry
-; 64R2-NEXT: movn $5, $6, $4
-; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: movn $2, $6, $4
;
; 64R6-LABEL: i32_icmp_ne_i32_val:
; 64R6: # %bb.0: # %entry
@@ -60,23 +62,23 @@ entry:
define i64 @i32_icmp_ne_i64_val(i32 signext %s, i64 %f0, i64 %f1) nounwind readnone {
; 32-LABEL: i32_icmp_ne_i64_val:
; 32: # %bb.0: # %entry
+; 32-NEXT: move $3, $7
+; 32-NEXT: move $2, $6
; 32-NEXT: lw $1, 16($sp)
-; 32-NEXT: movn $6, $1, $4
+; 32-NEXT: movn $2, $1, $4
; 32-NEXT: lw $1, 20($sp)
-; 32-NEXT: movn $7, $1, $4
-; 32-NEXT: move $2, $6
; 32-NEXT: jr $ra
-; 32-NEXT: move $3, $7
+; 32-NEXT: movn $3, $1, $4
;
; 32R2-LABEL: i32_icmp_ne_i64_val:
; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: move $3, $7
+; 32R2-NEXT: move $2, $6
; 32R2-NEXT: lw $1, 16($sp)
-; 32R2-NEXT: movn $6, $1, $4
+; 32R2-NEXT: movn $2, $1, $4
; 32R2-NEXT: lw $1, 20($sp)
-; 32R2-NEXT: movn $7, $1, $4
-; 32R2-NEXT: move $2, $6
; 32R2-NEXT: jr $ra
-; 32R2-NEXT: move $3, $7
+; 32R2-NEXT: movn $3, $1, $4
;
; 32R6-LABEL: i32_icmp_ne_i64_val:
; 32R6: # %bb.0: # %entry
@@ -92,15 +94,15 @@ define i64 @i32_icmp_ne_i64_val(i32 signext %s, i64 %f0, i64 %f1) nounwind readn
;
; 64-LABEL: i32_icmp_ne_i64_val:
; 64: # %bb.0: # %entry
-; 64-NEXT: movn $5, $6, $4
-; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
+; 64-NEXT: jr $ra
+; 64-NEXT: movn $2, $6, $4
;
; 64R2-LABEL: i32_icmp_ne_i64_val:
; 64R2: # %bb.0: # %entry
-; 64R2-NEXT: movn $5, $6, $4
-; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: movn $2, $6, $4
;
; 64R6-LABEL: i32_icmp_ne_i64_val:
; 64R6: # %bb.0: # %entry
@@ -118,25 +120,25 @@ entry:
define i64 @i64_icmp_ne_i64_val(i64 %s, i64 %f0, i64 %f1) nounwind readnone {
; 32-LABEL: i64_icmp_ne_i64_val:
; 32: # %bb.0: # %entry
-; 32-NEXT: or $1, $4, $5
-; 32-NEXT: lw $2, 16($sp)
-; 32-NEXT: movn $6, $2, $1
-; 32-NEXT: lw $2, 20($sp)
-; 32-NEXT: movn $7, $2, $1
+; 32-NEXT: move $3, $7
; 32-NEXT: move $2, $6
+; 32-NEXT: or $1, $4, $5
+; 32-NEXT: lw $4, 16($sp)
+; 32-NEXT: movn $2, $4, $1
+; 32-NEXT: lw $4, 20($sp)
; 32-NEXT: jr $ra
-; 32-NEXT: move $3, $7
+; 32-NEXT: movn $3, $4, $1
;
; 32R2-LABEL: i64_icmp_ne_i64_val:
; 32R2: # %bb.0: # %entry
-; 32R2-NEXT: or $1, $4, $5
-; 32R2-NEXT: lw $2, 16($sp)
-; 32R2-NEXT: movn $6, $2, $1
-; 32R2-NEXT: lw $2, 20($sp)
-; 32R2-NEXT: movn $7, $2, $1
+; 32R2-NEXT: move $3, $7
; 32R2-NEXT: move $2, $6
+; 32R2-NEXT: or $1, $4, $5
+; 32R2-NEXT: lw $4, 16($sp)
+; 32R2-NEXT: movn $2, $4, $1
+; 32R2-NEXT: lw $4, 20($sp)
; 32R2-NEXT: jr $ra
-; 32R2-NEXT: move $3, $7
+; 32R2-NEXT: movn $3, $4, $1
;
; 32R6-LABEL: i64_icmp_ne_i64_val:
; 32R6: # %bb.0: # %entry
@@ -153,15 +155,15 @@ define i64 @i64_icmp_ne_i64_val(i64 %s, i64 %f0, i64 %f1) nounwind readnone {
;
; 64-LABEL: i64_icmp_ne_i64_val:
; 64: # %bb.0: # %entry
-; 64-NEXT: movn $5, $6, $4
-; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
+; 64-NEXT: jr $ra
+; 64-NEXT: movn $2, $6, $4
;
; 64R2-LABEL: i64_icmp_ne_i64_val:
; 64R2: # %bb.0: # %entry
-; 64R2-NEXT: movn $5, $6, $4
-; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: movn $2, $6, $4
;
; 64R6-LABEL: i64_icmp_ne_i64_val:
; 64R6: # %bb.0: # %entry
@@ -700,21 +702,21 @@ entry:
define i32 @f32_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
; 32-LABEL: f32_fcmp_oeq_i32_val:
; 32: # %bb.0: # %entry
+; 32-NEXT: move $2, $5
; 32-NEXT: mtc1 $7, $f0
; 32-NEXT: mtc1 $6, $f1
; 32-NEXT: c.eq.s $f1, $f0
-; 32-NEXT: movt $5, $4, $fcc0
; 32-NEXT: jr $ra
-; 32-NEXT: move $2, $5
+; 32-NEXT: movt $2, $4, $fcc0
;
; 32R2-LABEL: f32_fcmp_oeq_i32_val:
; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: move $2, $5
; 32R2-NEXT: mtc1 $7, $f0
; 32R2-NEXT: mtc1 $6, $f1
; 32R2-NEXT: c.eq.s $f1, $f0
-; 32R2-NEXT: movt $5, $4, $fcc0
; 32R2-NEXT: jr $ra
-; 32R2-NEXT: move $2, $5
+; 32R2-NEXT: movt $2, $4, $fcc0
;
; 32R6-LABEL: f32_fcmp_oeq_i32_val:
; 32R6: # %bb.0: # %entry
@@ -730,17 +732,19 @@ define i32 @f32_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1, float %f2, fl
;
; 64-LABEL: f32_fcmp_oeq_i32_val:
; 64: # %bb.0: # %entry
+; 64-NEXT: move $2, $5
; 64-NEXT: c.eq.s $f14, $f15
-; 64-NEXT: movt $5, $4, $fcc0
+; 64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64-NEXT: jr $ra
-; 64-NEXT: move $2, $5
+; 64-NEXT: movt $2, $4, $fcc0
;
; 64R2-LABEL: f32_fcmp_oeq_i32_val:
; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: move $2, $5
; 64R2-NEXT: c.eq.s $f14, $f15
-; 64R2-NEXT: movt $5, $4, $fcc0
+; 64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64R2-NEXT: jr $ra
-; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: movt $2, $4, $fcc0
;
; 64R6-LABEL: f32_fcmp_oeq_i32_val:
; 64R6: # %bb.0: # %entry
@@ -760,21 +764,21 @@ entry:
define i32 @f32_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
; 32-LABEL: f32_fcmp_olt_i32_val:
; 32: # %bb.0: # %entry
+; 32-NEXT: move $2, $5
; 32-NEXT: mtc1 $7, $f0
; 32-NEXT: mtc1 $6, $f1
; 32-NEXT: c.olt.s $f1, $f0
-; 32-NEXT: movt $5, $4, $fcc0
; 32-NEXT: jr $ra
-; 32-NEXT: move $2, $5
+; 32-NEXT: movt $2, $4, $fcc0
;
; 32R2-LABEL: f32_fcmp_olt_i32_val:
; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: move $2, $5
; 32R2-NEXT: mtc1 $7, $f0
; 32R2-NEXT: mtc1 $6, $f1
; 32R2-NEXT: c.olt.s $f1, $f0
-; 32R2-NEXT: movt $5, $4, $fcc0
; 32R2-NEXT: jr $ra
-; 32R2-NEXT: move $2, $5
+; 32R2-NEXT: movt $2, $4, $fcc0
;
; 32R6-LABEL: f32_fcmp_olt_i32_val:
; 32R6: # %bb.0: # %entry
@@ -790,17 +794,19 @@ define i32 @f32_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, fl
;
; 64-LABEL: f32_fcmp_olt_i32_val:
; 64: # %bb.0: # %entry
+; 64-NEXT: move $2, $5
; 64-NEXT: c.olt.s $f14, $f15
-; 64-NEXT: movt $5, $4, $fcc0
+; 64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64-NEXT: jr $ra
-; 64-NEXT: move $2, $5
+; 64-NEXT: movt $2, $4, $fcc0
;
; 64R2-LABEL: f32_fcmp_olt_i32_val:
; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: move $2, $5
; 64R2-NEXT: c.olt.s $f14, $f15
-; 64R2-NEXT: movt $5, $4, $fcc0
+; 64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64R2-NEXT: jr $ra
-; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: movt $2, $4, $fcc0
;
; 64R6-LABEL: f32_fcmp_olt_i32_val:
; 64R6: # %bb.0: # %entry
@@ -820,21 +826,21 @@ entry:
define i32 @f32_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
; 32-LABEL: f32_fcmp_ogt_i32_val:
; 32: # %bb.0: # %entry
+; 32-NEXT: move $2, $5
; 32-NEXT: mtc1 $7, $f0
; 32-NEXT: mtc1 $6, $f1
; 32-NEXT: c.ule.s $f1, $f0
-; 32-NEXT: movf $5, $4, $fcc0
; 32-NEXT: jr $ra
-; 32-NEXT: move $2, $5
+; 32-NEXT: movf $2, $4, $fcc0
;
; 32R2-LABEL: f32_fcmp_ogt_i32_val:
; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: move $2, $5
; 32R2-NEXT: mtc1 $7, $f0
; 32R2-NEXT: mtc1 $6, $f1
; 32R2-NEXT: c.ule.s $f1, $f0
-; 32R2-NEXT: movf $5, $4, $fcc0
; 32R2-NEXT: jr $ra
-; 32R2-NEXT: move $2, $5
+; 32R2-NEXT: movf $2, $4, $fcc0
;
; 32R6-LABEL: f32_fcmp_ogt_i32_val:
; 32R6: # %bb.0: # %entry
@@ -850,17 +856,19 @@ define i32 @f32_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, fl
;
; 64-LABEL: f32_fcmp_ogt_i32_val:
; 64: # %bb.0: # %entry
+; 64-NEXT: move $2, $5
; 64-NEXT: c.ule.s $f14, $f15
-; 64-NEXT: movf $5, $4, $fcc0
+; 64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64-NEXT: jr $ra
-; 64-NEXT: move $2, $5
+; 64-NEXT: movf $2, $4, $fcc0
;
; 64R2-LABEL: f32_fcmp_ogt_i32_val:
; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: move $2, $5
; 64R2-NEXT: c.ule.s $f14, $f15
-; 64R2-NEXT: movf $5, $4, $fcc0
+; 64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64R2-NEXT: jr $ra
-; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: movf $2, $4, $fcc0
;
; 64R6-LABEL: f32_fcmp_ogt_i32_val:
; 64R6: # %bb.0: # %entry
@@ -883,28 +891,28 @@ define i32 @f64_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1) nounwind read
; 32-NEXT: lui $2, %hi(_gp_disp)
; 32-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32-NEXT: addu $1, $2, $25
-; 32-NEXT: lw $2, %got(d3)($1)
-; 32-NEXT: ldc1 $f0, 0($2)
+; 32-NEXT: move $2, $5
+; 32-NEXT: lw $3, %got(d3)($1)
+; 32-NEXT: ldc1 $f0, 0($3)
; 32-NEXT: lw $1, %got(d2)($1)
; 32-NEXT: ldc1 $f2, 0($1)
; 32-NEXT: c.eq.d $f2, $f0
-; 32-NEXT: movt $5, $4, $fcc0
; 32-NEXT: jr $ra
-; 32-NEXT: move $2, $5
+; 32-NEXT: movt $2, $4, $fcc0
;
; 32R2-LABEL: f64_fcmp_oeq_i32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: lui $2, %hi(_gp_disp)
; 32R2-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32R2-NEXT: addu $1, $2, $25
-; 32R2-NEXT: lw $2, %got(d3)($1)
-; 32R2-NEXT: ldc1 $f0, 0($2)
+; 32R2-NEXT: move $2, $5
+; 32R2-NEXT: lw $3, %got(d3)($1)
+; 32R2-NEXT: ldc1 $f0, 0($3)
; 32R2-NEXT: lw $1, %got(d2)($1)
; 32R2-NEXT: ldc1 $f2, 0($1)
; 32R2-NEXT: c.eq.d $f2, $f0
-; 32R2-NEXT: movt $5, $4, $fcc0
; 32R2-NEXT: jr $ra
-; 32R2-NEXT: move $2, $5
+; 32R2-NEXT: movt $2, $4, $fcc0
;
; 32R6-LABEL: f64_fcmp_oeq_i32_val:
; 32R6: # %bb.0: # %entry
@@ -928,28 +936,30 @@ define i32 @f64_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1) nounwind read
; 64-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
; 64-NEXT: daddu $1, $1, $25
; 64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
-; 64-NEXT: ld $2, %got_disp(d3)($1)
-; 64-NEXT: ldc1 $f0, 0($2)
+; 64-NEXT: move $2, $5
+; 64-NEXT: ld $3, %got_disp(d3)($1)
+; 64-NEXT: ldc1 $f0, 0($3)
; 64-NEXT: ld $1, %got_disp(d2)($1)
; 64-NEXT: ldc1 $f1, 0($1)
; 64-NEXT: c.eq.d $f1, $f0
-; 64-NEXT: movt $5, $4, $fcc0
+; 64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64-NEXT: jr $ra
-; 64-NEXT: move $2, $5
+; 64-NEXT: movt $2, $4, $fcc0
;
; 64R2-LABEL: f64_fcmp_oeq_i32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
; 64R2-NEXT: daddu $1, $1, $25
; 64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
-; 64R2-NEXT: ld $2, %got_disp(d3)($1)
-; 64R2-NEXT: ldc1 $f0, 0($2)
+; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: ld $3, %got_disp(d3)($1)
+; 64R2-NEXT: ldc1 $f0, 0($3)
; 64R2-NEXT: ld $1, %got_disp(d2)($1)
; 64R2-NEXT: ldc1 $f1, 0($1)
; 64R2-NEXT: c.eq.d $f1, $f0
-; 64R2-NEXT: movt $5, $4, $fcc0
+; 64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64R2-NEXT: jr $ra
-; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: movt $2, $4, $fcc0
;
; 64R6-LABEL: f64_fcmp_oeq_i32_val:
; 64R6: # %bb.0: # %entry
@@ -981,28 +991,28 @@ define i32 @f64_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1) nounwind read
; 32-NEXT: lui $2, %hi(_gp_disp)
; 32-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32-NEXT: addu $1, $2, $25
-; 32-NEXT: lw $2, %got(d3)($1)
-; 32-NEXT: ldc1 $f0, 0($2)
+; 32-NEXT: move $2, $5
+; 32-NEXT: lw $3, %got(d3)($1)
+; 32-NEXT: ldc1 $f0, 0($3)
; 32-NEXT: lw $1, %got(d2)($1)
; 32-NEXT: ldc1 $f2, 0($1)
; 32-NEXT: c.olt.d $f2, $f0
-; 32-NEXT: movt $5, $4, $fcc0
; 32-NEXT: jr $ra
-; 32-NEXT: move $2, $5
+; 32-NEXT: movt $2, $4, $fcc0
;
; 32R2-LABEL: f64_fcmp_olt_i32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: lui $2, %hi(_gp_disp)
; 32R2-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32R2-NEXT: addu $1, $2, $25
-; 32R2-NEXT: lw $2, %got(d3)($1)
-; 32R2-NEXT: ldc1 $f0, 0($2)
+; 32R2-NEXT: move $2, $5
+; 32R2-NEXT: lw $3, %got(d3)($1)
+; 32R2-NEXT: ldc1 $f0, 0($3)
; 32R2-NEXT: lw $1, %got(d2)($1)
; 32R2-NEXT: ldc1 $f2, 0($1)
; 32R2-NEXT: c.olt.d $f2, $f0
-; 32R2-NEXT: movt $5, $4, $fcc0
; 32R2-NEXT: jr $ra
-; 32R2-NEXT: move $2, $5
+; 32R2-NEXT: movt $2, $4, $fcc0
;
; 32R6-LABEL: f64_fcmp_olt_i32_val:
; 32R6: # %bb.0: # %entry
@@ -1026,28 +1036,30 @@ define i32 @f64_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1) nounwind read
; 64-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
; 64-NEXT: daddu $1, $1, $25
; 64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
-; 64-NEXT: ld $2, %got_disp(d3)($1)
-; 64-NEXT: ldc1 $f0, 0($2)
+; 64-NEXT: move $2, $5
+; 64-NEXT: ld $3, %got_disp(d3)($1)
+; 64-NEXT: ldc1 $f0, 0($3)
; 64-NEXT: ld $1, %got_disp(d2)($1)
; 64-NEXT: ldc1 $f1, 0($1)
; 64-NEXT: c.olt.d $f1, $f0
-; 64-NEXT: movt $5, $4, $fcc0
+; 64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64-NEXT: jr $ra
-; 64-NEXT: move $2, $5
+; 64-NEXT: movt $2, $4, $fcc0
;
; 64R2-LABEL: f64_fcmp_olt_i32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
; 64R2-NEXT: daddu $1, $1, $25
; 64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
-; 64R2-NEXT: ld $2, %got_disp(d3)($1)
-; 64R2-NEXT: ldc1 $f0, 0($2)
+; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: ld $3, %got_disp(d3)($1)
+; 64R2-NEXT: ldc1 $f0, 0($3)
; 64R2-NEXT: ld $1, %got_disp(d2)($1)
; 64R2-NEXT: ldc1 $f1, 0($1)
; 64R2-NEXT: c.olt.d $f1, $f0
-; 64R2-NEXT: movt $5, $4, $fcc0
+; 64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64R2-NEXT: jr $ra
-; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: movt $2, $4, $fcc0
;
; 64R6-LABEL: f64_fcmp_olt_i32_val:
; 64R6: # %bb.0: # %entry
@@ -1079,28 +1091,28 @@ define i32 @f64_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1) nounwind read
; 32-NEXT: lui $2, %hi(_gp_disp)
; 32-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32-NEXT: addu $1, $2, $25
-; 32-NEXT: lw $2, %got(d3)($1)
-; 32-NEXT: ldc1 $f0, 0($2)
+; 32-NEXT: move $2, $5
+; 32-NEXT: lw $3, %got(d3)($1)
+; 32-NEXT: ldc1 $f0, 0($3)
; 32-NEXT: lw $1, %got(d2)($1)
; 32-NEXT: ldc1 $f2, 0($1)
; 32-NEXT: c.ule.d $f2, $f0
-; 32-NEXT: movf $5, $4, $fcc0
; 32-NEXT: jr $ra
-; 32-NEXT: move $2, $5
+; 32-NEXT: movf $2, $4, $fcc0
;
; 32R2-LABEL: f64_fcmp_ogt_i32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: lui $2, %hi(_gp_disp)
; 32R2-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32R2-NEXT: addu $1, $2, $25
-; 32R2-NEXT: lw $2, %got(d3)($1)
-; 32R2-NEXT: ldc1 $f0, 0($2)
+; 32R2-NEXT: move $2, $5
+; 32R2-NEXT: lw $3, %got(d3)($1)
+; 32R2-NEXT: ldc1 $f0, 0($3)
; 32R2-NEXT: lw $1, %got(d2)($1)
; 32R2-NEXT: ldc1 $f2, 0($1)
; 32R2-NEXT: c.ule.d $f2, $f0
-; 32R2-NEXT: movf $5, $4, $fcc0
; 32R2-NEXT: jr $ra
-; 32R2-NEXT: move $2, $5
+; 32R2-NEXT: movf $2, $4, $fcc0
;
; 32R6-LABEL: f64_fcmp_ogt_i32_val:
; 32R6: # %bb.0: # %entry
@@ -1124,28 +1136,30 @@ define i32 @f64_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1) nounwind read
; 64-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
; 64-NEXT: daddu $1, $1, $25
; 64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
-; 64-NEXT: ld $2, %got_disp(d3)($1)
-; 64-NEXT: ldc1 $f0, 0($2)
+; 64-NEXT: move $2, $5
+; 64-NEXT: ld $3, %got_disp(d3)($1)
+; 64-NEXT: ldc1 $f0, 0($3)
; 64-NEXT: ld $1, %got_disp(d2)($1)
; 64-NEXT: ldc1 $f1, 0($1)
; 64-NEXT: c.ule.d $f1, $f0
-; 64-NEXT: movf $5, $4, $fcc0
+; 64-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64-NEXT: jr $ra
-; 64-NEXT: move $2, $5
+; 64-NEXT: movf $2, $4, $fcc0
;
; 64R2-LABEL: f64_fcmp_ogt_i32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
; 64R2-NEXT: daddu $1, $1, $25
; 64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
-; 64R2-NEXT: ld $2, %got_disp(d3)($1)
-; 64R2-NEXT: ldc1 $f0, 0($2)
+; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: ld $3, %got_disp(d3)($1)
+; 64R2-NEXT: ldc1 $f0, 0($3)
; 64R2-NEXT: ld $1, %got_disp(d2)($1)
; 64R2-NEXT: ldc1 $f1, 0($1)
; 64R2-NEXT: c.ule.d $f1, $f0
-; 64R2-NEXT: movf $5, $4, $fcc0
+; 64R2-NEXT: # kill: def $r2 killed $r2 killed $r2_64
; 64R2-NEXT: jr $ra
-; 64R2-NEXT: move $2, $5
+; 64R2-NEXT: movf $2, $4, $fcc0
;
; 64R6-LABEL: f64_fcmp_ogt_i32_val:
; 64R6: # %bb.0: # %entry
diff --git a/llvm/test/DebugInfo/Mips/eh_frame.ll b/llvm/test/DebugInfo/Mips/eh_frame.ll
index d53bc156ef29f..f5345b6b83856 100644
--- a/llvm/test/DebugInfo/Mips/eh_frame.ll
+++ b/llvm/test/DebugInfo/Mips/eh_frame.ll
@@ -26,9 +26,9 @@
; CHECK-READELF-PIC-NEXT: R_MIPS_PC32
; CHECK-READELF-NEXT: .gcc_except_table
-; EXCEPT-TABLE-STATIC: 0000 ff9b1501 0c001400 00140e22 01221e00 ..........."."..
+; EXCEPT-TABLE-STATIC: 0000 ff9b1501 0c001200 00121022 01221e00 ..........."."..
; EXCEPT-TABLE-STATIC: 0010 00010000 00000000
-; EXCEPT-TABLE-PIC: 0000 ff9b1501 0c002c00 002c123e 013e2a00 ......,..,.>.>*.
+; EXCEPT-TABLE-PIC: 0000 ff9b1501 0c002a00 002a143e 013e2a00 ......*..*.>.>*.
; EXCEPT-TABLE-PIC: 0010 00010000 00000000 ........
@_ZTIi = external constant ptr
>From 8ed5731ca1718d0d3d1d5783aafa396ed020600d Mon Sep 17 00:00:00 2001
From: Anton Rapetov <anton.rapetov at mediatek.com>
Date: Wed, 7 Oct 2026 14:55:36 -0400
Subject: [PATCH 6/7] [Mips] Remove the GPR role aliases; use Mips::R<n> and
ABI accessors
Drop the compatibility aliases added by the previous commits (TableGen
defvars and the constexpr constants in MipsMCTargetDesc.h) and use
Mips::R<n> directly.
Where a register's role depends on the ABI, use the MipsABIInfo accessors
instead: the base-pointer reservation, CC_MipsO32, the MIPS16 FP stubs,
the assembler's $t9 uses and llvm-exegesis' scratch register.
Co-authored-By: Claude Sonnet <noreply at anthropic.com>
---
.../Target/Mips/AsmParser/MipsAsmParser.cpp | 461 +++++++++---------
.../Mips/Disassembler/MipsDisassembler.cpp | 48 +-
.../Target/Mips/MCTargetDesc/MipsABIInfo.cpp | 70 +--
.../Mips/MCTargetDesc/MipsInstPrinter.cpp | 26 +-
.../Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 54 +-
.../Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 84 ++--
.../Mips/MCTargetDesc/MipsMCTargetDesc.h | 122 -----
.../Mips/MCTargetDesc/MipsTargetStreamer.cpp | 26 +-
.../lib/Target/Mips/MicroMips32r6InstrInfo.td | 72 +--
llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 4 +-
llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 50 +-
.../Target/Mips/MicroMipsSizeReduction.cpp | 40 +-
llvm/lib/Target/Mips/Mips16FrameLowering.cpp | 20 +-
llvm/lib/Target/Mips/Mips16ISelLowering.cpp | 8 +-
llvm/lib/Target/Mips/Mips16InstrInfo.cpp | 34 +-
llvm/lib/Target/Mips/Mips16InstrInfo.td | 62 +--
llvm/lib/Target/Mips/Mips16RegisterInfo.cpp | 10 +-
llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 44 +-
llvm/lib/Target/Mips/Mips64InstrInfo.td | 66 +--
llvm/lib/Target/Mips/Mips64r6InstrInfo.td | 10 +-
llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 49 +-
llvm/lib/Target/Mips/MipsBranchExpansion.cpp | 108 ++--
llvm/lib/Target/Mips/MipsCallLowering.cpp | 8 +-
llvm/lib/Target/Mips/MipsCallingConv.td | 104 ++--
llvm/lib/Target/Mips/MipsDSPInstrInfo.td | 8 +-
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 20 +-
llvm/lib/Target/Mips/MipsExpandPseudo.cpp | 30 +-
llvm/lib/Target/Mips/MipsFastISel.cpp | 16 +-
llvm/lib/Target/Mips/MipsFrameLowering.cpp | 2 +-
llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp | 2 +-
llvm/lib/Target/Mips/MipsISelLowering.cpp | 46 +-
llvm/lib/Target/Mips/MipsISelLowering.h | 2 +-
llvm/lib/Target/Mips/MipsInstrFPU.td | 12 +-
llvm/lib/Target/Mips/MipsInstrInfo.cpp | 26 +-
llvm/lib/Target/Mips/MipsInstrInfo.td | 102 ++--
.../Target/Mips/MipsInstructionSelector.cpp | 10 +-
llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 2 +-
llvm/lib/Target/Mips/MipsMTInstrInfo.td | 10 +-
llvm/lib/Target/Mips/MipsMachineFunction.cpp | 8 +-
llvm/lib/Target/Mips/MipsOptimizePICCall.cpp | 6 +-
llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 47 +-
llvm/lib/Target/Mips/MipsRegisterInfo.td | 210 ++------
llvm/lib/Target/Mips/MipsSEFrameLowering.cpp | 60 +--
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 56 +--
llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 10 +-
llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 40 +-
llvm/tools/llvm-exegesis/lib/Mips/Target.cpp | 9 +-
.../Mips/BenchmarkResultTest.cpp | 10 +-
.../Mips/RegisterAliasingTest.cpp | 16 +-
.../tools/llvm-exegesis/Mips/TargetTest.cpp | 18 +-
50 files changed, 1062 insertions(+), 1296 deletions(-)
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 99cb6d26d2039..52847a1ea9010 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1340,19 +1340,19 @@ class MipsOperand : public MCParsedAsmOperand {
template <unsigned Bits> bool isMemWithUimmOffsetSP() const {
return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
- && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);
+ && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::R29);
}
template <unsigned Bits> bool isMemWithUimmWordAlignedOffsetSP() const {
return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
&& (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
- && (getMemBase()->getGPR32Reg() == Mips::SP);
+ && (getMemBase()->getGPR32Reg() == Mips::R29);
}
template <unsigned Bits> bool isMemWithSimmWordAlignedOffsetGP() const {
return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
&& (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
- && (getMemBase()->getGPR32Reg() == Mips::GP);
+ && (getMemBase()->getGPR32Reg() == Mips::R28);
}
template <unsigned Bits, unsigned ShiftLeftAmount>
@@ -1385,8 +1385,8 @@ class MipsOperand : public MCParsedAsmOperand {
MCRegister R0 = RegList.List->front();
MCRegister R1 = RegList.List->back();
- if (!((R0 == Mips::S0 && R1 == Mips::RA) ||
- (R0 == Mips::S0_64 && R1 == Mips::RA_64)))
+ if (!((R0 == Mips::R16 && R1 == Mips::R31) ||
+ (R0 == Mips::R16_64 && R1 == Mips::R31_64)))
return false;
MCRegister PrevReg = RegList.List->front();
@@ -2020,8 +2020,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
if (!Inst.getOperand(2).isImm())
return Error(IDLoc, "expected immediate operand kind");
if (Inst.getOperand(2).getImm() == 0) {
- if (Inst.getOperand(1).getReg() == Mips::ZERO ||
- Inst.getOperand(1).getReg() == Mips::ZERO_64)
+ if (Inst.getOperand(1).getReg() == Mips::R0 ||
+ Inst.getOperand(1).getReg() == Mips::R0_64)
Warning(IDLoc, "dividing zero by zero");
else
Warning(IDLoc, "division by zero");
@@ -2046,10 +2046,10 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
case Mips::DDIVU:
case Mips::DIVU_MMR6:
case Mips::DIV_MMR6:
- if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
- Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) {
- if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
- Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64)
+ if (Inst.getOperand(SecondOp).getReg() == Mips::R0 ||
+ Inst.getOperand(SecondOp).getReg() == Mips::R0_64) {
+ if (Inst.getOperand(FirstOp).getReg() == Mips::R0 ||
+ Inst.getOperand(FirstOp).getReg() == Mips::R0_64)
Warning(IDLoc, "dividing zero by zero");
else
Warning(IDLoc, "division by zero");
@@ -2061,8 +2061,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
if ((Opcode == Mips::J || Opcode == Mips::J_MM) && inPicMode()) {
MCInst BInst;
BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ);
- BInst.addOperand(MCOperand::createReg(Mips::ZERO));
- BInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ BInst.addOperand(MCOperand::createReg(Mips::R0));
+ BInst.addOperand(MCOperand::createReg(Mips::R0));
BInst.addOperand(Inst.getOperand(0));
Inst = BInst;
}
@@ -2087,7 +2087,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
// of the assembler. We ought to leave it to those later stages.
const MCSymbol *JalSym = getSingleMCSymbol(JalExpr);
- if (expandLoadAddress(Mips::T9, MCRegister(), Inst.getOperand(0),
+ if (expandLoadAddress(getABI().getTempReg(9), MCRegister(), Inst.getOperand(0),
!isGP64bit(), IDLoc, Out, STI))
return true;
@@ -2096,8 +2096,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
JalrInst.setOpcode(IsCpRestoreSet ? Mips::JALRS_MM : Mips::JALR_MM);
else
JalrInst.setOpcode(Mips::JALR);
- JalrInst.addOperand(MCOperand::createReg(Mips::RA));
- JalrInst.addOperand(MCOperand::createReg(Mips::T9));
+ JalrInst.addOperand(MCOperand::createReg(Mips::R31));
+ JalrInst.addOperand(MCOperand::createReg(getABI().getTempReg(9)));
if (isJalrRelocAvailable(JalExpr)) {
// As an optimization hint for the linker, before the JALR we add:
@@ -2149,10 +2149,10 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
if (isInt<9>(MemOffset) && (MemOffset % 4 == 0) &&
getContext().getRegisterInfo()->getRegClass(
Mips::GPRMM16RegClassID).contains(DstReg.getReg()) &&
- (BaseReg.getReg() == Mips::GP ||
- BaseReg.getReg() == Mips::GP_64)) {
+ (BaseReg.getReg() == Mips::R28 ||
+ BaseReg.getReg() == Mips::R28_64)) {
- TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset,
+ TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::R28, MemOffset,
IDLoc, STI);
return false;
}
@@ -2261,21 +2261,21 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
break;
case Mips::LWP_MM:
case Mips::SWP_MM:
- if (Inst.getOperand(0).getReg() == Mips::RA)
+ if (Inst.getOperand(0).getReg() == Mips::R31)
return Error(IDLoc, "invalid operand for instruction");
break;
case Mips::MOVEP_MM:
case Mips::MOVEP_MMR6: {
MCRegister R0 = Inst.getOperand(0).getReg();
MCRegister R1 = Inst.getOperand(1).getReg();
- bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) ||
- (R0 == Mips::A1 && R1 == Mips::A3) ||
- (R0 == Mips::A2 && R1 == Mips::A3) ||
- (R0 == Mips::A0 && R1 == Mips::S5) ||
- (R0 == Mips::A0 && R1 == Mips::S6) ||
- (R0 == Mips::A0 && R1 == Mips::A1) ||
- (R0 == Mips::A0 && R1 == Mips::A2) ||
- (R0 == Mips::A0 && R1 == Mips::A3));
+ bool RegPair = ((R0 == Mips::R5 && R1 == Mips::R6) ||
+ (R0 == Mips::R5 && R1 == Mips::R7) ||
+ (R0 == Mips::R6 && R1 == Mips::R7) ||
+ (R0 == Mips::R4 && R1 == Mips::R21) ||
+ (R0 == Mips::R4 && R1 == Mips::R22) ||
+ (R0 == Mips::R4 && R1 == Mips::R5) ||
+ (R0 == Mips::R4 && R1 == Mips::R6) ||
+ (R0 == Mips::R4 && R1 == Mips::R7));
if (!RegPair)
return Error(IDLoc, "invalid operand for instruction");
break;
@@ -2681,7 +2681,7 @@ bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
JalrInst.addOperand(FirstRegOp);
} else {
JalrInst.setOpcode(Mips::JALR);
- JalrInst.addOperand(MCOperand::createReg(Mips::RA));
+ JalrInst.addOperand(MCOperand::createReg(Mips::R31));
JalrInst.addOperand(FirstRegOp);
}
} else if (Opcode == Mips::JalTwoReg) {
@@ -2940,7 +2940,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
bool UseSrcReg =
- SrcReg.isValid() && SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64;
+ SrcReg.isValid() && SrcReg != Mips::R0 && SrcReg != Mips::R0_64;
warnIfNoMacro(IDLoc);
if (inPicMode()) {
@@ -2971,7 +2971,8 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
// symbol in the final relocation is external and not modified with a
// constant then we must use R_MIPS_CALL16 instead of R_MIPS_GOT16
// or R_MIPS_CALL16 instead of R_MIPS_GOT_DISP in 64-bit case.
- if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg &&
+ if ((DstReg == getABI().getTempReg(9, false) ||
+ DstReg == getABI().getTempReg(9, true)) && !UseSrcReg &&
Res.getConstant() == 0 && !IsLocalSym) {
if (UseXGOT) {
const MCExpr *CallHiExpr =
@@ -3257,38 +3258,38 @@ static MCRegister nextReg(MCRegister Reg) {
return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1;
switch (Reg.id()) {
default: llvm_unreachable("Unknown register in assembly macro expansion!");
- case Mips::ZERO: return Mips::AT;
- case Mips::AT: return Mips::V0;
- case Mips::V0: return Mips::V1;
- case Mips::V1: return Mips::A0;
- case Mips::A0: return Mips::A1;
- case Mips::A1: return Mips::A2;
- case Mips::A2: return Mips::A3;
- case Mips::A3: return Mips::T0;
- case Mips::T0: return Mips::T1;
- case Mips::T1: return Mips::T2;
- case Mips::T2: return Mips::T3;
- case Mips::T3: return Mips::T4;
- case Mips::T4: return Mips::T5;
- case Mips::T5: return Mips::T6;
- case Mips::T6: return Mips::T7;
- case Mips::T7: return Mips::S0;
- case Mips::S0: return Mips::S1;
- case Mips::S1: return Mips::S2;
- case Mips::S2: return Mips::S3;
- case Mips::S3: return Mips::S4;
- case Mips::S4: return Mips::S5;
- case Mips::S5: return Mips::S6;
- case Mips::S6: return Mips::S7;
- case Mips::S7: return Mips::T8;
- case Mips::T8: return Mips::T9;
- case Mips::T9: return Mips::K0;
- case Mips::K0: return Mips::K1;
- case Mips::K1: return Mips::GP;
- case Mips::GP: return Mips::SP;
- case Mips::SP: return Mips::FP;
- case Mips::FP: return Mips::RA;
- case Mips::RA: return Mips::ZERO;
+ case Mips::R0: return Mips::R1;
+ case Mips::R1: return Mips::R2;
+ case Mips::R2: return Mips::R3;
+ case Mips::R3: return Mips::R4;
+ case Mips::R4: return Mips::R5;
+ case Mips::R5: return Mips::R6;
+ case Mips::R6: return Mips::R7;
+ case Mips::R7: return Mips::R8;
+ case Mips::R8: return Mips::R9;
+ case Mips::R9: return Mips::R10;
+ case Mips::R10: return Mips::R11;
+ case Mips::R11: return Mips::R12;
+ case Mips::R12: return Mips::R13;
+ case Mips::R13: return Mips::R14;
+ case Mips::R14: return Mips::R15;
+ case Mips::R15: return Mips::R16;
+ case Mips::R16: return Mips::R17;
+ case Mips::R17: return Mips::R18;
+ case Mips::R18: return Mips::R19;
+ case Mips::R19: return Mips::R20;
+ case Mips::R20: return Mips::R21;
+ case Mips::R21: return Mips::R22;
+ case Mips::R22: return Mips::R23;
+ case Mips::R23: return Mips::R24;
+ case Mips::R24: return Mips::R25;
+ case Mips::R25: return Mips::R26;
+ case Mips::R26: return Mips::R27;
+ case Mips::R27: return Mips::R28;
+ case Mips::R28: return Mips::R29;
+ case Mips::R29: return Mips::R30;
+ case Mips::R30: return Mips::R31;
+ case Mips::R31: return Mips::R0;
case Mips::D0: return Mips::F1;
case Mips::D1: return Mips::F3;
case Mips::D2: return Mips::F5;
@@ -3299,12 +3300,12 @@ static MCRegister nextReg(MCRegister Reg) {
case Mips::D7: return Mips::F15;
case Mips::D8: return Mips::F17;
case Mips::D9: return Mips::F19;
- case Mips::D10: return Mips::F21;
- case Mips::D11: return Mips::F23;
- case Mips::D12: return Mips::F25;
- case Mips::D13: return Mips::F27;
- case Mips::D14: return Mips::F29;
- case Mips::D15: return Mips::F31;
+ case Mips::D10: return Mips::F21;
+ case Mips::D11: return Mips::F23;
+ case Mips::D12: return Mips::F25;
+ case Mips::D13: return Mips::F27;
+ case Mips::D14: return Mips::F29;
+ case Mips::D15: return Mips::F31;
}
}
@@ -3415,7 +3416,7 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
uint32_t ImmOp32 = covertDoubleImmToSingleImm(ImmOp64);
- MCRegister TmpReg = Mips::ZERO;
+ MCRegister TmpReg = Mips::R0;
if (ImmOp32 != 0) {
TmpReg = getATReg(IDLoc);
if (!TmpReg)
@@ -3423,8 +3424,8 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
}
if (Lo_32(ImmOp64) == 0) {
- if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, MCRegister(),
- true, false, IDLoc, Out, STI))
+ if (TmpReg != Mips::R0 && loadImmediate(ImmOp32, TmpReg, MCRegister(),
+ true, false, IDLoc, Out, STI))
return true;
TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
return false;
@@ -3528,7 +3529,7 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
ImmOp64 = convertIntToDoubleImm(ImmOp64);
- MCRegister TmpReg = Mips::ZERO;
+ MCRegister TmpReg = Mips::R0;
if (ImmOp64 != 0) {
TmpReg = getATReg(IDLoc);
if (!TmpReg)
@@ -3538,24 +3539,24 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
if ((Lo_32(ImmOp64) == 0) &&
!((Hi_32(ImmOp64) & 0xffff0000) && (Hi_32(ImmOp64) & 0x0000ffff))) {
if (isGP64bit()) {
- if (TmpReg != Mips::ZERO && loadImmediate(ImmOp64, TmpReg, MCRegister(),
- false, false, IDLoc, Out, STI))
+ if (TmpReg != Mips::R0 && loadImmediate(ImmOp64, TmpReg, MCRegister(),
+ false, false, IDLoc, Out, STI))
return true;
TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
return false;
}
- if (TmpReg != Mips::ZERO &&
+ if (TmpReg != Mips::R0 &&
loadImmediate(Hi_32(ImmOp64), TmpReg, MCRegister(), true, false, IDLoc,
Out, STI))
return true;
if (hasMips32r2()) {
- TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
+ TOut.emitRR(Mips::MTC1, FirstReg, Mips::R0, IDLoc, STI);
TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI);
} else {
TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);
- TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
+ TOut.emitRR(Mips::MTC1, FirstReg, Mips::R0, IDLoc, STI);
}
return false;
}
@@ -3597,8 +3598,8 @@ bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
if (Offset.isExpr()) {
Inst.clear();
Inst.setOpcode(Mips::BEQ_MM);
- Inst.addOperand(MCOperand::createReg(Mips::ZERO));
- Inst.addOperand(MCOperand::createReg(Mips::ZERO));
+ Inst.addOperand(MCOperand::createReg(Mips::R0));
+ Inst.addOperand(MCOperand::createReg(Mips::R0));
Inst.addOperand(MCOperand::createExpr(Offset.getExpr()));
} else {
assert(Offset.isImm() && "expected immediate operand kind");
@@ -3614,8 +3615,8 @@ bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
return Error(IDLoc, "branch to misaligned address");
Inst.clear();
Inst.setOpcode(Mips::BEQ_MM);
- Inst.addOperand(MCOperand::createReg(Mips::ZERO));
- Inst.addOperand(MCOperand::createReg(Mips::ZERO));
+ Inst.addOperand(MCOperand::createReg(Mips::R0));
+ Inst.addOperand(MCOperand::createReg(Mips::R0));
Inst.addOperand(MCOperand::createImm(Offset.getImm()));
}
}
@@ -3669,11 +3670,11 @@ bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
int64_t ImmValue = ImmOp.getImm();
if (ImmValue == 0) {
if (IsLikely) {
- TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,
+ TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::R0,
MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI);
- TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
+ TOut.emitRRI(Mips::SLL, Mips::R0, Mips::R0, 0, IDLoc, STI);
} else
- TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
+ TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::R0, MemOffsetOp, IDLoc,
STI);
} else {
warnIfNoMacro(IDLoc);
@@ -3689,7 +3690,7 @@ bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
if (IsLikely && MemOffsetOp.isExpr()) {
TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg,
MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI);
- TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
+ TOut.emitRRI(Mips::SLL, Mips::R0, Mips::R0, 0, IDLoc, STI);
} else
TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
}
@@ -3756,7 +3757,7 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return;
}
- if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
+ if (BaseReg != Mips::R0 && BaseReg != Mips::R0_64)
TOut.emitRRR(ABI.ArePtrs64bit() ? Mips::DADDu : Mips::ADDu, TmpReg,
TmpReg, BaseReg, IDLoc, STI);
emitInstWithOffset(MCOperand::createImm(int16_t(LoOffset)));
@@ -3808,13 +3809,13 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HiOperand, IDLoc, STI);
TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
- if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
+ if (BaseReg != Mips::R0 && BaseReg != Mips::R0_64)
TOut.emitRRR(Mips::DADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
emitInstWithOffset(LoOperand);
} else {
// Generate the base address in TmpReg.
TOut.emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
- if (BaseReg != Mips::ZERO)
+ if (BaseReg != Mips::R0)
TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
// Emit the load or store with the adjusted base and offset.
emitInstWithOffset(LoOperand);
@@ -3900,10 +3901,10 @@ bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 &&
Inst.getOperand(OpNum - 1).getImm() >= 0 &&
- (Inst.getOperand(OpNum - 2).getReg() == Mips::SP ||
- Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) &&
- (Inst.getOperand(OpNum - 3).getReg() == Mips::RA ||
- Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) {
+ (Inst.getOperand(OpNum - 2).getReg() == Mips::R29 ||
+ Inst.getOperand(OpNum - 2).getReg() == Mips::R29_64) &&
+ (Inst.getOperand(OpNum - 3).getReg() == Mips::R31 ||
+ Inst.getOperand(OpNum - 3).getReg() == Mips::R31_64)) {
// It can be implemented as SWM16 or LWM16 instruction.
if (inMicroMipsMode() && hasMips32r6())
NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6;
@@ -4051,43 +4052,43 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
llvm_unreachable("unknown opcode for branch pseudo-instruction");
}
- bool IsTrgRegZero = (TrgReg == Mips::ZERO);
- bool IsSrcRegZero = (SrcReg == Mips::ZERO);
+ bool IsTrgRegZero = (TrgReg == Mips::R0);
+ bool IsSrcRegZero = (SrcReg == Mips::R0);
if (IsSrcRegZero && IsTrgRegZero) {
// FIXME: All of these Opcode-specific if's are needed for compatibility
// with GAS' behaviour. However, they may not generate the most efficient
// code in some circumstances.
if (PseudoOpcode == Mips::BLT) {
- TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
+ TOut.emitRX(Mips::BLTZ, Mips::R0, MCOperand::createExpr(OffsetExpr),
IDLoc, STI);
return false;
}
if (PseudoOpcode == Mips::BLE) {
- TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
+ TOut.emitRX(Mips::BLEZ, Mips::R0, MCOperand::createExpr(OffsetExpr),
IDLoc, STI);
Warning(IDLoc, "branch is always taken");
return false;
}
if (PseudoOpcode == Mips::BGE) {
- TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
+ TOut.emitRX(Mips::BGEZ, Mips::R0, MCOperand::createExpr(OffsetExpr),
IDLoc, STI);
Warning(IDLoc, "branch is always taken");
return false;
}
if (PseudoOpcode == Mips::BGT) {
- TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
+ TOut.emitRX(Mips::BGTZ, Mips::R0, MCOperand::createExpr(OffsetExpr),
IDLoc, STI);
return false;
}
if (PseudoOpcode == Mips::BGTU) {
- TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
+ TOut.emitRRX(Mips::BNE, Mips::R0, Mips::R0,
MCOperand::createExpr(OffsetExpr), IDLoc, STI);
return false;
}
if (AcceptsEquality) {
// If both registers are $0 and the pseudo-branch accepts equality, it
// will always be taken, so we emit an unconditional branch.
- TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
+ TOut.emitRRX(Mips::BEQ, Mips::R0, Mips::R0,
MCOperand::createExpr(OffsetExpr), IDLoc, STI);
Warning(IDLoc, "branch is always taken");
return false;
@@ -4112,7 +4113,7 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
// the pseudo-branch will always be taken, so we emit an unconditional
// branch.
// This only applies to unsigned pseudo-branches.
- TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
+ TOut.emitRRX(Mips::BEQ, Mips::R0, Mips::R0,
MCOperand::createExpr(OffsetExpr), IDLoc, STI);
Warning(IDLoc, "branch is always taken");
return false;
@@ -4131,7 +4132,7 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
// Because only BLEU and BGEU branch on equality, we can use the
// AcceptsEquality variable to decide when to emit the BEQZ.
TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE,
- IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO,
+ IsSrcRegZero ? TrgReg : SrcReg, Mips::R0,
MCOperand::createExpr(OffsetExpr), IDLoc, STI);
return false;
}
@@ -4174,7 +4175,7 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL)
: (AcceptsEquality ? Mips::BEQ : Mips::BNE),
- ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
+ ATRegNum, Mips::R0, MCOperand::createExpr(OffsetExpr), IDLoc,
STI);
return false;
}
@@ -4219,11 +4220,11 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
if (IsMips64) {
DivOp = Signed ? Mips::DSDIV : Mips::DUDIV;
- ZeroReg = Mips::ZERO_64;
+ ZeroReg = Mips::R0_64;
SubOp = Mips::DSUB;
} else {
DivOp = Signed ? Mips::SDIV : Mips::UDIV;
- ZeroReg = Mips::ZERO;
+ ZeroReg = Mips::R0;
SubOp = Mips::SUB;
}
@@ -4257,7 +4258,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI);
return false;
} else if (isDiv && ImmValue == 1) {
- TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
+ TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::R0, IDLoc, STI);
return false;
} else if (isDiv && Signed && ImmValue == -1) {
TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI);
@@ -4277,7 +4278,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
// break, insert the trap/break and exit. This gives a different result to
// GAS. GAS has an inconsistency/missed optimization in that not all cases
// are handled equivalently. As the observed behaviour is the same, we're ok.
- if (!NoZeroDivCheck && (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)) {
+ if (!NoZeroDivCheck && (RtReg == Mips::R0 || RtReg == Mips::R0_64)) {
if (UseTraps) {
TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
return false;
@@ -4288,7 +4289,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
// (d)rem(u) $0, $X, $Y is a special case. Like div $zero, $X, $Y, it does
// not expand to macro sequence.
- if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) {
+ if (isRem && (RdReg == Mips::R0 || RdReg == Mips::R0_64)) {
TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
return false;
}
@@ -4339,17 +4340,17 @@ bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
- TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
- TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
+ TOut.emitRR(Mips::CFC1, ThirdReg, Mips::R31, IDLoc, STI);
+ TOut.emitRR(Mips::CFC1, ThirdReg, Mips::R31, IDLoc, STI);
TOut.emitNop(IDLoc, STI);
TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI);
TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI);
- TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI);
+ TOut.emitRR(Mips::CTC1, Mips::R31, ATReg, IDLoc, STI);
TOut.emitNop(IDLoc, STI);
TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)
: Mips::CVT_W_S,
FirstReg, SecondReg, IDLoc, STI);
- TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI);
+ TOut.emitRR(Mips::CTC1, Mips::R31, ThirdReg, IDLoc, STI);
TOut.emitNop(IDLoc, STI);
return false;
}
@@ -4514,7 +4515,7 @@ bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI);
if (DoMove)
- TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);
+ TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::R0, IDLoc, STI);
return false;
}
@@ -4865,7 +4866,7 @@ bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
}
if (Inst.getOpcode() == Mips::ROL) {
- TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
+ TOut.emitRRR(Mips::SUBu, TmpReg, Mips::R0, TReg, Inst.getLoc(), STI);
TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
return false;
}
@@ -4896,7 +4897,7 @@ bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
if (!ATReg)
return true;
- TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
+ TOut.emitRRR(Mips::SUBu, ATReg, Mips::R0, TReg, Inst.getLoc(), STI);
TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
@@ -4990,7 +4991,7 @@ bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
}
if (Inst.getOpcode() == Mips::DROL) {
- TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
+ TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::R0, TReg, Inst.getLoc(), STI);
TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
return false;
}
@@ -5021,7 +5022,7 @@ bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
if (!ATReg)
return true;
- TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
+ TOut.emitRRR(Mips::DSUBu, ATReg, Mips::R0, TReg, Inst.getLoc(), STI);
TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
@@ -5135,10 +5136,10 @@ bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI);
if (FirstRegOp != SecondRegOp)
- TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);
+ TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::R0, IDLoc, STI);
else
TOut.emitEmptyDelaySlot(false, IDLoc, STI);
- TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);
+ TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::R0, SecondRegOp, IDLoc, STI);
return false;
}
@@ -5225,14 +5226,14 @@ bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
if (useTraps()) {
- TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI);
+ TOut.emitRRI(Mips::TNE, ATReg, Mips::R0, 6, IDLoc, STI);
} else {
MCContext &Context = TOut.getContext();
MCSymbol * BrTarget = Context.createTempSymbol();
MCOperand LabelOp =
MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
- TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI);
+ TOut.emitRRX(Mips::BEQ, ATReg, Mips::R0, LabelOp, IDLoc, STI);
if (AssemblerOptions.back()->isReorder())
TOut.emitNop(IDLoc, STI);
TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
@@ -5361,13 +5362,13 @@ bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
warnIfNoMacro(IDLoc);
- if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
+ if (SrcReg != Mips::R0 && OpReg != Mips::R0) {
TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
return false;
}
- MCRegister Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
+ MCRegister Reg = SrcReg == Mips::R0 ? OpReg : SrcReg;
TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI);
return false;
}
@@ -5392,7 +5393,7 @@ bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return false;
}
- if (SrcReg == Mips::ZERO) {
+ if (SrcReg == Mips::R0) {
Warning(IDLoc, "comparison is always false");
TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu,
DstReg, SrcReg, SrcReg, IDLoc, STI);
@@ -5442,14 +5443,14 @@ bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
warnIfNoMacro(IDLoc);
- if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
+ if (SrcReg != Mips::R0 && OpReg != Mips::R0) {
TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
- TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
+ TOut.emitRRR(Mips::SLTu, DstReg, Mips::R0, DstReg, IDLoc, STI);
return false;
}
- MCRegister Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
- TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI);
+ MCRegister Reg = SrcReg == Mips::R0 ? OpReg : SrcReg;
+ TOut.emitRRR(Mips::SLTu, DstReg, Mips::R0, Reg, IDLoc, STI);
return false;
}
@@ -5469,11 +5470,11 @@ bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
warnIfNoMacro(IDLoc);
if (ImmValue == 0) {
- TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI);
+ TOut.emitRRR(Mips::SLTu, DstReg, Mips::R0, SrcReg, IDLoc, STI);
return false;
}
- if (SrcReg == Mips::ZERO) {
+ if (SrcReg == Mips::R0) {
Warning(IDLoc, "comparison is always true");
if (loadImmediate(1, DstReg, MCRegister(), true, false, IDLoc, Out, STI))
return true;
@@ -5490,7 +5491,7 @@ bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
if (isUInt<16>(ImmValue)) {
TOut.emitRRI(Opc, DstReg, SrcReg, ImmValue, IDLoc, STI);
- TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
+ TOut.emitRRR(Mips::SLTu, DstReg, Mips::R0, DstReg, IDLoc, STI);
return false;
}
@@ -5503,7 +5504,7 @@ bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return true;
TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
- TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
+ TOut.emitRRR(Mips::SLTu, DstReg, Mips::R0, DstReg, IDLoc, STI);
return false;
}
@@ -5516,13 +5517,13 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
case Mips::MTTLO:
switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg().id()) {
case Mips::AC0:
- return Mips::ZERO;
+ return Mips::R0;
case Mips::AC1:
- return Mips::A0;
+ return Mips::R4;
case Mips::AC2:
- return Mips::T0;
+ return Mips::R8;
case Mips::AC3:
- return Mips::T4;
+ return Mips::R12;
default:
llvm_unreachable("Unknown register for 'mttr' alias!");
}
@@ -5530,13 +5531,13 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
case Mips::MTTHI:
switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg().id()) {
case Mips::AC0:
- return Mips::AT;
+ return Mips::R1;
case Mips::AC1:
- return Mips::A1;
+ return Mips::R5;
case Mips::AC2:
- return Mips::T1;
+ return Mips::R9;
case Mips::AC3:
- return Mips::T5;
+ return Mips::R13;
default:
llvm_unreachable("Unknown register for 'mttr' alias!");
}
@@ -5544,19 +5545,19 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
case Mips::MTTACX:
switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg().id()) {
case Mips::AC0:
- return Mips::V0;
+ return Mips::R2;
case Mips::AC1:
- return Mips::A2;
+ return Mips::R6;
case Mips::AC2:
- return Mips::T2;
+ return Mips::R10;
case Mips::AC3:
- return Mips::T6;
+ return Mips::R14;
default:
llvm_unreachable("Unknown register for 'mttr' alias!");
}
case Mips::MFTDSP:
case Mips::MTTDSP:
- return Mips::S0;
+ return Mips::R16;
default:
llvm_unreachable("Unknown instruction for 'mttr' dsp alias!");
}
@@ -5566,38 +5567,38 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
// operand.
static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg().id()) {
- case Mips::F0: return Mips::ZERO;
- case Mips::F1: return Mips::AT;
- case Mips::F2: return Mips::V0;
- case Mips::F3: return Mips::V1;
- case Mips::F4: return Mips::A0;
- case Mips::F5: return Mips::A1;
- case Mips::F6: return Mips::A2;
- case Mips::F7: return Mips::A3;
- case Mips::F8: return Mips::T0;
- case Mips::F9: return Mips::T1;
- case Mips::F10: return Mips::T2;
- case Mips::F11: return Mips::T3;
- case Mips::F12: return Mips::T4;
- case Mips::F13: return Mips::T5;
- case Mips::F14: return Mips::T6;
- case Mips::F15: return Mips::T7;
- case Mips::F16: return Mips::S0;
- case Mips::F17: return Mips::S1;
- case Mips::F18: return Mips::S2;
- case Mips::F19: return Mips::S3;
- case Mips::F20: return Mips::S4;
- case Mips::F21: return Mips::S5;
- case Mips::F22: return Mips::S6;
- case Mips::F23: return Mips::S7;
- case Mips::F24: return Mips::T8;
- case Mips::F25: return Mips::T9;
- case Mips::F26: return Mips::K0;
- case Mips::F27: return Mips::K1;
- case Mips::F28: return Mips::GP;
- case Mips::F29: return Mips::SP;
- case Mips::F30: return Mips::FP;
- case Mips::F31: return Mips::RA;
+ case Mips::F0: return Mips::R0;
+ case Mips::F1: return Mips::R1;
+ case Mips::F2: return Mips::R2;
+ case Mips::F3: return Mips::R3;
+ case Mips::F4: return Mips::R4;
+ case Mips::F5: return Mips::R5;
+ case Mips::F6: return Mips::R6;
+ case Mips::F7: return Mips::R7;
+ case Mips::F8: return Mips::R8;
+ case Mips::F9: return Mips::R9;
+ case Mips::F10: return Mips::R10;
+ case Mips::F11: return Mips::R11;
+ case Mips::F12: return Mips::R12;
+ case Mips::F13: return Mips::R13;
+ case Mips::F14: return Mips::R14;
+ case Mips::F15: return Mips::R15;
+ case Mips::F16: return Mips::R16;
+ case Mips::F17: return Mips::R17;
+ case Mips::F18: return Mips::R18;
+ case Mips::F19: return Mips::R19;
+ case Mips::F20: return Mips::R20;
+ case Mips::F21: return Mips::R21;
+ case Mips::F22: return Mips::R22;
+ case Mips::F23: return Mips::R23;
+ case Mips::F24: return Mips::R24;
+ case Mips::F25: return Mips::R25;
+ case Mips::F26: return Mips::R26;
+ case Mips::F27: return Mips::R27;
+ case Mips::F28: return Mips::R28;
+ case Mips::F29: return Mips::R29;
+ case Mips::F30: return Mips::R30;
+ case Mips::F31: return Mips::R31;
default: llvm_unreachable("Unknown register for mttc1 alias!");
}
}
@@ -5605,38 +5606,38 @@ static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
// Map the coprocessor operand the corresponding gpr register operand.
static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg().id()) {
- case Mips::COP00: return Mips::ZERO;
- case Mips::COP01: return Mips::AT;
- case Mips::COP02: return Mips::V0;
- case Mips::COP03: return Mips::V1;
- case Mips::COP04: return Mips::A0;
- case Mips::COP05: return Mips::A1;
- case Mips::COP06: return Mips::A2;
- case Mips::COP07: return Mips::A3;
- case Mips::COP08: return Mips::T0;
- case Mips::COP09: return Mips::T1;
- case Mips::COP010: return Mips::T2;
- case Mips::COP011: return Mips::T3;
- case Mips::COP012: return Mips::T4;
- case Mips::COP013: return Mips::T5;
- case Mips::COP014: return Mips::T6;
- case Mips::COP015: return Mips::T7;
- case Mips::COP016: return Mips::S0;
- case Mips::COP017: return Mips::S1;
- case Mips::COP018: return Mips::S2;
- case Mips::COP019: return Mips::S3;
- case Mips::COP020: return Mips::S4;
- case Mips::COP021: return Mips::S5;
- case Mips::COP022: return Mips::S6;
- case Mips::COP023: return Mips::S7;
- case Mips::COP024: return Mips::T8;
- case Mips::COP025: return Mips::T9;
- case Mips::COP026: return Mips::K0;
- case Mips::COP027: return Mips::K1;
- case Mips::COP028: return Mips::GP;
- case Mips::COP029: return Mips::SP;
- case Mips::COP030: return Mips::FP;
- case Mips::COP031: return Mips::RA;
+ case Mips::COP00: return Mips::R0;
+ case Mips::COP01: return Mips::R1;
+ case Mips::COP02: return Mips::R2;
+ case Mips::COP03: return Mips::R3;
+ case Mips::COP04: return Mips::R4;
+ case Mips::COP05: return Mips::R5;
+ case Mips::COP06: return Mips::R6;
+ case Mips::COP07: return Mips::R7;
+ case Mips::COP08: return Mips::R8;
+ case Mips::COP09: return Mips::R9;
+ case Mips::COP010: return Mips::R10;
+ case Mips::COP011: return Mips::R11;
+ case Mips::COP012: return Mips::R12;
+ case Mips::COP013: return Mips::R13;
+ case Mips::COP014: return Mips::R14;
+ case Mips::COP015: return Mips::R15;
+ case Mips::COP016: return Mips::R16;
+ case Mips::COP017: return Mips::R17;
+ case Mips::COP018: return Mips::R18;
+ case Mips::COP019: return Mips::R19;
+ case Mips::COP020: return Mips::R20;
+ case Mips::COP021: return Mips::R21;
+ case Mips::COP022: return Mips::R22;
+ case Mips::COP023: return Mips::R23;
+ case Mips::COP024: return Mips::R24;
+ case Mips::COP025: return Mips::R25;
+ case Mips::COP026: return Mips::R26;
+ case Mips::COP027: return Mips::R27;
+ case Mips::COP028: return Mips::R28;
+ case Mips::COP029: return Mips::R29;
+ case Mips::COP030: return Mips::R30;
+ case Mips::COP031: return Mips::R31;
default: llvm_unreachable("Unknown register for mttc0 alias!");
}
}
@@ -5766,8 +5767,8 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
// As described by the MIPSR6 spec, daui must not use the zero operand for
// its source operand.
case Mips::DAUI:
- if (Inst.getOperand(1).getReg() == Mips::ZERO ||
- Inst.getOperand(1).getReg() == Mips::ZERO_64)
+ if (Inst.getOperand(1).getReg() == Mips::R0 ||
+ Inst.getOperand(1).getReg() == Mips::R0_64)
return Match_RequiresNoZeroRegister;
return Match_Success;
// As described by the Mips32r2 spec, the registers Rd and Rs for
@@ -5820,8 +5821,8 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
case Mips::BLTZC64:
case Mips::BEQZC64:
case Mips::BNEZC64:
- if (Inst.getOperand(0).getReg() == Mips::ZERO ||
- Inst.getOperand(0).getReg() == Mips::ZERO_64)
+ if (Inst.getOperand(0).getReg() == Mips::R0 ||
+ Inst.getOperand(0).getReg() == Mips::R0_64)
return Match_RequiresNoZeroRegister;
return Match_Success;
case Mips::BGEC: case Mips::BGEC_MMR6:
@@ -5836,11 +5837,11 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
case Mips::BLTUC64:
case Mips::BEQC64:
case Mips::BNEC64:
- if (Inst.getOperand(0).getReg() == Mips::ZERO ||
- Inst.getOperand(0).getReg() == Mips::ZERO_64)
+ if (Inst.getOperand(0).getReg() == Mips::R0 ||
+ Inst.getOperand(0).getReg() == Mips::R0_64)
return Match_RequiresNoZeroRegister;
- if (Inst.getOperand(1).getReg() == Mips::ZERO ||
- Inst.getOperand(1).getReg() == Mips::ZERO_64)
+ if (Inst.getOperand(1).getReg() == Mips::R0 ||
+ Inst.getOperand(1).getReg() == Mips::R0_64)
return Match_RequiresNoZeroRegister;
if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
return Match_RequiresDifferentOperands;
@@ -6763,14 +6764,14 @@ ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) {
if (RegRange) {
// Remove last register operand because registers from register range
// should be inserted first.
- if ((isGP64bit() && Reg == Mips::RA_64) ||
- (!isGP64bit() && Reg == Mips::RA)) {
+ if ((isGP64bit() && Reg == Mips::R31_64) ||
+ (!isGP64bit() && Reg == Mips::R31)) {
Regs.push_back(Reg);
} else {
MCRegister TmpReg = PrevReg + 1;
while (TmpReg <= Reg) {
- if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) ||
- (((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) &&
+ if ((((TmpReg < Mips::R16) || (TmpReg > Mips::R23)) && !isGP64bit()) ||
+ (((TmpReg < Mips::R16_64) || (TmpReg > Mips::R23_64)) &&
isGP64bit()))
return Error(E, "invalid register operand");
@@ -6783,19 +6784,19 @@ ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) {
RegRange = false;
} else {
if (!PrevReg.isValid() &&
- ((isGP64bit() && (Reg != Mips::S0_64) && (Reg != Mips::RA_64)) ||
- (!isGP64bit() && (Reg != Mips::S0) && (Reg != Mips::RA))))
+ ((isGP64bit() && (Reg != Mips::R16_64) && (Reg != Mips::R31_64)) ||
+ (!isGP64bit() && (Reg != Mips::R16) && (Reg != Mips::R31))))
return Error(E, "$16 or $31 expected");
- if (!(((Reg == Mips::FP || Reg == Mips::RA ||
- (Reg >= Mips::S0 && Reg <= Mips::S7)) &&
+ if (!(((Reg == Mips::R30 || Reg == Mips::R31 ||
+ (Reg >= Mips::R16 && Reg <= Mips::R23)) &&
!isGP64bit()) ||
- ((Reg == Mips::FP_64 || Reg == Mips::RA_64 ||
- (Reg >= Mips::S0_64 && Reg <= Mips::S7_64)) &&
+ ((Reg == Mips::R30_64 || Reg == Mips::R31_64 ||
+ (Reg >= Mips::R16_64 && Reg <= Mips::R23_64)) &&
isGP64bit())))
return Error(E, "invalid register operand");
if (PrevReg.isValid() && (Reg != PrevReg + 1) &&
- ((Reg != Mips::FP && Reg != Mips::RA && !isGP64bit()) ||
- (Reg != Mips::FP_64 && Reg != Mips::RA_64 && isGP64bit())))
+ ((Reg != Mips::R30 && Reg != Mips::R31 && !isGP64bit()) ||
+ (Reg != Mips::R30_64 && Reg != Mips::R31_64 && isGP64bit())))
return Error(E, "consecutive register numbers expected");
Regs.push_back(Reg);
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index bbd614fc64423..d6a6cb5a3fa43 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -241,8 +241,8 @@ static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
- unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4,
- Mips::S5, Mips::S6, Mips::S7, Mips::FP};
+ unsigned Regs[] = {Mips::R16, Mips::R17, Mips::R18, Mips::R19, Mips::R20,
+ Mips::R21, Mips::R22, Mips::R23, Mips::R30};
unsigned RegNum;
unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
@@ -261,7 +261,7 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
Inst.addOperand(MCOperand::createReg(Regs[i]));
if (RegLst & 0x10)
- Inst.addOperand(MCOperand::createReg(Mips::RA));
+ Inst.addOperand(MCOperand::createReg(Mips::R31));
return MCDisassembler::Success;
}
@@ -269,7 +269,7 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
- unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
+ unsigned Regs[] = {Mips::R16, Mips::R17, Mips::R18, Mips::R19};
unsigned RegLst;
switch (Inst.getOpcode()) {
default:
@@ -285,7 +285,7 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
for (unsigned i = 0; i <= RegNum; i++)
Inst.addOperand(MCOperand::createReg(Regs[i]));
- Inst.addOperand(MCOperand::createReg(Mips::RA));
+ Inst.addOperand(MCOperand::createReg(Mips::R31));
return MCDisassembler::Success;
}
@@ -1289,7 +1289,7 @@ static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
- Inst.addOperand(MCOperand::createReg(Mips::SP));
+ Inst.addOperand(MCOperand::createReg(Mips::R29));
Inst.addOperand(MCOperand::createImm(Offset << 2));
return MCDisassembler::Success;
@@ -1304,7 +1304,7 @@ static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
- Inst.addOperand(MCOperand::createReg(Mips::GP));
+ Inst.addOperand(MCOperand::createReg(Mips::R28));
Inst.addOperand(MCOperand::createImm(Offset << 2));
return MCDisassembler::Success;
@@ -1328,7 +1328,7 @@ static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
== MCDisassembler::Fail)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createReg(Mips::SP));
+ Inst.addOperand(MCOperand::createReg(Mips::R29));
Inst.addOperand(MCOperand::createImm(Offset << 2));
return MCDisassembler::Success;
@@ -1740,36 +1740,36 @@ static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
default:
return MCDisassembler::Fail;
case 0:
- Inst.addOperand(MCOperand::createReg(Mips::A1));
- Inst.addOperand(MCOperand::createReg(Mips::A2));
+ Inst.addOperand(MCOperand::createReg(Mips::R5));
+ Inst.addOperand(MCOperand::createReg(Mips::R6));
break;
case 1:
- Inst.addOperand(MCOperand::createReg(Mips::A1));
- Inst.addOperand(MCOperand::createReg(Mips::A3));
+ Inst.addOperand(MCOperand::createReg(Mips::R5));
+ Inst.addOperand(MCOperand::createReg(Mips::R7));
break;
case 2:
- Inst.addOperand(MCOperand::createReg(Mips::A2));
- Inst.addOperand(MCOperand::createReg(Mips::A3));
+ Inst.addOperand(MCOperand::createReg(Mips::R6));
+ Inst.addOperand(MCOperand::createReg(Mips::R7));
break;
case 3:
- Inst.addOperand(MCOperand::createReg(Mips::A0));
- Inst.addOperand(MCOperand::createReg(Mips::S5));
+ Inst.addOperand(MCOperand::createReg(Mips::R4));
+ Inst.addOperand(MCOperand::createReg(Mips::R21));
break;
case 4:
- Inst.addOperand(MCOperand::createReg(Mips::A0));
- Inst.addOperand(MCOperand::createReg(Mips::S6));
+ Inst.addOperand(MCOperand::createReg(Mips::R4));
+ Inst.addOperand(MCOperand::createReg(Mips::R22));
break;
case 5:
- Inst.addOperand(MCOperand::createReg(Mips::A0));
- Inst.addOperand(MCOperand::createReg(Mips::A1));
+ Inst.addOperand(MCOperand::createReg(Mips::R4));
+ Inst.addOperand(MCOperand::createReg(Mips::R5));
break;
case 6:
- Inst.addOperand(MCOperand::createReg(Mips::A0));
- Inst.addOperand(MCOperand::createReg(Mips::A2));
+ Inst.addOperand(MCOperand::createReg(Mips::R4));
+ Inst.addOperand(MCOperand::createReg(Mips::R6));
break;
case 7:
- Inst.addOperand(MCOperand::createReg(Mips::A0));
- Inst.addOperand(MCOperand::createReg(Mips::A3));
+ Inst.addOperand(MCOperand::createReg(Mips::R4));
+ Inst.addOperand(MCOperand::createReg(Mips::R7));
break;
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 57b1324af9481..68c8470d87080 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -26,14 +26,14 @@ cl::opt<bool>
cl::init(false));
namespace {
-static constexpr MCPhysReg O32IntRegs[] = {Mips::A0, Mips::A1, Mips::A2,
- Mips::A3};
-static constexpr MCPhysReg NABIIntRegs[] = {Mips::A0, Mips::A1, Mips::A2,
- Mips::A3, Mips::A4_N, Mips::A5_N,
- Mips::A6_N, Mips::A7_N};
+static constexpr MCPhysReg O32IntRegs[] = {Mips::R4, Mips::R5, Mips::R6,
+ Mips::R7};
+static constexpr MCPhysReg NABIIntRegs[] = {Mips::R4, Mips::R5, Mips::R6,
+ Mips::R7, Mips::R8, Mips::R9,
+ Mips::R10, Mips::R11};
static constexpr MCPhysReg Mips64IntRegs[] = {
- Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
- Mips::A4_N_64, Mips::A5_N_64, Mips::A6_N_64, Mips::A7_N_64};
+ Mips::R4_64, Mips::R5_64, Mips::R6_64, Mips::R7_64,
+ Mips::R8_64, Mips::R9_64, Mips::R10_64, Mips::R11_64};
struct GPR {
MCPhysReg Reg32;
@@ -41,47 +41,47 @@ struct GPR {
};
static constexpr GPR OABITempRegs[] = {
- {Mips::T0, Mips::T0_64}, {Mips::T1, Mips::T1_64}, {Mips::T2, Mips::T2_64},
- {Mips::T3, Mips::T3_64}, {Mips::T4, Mips::T4_64}, {Mips::T5, Mips::T5_64},
- {Mips::T6, Mips::T6_64}, {Mips::T7, Mips::T7_64}, {Mips::T8, Mips::T8_64},
- {Mips::T9, Mips::T9_64},
+ {Mips::R8, Mips::R8_64}, {Mips::R9, Mips::R9_64}, {Mips::R10, Mips::R10_64},
+ {Mips::R11, Mips::R11_64}, {Mips::R12, Mips::R12_64}, {Mips::R13, Mips::R13_64},
+ {Mips::R14, Mips::R14_64}, {Mips::R15, Mips::R15_64}, {Mips::R24, Mips::R24_64},
+ {Mips::R25, Mips::R25_64},
};
static constexpr GPR NABITempRegs[] = {
- {Mips::T0_N, Mips::T0_N_64},
- {Mips::T1_N, Mips::T1_N_64},
- {Mips::T2_N, Mips::T2_N_64},
- {Mips::T3_N, Mips::T3_N_64},
+ {Mips::R12, Mips::R12_64},
+ {Mips::R13, Mips::R13_64},
+ {Mips::R14, Mips::R14_64},
+ {Mips::R15, Mips::R15_64},
{Mips::NoRegister, Mips::NoRegister},
{Mips::NoRegister, Mips::NoRegister},
{Mips::NoRegister, Mips::NoRegister},
{Mips::NoRegister, Mips::NoRegister},
- {Mips::T8, Mips::T8_64},
- {Mips::T9, Mips::T9_64},
+ {Mips::R24, Mips::R24_64},
+ {Mips::R25, Mips::R25_64},
};
static constexpr GPR PABITempRegs[] = {
- {Mips::T0_P, Mips::T0_P_64},
- {Mips::T1_P, Mips::T1_P_64},
- {Mips::T2_P, Mips::T2_P_64},
- {Mips::T3_P, Mips::T3_P_64},
- {Mips::T4_P, Mips::T4_P_64},
- {Mips::T5_P, Mips::T5_P_64},
+ {Mips::R12, Mips::R12_64},
+ {Mips::R13, Mips::R13_64},
+ {Mips::R14, Mips::R14_64},
+ {Mips::R15, Mips::R15_64},
+ {Mips::R2, Mips::R2_64},
+ {Mips::R3, Mips::R3_64},
{Mips::NoRegister, Mips::NoRegister},
{Mips::NoRegister, Mips::NoRegister},
- {Mips::T8, Mips::T8_64},
- {Mips::T9, Mips::T9_64},
+ {Mips::R24, Mips::R24_64},
+ {Mips::R25, Mips::R25_64},
};
static constexpr GPR SavedRegs[] = {
- {Mips::S0, Mips::S0_64}, {Mips::S1, Mips::S1_64}, {Mips::S2, Mips::S2_64},
- {Mips::S3, Mips::S3_64}, {Mips::S4, Mips::S4_64}, {Mips::S5, Mips::S5_64},
- {Mips::S6, Mips::S6_64}, {Mips::S7, Mips::S7_64},
+ {Mips::R16, Mips::R16_64}, {Mips::R17, Mips::R17_64}, {Mips::R18, Mips::R18_64},
+ {Mips::R19, Mips::R19_64}, {Mips::R20, Mips::R20_64}, {Mips::R21, Mips::R21_64},
+ {Mips::R22, Mips::R22_64}, {Mips::R23, Mips::R23_64},
};
static constexpr GPR ReturnRegs[] = {
- {Mips::V0, Mips::V0_64},
- {Mips::V1, Mips::V1_64},
+ {Mips::R2, Mips::R2_64},
+ {Mips::R3, Mips::R3_64},
};
MCRegister getReg(ArrayRef<GPR> Regs, unsigned I, bool Is64Bit) {
@@ -189,25 +189,25 @@ MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef ABIName) {
}
unsigned MipsABIInfo::GetStackPtr() const {
- return ArePtrs64bit() ? Mips::SP_64 : Mips::SP;
+ return ArePtrs64bit() ? Mips::R29_64 : Mips::R29;
}
unsigned MipsABIInfo::GetFramePtr() const {
- return ArePtrs64bit() ? Mips::FP_64 : Mips::FP;
+ return ArePtrs64bit() ? Mips::R30_64 : Mips::R30;
}
unsigned MipsABIInfo::GetBasePtr() const { return getSavedRegPtr(7); }
unsigned MipsABIInfo::GetGlobalPtr() const {
- return ArePtrs64bit() ? Mips::GP_64 : Mips::GP;
+ return ArePtrs64bit() ? Mips::R28_64 : Mips::R28;
}
unsigned MipsABIInfo::GetNullPtr() const {
- return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO;
+ return ArePtrs64bit() ? Mips::R0_64 : Mips::R0;
}
unsigned MipsABIInfo::GetZeroReg() const {
- return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO;
+ return AreGprs64bit() ? Mips::R0_64 : Mips::R0;
}
unsigned MipsABIInfo::GetPtrAdduOp() const {
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
index f67356c105a4d..6391792726384 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
@@ -274,26 +274,26 @@ bool MipsInstPrinter::printAlias(const MCInst &MI, uint64_t Address,
case Mips::BEQ_MM:
// beq $zero, $zero, $L2 => b $L2
// beq $r0, $zero, $L2 => beqz $r0, $L2
- return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
+ return (isReg<Mips::R0>(MI, 0) && isReg<Mips::R0>(MI, 1) &&
printAlias("b", MI, Address, 2, STI, OS, true)) ||
- (isReg<Mips::ZERO>(MI, 1) &&
+ (isReg<Mips::R0>(MI, 1) &&
printAlias("beqz", MI, Address, 0, 2, STI, OS, true));
case Mips::BEQ64:
// beq $r0, $zero, $L2 => beqz $r0, $L2
- return isReg<Mips::ZERO_64>(MI, 1) &&
+ return isReg<Mips::R0_64>(MI, 1) &&
printAlias("beqz", MI, Address, 0, 2, STI, OS, true);
case Mips::BNE:
case Mips::BNE_MM:
// bne $r0, $zero, $L2 => bnez $r0, $L2
- return isReg<Mips::ZERO>(MI, 1) &&
+ return isReg<Mips::R0>(MI, 1) &&
printAlias("bnez", MI, Address, 0, 2, STI, OS, true);
case Mips::BNE64:
// bne $r0, $zero, $L2 => bnez $r0, $L2
- return isReg<Mips::ZERO_64>(MI, 1) &&
+ return isReg<Mips::R0_64>(MI, 1) &&
printAlias("bnez", MI, Address, 0, 2, STI, OS, true);
case Mips::BGEZAL:
// bgezal $zero, $L1 => bal $L1
- return isReg<Mips::ZERO>(MI, 0) &&
+ return isReg<Mips::R0>(MI, 0) &&
printAlias("bal", MI, Address, 1, STI, OS, true);
case Mips::BC1T:
// bc1t $fcc0, $L1 => bc1t $L1
@@ -306,32 +306,32 @@ bool MipsInstPrinter::printAlias(const MCInst &MI, uint64_t Address,
case Mips::JALR:
// jalr $zero, $r1 => jr $r1
// jalr $ra, $r1 => jalr $r1
- return (isReg<Mips::ZERO>(MI, 0) &&
+ return (isReg<Mips::R0>(MI, 0) &&
printAlias("jr", MI, Address, 1, STI, OS)) ||
- (isReg<Mips::RA>(MI, 0) &&
+ (isReg<Mips::R31>(MI, 0) &&
printAlias("jalr", MI, Address, 1, STI, OS));
case Mips::JALR64:
// jalr $zero, $r1 => jr $r1
// jalr $ra, $r1 => jalr $r1
- return (isReg<Mips::ZERO_64>(MI, 0) &&
+ return (isReg<Mips::R0_64>(MI, 0) &&
printAlias("jr", MI, Address, 1, STI, OS)) ||
- (isReg<Mips::RA_64>(MI, 0) &&
+ (isReg<Mips::R31_64>(MI, 0) &&
printAlias("jalr", MI, Address, 1, STI, OS));
case Mips::NOR:
case Mips::NOR_MM:
case Mips::NOR_MMR6:
// nor $r0, $r1, $zero => not $r0, $r1
- return isReg<Mips::ZERO>(MI, 2) &&
+ return isReg<Mips::R0>(MI, 2) &&
printAlias("not", MI, Address, 0, 1, STI, OS);
case Mips::NOR64:
// nor $r0, $r1, $zero => not $r0, $r1
- return isReg<Mips::ZERO_64>(MI, 2) &&
+ return isReg<Mips::R0_64>(MI, 2) &&
printAlias("not", MI, Address, 0, 1, STI, OS);
case Mips::OR:
case Mips::ADDu:
// or $r0, $r1, $zero => move $r0, $r1
// addu $r0, $r1, $zero => move $r0, $r1
- return isReg<Mips::ZERO>(MI, 2) &&
+ return isReg<Mips::R0>(MI, 2) &&
printAlias("move", MI, Address, 0, 1, STI, OS);
default:
return false;
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index bbfd0872cc4cd..10e0fa5e3e226 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -815,8 +815,8 @@ getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
const MCSubtargetInfo &STI) const {
// Register is encoded in bits 9-5, offset is encoded in bits 4-0.
assert(MI.getOperand(OpNo).isReg() &&
- (MI.getOperand(OpNo).getReg() == Mips::SP ||
- MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
+ (MI.getOperand(OpNo).getReg() == Mips::R29 ||
+ MI.getOperand(OpNo).getReg() == Mips::R29_64) &&
"Unexpected base register!");
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
Fixups, STI) >> 2;
@@ -830,7 +830,7 @@ getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
const MCSubtargetInfo &STI) const {
// Register is encoded in bits 9-7, offset is encoded in bits 6-0.
assert(MI.getOperand(OpNo).isReg() &&
- MI.getOperand(OpNo).getReg() == Mips::GP &&
+ MI.getOperand(OpNo).getReg() == Mips::R28 &&
"Unexpected base register!");
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
@@ -1068,29 +1068,29 @@ MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
const MCSubtargetInfo &STI) const {
unsigned res = 0;
- if (MI.getOperand(0).getReg() == Mips::A1 &&
- MI.getOperand(1).getReg() == Mips::A2)
+ if (MI.getOperand(0).getReg() == Mips::R5 &&
+ MI.getOperand(1).getReg() == Mips::R6)
res = 0;
- else if (MI.getOperand(0).getReg() == Mips::A1 &&
- MI.getOperand(1).getReg() == Mips::A3)
+ else if (MI.getOperand(0).getReg() == Mips::R5 &&
+ MI.getOperand(1).getReg() == Mips::R7)
res = 1;
- else if (MI.getOperand(0).getReg() == Mips::A2 &&
- MI.getOperand(1).getReg() == Mips::A3)
+ else if (MI.getOperand(0).getReg() == Mips::R6 &&
+ MI.getOperand(1).getReg() == Mips::R7)
res = 2;
- else if (MI.getOperand(0).getReg() == Mips::A0 &&
- MI.getOperand(1).getReg() == Mips::S5)
+ else if (MI.getOperand(0).getReg() == Mips::R4 &&
+ MI.getOperand(1).getReg() == Mips::R21)
res = 3;
- else if (MI.getOperand(0).getReg() == Mips::A0 &&
- MI.getOperand(1).getReg() == Mips::S6)
+ else if (MI.getOperand(0).getReg() == Mips::R4 &&
+ MI.getOperand(1).getReg() == Mips::R22)
res = 4;
- else if (MI.getOperand(0).getReg() == Mips::A0 &&
- MI.getOperand(1).getReg() == Mips::A1)
+ else if (MI.getOperand(0).getReg() == Mips::R4 &&
+ MI.getOperand(1).getReg() == Mips::R5)
res = 5;
- else if (MI.getOperand(0).getReg() == Mips::A0 &&
- MI.getOperand(1).getReg() == Mips::A2)
+ else if (MI.getOperand(0).getReg() == Mips::R4 &&
+ MI.getOperand(1).getReg() == Mips::R6)
res = 6;
- else if (MI.getOperand(0).getReg() == Mips::A0 &&
- MI.getOperand(1).getReg() == Mips::A3)
+ else if (MI.getOperand(0).getReg() == Mips::R4 &&
+ MI.getOperand(1).getReg() == Mips::R7)
res = 7;
return res;
@@ -1108,14 +1108,14 @@ MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
switch (Op.getReg().id()) {
default:
llvm_unreachable("Unknown register for movep!");
- case Mips::ZERO: return 0;
- case Mips::S1: return 1;
- case Mips::V0: return 2;
- case Mips::V1: return 3;
- case Mips::S0: return 4;
- case Mips::S2: return 5;
- case Mips::S3: return 6;
- case Mips::S4: return 7;
+ case Mips::R0: return 0;
+ case Mips::R17: return 1;
+ case Mips::R2: return 2;
+ case Mips::R3: return 3;
+ case Mips::R16: return 4;
+ case Mips::R18: return 5;
+ case Mips::R19: return 6;
+ case Mips::R20: return 7;
}
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
index fb4cff6b25a1b..35cae6654be70 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
@@ -84,10 +84,10 @@ int MIPS_MC::getCPURegisterIndex(StringRef Name, const MCRegisterInfo &MRI,
// NoRegAltName applies to all ABIs.
unsigned AltIdx;
} Aliases[] = {
- {"AT", Mips::AT, Mips::NoRegAltName},
- {"s8", Mips::FP, Mips::NoRegAltName},
- {"kt0", Mips::K0, Mips::NABIRegAltName},
- {"kt1", Mips::K1, Mips::NABIRegAltName},
+ {"AT", Mips::R1, Mips::NoRegAltName},
+ {"s8", Mips::R30, Mips::NoRegAltName},
+ {"kt0", Mips::R26, Mips::NABIRegAltName},
+ {"kt1", Mips::R27, Mips::NABIRegAltName},
};
for (const auto &Alias : Aliases)
if (Name == Alias.Name &&
@@ -100,10 +100,10 @@ int MIPS_MC::getCPURegisterIndex(StringRef Name, const MCRegisterInfo &MRI,
StringLiteral Name;
MCPhysReg Reg;
} Deprecated[] = {
- {"t4", Mips::T4},
- {"t5", Mips::T5},
- {"t6", Mips::T6},
- {"t7", Mips::T7},
+ {"t4", Mips::R12},
+ {"t5", Mips::R13},
+ {"t6", Mips::R14},
+ {"t7", Mips::R15},
};
for (const auto &Alias : Deprecated) {
if (Name == Alias.Name) {
@@ -122,38 +122,38 @@ void MIPS_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
codeview::RegisterId CVReg;
MCPhysReg Reg;
} RegMap[] = {
- {codeview::RegisterId::MIPS_ZERO, Mips::ZERO},
- {codeview::RegisterId::MIPS_AT, Mips::AT},
- {codeview::RegisterId::MIPS_V0, Mips::V0},
- {codeview::RegisterId::MIPS_V1, Mips::V1},
- {codeview::RegisterId::MIPS_A0, Mips::A0},
- {codeview::RegisterId::MIPS_A1, Mips::A1},
- {codeview::RegisterId::MIPS_A2, Mips::A2},
- {codeview::RegisterId::MIPS_A3, Mips::A3},
- {codeview::RegisterId::MIPS_T0, Mips::T0},
- {codeview::RegisterId::MIPS_T1, Mips::T1},
- {codeview::RegisterId::MIPS_T2, Mips::T2},
- {codeview::RegisterId::MIPS_T3, Mips::T3},
- {codeview::RegisterId::MIPS_T4, Mips::T4},
- {codeview::RegisterId::MIPS_T5, Mips::T5},
- {codeview::RegisterId::MIPS_T6, Mips::T6},
- {codeview::RegisterId::MIPS_T7, Mips::T7},
- {codeview::RegisterId::MIPS_S0, Mips::S0},
- {codeview::RegisterId::MIPS_S1, Mips::S1},
- {codeview::RegisterId::MIPS_S2, Mips::S2},
- {codeview::RegisterId::MIPS_S3, Mips::S3},
- {codeview::RegisterId::MIPS_S4, Mips::S4},
- {codeview::RegisterId::MIPS_S5, Mips::S5},
- {codeview::RegisterId::MIPS_S6, Mips::S6},
- {codeview::RegisterId::MIPS_S7, Mips::S7},
- {codeview::RegisterId::MIPS_T8, Mips::T8},
- {codeview::RegisterId::MIPS_T9, Mips::T9},
- {codeview::RegisterId::MIPS_K0, Mips::K0},
- {codeview::RegisterId::MIPS_K1, Mips::K1},
- {codeview::RegisterId::MIPS_GP, Mips::GP},
- {codeview::RegisterId::MIPS_SP, Mips::SP},
- {codeview::RegisterId::MIPS_S8, Mips::FP},
- {codeview::RegisterId::MIPS_RA, Mips::RA},
+ {codeview::RegisterId::MIPS_ZERO, Mips::R0},
+ {codeview::RegisterId::MIPS_AT, Mips::R1},
+ {codeview::RegisterId::MIPS_V0, Mips::R2},
+ {codeview::RegisterId::MIPS_V1, Mips::R3},
+ {codeview::RegisterId::MIPS_A0, Mips::R4},
+ {codeview::RegisterId::MIPS_A1, Mips::R5},
+ {codeview::RegisterId::MIPS_A2, Mips::R6},
+ {codeview::RegisterId::MIPS_A3, Mips::R7},
+ {codeview::RegisterId::MIPS_T0, Mips::R8},
+ {codeview::RegisterId::MIPS_T1, Mips::R9},
+ {codeview::RegisterId::MIPS_T2, Mips::R10},
+ {codeview::RegisterId::MIPS_T3, Mips::R11},
+ {codeview::RegisterId::MIPS_T4, Mips::R12},
+ {codeview::RegisterId::MIPS_T5, Mips::R13},
+ {codeview::RegisterId::MIPS_T6, Mips::R14},
+ {codeview::RegisterId::MIPS_T7, Mips::R15},
+ {codeview::RegisterId::MIPS_S0, Mips::R16},
+ {codeview::RegisterId::MIPS_S1, Mips::R17},
+ {codeview::RegisterId::MIPS_S2, Mips::R18},
+ {codeview::RegisterId::MIPS_S3, Mips::R19},
+ {codeview::RegisterId::MIPS_S4, Mips::R20},
+ {codeview::RegisterId::MIPS_S5, Mips::R21},
+ {codeview::RegisterId::MIPS_S6, Mips::R22},
+ {codeview::RegisterId::MIPS_S7, Mips::R23},
+ {codeview::RegisterId::MIPS_T8, Mips::R24},
+ {codeview::RegisterId::MIPS_T9, Mips::R25},
+ {codeview::RegisterId::MIPS_K0, Mips::R26},
+ {codeview::RegisterId::MIPS_K1, Mips::R27},
+ {codeview::RegisterId::MIPS_GP, Mips::R28},
+ {codeview::RegisterId::MIPS_SP, Mips::R29},
+ {codeview::RegisterId::MIPS_S8, Mips::R30},
+ {codeview::RegisterId::MIPS_RA, Mips::R31},
{codeview::RegisterId::MIPS_LO, Mips::HI0},
{codeview::RegisterId::MIPS_HI, Mips::LO0},
{codeview::RegisterId::MIPS_Fir, Mips::FCR0},
@@ -229,7 +229,7 @@ static MCInstrInfo *createMipsMCInstrInfo() {
static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
MCRegisterInfo *X = new MCRegisterInfo();
- InitMipsMCRegisterInfo(X, Mips::RA);
+ InitMipsMCRegisterInfo(X, Mips::R31);
return X;
}
@@ -249,7 +249,7 @@ static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
else
MAI = new MipsELFMCAsmInfo(TT, Options);
- unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
+ unsigned SP = MRI.getDwarfRegNum(Mips::R29, true);
MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP);
MAI->addInitialFrameState(Inst);
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
index 23d812337a771..d21d76ab2db22 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
@@ -79,128 +79,6 @@ int getCPURegisterIndex(StringRef Name, const MCRegisterInfo &MRI,
#define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc"
-namespace llvm {
-namespace Mips {
-// R2-R3 and R8-R15 have different names in the O32 (O), N32/N64 (N) and
-// P32/P64 (P) ABIs. These aliases match the ones in MipsRegisterInfo.td; the
-// unsuffixed O names are kept for compatibility. The remaining O32-role
-// aliases (ZERO, AT, A0-A3, S0-S7, T8-T9, K0-K1, GP, SP, FP, RA) below are
-// to be removed in favour of MipsABIInfo accessors or plain R<n> names.
-
-// O32 names for R2-R3/R8-R15.
-inline constexpr MCPhysReg V0 = R2;
-inline constexpr MCPhysReg V1 = R3;
-inline constexpr MCPhysReg T0 = R8;
-inline constexpr MCPhysReg T1 = R9;
-inline constexpr MCPhysReg T2 = R10;
-inline constexpr MCPhysReg T3 = R11;
-inline constexpr MCPhysReg T4 = R12;
-inline constexpr MCPhysReg T5 = R13;
-inline constexpr MCPhysReg T6 = R14;
-inline constexpr MCPhysReg T7 = R15;
-inline constexpr MCPhysReg V0_64 = R2_64;
-inline constexpr MCPhysReg V1_64 = R3_64;
-inline constexpr MCPhysReg T0_64 = R8_64;
-inline constexpr MCPhysReg T1_64 = R9_64;
-inline constexpr MCPhysReg T2_64 = R10_64;
-inline constexpr MCPhysReg T3_64 = R11_64;
-inline constexpr MCPhysReg T4_64 = R12_64;
-inline constexpr MCPhysReg T5_64 = R13_64;
-inline constexpr MCPhysReg T6_64 = R14_64;
-inline constexpr MCPhysReg T7_64 = R15_64;
-
-// N32/N64 names.
-inline constexpr MCPhysReg V0_N = R2;
-inline constexpr MCPhysReg V1_N = R3;
-inline constexpr MCPhysReg A4_N = R8;
-inline constexpr MCPhysReg A5_N = R9;
-inline constexpr MCPhysReg A6_N = R10;
-inline constexpr MCPhysReg A7_N = R11;
-inline constexpr MCPhysReg T0_N = R12;
-inline constexpr MCPhysReg T1_N = R13;
-inline constexpr MCPhysReg T2_N = R14;
-inline constexpr MCPhysReg T3_N = R15;
-inline constexpr MCPhysReg V0_N_64 = R2_64;
-inline constexpr MCPhysReg V1_N_64 = R3_64;
-inline constexpr MCPhysReg A4_N_64 = R8_64;
-inline constexpr MCPhysReg A5_N_64 = R9_64;
-inline constexpr MCPhysReg A6_N_64 = R10_64;
-inline constexpr MCPhysReg A7_N_64 = R11_64;
-inline constexpr MCPhysReg T0_N_64 = R12_64;
-inline constexpr MCPhysReg T1_N_64 = R13_64;
-inline constexpr MCPhysReg T2_N_64 = R14_64;
-inline constexpr MCPhysReg T3_N_64 = R15_64;
-
-// P32/P64 names.
-inline constexpr MCPhysReg T4_P = R2;
-inline constexpr MCPhysReg T5_P = R3;
-inline constexpr MCPhysReg A4_P = R8;
-inline constexpr MCPhysReg A5_P = R9;
-inline constexpr MCPhysReg A6_P = R10;
-inline constexpr MCPhysReg A7_P = R11;
-inline constexpr MCPhysReg T0_P = R12;
-inline constexpr MCPhysReg T1_P = R13;
-inline constexpr MCPhysReg T2_P = R14;
-inline constexpr MCPhysReg T3_P = R15;
-inline constexpr MCPhysReg T4_P_64 = R2_64;
-inline constexpr MCPhysReg T5_P_64 = R3_64;
-inline constexpr MCPhysReg A4_P_64 = R8_64;
-inline constexpr MCPhysReg A5_P_64 = R9_64;
-inline constexpr MCPhysReg A6_P_64 = R10_64;
-inline constexpr MCPhysReg A7_P_64 = R11_64;
-inline constexpr MCPhysReg T0_P_64 = R12_64;
-inline constexpr MCPhysReg T1_P_64 = R13_64;
-inline constexpr MCPhysReg T2_P_64 = R14_64;
-inline constexpr MCPhysReg T3_P_64 = R15_64;
-
-// O32-role names for the remaining registers.
-inline constexpr MCPhysReg ZERO = R0;
-inline constexpr MCPhysReg AT = R1;
-inline constexpr MCPhysReg A0 = R4;
-inline constexpr MCPhysReg A1 = R5;
-inline constexpr MCPhysReg A2 = R6;
-inline constexpr MCPhysReg A3 = R7;
-inline constexpr MCPhysReg S0 = R16;
-inline constexpr MCPhysReg S1 = R17;
-inline constexpr MCPhysReg S2 = R18;
-inline constexpr MCPhysReg S3 = R19;
-inline constexpr MCPhysReg S4 = R20;
-inline constexpr MCPhysReg S5 = R21;
-inline constexpr MCPhysReg S6 = R22;
-inline constexpr MCPhysReg S7 = R23;
-inline constexpr MCPhysReg T8 = R24;
-inline constexpr MCPhysReg T9 = R25;
-inline constexpr MCPhysReg K0 = R26;
-inline constexpr MCPhysReg K1 = R27;
-inline constexpr MCPhysReg GP = R28;
-inline constexpr MCPhysReg SP = R29;
-inline constexpr MCPhysReg FP = R30;
-inline constexpr MCPhysReg RA = R31;
-inline constexpr MCPhysReg ZERO_64 = R0_64;
-inline constexpr MCPhysReg AT_64 = R1_64;
-inline constexpr MCPhysReg A0_64 = R4_64;
-inline constexpr MCPhysReg A1_64 = R5_64;
-inline constexpr MCPhysReg A2_64 = R6_64;
-inline constexpr MCPhysReg A3_64 = R7_64;
-inline constexpr MCPhysReg S0_64 = R16_64;
-inline constexpr MCPhysReg S1_64 = R17_64;
-inline constexpr MCPhysReg S2_64 = R18_64;
-inline constexpr MCPhysReg S3_64 = R19_64;
-inline constexpr MCPhysReg S4_64 = R20_64;
-inline constexpr MCPhysReg S5_64 = R21_64;
-inline constexpr MCPhysReg S6_64 = R22_64;
-inline constexpr MCPhysReg S7_64 = R23_64;
-inline constexpr MCPhysReg T8_64 = R24_64;
-inline constexpr MCPhysReg T9_64 = R25_64;
-inline constexpr MCPhysReg K0_64 = R26_64;
-inline constexpr MCPhysReg K1_64 = R27_64;
-inline constexpr MCPhysReg GP_64 = R28_64;
-inline constexpr MCPhysReg SP_64 = R29_64;
-inline constexpr MCPhysReg FP_64 = R30_64;
-inline constexpr MCPhysReg RA_64 = R31_64;
-} // namespace Mips
-} // namespace llvm
-
// Defines symbolic names for the Mips instructions.
#define GET_INSTRINFO_ENUM
#define GET_INSTRINFO_MC_HELPER_DECLS
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index f62ebc8b93b61..84ce25e0d7f0d 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -47,7 +47,7 @@ static bool isMips32r6(const MCSubtargetInfo *STI) {
}
MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
- : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
+ : MCTargetStreamer(S), GPReg(Mips::R28), ModuleDirectiveAllowed(true) {
GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
}
@@ -300,27 +300,27 @@ void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
unsigned Opc = Mips::SLL;
if (isMicroMips(STI) && hasShortDelaySlot) {
Opc = isMips32r6(STI) ? Mips::MOVE16_MMR6 : Mips::MOVE16_MM;
- emitRR(Opc, Mips::ZERO, Mips::ZERO, IDLoc, STI);
+ emitRR(Opc, Mips::R0, Mips::R0, IDLoc, STI);
return;
}
if (isMicroMips(STI))
Opc = isMips32r6(STI) ? Mips::SLL_MMR6 : Mips::SLL_MM;
- emitRRI(Opc, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
+ emitRRI(Opc, Mips::R0, Mips::R0, 0, IDLoc, STI);
}
void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
if (isMicroMips(STI))
- emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
+ emitRR(Mips::MOVE16_MM, Mips::R0, Mips::R0, IDLoc, STI);
else
- emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
+ emitRRI(Mips::SLL, Mips::R0, Mips::R0, 0, IDLoc, STI);
}
/// Emit the $gp restore operation for .cprestore.
void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
- emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
+ emitLoadWithImmOffset(Mips::LW, GPReg, Mips::R29, Offset, GPReg, IDLoc, STI);
}
/// Emit a store instruction with an immediate offset.
@@ -351,7 +351,7 @@ void MipsTargetStreamer::emitStoreWithImmOffset(
// Generate the base address in ATReg.
emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
- if (BaseReg != Mips::ZERO)
+ if (BaseReg != Mips::R0)
emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
// Emit the store with the adjusted base and offset.
emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
@@ -386,7 +386,7 @@ void MipsTargetStreamer::emitLoadWithImmOffset(
// Generate the base address in TmpReg.
emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
- if (BaseReg != Mips::ZERO)
+ if (BaseReg != Mips::R0)
emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
// Emit the load with the adjusted base and offset.
emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
@@ -1356,7 +1356,7 @@ bool MipsTargetELFStreamer::emitDirectiveCpRestore(
return true;
// Store the $gp on the stack.
- emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
+ emitStoreWithImmOffset(Mips::SW, GPReg, Mips::R29, Offset, GetATReg, IDLoc,
STI);
return true;
}
@@ -1377,10 +1377,10 @@ void MipsTargetELFStreamer::emitDirectiveCpsetup(MCRegister Reg,
// Either store the old $gp in a register or on the stack
if (IsReg) {
// move $save, $gpreg
- emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
+ emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::R0, SMLoc(), &STI);
} else {
// sd $gpreg, offset($sp)
- emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
+ emitRRI(Mips::SD, GPReg, Mips::R29, RegOrOffset, SMLoc(), &STI);
}
auto *HiExpr =
@@ -1416,11 +1416,11 @@ void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
Inst.setOpcode(Mips::OR);
Inst.addOperand(MCOperand::createReg(GPReg));
Inst.addOperand(MCOperand::createReg(SaveLocation));
- Inst.addOperand(MCOperand::createReg(Mips::ZERO));
+ Inst.addOperand(MCOperand::createReg(Mips::R0));
} else {
Inst.setOpcode(Mips::LD);
Inst.addOperand(MCOperand::createReg(GPReg));
- Inst.addOperand(MCOperand::createReg(Mips::SP));
+ Inst.addOperand(MCOperand::createReg(Mips::R29));
Inst.addOperand(MCOperand::createImm(SaveLocation));
}
getStreamer().emitInstruction(Inst, STI);
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
index 5487254c14ab3..0c62a473999a2 100644
--- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -279,37 +279,37 @@ class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
}
class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm,
@@ -326,7 +326,7 @@ class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
}
class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
@@ -361,7 +361,7 @@ class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm> {
bit isCall = 1;
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm> {
list<dag> Pattern = [(br bb:$offset)];
@@ -376,7 +376,7 @@ class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
let isBarrier = 1;
let hasDelaySlot = 0;
let AdditionalPredicates = [RelocPIC];
- let Defs = [AT];
+ let Defs = [R1];
}
class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
@@ -385,7 +385,7 @@ class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 0;
- let Defs = [AT];
+ let Defs = [R1];
}
class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
@@ -453,7 +453,7 @@ class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
MMR6Arch<opstr> {
let isCall = 1;
let hasDelaySlot = 0;
- let Defs = [RA];
+ let Defs = [R31];
let hasPostISelHook = 1;
}
class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
@@ -471,13 +471,13 @@ class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
GPR32Opnd> {
bit isCall = 1;
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
GPR32Opnd> {
bit isBarrier = 1;
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
}
class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
@@ -1188,7 +1188,7 @@ class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
!strconcat(opstr, "\t$rt, $offset"), [], FrmI>,
HARDFLOAT, BRANCH_DESC_BASE {
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
}
class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
@@ -1199,7 +1199,7 @@ class BRANCH_COP2_MMR6_DESC_BASE<string opstr>
dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(opstr, "\t$rt, $offset");
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
}
class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc">;
@@ -1234,7 +1234,7 @@ class JALRC_MMR6_DESC {
list<dag> Pattern = [];
bit isCall = 1;
bit hasDelaySlot = 0;
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
@@ -1243,7 +1243,7 @@ class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
}
class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
@@ -1581,9 +1581,9 @@ def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
//
//===----------------------------------------------------------------------===//
-def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
-def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
-def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
+def : MipsInstAlias<"ei", (EI_MMR6 R0), 1>, ISA_MICROMIPS32R6;
+def : MipsInstAlias<"di", (DI_MMR6 R0), 1>, ISA_MICROMIPS32R6;
+def : MipsInstAlias<"nop", (SLL_MMR6 R0, R0, 0), 1>, ISA_MICROMIPS32R6;
def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
!strconcat("b", "\t$offset")> {
string DecoderNamespace = "MicroMipsR6";
@@ -1606,13 +1606,13 @@ def : MipsInstAlias<"mfc0 $rt, $rs",
def : MipsInstAlias<"mfhc0 $rt, $rs",
(MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
ISA_MICROMIPS32R6;
-def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
+def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 R31, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"jal $offset", (BALC_MMR6 brtarget26_mm:$offset), 0>,
ISA_MICROMIPS32R6;
-def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
-def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
-def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
+def : MipsInstAlias<"dvp", (DVP_MMR6 R0), 0>, ISA_MICROMIPS32R6;
+def : MipsInstAlias<"evp", (EVP_MMR6 R0), 0>, ISA_MICROMIPS32R6;
+def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 R31, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"and $rs, $rt, $imm",
(ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
@@ -1633,25 +1633,25 @@ def : MipsInstAlias<"xor $rs, $imm",
(XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"not $rt, $rs",
- (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
+ (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, R0), 0>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"not $rt",
- (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
+ (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rt, R0), 0>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"lapc $rd, $imm",
(ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"neg $rt, $rs",
- (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
+ (SUB_MMR6 GPR32Opnd:$rt, R0, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"neg $rt",
- (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
+ (SUB_MMR6 GPR32Opnd:$rt, R0, GPR32Opnd:$rt), 1>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"negu $rt, $rs",
- (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
+ (SUBU_MMR6 GPR32Opnd:$rt, R0, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"negu $rt",
- (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
+ (SUBU_MMR6 GPR32Opnd:$rt, R0, GPR32Opnd:$rt), 1>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"beqz16 $rs, $offset", (BEQZC16_MMR6 GPRMM16Opnd:$rs,
brtarget7_mm:$offset),
@@ -1690,8 +1690,8 @@ defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
defm S_MMR6 : Cmp_Pats<f32>, ISA_MICROMIPS32R6;
defm D_MMR6 : Cmp_Pats<f64>, ISA_MICROMIPS32R6;
-def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
-def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6(MTC1_MMR6 ZERO))>,
+def : MipsPat<(f32 fpimm0), (MTC1_MMR6 R0)>, ISA_MICROMIPS32R6;
+def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6(MTC1_MMR6 R0))>,
ISA_MICROMIPS32R6;
def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
(TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
@@ -1704,18 +1704,18 @@ def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
def : MipsPat<(and GPR32:$src, immZExt16:$imm),
(ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
def : MipsPat<(i32 immZExt16:$imm),
- (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6;
+ (XORI_MMR6 R0, immZExt16:$imm)>, ISA_MICROMIPS32R6;
def : MipsPat<(not GPRMM16:$in),
(NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
def : MipsPat<(not GPR32:$in),
- (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
+ (NOR_MMR6 GPR32Opnd:$in, R0)>, ISA_MICROMIPS32R6;
// Patterns for load with a reg+imm operand.
let AddedComplexity = 41 in {
def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
}
-let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in {
+let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [R31] in {
class JumpLinkMMR6<Instruction JumpInst, DAGOperand Opnd> :
PseudoSE<(outs), (ins calltarget:$target), []>,
PseudoInstExpansion<(JumpInst Opnd:$target)>;
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
index 0c4344dde095e..dfe1b74288e0e 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
@@ -439,8 +439,8 @@ let AddedComplexity = 40 in {
def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src),
(MTC1_D64_MM GPR32Opnd:$src)>, ISA_MICROMIPS, FGR_64;
-def : MipsPat<(f32 fpimm0), (MTC1_MM ZERO)>, ISA_MICROMIPS32_NOT_MIPS32R6;
-def : MipsPat<(f32 fpimm0neg), (FNEG_S_MM (MTC1_MM ZERO))>,
+def : MipsPat<(f32 fpimm0), (MTC1_MM R0)>, ISA_MICROMIPS32_NOT_MIPS32R6;
+def : MipsPat<(f32 fpimm0neg), (FNEG_S_MM (MTC1_MM R0))>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsPat<(f32 (fpround FGR64Opnd:$src)),
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index d5f3ced35485b..e120fe9b89acf 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -200,7 +200,7 @@ class CompactBranchMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 0;
- let Defs = [AT];
+ let Defs = [R1];
}
let canFoldAsLoad = 1 in
@@ -412,7 +412,7 @@ class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
[(MipsJmpLink RO:$rs)], FrmR> {
let isCall = 1;
let hasDelaySlot = 1;
- let Defs = [RA];
+ let Defs = [R31];
let hasPostISelHook = 1;
}
@@ -441,7 +441,7 @@ class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
[], FrmR> {
let isCall = 1;
let hasDelaySlot = 1;
- let Defs = [RA];
+ let Defs = [R31];
}
// 16-bit Jump Register Compact - No delay slot
@@ -466,11 +466,11 @@ class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
- let Defs = [AT];
+ let Defs = [R1];
}
// MicroMIPS Jump and Link (Call) - Short Delay Slot
-let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
+let isCall = 1, hasDelaySlot = 1, Defs = [R31] in {
class JumpLinkMM<string opstr, DAGOperand opnd> :
InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
[], FrmJ, opstr> {
@@ -564,7 +564,7 @@ class UncondBranchMM16<string opstr> :
let isBarrier = 1;
let hasDelaySlot = 1;
let Predicates = [RelocPIC, InMicroMips];
- let Defs = [AT];
+ let Defs = [R1];
}
class HypcallMM<string opstr> :
@@ -1145,7 +1145,7 @@ let DecoderNamespace = "MicroMips" in {
// MicroMips arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
-defm : MipsHiLoRelocs<LUi_MM, ADDiu_MM, ZERO, GPR32Opnd>, ISA_MICROMIPS;
+defm : MipsHiLoRelocs<LUi_MM, ADDiu_MM, R0, GPR32Opnd>, ISA_MICROMIPS;
def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi_MM tglobaladdr:$in)>,
ISA_MICROMIPS;
@@ -1175,12 +1175,12 @@ def : MipsPat<(atomic_load_nonext_32 addr:$a), (LW_MM addr:$a)>, ISA_MICROMIPS;
def : MipsPat<(i32 immLi16:$imm),
(LI16_MM immLi16:$imm)>, ISA_MICROMIPS;
-defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>, ISA_MICROMIPS;
+defm : MaterializeImms<i32, R0, ADDiu_MM, LUi_MM, ORi_MM>, ISA_MICROMIPS;
def : MipsPat<(not GPRMM16:$in),
(NOT16_MM GPRMM16:$in)>, ISA_MICROMIPS;
def : MipsPat<(not GPR32:$in),
- (NOR_MM GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS;
+ (NOR_MM GPR32Opnd:$in, R0)>, ISA_MICROMIPS;
def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
(ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>, ISA_MICROMIPS;
@@ -1250,14 +1250,14 @@ def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
(TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
- SLTiu_MM, ZERO>, ISA_MICROMIPS32_NOT_MIPS32R6;
+ SLTiu_MM, R0>, ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
(BLEZ_MM i32:$lhs, bb:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
(BGEZ_MM i32:$lhs, bb:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
-defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>, ISA_MICROMIPS;
+defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, R0>, ISA_MICROMIPS;
defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>, ISA_MICROMIPS;
defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>, ISA_MICROMIPS;
defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>, ISA_MICROMIPS;
@@ -1309,21 +1309,21 @@ let EncodingPredicates = [InMicroMips] in {
0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
- def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
- def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>, ISA_MICROMIPS;
- def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
- def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;
+ def : MipsInstAlias<"nop", (SLL_MM R0, R0, 0), 1>, ISA_MICROMIPS;
+ def : MipsInstAlias<"nop", (MOVE16_MM R0, R0), 1>, ISA_MICROMIPS;
+ def : MipsInstAlias<"ei", (EI_MM R0), 1>, ISA_MICROMIPS;
+ def : MipsInstAlias<"di", (DI_MM R0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"neg $rt, $rs",
- (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
+ (SUB_MM GPR32Opnd:$rt, R0, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"neg $rt",
- (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
+ (SUB_MM GPR32Opnd:$rt, R0, GPR32Opnd:$rt), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"negu $rt, $rs",
- (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
+ (SUBu_MM GPR32Opnd:$rt, R0, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"negu $rt",
- (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
+ (SUBu_MM GPR32Opnd:$rt, R0, GPR32Opnd:$rt), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"teq $rs, $rt",
(TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
@@ -1388,16 +1388,16 @@ let EncodingPredicates = [InMicroMips] in {
defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>, ISA_MICROMIPS;
def : MipsInstAlias<"not $rt, $rs",
- (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
+ (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, R0), 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"not $rt",
- (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
+ (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, R0), 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"bnez $rs,$offset",
- (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
+ (BNE_MM GPR32Opnd:$rs, R0, brtarget:$offset), 0>,
ISA_MICROMIPS;
def : MipsInstAlias<"beqz $rs,$offset",
- (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
+ (BEQ_MM GPR32Opnd:$rs, R0, brtarget:$offset), 0>,
ISA_MICROMIPS;
def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MICROMIPS;
@@ -1406,10 +1406,10 @@ let EncodingPredicates = [InMicroMips] in {
def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>,
ISA_MICROMIPS;
- def : MipsInstAlias<"bal $offset", (BGEZAL_MM ZERO, brtarget_mm:$offset), 1>,
+ def : MipsInstAlias<"bal $offset", (BGEZAL_MM R0, brtarget_mm:$offset), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def : MipsInstAlias<"jalr.hb $rs", (JALR_HB_MM RA, GPR32Opnd:$rs), 0>,
+ def : MipsInstAlias<"jalr.hb $rs", (JALR_HB_MM R31, GPR32Opnd:$rs), 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsInstAlias<"j $rs", (JR_MM GPR32Opnd:$rs), 0>,
diff --git a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
index 4633df5d1b6a5..8168decac7e87 100644
--- a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
+++ b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
@@ -284,7 +284,7 @@ INITIALIZE_PASS(MicroMipsSizeReduce, DEBUG_TYPE, MICROMIPS_SIZE_REDUCE_NAME,
// Returns true if the machine operand MO is register SP.
static bool IsSP(const MachineOperand &MO) {
- if (MO.isReg() && ((MO.getReg() == Mips::SP)))
+ if (MO.isReg() && ((MO.getReg() == Mips::R29)))
return true;
return false;
}
@@ -362,7 +362,7 @@ static bool CheckXWPInstr(MachineInstr *MI, bool ReduceToLwp,
return false;
Register reg = MI->getOperand(0).getReg();
- if (reg == Mips::RA)
+ if (reg == Mips::R31)
return false;
if (!ImmInRange(MI, Entry))
@@ -377,11 +377,11 @@ static bool CheckXWPInstr(MachineInstr *MI, bool ReduceToLwp,
// Returns true if the registers Reg1 and Reg2 are consecutive
static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) {
constexpr std::array<unsigned, 31> Registers = {
- {Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
- Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6,
- Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
- Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP,
- Mips::SP, Mips::FP, Mips::RA}};
+ {Mips::R1, Mips::R2, Mips::R3, Mips::R4, Mips::R5, Mips::R6, Mips::R7,
+ Mips::R8, Mips::R9, Mips::R10, Mips::R11, Mips::R12, Mips::R13, Mips::R14,
+ Mips::R15, Mips::R16, Mips::R17, Mips::R18, Mips::R19, Mips::R20, Mips::R21,
+ Mips::R22, Mips::R23, Mips::R24, Mips::R25, Mips::R26, Mips::R27, Mips::R28,
+ Mips::R29, Mips::R30, Mips::R31}};
for (uint8_t i = 0; i < Registers.size() - 1; i++) {
if (Registers[i] == Reg1) {
@@ -572,9 +572,9 @@ bool MicroMipsSizeReduce::ReduceSXtoSX16(ReduceEntryFunArgs *Arguments) {
// of MOVEP instruction
static bool IsMovepSrcRegister(unsigned Reg) {
- if (Reg == Mips::ZERO || Reg == Mips::V0 || Reg == Mips::V1 ||
- Reg == Mips::S0 || Reg == Mips::S1 || Reg == Mips::S2 ||
- Reg == Mips::S3 || Reg == Mips::S4)
+ if (Reg == Mips::R0 || Reg == Mips::R2 || Reg == Mips::R3 ||
+ Reg == Mips::R16 || Reg == Mips::R17 || Reg == Mips::R18 ||
+ Reg == Mips::R19 || Reg == Mips::R20)
return true;
return false;
@@ -584,8 +584,8 @@ static bool IsMovepSrcRegister(unsigned Reg) {
// of MOVEP instruction
static bool IsMovepDestinationReg(unsigned Reg) {
- if (Reg == Mips::A0 || Reg == Mips::A1 || Reg == Mips::A2 ||
- Reg == Mips::A3 || Reg == Mips::S5 || Reg == Mips::S6)
+ if (Reg == Mips::R4 || Reg == Mips::R5 || Reg == Mips::R6 ||
+ Reg == Mips::R7 || Reg == Mips::R21 || Reg == Mips::R22)
return true;
return false;
@@ -595,14 +595,14 @@ static bool IsMovepDestinationReg(unsigned Reg) {
// registers in MOVEP instruction
static bool IsMovepDestinationRegPair(unsigned R0, unsigned R1) {
- if ((R0 == Mips::A0 && R1 == Mips::S5) ||
- (R0 == Mips::A0 && R1 == Mips::S6) ||
- (R0 == Mips::A0 && R1 == Mips::A1) ||
- (R0 == Mips::A0 && R1 == Mips::A2) ||
- (R0 == Mips::A0 && R1 == Mips::A3) ||
- (R0 == Mips::A1 && R1 == Mips::A2) ||
- (R0 == Mips::A1 && R1 == Mips::A3) ||
- (R0 == Mips::A2 && R1 == Mips::A3))
+ if ((R0 == Mips::R4 && R1 == Mips::R21) ||
+ (R0 == Mips::R4 && R1 == Mips::R22) ||
+ (R0 == Mips::R4 && R1 == Mips::R5) ||
+ (R0 == Mips::R4 && R1 == Mips::R6) ||
+ (R0 == Mips::R4 && R1 == Mips::R7) ||
+ (R0 == Mips::R5 && R1 == Mips::R6) ||
+ (R0 == Mips::R5 && R1 == Mips::R7) ||
+ (R0 == Mips::R6 && R1 == Mips::R7))
return true;
return false;
diff --git a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp
index 44fc720e6ce14..b6bff54c31a6d 100644
--- a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp
+++ b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp
@@ -51,7 +51,7 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
if (StackSize == 0 && !MFI.adjustsStack()) return;
// Adjust stack.
- TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
+ TII.makeFrame(Mips::R29, StackSize, MBB, MBBI);
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::NoFlags);
CFIBuilder.buildDefCFAOffset(StackSize);
@@ -64,8 +64,8 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
}
if (hasFP(MF))
- BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
- .addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::R16)
+ .addReg(Mips::R29).setMIFlag(MachineInstr::FrameSetup);
}
void Mips16FrameLowering::emitEpilogue(MachineFunction &MF,
@@ -81,12 +81,12 @@ void Mips16FrameLowering::emitEpilogue(MachineFunction &MF,
return;
if (hasFP(MF))
- BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
- .addReg(Mips::S0);
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::R29)
+ .addReg(Mips::R16);
// Adjust stack.
// assumes stacksize multiple of 8
- TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
+ TII.restoreFrame(Mips::R29, StackSize, MBB, MBBI);
}
bool Mips16FrameLowering::spillCalleeSavedRegisters(
@@ -106,7 +106,7 @@ bool Mips16FrameLowering::spillCalleeSavedRegisters(
// It's killed at the spill, unless the register is RA and return address
// is taken.
MCRegister Reg = I.getReg();
- bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
+ bool IsRAAndRetAddrIsTaken = (Reg == Mips::R31)
&& MF->getFrameInfo().isReturnAddressTaken();
if (!IsRAAndRetAddrIsTaken)
MBB.addLiveIn(Reg);
@@ -144,11 +144,11 @@ void Mips16FrameLowering::determineCalleeSaves(MachineFunction &MF,
*static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
const MipsRegisterInfo &RI = TII.getRegisterInfo();
const BitVector Reserved = RI.getReservedRegs(MF);
- bool SaveS2 = Reserved[Mips::S2];
+ bool SaveS2 = Reserved[Mips::R18];
if (SaveS2)
- SavedRegs.set(Mips::S2);
+ SavedRegs.set(Mips::R18);
if (hasFP(MF))
- SavedRegs.set(Mips::S0);
+ SavedRegs.set(Mips::R16);
}
const MipsFrameLowering *
diff --git a/llvm/lib/Target/Mips/Mips16ISelLowering.cpp b/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
index 122df08af99c1..25dbfdcff25e4 100644
--- a/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
+++ b/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
@@ -426,7 +426,7 @@ void Mips16TargetLowering::getOpndList(
// T9 should contain the address of the callee function if
// -relocation-model=pic or it is an indirect call.
if (IsPICCall || !GlobalOrExternal) {
- unsigned V0Reg = Mips::V0;
+ unsigned V0Reg = Mips::R2;
if (NeedMips16Helper) {
RegsToPass.push_front(std::make_pair(V0Reg, Callee));
JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction,
@@ -436,7 +436,7 @@ void Mips16TargetLowering::getOpndList(
MipsII::MO_GOT, Chain,
FuncInfo->callPtrInfo(MF, S->getSymbol()));
} else
- RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
+ RegsToPass.push_front(std::make_pair((unsigned)Mips::R25, Callee));
}
Ops.push_back(JumpTarget);
@@ -704,7 +704,7 @@ Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
.addReg(regX)
.addReg(regY);
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
- .addReg(Mips::T8);
+ .addReg(Mips::R24);
MI.eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
@@ -722,7 +722,7 @@ Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc,
unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
- .addReg(Mips::T8);
+ .addReg(Mips::R24);
MI.eraseFromParent(); // The pseudo instruction is gone now.
return BB;
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index f954ffb6cd6ed..a2224de2ce3e9 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -183,12 +183,12 @@ static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
// is taken.
Register Reg = CSI[e-i-1].getReg();
switch (Reg) {
- case Mips::RA:
- case Mips::S0:
- case Mips::S1:
+ case Mips::R31:
+ case Mips::R16:
+ case Mips::R17:
MIB.addReg(Reg, Flags);
break;
- case Mips::S2:
+ case Mips::R18:
break;
default:
llvm_unreachable("unexpected mips16 callee saved register");
@@ -205,14 +205,14 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
const BitVector Reserved = RI.getReservedRegs(MF);
- bool SaveS2 = Reserved[Mips::S2];
+ bool SaveS2 = Reserved[Mips::R18];
MachineInstrBuilder MIB;
unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
MIB = BuildMI(MBB, I, DL, get(Opc));
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
addSaveRestoreRegs(MIB, CSI);
if (SaveS2)
- MIB.addReg(Mips::S2);
+ MIB.addReg(Mips::R18);
if (isUInt<11>(FrameSize))
MIB.addImm(FrameSize);
else {
@@ -223,7 +223,7 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
if (isInt<16>(-Remainder))
BuildAddiuSpImm(MBB, I, -Remainder);
else
- adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
+ adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::R2, Mips::R3);
}
}
@@ -235,7 +235,7 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
MachineFunction *MF = MBB.getParent();
MachineFrameInfo &MFI = MF->getFrameInfo();
const BitVector Reserved = RI.getReservedRegs(*MF);
- bool SaveS2 = Reserved[Mips::S2];
+ bool SaveS2 = Reserved[Mips::R18];
MachineInstrBuilder MIB;
unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
Mips::Restore16:Mips::RestoreX16;
@@ -249,13 +249,13 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
if (isInt<16>(Remainder))
BuildAddiuSpImm(MBB, I, Remainder);
else
- adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
+ adjustStackPtrBig(SP, Remainder, MBB, I, Mips::R4, Mips::R5);
}
MIB = BuildMI(MBB, I, DL, get(Opc));
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
addSaveRestoreRegs(MIB, CSI, RegState::Define);
if (SaveS2)
- MIB.addReg(Mips::S2, RegState::Define);
+ MIB.addReg(Mips::R18, RegState::Define);
MIB.addImm(FrameSize);
}
@@ -278,12 +278,12 @@ void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
MIB1.addImm(Amount).addImm(-1);
MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
- MIB2.addReg(Mips::SP, RegState::Kill);
+ MIB2.addReg(Mips::R29, RegState::Kill);
MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
MIB3.addReg(Reg1);
MIB3.addReg(Reg2, RegState::Kill);
MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
- Mips::SP);
+ Mips::R29);
MIB4.addReg(Reg1, RegState::Kill);
}
@@ -380,7 +380,7 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
Candidates.reset(Reg);
if (DefReg != Reg) {
FirstRegSaved = Reg;
- FirstRegSavedTo = Mips::T0;
+ FirstRegSavedTo = Mips::R8;
copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
}
}
@@ -388,21 +388,21 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
Available.reset(Reg);
BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
NewImm = 0;
- if (FrameReg == Mips::SP) {
+ if (FrameReg == Mips::R29) {
SpReg = Available.find_first();
if (SpReg == -1) {
SpReg = Candidates.find_first();
// Candidates.reset(SpReg); // not really needed
if (DefReg!= SpReg) {
SecondRegSaved = SpReg;
- SecondRegSavedTo = Mips::T1;
+ SecondRegSavedTo = Mips::R9;
}
if (SecondRegSaved)
copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
} else {
Available.reset(SpReg);
}
- copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
+ copyPhysReg(MBB, II, DL, SpReg, Mips::R29, false);
BuildMI(MBB, II, DL, get(Mips::AdduRxRyRz16), Reg)
.addReg(SpReg, RegState::Kill)
.addReg(Reg);
@@ -473,7 +473,7 @@ bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
case Mips::LwRxSpImmX16:
return isInt<16>(Amount);
case Mips::AddiuRxRyOffMemX16:
- if ((Reg == Mips::PC) || (Reg == Mips::SP))
+ if ((Reg == Mips::PC) || (Reg == Mips::R29))
return isInt<16>(Amount);
return isInt<15>(Amount);
}
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.td b/llvm/lib/Target/Mips/Mips16InstrInfo.td
index 1505e50de1cf2..c9bae6b0e5416 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.td
@@ -529,15 +529,15 @@ def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu">;
//
def AddiuSpImm16
: FI816_SP_ins<0b011, "addiu"> {
- let Defs = [SP];
- let Uses = [SP];
+ let Defs = [R29];
+ let Uses = [R29];
let AddedComplexity = 5;
}
def AddiuSpImmX16
: FEXT_I816_SP_ins<0b011, "addiu"> {
- let Defs = [SP];
- let Uses = [SP];
+ let Defs = [R29];
+ let Uses = [R29];
}
//
@@ -612,11 +612,11 @@ def Break16: FRRBreakNull16_ins<"break 0">;
// To test special register T then do a PC-relative conditional branch.
//
def Bteqz16: FI816_ins<0b000, "bteqz">, cbranch16 {
- let Uses = [T8];
+ let Uses = [R24];
}
def BteqzX16: FEXT_I816_ins<0b000, "bteqz">, cbranch16 {
- let Uses = [T8];
+ let Uses = [R24];
}
def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
@@ -640,11 +640,11 @@ def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
//
def Btnez16: FI816_ins<0b001, "btnez">, cbranch16 {
- let Uses = [T8];
+ let Uses = [R24];
}
def BtnezX16: FEXT_I816_ins<0b001, "btnez"> ,cbranch16 {
- let Uses = [T8];
+ let Uses = [R24];
}
def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
@@ -666,7 +666,7 @@ def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
// To compare the contents of two GPRs.
//
def CmpRxRy16: FRR16R_ins<0b01010, "cmp"> {
- let Defs = [T8];
+ let Defs = [R24];
}
//
@@ -675,7 +675,7 @@ def CmpRxRy16: FRR16R_ins<0b01010, "cmp"> {
// To compare a constant with the contents of a GPR.
//
def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi"> {
- let Defs = [T8];
+ let Defs = [R24];
}
//
@@ -684,7 +684,7 @@ def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi"> {
// To compare a constant with the contents of a GPR.
//
def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi"> {
- let Defs = [T8];
+ let Defs = [R24];
}
@@ -715,13 +715,13 @@ def DivuRxRy16: FRR16_div_ins<0b11011, "divu"> {
def Jal16 : FJAL16_ins<0b0, "jal"> {
let hasDelaySlot = 0; // not true, but we add the nop for now
let isCall=1;
- let Defs = [RA];
+ let Defs = [R31];
}
def JalB16 : FJALB16_ins<0b0, "jal">, branch16 {
let hasDelaySlot = 0; // not true, but we add the nop for now
let isBranch=1;
- let Defs = [RA];
+ let Defs = [R31];
}
//
@@ -941,8 +941,8 @@ def Restore16:
FI8_SVRS16<0b1, (outs), (ins variable_ops),
"", [] >, MayLoad {
let isCodeGenOnly = 1;
- let Defs = [SP];
- let Uses = [SP];
+ let Defs = [R29];
+ let Uses = [R29];
}
@@ -950,8 +950,8 @@ def RestoreX16:
FI8_SVRS16<0b1, (outs), (ins variable_ops),
"", [] >, MayLoad {
let isCodeGenOnly = 1;
- let Defs = [SP];
- let Uses = [SP];
+ let Defs = [R29];
+ let Uses = [R29];
}
//
@@ -965,16 +965,16 @@ def Save16:
FI8_SVRS16<0b1, (outs), (ins variable_ops),
"", [] >, MayStore {
let isCodeGenOnly = 1;
- let Uses = [SP];
- let Defs = [SP];
+ let Uses = [R29];
+ let Defs = [R29];
}
def SaveX16:
FI8_SVRS16<0b1, (outs), (ins variable_ops),
"", [] >, MayStore {
let isCodeGenOnly = 1;
- let Uses = [SP];
- let Defs = [SP];
+ let Uses = [R29];
+ let Defs = [R29];
}
//
// Format: SB ry, offset(rx) MIPS16e
@@ -1144,7 +1144,7 @@ def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv">;
//
//
def SltiRxImm16: FRI16R_ins<0b01010, "slti"> {
- let Defs = [T8];
+ let Defs = [R24];
}
//
@@ -1154,7 +1154,7 @@ def SltiRxImm16: FRI16R_ins<0b01010, "slti"> {
//
//
def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti"> {
- let Defs = [T8];
+ let Defs = [R24];
}
def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
@@ -1165,7 +1165,7 @@ def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
//
//
def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu"> {
- let Defs = [T8];
+ let Defs = [R24];
}
//
@@ -1175,7 +1175,7 @@ def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu"> {
//
//
def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu"> {
- let Defs = [T8];
+ let Defs = [R24];
}
//
// Format: SLTIU rx, immediate MIPS16e
@@ -1190,7 +1190,7 @@ def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
// To record the result of a less-than comparison.
//
def SltRxRy16: FRR16R_ins<0b00010, "slt">{
- let Defs = [T8];
+ let Defs = [R24];
}
def SltCCRxRy16: FCCRR16_ins<"slt">;
@@ -1200,12 +1200,12 @@ def SltCCRxRy16: FCCRR16_ins<"slt">;
// To record the result of an unsigned less-than comparison.
//
def SltuRxRy16: FRR16R_ins<0b00011, "sltu">{
- let Defs = [T8];
+ let Defs = [R24];
}
def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
let isCodeGenOnly=1;
- let Defs = [T8];
+ let Defs = [R24];
}
@@ -1360,7 +1360,7 @@ let isCall=1, hasDelaySlot=0 in
def JumpLinkReg16:
FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rx),
"jalrc\t$rx", [(MipsJmpLink CPU16Regs:$rx)]> {
- let Defs = [RA];
+ let Defs = [R31];
}
// Mips16 pseudos
@@ -1521,7 +1521,7 @@ def: UncondBranch16_pat<br, Bimm16>;
// Small immediates
def: Mips16Pat<(i32 immSExt16:$in),
- (AddiuRxRxImmX16 (MoveR3216 ZERO), immSExt16:$in)>;
+ (AddiuRxRxImmX16 (MoveR3216 R0), immSExt16:$in)>;
def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
@@ -1889,4 +1889,4 @@ MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
// Instruction Aliases
let EncodingPredicates = [InMips16Mode] in
-def : MipsInstAlias<"nop", (Move32R16 ZERO, S0)>;
+def : MipsInstAlias<"nop", (Move32R16 R0, R16)>;
diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
index 66099593b6311..6f6cd1f55c9bb 100644
--- a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
@@ -51,8 +51,8 @@ bool Mips16RegisterInfo::saveScavengerRegister(
Register Reg) const {
DebugLoc DL;
const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
- TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
- TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
+ TII.copyPhysReg(MBB, I, DL, Mips::R8, Reg, true);
+ TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::R8, true);
return true;
}
@@ -89,17 +89,17 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
Register FrameReg;
if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)
- FrameReg = Mips::SP;
+ FrameReg = Mips::R29;
else {
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
if (TFI->hasFP(MF)) {
- FrameReg = Mips::S0;
+ FrameReg = Mips::R16;
}
else {
if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
FrameReg = MI.getOperand(OpNo+2).getReg();
else
- FrameReg = Mips::SP;
+ FrameReg = Mips::R29;
}
}
// Calculate final offset.
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 5283a5da43eee..a373cabcfccb8 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -389,7 +389,7 @@ class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
bit hasForbiddenSlot = 1;
bit isCTI = 1;
}
@@ -400,7 +400,7 @@ class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
bit hasForbiddenSlot = 1;
bit isCTI = 1;
}
@@ -411,7 +411,7 @@ class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
bit hasForbiddenSlot = 1;
bit isCTI = 1;
}
@@ -419,19 +419,19 @@ class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
bit isCall = 1;
bit hasDelaySlot = 1;
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
bit isCTI = 1;
}
class NAL_DESC : NAL_DESC_BASE<"nal"> {
bit hasDelaySlot = 1;
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
bit isCTI = 1;
}
class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
bit isCall = 1;
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
bit isCTI = 1;
}
@@ -492,14 +492,14 @@ class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
GPR32Opnd> {
bit isCall = 1;
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
GPR32Opnd> {
bit isBarrier = 1;
bit isTerminator = 1;
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
}
class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
@@ -551,27 +551,27 @@ class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
@@ -953,13 +953,13 @@ let AdditionalPredicates = [NotInMicroMips] in {
//
//===----------------------------------------------------------------------===//
-def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6;
-def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;
+def : MipsInstAlias<"dvp", (DVP R0), 0>, ISA_MIPS32R6;
+def : MipsInstAlias<"evp", (EVP R0), 0>, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
def : MipsInstAlias<"sigrie", (SIGRIE 0)>, ISA_MIPS32R6;
-def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>,
+def : MipsInstAlias<"jr $rs", (JALR R0, GPR32Opnd:$rs), 1>,
ISA_MIPS32R6, GPR_32;
}
@@ -1118,18 +1118,18 @@ def to_fclass_mask: SDNodeXForm<imm, [{
}]>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(is_fpclass f32:$lhs, i32:$imm),
- (SLTu ZERO, (ANDi (MFC1 (CLASS_S f32:$lhs)),
+ (SLTu R0, (ANDi (MFC1 (CLASS_S f32:$lhs)),
(to_fclass_mask imm:$imm)))>,
ISA_MIPS32R6;
def : MipsPat<(is_fpclass f64:$lhs, i32:$imm),
- (SLTu ZERO, (ANDi (MFC1_D64 (CLASS_D f64:$lhs)),
+ (SLTu R0, (ANDi (MFC1_D64 (CLASS_D f64:$lhs)),
(to_fclass_mask imm:$imm)))>,
ISA_MIPS32R6;
}
// Pseudo instructions
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
- hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT], hasPostISelHook = 1 in {
+ hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [R1], hasPostISelHook = 1 in {
class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> :
PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)]>,
PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>;
@@ -1150,8 +1150,8 @@ class PseudoIndirectBranchBaseR6<Instruction JumpInst, Register RT,
let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
NoIndirectJumpGuards] in {
- def TAILCALLR6REG : TailCallRegR6<JALR, ZERO, GPR32Opnd>, ISA_MIPS32R6;
- def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, ZERO,
+ def TAILCALLR6REG : TailCallRegR6<JALR, R0, GPR32Opnd>, ISA_MIPS32R6;
+ def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, R0,
GPR32Opnd>,
ISA_MIPS32R6;
}
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index b6d820bbc1025..bf927fbc12dbb 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -281,7 +281,7 @@ let isCodeGenOnly = 1 in {
def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>,
GPR_64;
let AdditionalPredicates = [NoIndirectJumpGuards] in
- def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>,
+ def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, R31, GPR32Opnd>,
PTR_64;
}
let AdditionalPredicates = [NotInMicroMips],
@@ -507,7 +507,7 @@ class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
- let Defs = [AT];
+ let Defs = [R1];
}
class MFC2OP<string asmstr, RegisterOperand RO> :
@@ -649,20 +649,20 @@ let DecoderNamespace = "Mips64" in {
}
let AdditionalPredicates = [UseIndirectJumpsHazard] in
- def JALRHB64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR_HB64, RA_64>, PTR_64;
+ def JALRHB64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR_HB64, R31_64>, PTR_64;
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
// Materialize i64 constants.
-defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>, ISA_MIPS3, GPR_64;
+defm : MaterializeImms<i64, R0_64, DADDiu, LUi64, ORi64>, ISA_MIPS3, GPR_64;
def : MipsPat<(i64 immZExt32Low16Zero:$imm),
- (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>, ISA_MIPS3, GPR_64;
+ (DSLL (ORi64 R0_64, (HI16 imm:$imm)), 16)>, ISA_MIPS3, GPR_64;
def : MipsPat<(i64 immZExt32:$imm),
- (ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16),
+ (ORi64 (DSLL (ORi64 R0_64, (HI16 imm:$imm)), 16),
(LO16 imm:$imm))>, ISA_MIPS3, GPR_64;
// extended loads
@@ -677,7 +677,7 @@ def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>, ISA_MIPS3,
// hi/lo relocs
let AdditionalPredicates = [NotInMicroMips] in
-defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, ISA_MIPS3, GPR_64,
+defm : MipsHiLoRelocs<LUi64, DADDiu, R0_64, GPR64Opnd>, ISA_MIPS3, GPR_64,
SYM_32;
def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>, ISA_MIPS3,
@@ -705,15 +705,15 @@ let AdditionalPredicates = [NotInMicroMips] in {
(LUi64 texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)),
- (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsHigher (i64 tblockaddress:$in)),
- (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsHigher (i64 tjumptable:$in)),
- (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsHigher (i64 tconstpool:$in)),
- (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsHigher (i64 texternalsym:$in)),
- (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))),
(DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
@@ -729,15 +729,15 @@ let AdditionalPredicates = [NotInMicroMips] in {
ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsHi (i64 tglobaladdr:$in)),
- (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsHi (i64 tblockaddress:$in)),
- (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsHi (i64 tjumptable:$in)),
- (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsHi (i64 tconstpool:$in)),
- (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsHi (i64 texternalsym:$in)),
- (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))),
(DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
@@ -753,18 +753,18 @@ let AdditionalPredicates = [NotInMicroMips] in {
ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsLo (i64 tglobaladdr:$in)),
- (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsLo (i64 tblockaddress:$in)),
- (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsLo (i64 tjumptable:$in)),
- (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsLo (i64 tconstpool:$in)),
- (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsLo (i64 tglobaltlsaddr:$in)),
- (DADDiu ZERO_64, tglobaltlsaddr:$in)>,
+ (DADDiu R0_64, tglobaltlsaddr:$in)>,
ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(MipsLo (i64 texternalsym:$in)),
- (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64;
+ (DADDiu R0_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))),
(DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
@@ -784,7 +784,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
}
def : MipsPat<(MipsGPRel tglobaladdr:$in),
- (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, ABI_N64;
+ (DADDiu R0_64, tglobaladdr:$in)>, ISA_MIPS3, ABI_N64;
// gp_rel relocs
def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)),
@@ -801,7 +801,7 @@ def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>, ISA_MIPS3, GPR_64;
defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
- ZERO_64>, ISA_MIPS3, GPR_64;
+ R0_64>, ISA_MIPS3, GPR_64;
def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
(BLEZ64 i64:$lhs, bb:$dst)>, ISA_MIPS3, GPR_64;
def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
@@ -809,7 +809,7 @@ def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
// setcc patterns
let AdditionalPredicates = [NotInMicroMips] in {
- defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>, ISA_MIPS3, GPR_64;
+ defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, R0_64>, ISA_MIPS3, GPR_64;
defm : SetlePats<GPR64, XORi, SLT64, SLTu64>, ISA_MIPS3, GPR_64;
defm : SetgtPats<GPR64, SLT64, SLTu64>, ISA_MIPS3, GPR_64;
defm : SetgePats<GPR64, XORi, SLT64, SLTu64>, ISA_MIPS3, GPR_64;
@@ -969,10 +969,10 @@ def : MipsPat<(i64 (sext_like (i32 (sra GPR32:$src, GPR32:$src2)))),
//===----------------------------------------------------------------------===//
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"move $dst, $src",
- (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
+ (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, R0_64), 1>,
GPR_64;
def : MipsInstAlias<"move $dst, $src",
- (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
+ (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, R0_64), 1>,
GPR_64;
def : MipsInstAlias<"dadd $rs, $rt, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
@@ -998,16 +998,16 @@ let AdditionalPredicates = [NotInMicroMips] in {
}
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"dneg $rt, $rs",
- (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
+ (DSUB GPR64Opnd:$rt, R0_64, GPR64Opnd:$rs), 1>,
ISA_MIPS3;
def : MipsInstAlias<"dneg $rt",
- (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
+ (DSUB GPR64Opnd:$rt, R0_64, GPR64Opnd:$rt), 1>,
ISA_MIPS3;
def : MipsInstAlias<"dnegu $rt, $rs",
- (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
+ (DSUBu GPR64Opnd:$rt, R0_64, GPR64Opnd:$rs), 1>,
ISA_MIPS3;
def : MipsInstAlias<"dnegu $rt",
- (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
+ (DSUBu GPR64Opnd:$rt, R0_64, GPR64Opnd:$rt), 1>,
ISA_MIPS3;
}
def : MipsInstAlias<"dsubi $rs, $rt, $imm",
@@ -1062,7 +1062,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"dext $rt, $rs, $pos, $size",
(DEXTU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos,
uimm5_plus1:$size), 0>, ISA_MIPS64R2;
- def : MipsInstAlias<"jalr.hb $rs", (JALR_HB64 RA_64, GPR64Opnd:$rs), 1>,
+ def : MipsInstAlias<"jalr.hb $rs", (JALR_HB64 R31_64, GPR64Opnd:$rs), 1>,
ISA_MIPS64;
// Two operand (implicit 0 selector) versions:
def : MipsInstAlias<"dmtc0 $rt, $rd",
diff --git a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
index 450d1ae71b75c..35c047e02bb78 100644
--- a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
@@ -94,14 +94,14 @@ class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>;
class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
GPR64Opnd> {
bit isCall = 1;
- list<Register> Defs = [RA];
+ list<Register> Defs = [R31];
}
class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
GPR64Opnd> {
bit isBarrier = 1;
bit isTerminator = 1;
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
}
class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9_exp>;
@@ -191,7 +191,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
//
//===----------------------------------------------------------------------===//
-def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
+def : MipsInstAlias<"jr $rs", (JALR64 R0_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
@@ -321,8 +321,8 @@ def : MipsPat<(i64 (sext (i32 (urem GPR32:$src, GPR32:$src2)))),
let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
NoIndirectJumpGuards] in {
- def TAILCALL64R6REG : TailCallRegR6<JALR64, ZERO_64, GPR64Opnd>, ISA_MIPS64R6;
- def PseudoIndirectBranch64R6 : PseudoIndirectBranchBaseR6<JALR64, ZERO_64,
+ def TAILCALL64R6REG : TailCallRegR6<JALR64, R0_64, GPR64Opnd>, ISA_MIPS64R6;
+ def PseudoIndirectBranch64R6 : PseudoIndirectBranchBaseR6<JALR64, R0_64,
GPR64Opnd>,
ISA_MIPS64R6;
}
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index d2d7e491223c3..03234f3d06b50 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -130,7 +130,7 @@ void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
MCOperand MCOp;
if (HasLinkReg) {
- unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
+ unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::R0_64 : Mips::R0;
TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
}
@@ -904,28 +904,29 @@ void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
bool LE, bool ToFP) {
using namespace Mips16HardFloatInfo;
+ const MipsABIInfo &ABI = Subtarget->getABI();
unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
switch (PV) {
case FSig:
- EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
+ EmitInstrRegReg(STI, MovOpc, ABI.getArgReg(0), Mips::F12);
break;
case FFSig:
- EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12, Mips::F14, LE);
break;
case FDSig:
- EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
- EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
+ EmitInstrRegReg(STI, MovOpc, ABI.getArgReg(0), Mips::F12);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(2), ABI.getArgReg(3), Mips::F14, Mips::F15, LE);
break;
case DSig:
- EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12, Mips::F13, LE);
break;
case DDSig:
- EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
- EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12, Mips::F13, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(2), ABI.getArgReg(3), Mips::F14, Mips::F15, LE);
break;
case DFSig:
- EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
- EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12, Mips::F13, LE);
+ EmitInstrRegReg(STI, MovOpc, ABI.getArgReg(2), Mips::F14);
break;
case NoSig:
return;
@@ -937,20 +938,21 @@ void MipsAsmPrinter::EmitSwapFPIntRetval(
bool LE) {
using namespace Mips16HardFloatInfo;
+ const MipsABIInfo &ABI = Subtarget->getABI();
unsigned MovOpc = Mips::MFC1;
switch (RV) {
case FRet:
- EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
+ EmitInstrRegReg(STI, MovOpc, ABI.getReturnReg(0), Mips::F0);
break;
case DRet:
- EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getReturnReg(0), ABI.getReturnReg(1), Mips::F0, Mips::F1, LE);
break;
case CFRet:
- EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getReturnReg(0), ABI.getReturnReg(1), Mips::F0, Mips::F1, LE);
break;
case CDRet:
- EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
- EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getReturnReg(0), ABI.getReturnReg(1), Mips::F0, Mips::F1, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F2, Mips::F3, LE);
break;
case NoFPRet:
break;
@@ -1077,7 +1079,8 @@ void MipsAsmPrinter::EmitFPCallStub(
//
// Mov $18, $31
- EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
+ EmitInstrRegRegReg(*STI, Mips::OR, Subtarget->getABI().getSavedReg(2),
+ Mips::R31, Mips::R0);
EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
@@ -1092,7 +1095,7 @@ void MipsAsmPrinter::EmitFPCallStub(
// if (Signature->RetSig == NoFPRet)
// llvm_unreachable("should not be any stubs here with no return value");
// else
- EmitInstrReg(*STI, Mips::JR, Mips::S2);
+ EmitInstrReg(*STI, Mips::JR, Subtarget->getABI().getSavedReg(2));
MCSymbol *Tmp = OutContext.createTempSymbol();
OutStreamer->emitLabel(Tmp);
@@ -1194,14 +1197,14 @@ void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
// start of function
const MCExpr *TargetExpr = MCSymbolRefExpr::create(Target, OutContext);
EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)
- .addReg(Mips::ZERO)
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
+ .addReg(Mips::R0)
.addExpr(TargetExpr));
for (int8_t I = 0; I < NoopsInSledCount; I++)
EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)
- .addReg(Mips::ZERO)
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
+ .addReg(Mips::R0)
.addImm(0));
OutStreamer->emitLabel(Target);
@@ -1209,8 +1212,8 @@ void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
if (!Subtarget->isGP64bit()) {
EmitToStreamer(*OutStreamer,
MCInstBuilder(Mips::ADDiu)
- .addReg(Mips::T9)
- .addReg(Mips::T9)
+ .addReg(Mips::R25)
+ .addReg(Mips::R25)
.addImm(0x34));
}
diff --git a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
index 9d84ac0159fe1..bd8772e7cf12a 100644
--- a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
+++ b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
@@ -393,7 +393,7 @@ bool MipsBranchExpansion::buildProperJumpMI(MachineBasicBlock *MBB,
if (JumpOp == Mips::JIC && STI->inMicroMipsMode())
JumpOp = Mips::JIC_MMR6;
- unsigned ATReg = ABI.IsN64() ? Mips::AT_64 : Mips::AT;
+ unsigned ATReg = ABI.IsN64() ? Mips::R1_64 : Mips::R1;
MachineInstrBuilder Instr =
BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg);
if (AddImm)
@@ -464,12 +464,12 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
Pos = LongBrMBB->begin();
- BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
- .addReg(Mips::SP)
+ BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::R29)
+ .addReg(Mips::R29)
.addImm(-8);
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW))
- .addReg(Mips::RA)
- .addReg(Mips::SP)
+ .addReg(Mips::R31)
+ .addReg(Mips::R29)
.addImm(0);
// LUi and ADDiu instructions create 32-bit offset of the target basic
@@ -488,15 +488,15 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
// %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
// operands to lowered instructions.
- BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
+ BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::R1)
.addMBB(TgtMBB, MipsII::MO_ABS_HI)
.addMBB(BalTgtMBB);
MachineInstrBuilder BalInstr =
BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
MachineInstrBuilder ADDiuInstr =
- BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
- .addReg(Mips::AT)
+ BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::R1)
+ .addReg(Mips::R1)
.addMBB(TgtMBB, MipsII::MO_ABS_LO)
.addMBB(BalTgtMBB);
if (STI->hasMips32r6()) {
@@ -510,24 +510,24 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
Pos = BalTgtMBB->begin();
- BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
- .addReg(Mips::RA)
- .addReg(Mips::AT);
- BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
- .addReg(Mips::SP)
+ BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::R1)
+ .addReg(Mips::R31)
+ .addReg(Mips::R1);
+ BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::R31)
+ .addReg(Mips::R29)
.addImm(0);
// For MIPS32R6, we can skip using a delay slot branch.
bool hasDelaySlot = buildProperJumpMI(BalTgtMBB, Pos, DL);
if (!hasDelaySlot) {
- BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP)
- .addReg(Mips::SP)
+ BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::R29)
+ .addReg(Mips::R29)
.addImm(8);
}
if (hasDelaySlot) {
- BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
- .addReg(Mips::SP)
+ BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::R29)
+ .addReg(Mips::R29)
.addImm(8);
BalTgtMBB->rbegin()->bundleWithPred();
}
@@ -579,27 +579,27 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
Pos = LongBrMBB->begin();
- BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
- .addReg(Mips::SP_64)
+ BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::R29_64)
+ .addReg(Mips::R29_64)
.addImm(-16);
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD))
- .addReg(Mips::RA_64)
- .addReg(Mips::SP_64)
+ .addReg(Mips::R31_64)
+ .addReg(Mips::R29_64)
.addImm(0);
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
- Mips::AT_64)
- .addReg(Mips::ZERO_64)
+ Mips::R1_64)
+ .addReg(Mips::R0_64)
.addMBB(TgtMBB, MipsII::MO_ABS_HI)
.addMBB(BalTgtMBB);
- BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
- .addReg(Mips::AT_64)
+ BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::R1_64)
+ .addReg(Mips::R1_64)
.addImm(16);
MachineInstrBuilder BalInstr =
BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
MachineInstrBuilder DADDiuInstr =
- BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
- .addReg(Mips::AT_64)
+ BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::R1_64)
+ .addReg(Mips::R1_64)
.addMBB(TgtMBB, MipsII::MO_ABS_LO)
.addMBB(BalTgtMBB);
if (STI->hasMips32r6()) {
@@ -613,23 +613,23 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
Pos = BalTgtMBB->begin();
- BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
- .addReg(Mips::RA_64)
- .addReg(Mips::AT_64);
- BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
- .addReg(Mips::SP_64)
+ BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::R1_64)
+ .addReg(Mips::R31_64)
+ .addReg(Mips::R1_64);
+ BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::R31_64)
+ .addReg(Mips::R29_64)
.addImm(0);
bool hasDelaySlot = buildProperJumpMI(BalTgtMBB, Pos, DL);
// If there is no delay slot, Insert stack adjustment before
if (!hasDelaySlot) {
BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::DADDiu),
- Mips::SP_64)
- .addReg(Mips::SP_64)
+ Mips::R29_64)
+ .addReg(Mips::R29_64)
.addImm(16);
} else {
- BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
- .addReg(Mips::SP_64)
+ BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::R29_64)
+ .addReg(Mips::R29_64)
.addImm(16);
BalTgtMBB->rbegin()->bundleWithPred();
}
@@ -676,33 +676,33 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
// do branch register.
if (ABI.IsN64()) {
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi2Op_64),
- Mips::AT_64)
+ Mips::R1_64)
.addMBB(TgtMBB, MipsII::MO_HIGHEST);
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
- Mips::AT_64)
- .addReg(Mips::AT_64)
+ Mips::R1_64)
+ .addReg(Mips::R1_64)
.addMBB(TgtMBB, MipsII::MO_HIGHER);
- BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
- .addReg(Mips::AT_64)
+ BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::R1_64)
+ .addReg(Mips::R1_64)
.addImm(16);
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
- Mips::AT_64)
- .addReg(Mips::AT_64)
+ Mips::R1_64)
+ .addReg(Mips::R1_64)
.addMBB(TgtMBB, MipsII::MO_ABS_HI);
- BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
- .addReg(Mips::AT_64)
+ BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::R1_64)
+ .addReg(Mips::R1_64)
.addImm(16);
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
- Mips::AT_64)
- .addReg(Mips::AT_64)
+ Mips::R1_64)
+ .addReg(Mips::R1_64)
.addMBB(TgtMBB, MipsII::MO_ABS_LO);
} else {
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi2Op),
- Mips::AT)
+ Mips::R1)
.addMBB(TgtMBB, MipsII::MO_ABS_HI);
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_ADDiu2Op),
- Mips::AT)
- .addReg(Mips::AT)
+ Mips::R1)
+ .addReg(Mips::R1)
.addMBB(TgtMBB, MipsII::MO_ABS_LO);
}
buildProperJumpMI(LongBrMBB, Pos, DL);
@@ -723,12 +723,12 @@ static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
MachineBasicBlock &MBB = F.front();
MachineBasicBlock::iterator I = MBB.begin();
DebugLoc DL = MBB.findDebugLoc(MBB.begin());
- BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
+ BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::R2)
.addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
- BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
- .addReg(Mips::V0)
+ BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::R2)
+ .addReg(Mips::R2)
.addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
- MBB.removeLiveIn(Mips::V0);
+ MBB.removeLiveIn(Mips::R2);
}
template <typename Pred, typename Safe>
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp
index 13c740ed1991d..1ff75d20856f1 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -182,7 +182,7 @@ Register MipsOutgoingValueHandler::getStackAddress(uint64_t Size,
LLT p0 = LLT::pointer(0, 32);
LLT s32 = LLT::scalar(32);
- auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP));
+ auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::R29));
auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
@@ -420,7 +420,7 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
MIB.setOperandDead(0); // implicit-def $ra
- MIB.addDef(Mips::SP, RegState::Implicit);
+ MIB.addDef(Mips::R29, RegState::Implicit);
if (IsCalleeGlobalPIC) {
Register CalleeReg =
MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32));
@@ -475,9 +475,9 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
if (IsCalleeGlobalPIC) {
MIRBuilder.buildCopy(
- Register(Mips::GP),
+ Register(Mips::R28),
MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel(MF));
- MIB.addUse(Mips::GP, RegState::Implicit);
+ MIB.addUse(Mips::R28, RegState::Implicit);
}
MIRBuilder.insertInstr(MIB);
if (MIB->getOpcode() == Mips::JALRPseudo) {
diff --git a/llvm/lib/Target/Mips/MipsCallingConv.td b/llvm/lib/Target/Mips/MipsCallingConv.td
index d30b4bc686f70..7348ed32ddce8 100644
--- a/llvm/lib/Target/Mips/MipsCallingConv.td
+++ b/llvm/lib/Target/Mips/MipsCallingConv.td
@@ -35,9 +35,10 @@ class CCIfSpecialCallingConv<string CC, CCAction A>
: CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == "
"MipsCCState::" # CC, A>;
-// For soft-float, f128 values are returned in A0_64 rather than V1_64.
+// For soft-float, f128 values are returned in R2_64 and R4_64 rather than
+// R2_64 and R3_64.
def RetCC_F128SoftFloat : CallingConv<[
- CCAssignToReg<[V0_N_64, A0_64]>
+ CCAssignToReg<[R2_64, R4_64]>
]>;
// For hard-float, f128 values are returned as a pair of f64's rather than a
@@ -85,10 +86,10 @@ def RetCC_MipsO32 : CallingConv<[
// Promote i1/i8/i16 return values to i32.
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
- // i32 are returned in registers V0, V1, A0, A1, unless the original return
+ // i32 are returned in registers R2, R3, R4, R5, unless the original return
// type was a vector of floats.
CCIfOrigArgWasNotVectorFloat<CCIfType<[i32],
- CCAssignToReg<[V0, V1, A0, A1]>>>,
+ CCAssignToReg<[R2, R3, R4, R5]>>>,
// f32 are returned in registers F0, F2
CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
@@ -112,8 +113,8 @@ def CC_MipsO32_FP : CallingConv<[
//===----------------------------------------------------------------------===//
def CC_MipsN_SoftFloat : CallingConv<[
- CCAssignToRegWithShadow<[A0, A1, A2, A3,
- A4_N, A5_N, A6_N, A7_N],
+ CCAssignToRegWithShadow<[R4, R5, R6, R7,
+ R8, R9, R10, R11],
[D12_64, D13_64, D14_64, D15_64,
D16_64, D17_64, D18_64, D19_64]>,
CCAssignToStack<4, 8>
@@ -133,25 +134,25 @@ def CC_MipsN : CallingConv<[
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
// Integer arguments are passed in integer registers.
- CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
- A4_N_64, A5_N_64, A6_N_64,
- A7_N_64],
+ CCIfType<[i64], CCAssignToRegWithShadow<[R4_64, R5_64, R6_64, R7_64,
+ R8_64, R9_64, R10_64,
+ R11_64],
[D12_64, D13_64, D14_64, D15_64,
D16_64, D17_64, D18_64, D19_64]>>,
// f32 arguments are passed in single precision FP registers.
CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
F16, F17, F18, F19],
- [A0_64, A1_64, A2_64, A3_64,
- A4_N_64, A5_N_64, A6_N_64,
- A7_N_64]>>,
+ [R4_64, R5_64, R6_64, R7_64,
+ R8_64, R9_64, R10_64,
+ R11_64]>>,
// f64 arguments are passed in double precision FP registers.
CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
D16_64, D17_64, D18_64, D19_64],
- [A0_64, A1_64, A2_64, A3_64,
- A4_N_64, A5_N_64, A6_N_64,
- A7_N_64]>>,
+ [R4_64, R5_64, R6_64, R7_64,
+ R8_64, R9_64, R10_64,
+ R11_64]>>,
// All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
CCIfType<[f32], CCAssignToStack<4, 8>>,
@@ -168,10 +169,10 @@ def CC_MipsN_VarArg : CallingConv<[
// All integers are promoted to 64-bit.
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
- CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, A4_N, A5_N, A6_N, A7_N]>>,
+ CCIfType<[f32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>,
- CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
- A4_N_64, A5_N_64, A6_N_64, A7_N_64]>>,
+ CCIfType<[i64, f64], CCAssignToReg<[R4_64, R5_64, R6_64, R7_64,
+ R8_64, R9_64, R10_64, R11_64]>>,
// All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
CCIfType<[f32], CCAssignToStack<4, 8>>,
@@ -201,8 +202,8 @@ def RetCC_MipsN : CallingConv<[
CCIfType<[i8, i16, i32, i64],
CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
- // i64 are returned in registers V0_N_64, V1_N_64
- CCIfType<[i64], CCAssignToReg<[V0_N_64, V1_N_64]>>,
+ // i64 are returned in registers R2_64, R3_64
+ CCIfType<[i64], CCAssignToReg<[R2_64, R3_64]>>,
// f32 are returned in registers F0, F2
CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
@@ -237,9 +238,9 @@ def CC_MipsO32_FastCC : CallingConv<[
def CC_MipsN_FastCC : CallingConv<[
// Integer arguments are passed in integer registers.
- CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, A4_N_64,
- A5_N_64, A6_N_64, A7_N_64, T0_N_64, T1_N_64,
- T2_N_64, T3_N_64, T8_64, V1_N_64]>>,
+ CCIfType<[i64], CCAssignToReg<[R4_64, R5_64, R6_64, R7_64, R8_64,
+ R9_64, R10_64, R11_64, R12_64, R13_64,
+ R14_64, R15_64, R24_64, R3_64]>>,
// f64 arguments are passed in double-precision floating pointer registers.
CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
@@ -260,9 +261,10 @@ def CC_Mips_FastCC : CallingConv<[
CCIfType<[i8, i16], CCPromoteToType<i32>>,
// Integer arguments are passed in integer registers. All scratch registers,
- // except for AT, V0 and T9, are available to be used as argument registers.
+ // except for R1, R2 and R25, are available to be used as argument registers.
CCIfType<[i32],
- CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>,
+ CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R24,
+ R3]>>,
// f32 arguments are passed in single-precision floating pointer registers.
CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
@@ -299,7 +301,7 @@ def CC_Mips16RetHelper : CallingConv<[
CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
// Integer arguments are passed in integer registers.
- CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
+ CCIfType<[i32], CCAssignToReg<[R2, R3, R4, R5]>>
]>;
def CC_Mips_FixedArg : CallingConv<[
@@ -347,77 +349,77 @@ def CC_Mips : CallingConv<[
// Callee-saved register lists.
//===----------------------------------------------------------------------===//
-def CSR_O32_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 20), RA, FP,
+def CSR_O32_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 20), R31, R30,
(sequence "R%u", 23, 16))>;
-def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
+def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), R31, R30,
(sequence "R%u", 23, 16))> {
let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
}
-def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
+def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), R31, R30,
(sequence "R%u", 23, 16))>;
def CSR_O32_FP64 :
- CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
+ CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), R31, R30,
(sequence "R%u", 23, 16))>;
def CSR_N32 : CalleeSavedRegs<(add(decimate(sequence "D%u_64", 30, 20), 2),
- RA_64, FP_64, GP_64, (sequence "R%u_64", 23, 16))>;
+ R31_64, R30_64, R28_64, (sequence "R%u_64", 23, 16))>;
def CSR_N32_NoGP : CalleeSavedRegs<(add(decimate(sequence "D%u_64", 30, 20), 2),
- RA_64, FP_64, (sequence "R%u_64", 23, 16))>;
+ R31_64, R30_64, (sequence "R%u_64", 23, 16))>;
def CSR_N32_SingleFloat
- : CalleeSavedRegs<(add(decimate(sequence "F%u", 30, 20), 2), RA_64, FP_64,
- GP_64, (sequence "R%u_64", 23, 16))>;
+ : CalleeSavedRegs<(add(decimate(sequence "F%u", 30, 20), 2), R31_64, R30_64,
+ R28_64, (sequence "R%u_64", 23, 16))>;
def CSR_N32_SingleFloat_NoGP
- : CalleeSavedRegs<(add(decimate(sequence "F%u", 30, 20), 2), RA_64, FP_64,
+ : CalleeSavedRegs<(add(decimate(sequence "F%u", 30, 20), 2), R31_64, R30_64,
(sequence "R%u_64", 23, 16))>;
-def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
- GP_64, (sequence "R%u_64", 23, 16))>;
+def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), R31_64, R30_64,
+ R28_64, (sequence "R%u_64", 23, 16))>;
-def CSR_N64_NoGP : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
+def CSR_N64_NoGP : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), R31_64, R30_64,
(sequence "R%u_64", 23, 16))>;
-def CSR_N64_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 24), RA_64,
- FP_64, GP_64, (sequence "R%u_64", 23, 16))>;
+def CSR_N64_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 24), R31_64,
+ R30_64, R28_64, (sequence "R%u_64", 23, 16))>;
-def CSR_N64_SingleFloat_NoGP : CalleeSavedRegs<(add(sequence "F%u", 31, 24), RA_64,
- FP_64, (sequence "R%u_64", 23, 16))>;
+def CSR_N64_SingleFloat_NoGP : CalleeSavedRegs<(add(sequence "F%u", 31, 24), R31_64,
+ R30_64, (sequence "R%u_64", 23, 16))>;
def CSR_Mips16RetHelper :
- CalleeSavedRegs<(add V0, V1, FP,
+ CalleeSavedRegs<(add R2, R3, R30,
(sequence "R%u", 7, 4), (sequence "R%u", 23, 16),
(sequence "D%u", 15, 10))>;
def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "R%u", 7, 4),
(sequence "R%u", 23, 16),
(sequence "R%u", 3, 2),
- T9, T8,
+ R25, R24,
(sequence "R%u", 15, 8),
- RA, FP, GP, AT)>;
+ R31, R30, R28, R1)>;
def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "R%u", 7, 4),
(sequence "R%u", 23, 16),
(sequence "R%u", 3, 2),
- T9, T8,
+ R25, R24,
(sequence "R%u", 15, 8),
- RA, FP, GP, AT, LO0, HI0)>;
+ R31, R30, R28, R1, LO0, HI0)>;
def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "R%u_64", 7, 4),
(sequence "R%u_64", 3, 2),
(sequence "R%u_64", 23, 16),
- T9_64, T8_64,
+ R25_64, R24_64,
(sequence "R%u_64", 15, 8),
- RA_64, FP_64, GP_64, AT_64)>;
+ R31_64, R30_64, R28_64, R1_64)>;
def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "R%u_64", 7, 4),
(sequence "R%u_64", 23, 16),
- T9_64, T8_64,
+ R25_64, R24_64,
(sequence "R%u_64", 15, 8),
(sequence "R%u_64", 3, 2),
- RA_64, FP_64, GP_64, AT_64,
+ R31_64, R30_64, R28_64, R1_64,
LO0_64, HI0_64)>;
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
index 9d7f12fbe01ec..cbb3f2cfe51b6 100644
--- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
@@ -1363,15 +1363,15 @@ class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
CondCode CC> :
DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
- (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
- (ValTy ZERO)))>;
+ (ValTy (COPY_TO_REGCLASS (ADDiu R0, -1), DSPR)),
+ (ValTy R0)))>;
class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
CondCode CC> :
DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
- (ValTy ZERO),
- (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
+ (ValTy R0),
+ (ValTy (COPY_TO_REGCLASS (ADDiu R0, -1), DSPR))))>;
class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
CondCode CC> :
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 20afc2ea9ce89..af115e60635f2 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -492,13 +492,13 @@ void RegDefsUses::init(const MachineInstr &MI) {
// If MI is a call, add RA to Defs to prevent users of RA from going into
// delay slot.
if (MI.isCall())
- Defs.set(Mips::RA);
+ Defs.set(Mips::R31);
// Add all implicit register operands of branch instructions except
// register AT.
if (MI.isBranch()) {
update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
- Defs.reset(Mips::AT);
+ Defs.reset(Mips::R1);
}
}
@@ -508,17 +508,17 @@ void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
// Add RA/RA_64 to Defs to prevent users of RA/RA_64 from going into
// the delay slot. The reason is that RA/RA_64 must not be changed
// in the delay slot so that the callee can return to the caller.
- if (MI.definesRegister(Mips::RA, /*TRI=*/nullptr) ||
- MI.definesRegister(Mips::RA_64, /*TRI=*/nullptr)) {
- Defs.set(Mips::RA);
- Defs.set(Mips::RA_64);
+ if (MI.definesRegister(Mips::R31, /*TRI=*/nullptr) ||
+ MI.definesRegister(Mips::R31_64, /*TRI=*/nullptr)) {
+ Defs.set(Mips::R31);
+ Defs.set(Mips::R31_64);
}
// If MI is a call, add all caller-saved registers to Defs.
BitVector CallerSavedRegs(TRI.getNumRegs(), true);
- CallerSavedRegs.reset(Mips::ZERO);
- CallerSavedRegs.reset(Mips::ZERO_64);
+ CallerSavedRegs.reset(Mips::R0);
+ CallerSavedRegs.reset(Mips::R0_64);
for (const MCPhysReg *R = TRI.getCalleeSavedRegs(MI.getParent()->getParent());
*R; ++R)
@@ -535,8 +535,8 @@ void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) {
for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)
AllocSet.set(*AI);
- AllocSet.set(Mips::ZERO);
- AllocSet.set(Mips::ZERO_64);
+ AllocSet.set(Mips::R0);
+ AllocSet.set(Mips::R0_64);
Defs |= AllocSet.flip();
}
diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
index b39eb9863b042..08b11fef8fa1e 100644
--- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
+++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
@@ -80,7 +80,7 @@ bool MipsExpandPseudo::expandAtomicCmpSwapSubword(
DebugLoc DL = I->getDebugLoc();
unsigned LL, SC;
- unsigned ZERO = Mips::ZERO;
+ unsigned ZERO = Mips::R0;
unsigned BNE = Mips::BNE;
unsigned BEQ = Mips::BEQ;
unsigned SEOp =
@@ -228,12 +228,12 @@ bool MipsExpandPseudo::expandAtomicCmpSwap(MachineBasicBlock &BB,
BEQ = Mips::BEQ;
}
- ZERO = Mips::ZERO;
+ ZERO = Mips::R0;
MOVE = Mips::OR;
} else {
LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
- ZERO = Mips::ZERO_64;
+ ZERO = Mips::R0_64;
BNE = Mips::BNE64;
BEQ = Mips::BEQ64;
MOVE = Mips::OR64;
@@ -480,7 +480,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
.addReg(OldVal)
.addReg(Incr);
BuildMI(loopMBB, DL, TII->get(Mips::NOR), BinOpRes)
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
.addReg(BinOpRes);
BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
.addReg(BinOpRes)
@@ -517,7 +517,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
.addImm(ShiftImm);
}
BuildMI(loopMBB, DL, TII->get(Mips::OR), Dest)
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
.addReg(StoreVal);
DestOK = true;
BuildMI(loopMBB, DL, TII->get(Mips::SLLV), StoreVal)
@@ -553,7 +553,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
// movz BinOpRes, Incr, Scratch4, BinOpRes
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
.addReg(StoreVal)
- .addReg(Mips::ZERO);
+ .addReg(Mips::R0);
BuildMI(loopMBB, DL, TII->get(MOVIncr), BinOpRes)
.addReg(Incr)
.addReg(Scratch4)
@@ -583,21 +583,21 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
if (IsMin) {
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
.addReg(StoreVal)
- .addReg(Mips::ZERO);
+ .addReg(Mips::R0);
BuildMI(loop1MBB, DL, TII->get(OR), BinOpRes)
.addReg(Incr)
- .addReg(Mips::ZERO);
+ .addReg(Mips::R0);
} else {
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
.addReg(Incr)
- .addReg(Mips::ZERO);
+ .addReg(Mips::R0);
BuildMI(loop1MBB, DL, TII->get(OR), BinOpRes)
.addReg(StoreVal)
- .addReg(Mips::ZERO);
+ .addReg(Mips::R0);
}
BuildMI(loopMBB, DL, TII->get(BEQ))
.addReg(Scratch4)
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
.addMBB(loop1MBB);
BuildMI(loopMBB, DL, TII->get(Mips::J)).addMBB(loop2MBB);
}
@@ -645,7 +645,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
.addImm(0);
BuildMI(loop2MBB, DL, TII->get(BEQ))
.addReg(StoreVal)
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
.addMBB(loopMBB);
} else {
BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
@@ -660,7 +660,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
.addImm(0);
BuildMI(loopMBB, DL, TII->get(BEQ))
.addReg(StoreVal)
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
.addMBB(loopMBB);
}
@@ -745,11 +745,11 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
SELEQZ = Mips::SELEQZ;
}
- ZERO = Mips::ZERO;
+ ZERO = Mips::R0;
} else {
LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
- ZERO = Mips::ZERO_64;
+ ZERO = Mips::R0_64;
BEQ = Mips::BEQ64;
SLT = Mips::SLT64;
SLTu = Mips::SLTu64;
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index e223d453f771b..2f37c8bf656fa 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -363,10 +363,10 @@ unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
if (isInt<16>(Imm)) {
unsigned Opc = Mips::ADDiu;
- emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
+ emitInst(Opc, ResultReg).addReg(Mips::R0).addImm(Imm);
return ResultReg;
} else if (isUInt<16>(Imm)) {
- emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
+ emitInst(Mips::ORi, ResultReg).addReg(Mips::R0).addImm(Imm);
return ResultReg;
}
unsigned Lo = Imm & 0xFFFF;
@@ -652,7 +652,7 @@ bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
case CmpInst::ICMP_NE: {
Register TempReg = createResultReg(&Mips::GPR32RegClass);
emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
- emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
+ emitInst(Mips::SLTu, ResultReg).addReg(Mips::R0).addReg(TempReg);
break;
}
case CmpInst::ICMP_UGT:
@@ -734,8 +734,8 @@ bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
}
Register RegWithZero = createResultReg(&Mips::GPR32RegClass);
Register RegWithOne = createResultReg(&Mips::GPR32RegClass);
- emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
- emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
+ emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::R0).addImm(0);
+ emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::R0).addImm(1);
emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
.addReg(RightReg);
emitInst(CondMovOpc, ResultReg)
@@ -1269,7 +1269,7 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
Address Addr;
Addr.setKind(Address::RegBase);
- Addr.setReg(Mips::SP);
+ Addr.setReg(Mips::R29);
Addr.setOffset(VA.getLocMemOffset() + BEAlign);
Align Alignment = DL.getABITypeAlign(ArgVal->getType());
@@ -1566,7 +1566,7 @@ bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
emitInst(TargetOpcode::COPY, getABI().getTempReg(9, false))
.addReg(DestAddress);
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(Mips::JALR), Mips::RA)
+ TII.get(Mips::JALR), Mips::R31)
.addReg(getABI().getTempReg(9, false));
// Add implicit physical register uses to the call.
@@ -1953,7 +1953,7 @@ bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
if (!NoZeroDivCheck && (!isa<ConstantInt>(I->getOperand(1)) ||
dyn_cast<ConstantInt>(I->getOperand(1))->isZero())) {
- emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
+ emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::R0).addImm(7);
}
Register ResultReg = createResultReg(&Mips::GPR32RegClass);
diff --git a/llvm/lib/Target/Mips/MipsFrameLowering.cpp b/llvm/lib/Target/Mips/MipsFrameLowering.cpp
index d21d267b55a6d..ddd38e308ab9c 100644
--- a/llvm/lib/Target/Mips/MipsFrameLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsFrameLowering.cpp
@@ -129,7 +129,7 @@ uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const {
MachineBasicBlock::iterator MipsFrameLowering::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
- unsigned SP = STI.getABI().IsN64() ? Mips::SP_64 : Mips::SP;
+ unsigned SP = STI.getABI().IsN64() ? Mips::R29_64 : Mips::R29;
if (!hasReservedCallFrame(MF)) {
int64_t Amount = I->getOperand(0).getImm();
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 4e90d78048199..c99b89c027d55 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -248,7 +248,7 @@ void MipsDAGToDAGISel::PreprocessISelDAG() {
const auto *BaseReg = dyn_cast<RegisterSDNode>(Base);
if (!BaseReg ||
- (BaseReg->getReg() != Mips::GP && BaseReg->getReg() != Mips::GP_64) ||
+ (BaseReg->getReg() != Mips::R28 && BaseReg->getReg() != Mips::R28_64) ||
Sel.getOpcode() != ISD::SELECT)
continue;
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index d8fc88cd90566..30319a44d2728 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -443,7 +443,7 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8)
: Align(4));
- setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
+ setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::R29_64 : Mips::R29);
MaxStoresPerMemcpy = 16;
@@ -1328,7 +1328,7 @@ insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock &MBB,
// slot.
BuildMI(&MBB, DL, TII.get(Mips::BNE))
.addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
.addMBB(SinkMBB);
// BreakMBB: break 7
@@ -1349,7 +1349,7 @@ insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock &MBB,
TII.get(TrapKind == DivByZeroTrapKind::TeqMM ? Mips::TEQ_MM
: Mips::TEQ))
.addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
.addImm(7);
// Use the 32-bit sub-register if this is a 64-bit division.
@@ -1882,10 +1882,10 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
}
BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
- .addReg(Mips::ZERO).addImm(MaskImm);
+ .addReg(Mips::R0).addImm(MaskImm);
BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
.addReg(MaskUpper).addReg(ShiftAmt);
- BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
+ BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::R0).addReg(Mask);
BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
@@ -2070,10 +2070,10 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
}
BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
- .addReg(Mips::ZERO).addImm(MaskImm);
+ .addReg(Mips::R0).addImm(MaskImm);
BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
.addReg(MaskUpper).addReg(ShiftAmt);
- BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
+ BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::R0).addReg(Mask);
BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
.addReg(CmpVal).addImm(MaskImm);
BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
@@ -2131,7 +2131,7 @@ SDValue MipsTargetLowering::lowerConstantFP(SDValue Op,
// TODO: DAG.getConstant(0) should be optimized to avoid generate an extra
// instr `addiu $x, $zero, 0`.
SDValue Low =
- DAG.getCopyFromReg(DAG.getEntryNode(), DL, Mips::ZERO, MVT::i32);
+ DAG.getCopyFromReg(DAG.getEntryNode(), DL, Mips::R0, MVT::i32);
SDValue Hi = DAG.getConstant(INTVal.extractBits(32, 32), DL, MVT::i32);
return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Low, Hi);
}
@@ -2625,7 +2625,7 @@ SDValue MipsTargetLowering::lowerFABS32(SDValue Op, SelectionDAG &DAG,
// Clear MSB.
if (HasExtractInsert)
Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
- DAG.getRegister(Mips::ZERO, MVT::i32),
+ DAG.getRegister(Mips::R0, MVT::i32),
DAG.getConstant(31, DL, MVT::i32), Const1, X);
else {
// TODO: Provide DAG patterns which transform (and x, cst)
@@ -2661,7 +2661,7 @@ SDValue MipsTargetLowering::lowerFABS64(SDValue Op, SelectionDAG &DAG,
// Clear MSB.
if (HasExtractInsert)
Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
- DAG.getRegister(Mips::ZERO_64, MVT::i64),
+ DAG.getRegister(Mips::R0_64, MVT::i64),
DAG.getConstant(63, DL, MVT::i32), Const1, X);
else {
SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
@@ -2706,7 +2706,7 @@ lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc DL(Op);
SDValue FrameAddr = DAG.getCopyFromReg(
- DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
+ DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::R30_64 : Mips::R30, VT);
return FrameAddr;
}
@@ -2722,7 +2722,7 @@ SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
MVT VT = Op.getSimpleValueType();
- unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
+ unsigned RA = ABI.IsN64() ? Mips::R31_64 : Mips::R31;
MFI.setReturnAddressIsTaken(true);
// Return RA, which contains the return address. Mark it an implicit live-in.
@@ -3150,10 +3150,10 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
// shadow the register lost to alignment requirements.
if (ArgFlags.isSplit()) {
Reg = State.AllocateReg(FloatVectorIntRegs);
- if (Reg == Mips::A2)
- State.AllocateReg(Mips::A1);
+ if (Reg == IntRegs[2])
+ State.AllocateReg(IntRegs[1]);
else if (Reg == 0)
- State.AllocateReg(Mips::A3);
+ State.AllocateReg(IntRegs[3]);
} else {
// If we're an intermediate component of the split, we can just attempt to
// allocate a register directly.
@@ -3164,14 +3164,14 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
Reg = State.AllocateReg(IntRegs);
// If this is the first part of an i64 arg,
// the allocated register must be either A0 or A2.
- if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
+ if (isI64 && (Reg == IntRegs[1] || Reg == IntRegs[3]))
Reg = State.AllocateReg(IntRegs);
LocVT = MVT::i32;
} else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
// Allocate int register and shadow next int register. If first
- // available register is Mips::A1 or Mips::A3, shadow it too.
+ // available register is $a1 or $a3, shadow it too.
Reg = State.AllocateReg(IntRegs);
- if (Reg == Mips::A1 || Reg == Mips::A3)
+ if (Reg == IntRegs[1] || Reg == IntRegs[3])
Reg = State.AllocateReg(IntRegs);
if (Reg) {
@@ -3195,7 +3195,7 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
Reg = State.AllocateReg(F64Regs);
// Shadow int registers
MCRegister Reg2 = State.AllocateReg(IntRegs);
- if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
+ if (Reg2 == IntRegs[1] || Reg2 == IntRegs[3])
State.AllocateReg(IntRegs);
State.AllocateReg(IntRegs);
}
@@ -3284,7 +3284,7 @@ void MipsTargetLowering::getOpndList(
// used for the function (that is, Mips linker doesn't generate lazy binding
// stub for a function whose address is taken in the program).
if (IsPICCall && !LocalLinkage && IsCallReloc) {
- unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
+ unsigned GPReg = ABI.IsN64() ? Mips::R28_64 : Mips::R28;
EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
}
@@ -3507,7 +3507,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Chain = DAG.getCALLSEQ_START(Chain, StackSize, 0, DL);
SDValue StackPtr =
- DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
+ DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::R29_64 : Mips::R29,
getPointerTy(DAG.getDataLayout()));
std::deque<std::pair<unsigned, SDValue>> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
@@ -4902,7 +4902,7 @@ MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
// bne rs, $0, sinkMBB
BuildMI(BB, DL, TII->get(Opc))
.addReg(MI.getOperand(1).getReg())
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
.addMBB(sinkMBB);
}
@@ -4973,7 +4973,7 @@ MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
// bne rs, $0, sinkMBB
BuildMI(BB, DL, TII->get(Mips::BNE))
.addReg(MI.getOperand(2).getReg())
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
.addMBB(sinkMBB);
// copy0MBB:
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index 84af86e6cc088..ba1651937631b 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -273,7 +273,7 @@ using TargetRegisterClass = MCRegisterClass;
SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
return DAG.getNode(
ISD::ADD, DL, Ty,
- DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
+ DAG.getRegister(IsN64 ? Mips::R28_64 : Mips::R28, Ty),
DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
}
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 1555e17572334..b40ffdd4a539e 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -266,7 +266,7 @@ class BC1F_FT<string opstr, DAGOperand opnd,
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
- let Defs = [AT];
+ let Defs = [R1];
let hasFCCRegOperand = 1;
}
@@ -277,7 +277,7 @@ class BC1XL_FT<string opstr, DAGOperand opnd> :
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
- let Defs = [AT];
+ let Defs = [R1];
let hasFCCRegOperand = 1;
}
@@ -1020,8 +1020,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
//===----------------------------------------------------------------------===//
// Floating Point Patterns
//===----------------------------------------------------------------------===//
-def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1;
-def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1;
+def : MipsPat<(f32 fpimm0), (MTC1 R0)>, ISA_MIPS1;
+def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 R0))>, ISA_MIPS1;
def : MipsPat<(f32 (any_sint_to_fp GPR32Opnd:$src)),
(PseudoCVT_S_W GPR32Opnd:$src)>;
@@ -1054,8 +1054,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
(CVT_D32_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_32;
}
-def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64;
-def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64,
+def : MipsPat<(f64 fpimm0), (DMTC1 R0_64)>, ISA_MIPS3, GPR_64, FGR_64;
+def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 R0_64))>, ISA_MIPS3, GPR_64,
FGR_64;
def : MipsPat<(f32 (MipsExtractElementF64_FPR AFGR64Opnd:$src, 0)),
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index 9ca4b283b16fa..40660862605b5 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -63,8 +63,8 @@ bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
MCInst MipsInstrInfo::getNop() const {
return MCInstBuilder(Mips::SLL)
- .addReg(Mips::ZERO)
- .addReg(Mips::ZERO)
+ .addReg(Mips::R0)
+ .addReg(Mips::R0)
.addImm(0);
}
@@ -86,8 +86,8 @@ MachineInstrBuilder MipsInstrInfo::insertNop(MachineBasicBlock &MBB,
Subtarget.hasMips32r6() ? Mips::SLL_MMR6 : Mips::SLL_MM;
const unsigned Opc =
Subtarget.inMicroMipsMode() ? MMOpc : (unsigned)Mips::SLL;
- return BuildMI(MBB, MI, DL, get(Opc), Mips::ZERO)
- .addReg(Mips::ZERO)
+ return BuildMI(MBB, MI, DL, get(Opc), Mips::R0)
+ .addReg(Mips::R0)
.addImm(0);
}
@@ -501,11 +501,11 @@ unsigned MipsInstrInfo::getEquivalentCompactForm(
// MIPSR6 forbids both operands being the zero register.
if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
(I->getOperand(0).isReg() &&
- (I->getOperand(0).getReg() == Mips::ZERO ||
- I->getOperand(0).getReg() == Mips::ZERO_64)) &&
+ (I->getOperand(0).getReg() == Mips::R0 ||
+ I->getOperand(0).getReg() == Mips::R0_64)) &&
(I->getOperand(1).isReg() &&
- (I->getOperand(1).getReg() == Mips::ZERO ||
- I->getOperand(1).getReg() == Mips::ZERO_64)))
+ (I->getOperand(1).getReg() == Mips::R0 ||
+ I->getOperand(1).getReg() == Mips::R0_64)))
return 0;
if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
@@ -713,8 +713,8 @@ bool MipsInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
case Mips::DADDiu:
return ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
(MI.getOperand(1).isReg() &&
- (MI.getOperand(1).getReg() == Mips::ZERO ||
- MI.getOperand(1).getReg() == Mips::ZERO_64)));
+ (MI.getOperand(1).getReg() == Mips::R0 ||
+ MI.getOperand(1).getReg() == Mips::R0_64)));
}
return MI.isAsCheapAsAMove();
}
@@ -768,14 +768,14 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
// Additional MIPSR6 does not permit the use of register $zero for compact
// branches.
// FIXME: Certain atomic sequences on mips64 generate 32bit references to
- // Mips::ZERO, which is incorrect. This test should be updated to use
+ // Mips::R0, which is incorrect. This test should be updated to use
// Subtarget.getABI().GetZeroReg() when those atomic sequences and others
// are fixed.
int ZeroOperandPosition = -1;
bool BranchWithZeroOperand = false;
if (I->isBranch() && !I->isPseudo()) {
auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
- ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, TRI, false);
+ ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::R0, TRI, false);
BranchWithZeroOperand = ZeroOperandPosition != -1;
}
@@ -1020,7 +1020,7 @@ MipsInstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
int64_t Offset = RegImm->Imm;
// When SrcReg is $zero, treat loaded value as immediate only.
// Ex. $a2 = ADDiu $zero, 10
- if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) {
+ if (SrcReg == Mips::R0 || SrcReg == Mips::R0_64) {
return ParamLoadedValue(MI.getOperand(2), Expr);
}
Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 73824b28340e4..f6c5d54dc6855 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1512,7 +1512,7 @@ class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
- let Defs = [AT];
+ let Defs = [R1];
bit isCTI = 1;
}
@@ -1522,7 +1522,7 @@ class CBranchLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
- let Defs = [AT];
+ let Defs = [R1];
bit isCTI = 1;
}
@@ -1535,7 +1535,7 @@ class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
- let Defs = [AT];
+ let Defs = [R1];
bit isCTI = 1;
}
@@ -1545,7 +1545,7 @@ class CBranchZeroLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
- let Defs = [AT];
+ let Defs = [R1];
bit isCTI = 1;
}
@@ -1572,20 +1572,20 @@ class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
let isBarrier=1;
let hasDelaySlot = 1;
let DecoderMethod = "DecodeJumpTarget";
- let Defs = [AT];
+ let Defs = [R1];
bit isCTI = 1;
}
// Unconditional branch
class UncondBranch<Instruction BEQInst, DAGOperand opnd> :
PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)]>,
- PseudoInstExpansion<(BEQInst ZERO, ZERO, opnd:$offset)> {
+ PseudoInstExpansion<(BEQInst R0, R0, opnd:$offset)> {
let isBranch = 1;
let isTerminator = 1;
let isBarrier = 1;
let hasDelaySlot = 1;
let AdditionalPredicates = [RelocPIC];
- let Defs = [AT];
+ let Defs = [R1];
bit isCTI = 1;
}
@@ -1603,7 +1603,7 @@ class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
}
// Jump and Link (Call)
-let isCall=1, hasDelaySlot=1, isCTI=1, Defs = [RA] in {
+let isCall=1, hasDelaySlot=1, isCTI=1, Defs = [R31] in {
class JumpLink<string opstr, DAGOperand opnd> :
InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
[(MipsJmpLink tglobaladdr:$target)], FrmJ, opstr> {
@@ -1633,7 +1633,7 @@ let isCall=1, hasDelaySlot=1, isCTI=1, Defs = [RA] in {
}
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
- hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in {
+ hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [R1] in {
class TailCall<Instruction JumpInst, DAGOperand Opnd> :
PseudoSE<(outs), (ins calltarget:$target), []>,
PseudoInstExpansion<(JumpInst Opnd:$target)>;
@@ -1647,12 +1647,12 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
class BAL_BR_Pseudo<Instruction RealInst, DAGOperand opnd> :
PseudoSE<(outs), (ins opnd:$offset), []>,
- PseudoInstExpansion<(RealInst ZERO, opnd:$offset)> {
+ PseudoInstExpansion<(RealInst R0, opnd:$offset)> {
let isBranch = 1;
let isTerminator = 1;
let isBarrier = 1;
let hasDelaySlot = 1;
- let Defs = [RA];
+ let Defs = [R31];
bit isCTI = 1;
}
@@ -1922,7 +1922,7 @@ let isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, isCTI=1 in {
def ERet : PseudoSE<(outs), (ins), [(MipsERet)]>;
}
-let Defs = [SP], Uses = [SP], hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
+let Defs = [R29], Uses = [R29], hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
[(callseq_start timm:$amt1, timm:$amt2)]>;
def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
@@ -2300,7 +2300,7 @@ def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>, ISA_MIPS1;
let AdditionalPredicates = [NotInMicroMips, NoIndirectJumpGuards] in {
def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM, ISA_MIPS1;
- def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>, ISA_MIPS1;
+ def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, R31>, ISA_MIPS1;
}
let AdditionalPredicates = [NotInMicroMips] in {
@@ -2373,7 +2373,7 @@ def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
-let Uses = [V0, V1], isTerminator = 1, isReturn = 1,
+let Uses = [R2, R3], isTerminator = 1, isReturn = 1,
isBarrier = 1, isCTI = 1, hasNoSchedulingInfo = 1 in {
def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
[(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
@@ -2418,7 +2418,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
/// No operation.
def NOP : PseudoSE<(outs), (ins), []>,
- PseudoInstExpansion<(SLL ZERO, ZERO, 0)>, ISA_MIPS1;
+ PseudoInstExpansion<(SLL R0, R0, 0)>, ISA_MIPS1;
// FrameIndexes are legalized when they are operands from load/store
// instructions. The same not happens for stack address copies, so an
@@ -2542,7 +2542,7 @@ def JR_HB : MMRel, JR_HB_DESC<GPR32Opnd>, JR_HB_ENC,
def JALR_HB : MMRel, JALR_HB_DESC<GPR32Opnd>, JALR_HB_ENC, ISA_MIPS32;
let AdditionalPredicates = [NotInMicroMips, UseIndirectJumpsHazard] in
- def JALRHBPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR_HB, RA>;
+ def JALRHBPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR_HB, R31>;
let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
@@ -2722,32 +2722,32 @@ multiclass OneOrTwoOperandMacroImmediateAlias<string Memnomic,
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"move $dst, $src",
- (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
+ (OR GPR32Opnd:$dst, GPR32Opnd:$src, R0), 1>,
GPR_32, ISA_MIPS1;
def : MipsInstAlias<"move $dst, $src",
- (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
+ (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, R0), 1>,
GPR_32, ISA_MIPS1;
- def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 1>,
+ def : MipsInstAlias<"bal $offset", (BGEZAL R0, brtarget:$offset), 1>,
ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>, ISA_MIPS1_NOT_32R6_64R6;
- def : MipsInstAlias<"j $rs", (JALR RA, GPR32Opnd:$rs), 0>, ISA_MIPS32R6;
+ def : MipsInstAlias<"j $rs", (JALR R31, GPR32Opnd:$rs), 0>, ISA_MIPS32R6;
- def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<"jalr $rs", (JALR R31, GPR32Opnd:$rs), 0>;
- def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>,
+ def : MipsInstAlias<"jalr.hb $rs", (JALR_HB R31, GPR32Opnd:$rs), 1>,
ISA_MIPS32;
def : MipsInstAlias<"neg $rt, $rs",
- (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS1;
+ (SUB GPR32Opnd:$rt, R0, GPR32Opnd:$rs), 1>, ISA_MIPS1;
def : MipsInstAlias<"neg $rt",
- (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1;
+ (SUB GPR32Opnd:$rt, R0, GPR32Opnd:$rt), 1>, ISA_MIPS1;
def : MipsInstAlias<"negu $rt, $rs",
- (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS1;
+ (SUBu GPR32Opnd:$rt, R0, GPR32Opnd:$rs), 1>, ISA_MIPS1;
def : MipsInstAlias<"negu $rt",
- (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1;
+ (SUBu GPR32Opnd:$rt, R0, GPR32Opnd:$rt), 1>, ISA_MIPS1;
def SGE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
@@ -2836,12 +2836,12 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<
"not $rt, $rs",
- (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MIPS1;
+ (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, R0), 0>, ISA_MIPS1;
def : MipsInstAlias<
"not $rt",
- (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>, ISA_MIPS1;
+ (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, R0), 0>, ISA_MIPS1;
- def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MIPS1;
+ def : MipsInstAlias<"nop", (SLL R0, R0, 0), 1>, ISA_MIPS1;
defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>,
ISA_MIPS1_NOT_32R6_64R6;
@@ -2879,28 +2879,28 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>,
ISA_MIPS1;
- def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>,
+ def : MipsInstAlias<"b $offset", (BEQ R0, R0, brtarget:$offset), 0>,
ISA_MIPS1;
def : MipsInstAlias<"bnez $rs,$offset",
- (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
+ (BNE GPR32Opnd:$rs, R0, brtarget:$offset), 0>,
ISA_MIPS1;
def : MipsInstAlias<"bnezl $rs, $offset",
- (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 1>,
+ (BNEL GPR32Opnd:$rs, R0, brtarget:$offset), 1>,
ISA_MIPS2;
def : MipsInstAlias<"beqz $rs,$offset",
- (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
+ (BEQ GPR32Opnd:$rs, R0, brtarget:$offset), 0>,
ISA_MIPS1;
def : MipsInstAlias<"beqzl $rs, $offset",
- (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 1>,
+ (BEQL GPR32Opnd:$rs, R0, brtarget:$offset), 1>,
ISA_MIPS2;
def : MipsInstAlias<"syscall", (SYSCALL 0), 1>, ISA_MIPS1;
def : MipsInstAlias<"break", (BREAK 0, 0), 1>, ISA_MIPS1;
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>, ISA_MIPS1;
- def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
- def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
+ def : MipsInstAlias<"ei", (EI R0), 1>, ISA_MIPS32R2;
+ def : MipsInstAlias<"di", (DI R0), 1>, ISA_MIPS32R2;
def : MipsInstAlias<"teq $rs, $rt",
(TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
@@ -3099,7 +3099,7 @@ def : MipsInstAlias<"divu $rd, $imm", (UDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,
ISA_MIPS1_NOT_32R6_64R6;
-def : MipsInstAlias<"nal", (BLTZAL ZERO, 0), 1>, ISA_MIPS1_NOT_32R6_64R6;
+def : MipsInstAlias<"nal", (BLTZAL R0, 0), 1>, ISA_MIPS1_NOT_32R6_64R6;
def SRemMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
@@ -3186,7 +3186,7 @@ def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>;
}
let AdditionalPredicates = [NotInMicroMips] in
- defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>, ISA_MIPS1;
+ defm : MaterializeImms<i32, R0, ADDiu, LUi, ORi>, ISA_MIPS1;
// Carry MipsPatterns
let AdditionalPredicates = [NotInMicroMips] in {
@@ -3262,7 +3262,7 @@ class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
MipsPat<(MipsWrapper RC:$gp, node:$in), (ADDiuOp RC:$gp, node:$in)>;
let AdditionalPredicates = [NotInMicroMips] in {
- defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>, ISA_MIPS1;
+ defm : MipsHiLoRelocs<LUi, ADDiu, R0, GPR32Opnd>, ISA_MIPS1;
def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi tglobaladdr:$in)>, ISA_MIPS1;
def : MipsPat<(MipsGotHi texternalsym:$in), (LUi texternalsym:$in)>,
@@ -3286,7 +3286,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
// Mips does not have "not", so we expand our way
def : MipsPat<(not GPR32:$in),
- (NOR GPR32Opnd:$in, ZERO)>, ISA_MIPS1;
+ (NOR GPR32Opnd:$in, R0)>, ISA_MIPS1;
}
// extended loads
@@ -3296,7 +3296,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>, ISA_MIPS1;
// peepholes
- def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, ISA_MIPS1;
+ def : MipsPat<(store (i32 0), addr:$dst), (SW R0, addr:$dst)>, ISA_MIPS1;
}
// brcond patterns
@@ -3310,28 +3310,28 @@ def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
(BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
- (BEQOp1 (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTOp RC:$lhs, RC:$rhs), R0, bb:$dst)>;
def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
- (BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), R0, bb:$dst)>;
def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
- (BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), R0, bb:$dst)>;
def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
- (BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), R0, bb:$dst)>;
def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
- (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), R0, bb:$dst)>;
def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
- (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), R0, bb:$dst)>;
def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
- (BEQOp1 (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTOp RC:$rhs, RC:$lhs), R0, bb:$dst)>;
def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
- (BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), R0, bb:$dst)>;
def : MipsPat<(brcond RC:$cond, bb:$dst),
(BNEOp RC:$cond, ZEROReg, bb:$dst)>;
}
let AdditionalPredicates = [NotInMicroMips] in {
- defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>,
+ defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, R0>,
ISA_MIPS1;
def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
(BLEZ i32:$lhs, bb:$dst)>, ISA_MIPS1;
@@ -3384,7 +3384,7 @@ multiclass SetgeImmPats<RegisterClass RC, Instruction XORiOp,
}
let AdditionalPredicates = [NotInMicroMips] in {
- defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>, ISA_MIPS1;
+ defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, R0>, ISA_MIPS1;
defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1;
defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 339f1c8a8b557..c63e54c031dee 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -151,7 +151,7 @@ bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
// Ori zero extends immediate. Used for values with zeros in high 16 bits.
if (Imm.getHiBits(16).isZero()) {
MachineInstr *Inst =
- B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
+ B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::R0)})
.addImm(Imm.getLoBits(16).getLimitedValue());
constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
return true;
@@ -166,7 +166,7 @@ bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
// ADDiu sign extends immediate. Used for values with 1s in high 17 bits.
if (Imm.isSignedIntN(16)) {
MachineInstr *Inst =
- B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
+ B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::R0)})
.addImm(Imm.getLoBits(16).getLimitedValue());
constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
return true;
@@ -742,7 +742,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
break;
case CmpInst::ICMP_NE: // LHS != RHS -> 0 < (LHS ^ RHS)
Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
- Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
+ Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::R0, Temp);
break;
case CmpInst::ICMP_UGT: // LHS > RHS -> RHS < LHS
Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS);
@@ -845,7 +845,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
.addDef(TrueInReg)
- .addUse(Mips::ZERO)
+ .addUse(Mips::R0)
.addImm(1);
unsigned Size = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
@@ -860,7 +860,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode))
.addDef(I.getOperand(0).getReg())
- .addUse(Mips::ZERO)
+ .addUse(Mips::R0)
.addUse(Mips::FCC0)
.addUse(TrueInReg);
constrainSelectedInstRegOperands(*Move, TII, TRI, RBI);
diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
index 2512cc893c320..7513634318730 100644
--- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -1311,7 +1311,7 @@ class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
bit isBranch = 1;
bit isTerminator = 1;
bit hasDelaySlot = 1;
- list<Register> Defs = [AT];
+ list<Register> Defs = [R1];
}
class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
diff --git a/llvm/lib/Target/Mips/MipsMTInstrInfo.td b/llvm/lib/Target/Mips/MipsMTInstrInfo.td
index 4cb609df0639b..de8b574790bbe 100644
--- a/llvm/lib/Target/Mips/MipsMTInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsMTInstrInfo.td
@@ -172,15 +172,15 @@ def CTTC1 : MipsAsmPseudoInst<(outs FGR32CCOpnd:$ft), (ins GPR32Opnd:$rt),
//===----------------------------------------------------------------------===//
let AdditionalPredicates = [NotInMicroMips] in {
- def : MipsInstAlias<"dmt", (DMT ZERO), 1>, ASE_MT;
+ def : MipsInstAlias<"dmt", (DMT R0), 1>, ASE_MT;
- def : MipsInstAlias<"emt", (EMT ZERO), 1>, ASE_MT;
+ def : MipsInstAlias<"emt", (EMT R0), 1>, ASE_MT;
- def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT;
+ def : MipsInstAlias<"dvpe", (DVPE R0), 1>, ASE_MT;
- def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;
+ def : MipsInstAlias<"evpe", (EVPE R0), 1>, ASE_MT;
- def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT;
+ def : MipsInstAlias<"yield $rs", (YIELD R0, GPR32Opnd:$rs), 1>, ASE_MT;
def : MipsInstAlias<"mftc0 $rd, $rt", (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0),
1>, ASE_MT;
diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp
index 0c5c6822f7c71..4fda9b58e6f34 100644
--- a/llvm/lib/Target/Mips/MipsMachineFunction.cpp
+++ b/llvm/lib/Target/Mips/MipsMachineFunction.cpp
@@ -138,13 +138,13 @@ void MipsFunctionInfo::initGlobalBaseReg(MachineFunction &MF) {
// The two instructions are emitted during lowering to MC layer in order to
// avoid any reordering.
//
- // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
+ // Register $2 (Mips::R2) is added to the list of live-in registers to ensure
// the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
// reads it.
- MF.getRegInfo().addLiveIn(Mips::V0);
- MBB.addLiveIn(Mips::V0);
+ MF.getRegInfo().addLiveIn(Mips::R2);
+ MBB.addLiveIn(Mips::R2);
BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
- .addReg(Mips::V0)
+ .addReg(Mips::R2)
.addReg(T9);
}
diff --git a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
index 9d44aaa338d4d..50a66fff66297 100644
--- a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
+++ b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
@@ -165,7 +165,7 @@ static bool eraseGPOpnd(MachineInstr &MI) {
MachineFunction &MF = *MI.getParent()->getParent();
MVT::SimpleValueType Ty = getRegTy(MI.getOperand(0).getReg(), MF);
- unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64;
+ unsigned Reg = Ty == MVT::i32 ? Mips::R28 : Mips::R28_64;
for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
MachineOperand &MO = MI.getOperand(I);
@@ -264,9 +264,9 @@ bool OptimizePICCall::visitNode(MBBInfo &MBBI) {
setCallTargetReg(MBB, I);
}
- if (MachineOperand *Def = I->findRegisterDefOperand(Mips::GP, &TRI))
+ if (MachineOperand *Def = I->findRegisterDefOperand(Mips::R28, &TRI))
GPDef = Def;
- else if (I->readsRegister(Mips::GP, &TRI))
+ else if (I->readsRegister(Mips::R28, &TRI))
GPDef = nullptr;
}
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index 98e8e1f406cf8..774584ab7fe2d 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -39,11 +39,11 @@ using namespace llvm;
#include "MipsGenRegisterInfo.inc"
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &STI)
- : MipsGenRegisterInfo(Mips::RA), ArePtrs64bit(STI.getABI().ArePtrs64bit()) {
+ : MipsGenRegisterInfo(Mips::R31), ArePtrs64bit(STI.getABI().ArePtrs64bit()) {
MIPS_MC::initLLVMToCVRegMapping(this);
}
-unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
+unsigned MipsRegisterInfo::getPICCallReg() { return Mips::R25; }
unsigned
MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
@@ -163,11 +163,11 @@ const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
BitVector MipsRegisterInfo::
getReservedRegs(const MachineFunction &MF) const {
static const MCPhysReg ReservedGPR32[] = {
- Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
+ Mips::R0, Mips::R26, Mips::R27, Mips::R29
};
static const MCPhysReg ReservedGPR64[] = {
- Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
+ Mips::R0_64, Mips::R26_64, Mips::R27_64, Mips::R29_64
};
BitVector Reserved(getNumRegs());
@@ -183,7 +183,7 @@ getReservedRegs(const MachineFunction &MF) const {
// including jumps within a function. Keep it out of register allocation.
const auto &TM = static_cast<const MipsTargetMachine &>(MF.getTarget());
if (TM.isJIT() && TM.getRelocationModel() == Reloc::Static)
- markSuperRegs(Reserved, Mips::T9);
+ markSuperRegs(Reserved, Mips::R25);
// Mark user-reserved GPRs and their 64-bit super-registers.
for (unsigned I = 1; I < 32; ++I)
@@ -193,8 +193,8 @@ getReservedRegs(const MachineFunction &MF) const {
// For mno-abicalls, GP is a program invariant!
bool GPIsGlobal = isGPUsedAsGlobalRegister(MF);
if (!Subtarget.isABICalls() || GPIsGlobal) {
- Reserved.set(Mips::GP);
- Reserved.set(Mips::GP_64);
+ Reserved.set(Mips::R28);
+ Reserved.set(Mips::R28_64);
}
if (Subtarget.isFP64bit()) {
@@ -209,17 +209,18 @@ getReservedRegs(const MachineFunction &MF) const {
// Reserve FP if this function should have a dedicated frame pointer register.
if (Subtarget.getFrameLowering()->hasFP(MF)) {
if (Subtarget.inMips16Mode())
- Reserved.set(Mips::S0);
+ Reserved.set(Mips::R16);
else {
- Reserved.set(Mips::FP);
- Reserved.set(Mips::FP_64);
+ Reserved.set(Mips::R30);
+ Reserved.set(Mips::R30_64);
// Reserve the base register if we need to both realign the stack and
// allocate variable-sized objects at runtime. This should test the
// same conditions as MipsFrameLowering::hasBP().
if (hasStackRealignment(MF) && MF.getFrameInfo().hasVarSizedObjects()) {
- Reserved.set(Mips::S7);
- Reserved.set(Mips::S7_64);
+ const MipsABIInfo &ABI = Subtarget.getABI();
+ Reserved.set(ABI.getSavedReg(7, false));
+ Reserved.set(ABI.getSavedReg(7, true));
}
}
}
@@ -244,18 +245,18 @@ getReservedRegs(const MachineFunction &MF) const {
// Reserve RA if in mips16 mode.
if (Subtarget.inMips16Mode()) {
const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
- Reserved.set(Mips::RA);
- Reserved.set(Mips::RA_64);
- Reserved.set(Mips::T0);
- Reserved.set(Mips::T1);
+ Reserved.set(Mips::R31);
+ Reserved.set(Mips::R31_64);
+ Reserved.set(Mips::R8);
+ Reserved.set(Mips::R9);
if (MF.getFunction().hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
- Reserved.set(Mips::S2);
+ Reserved.set(Mips::R18);
}
// Reserve GP if small section is used.
if (Subtarget.useSmallSection()) {
- Reserved.set(Mips::GP);
- Reserved.set(Mips::GP_64);
+ Reserved.set(Mips::R28);
+ Reserved.set(Mips::R28_64);
}
return Reserved;
@@ -296,10 +297,10 @@ getFrameRegister(const MachineFunction &MF) const {
bool IsN64 = Subtarget.getABI().IsN64();
if (Subtarget.inMips16Mode())
- return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
+ return TFI->hasFP(MF) ? Mips::R16 : Mips::R29;
else
- return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
- (IsN64 ? Mips::SP_64 : Mips::SP);
+ return TFI->hasFP(MF) ? (IsN64 ? Mips::R30_64 : Mips::R30) :
+ (IsN64 ? Mips::R29_64 : Mips::R29);
}
bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
@@ -314,7 +315,7 @@ bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
return false;
const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
- unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
+ unsigned FP = Subtarget.isGP32bit() ? Mips::R30 : Mips::R30_64;
unsigned BP = Subtarget.getABI().getSavedReg(7, Subtarget.isGP64bit());
// Support dynamic stack realignment for all targets except Mips16.
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td
index 06291bca61303..c8aeec586445d 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.td
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td
@@ -104,8 +104,8 @@ class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
let Namespace = "Mips" in {
// General Purpose Registers
// Registers whose ABI names differ between the O, N and P ABIs use
- // ABI-independent R<n> record names; see the ABI aliases below.
- // Use MipsABIInfo accessors for ABI roles.
+ // ABI-independent R<n> record names. For ABI-specific roles use the
+ // aliases above (TableGen) or MipsABIInfo accessors (C++).
let isConstant = true in
def R0 : MipsGPRReg< 0, "zero", "zero">, DwarfRegNum<[0]>;
def R1 : MipsGPRReg< 1, "1", "at">, DwarfRegNum<[1]>;
@@ -300,128 +300,6 @@ let Namespace = "Mips" in {
}
-//===----------------------------------------------------------------------===//
-// ABI register aliases
-//===----------------------------------------------------------------------===//
-
-// R2-R3 and R8-R15 have different names in the O32 (O), N32/N64 (N) and
-// P32/P64 (P) ABIs. Provide aliases for each ABI; the unsuffixed O names are
-// kept for compatibility. MipsMCTargetDesc.h has the matching C++ aliases.
-
-// O32 names.
-defvar V0 = R2;
-defvar V1 = R3;
-defvar T0 = R8;
-defvar T1 = R9;
-defvar T2 = R10;
-defvar T3 = R11;
-defvar T4 = R12;
-defvar T5 = R13;
-defvar T6 = R14;
-defvar T7 = R15;
-defvar V0_64 = R2_64;
-defvar V1_64 = R3_64;
-defvar T0_64 = R8_64;
-defvar T1_64 = R9_64;
-defvar T2_64 = R10_64;
-defvar T3_64 = R11_64;
-defvar T4_64 = R12_64;
-defvar T5_64 = R13_64;
-defvar T6_64 = R14_64;
-defvar T7_64 = R15_64;
-
-// N32/N64 names.
-defvar V0_N = R2;
-defvar V1_N = R3;
-defvar A4_N = R8;
-defvar A5_N = R9;
-defvar A6_N = R10;
-defvar A7_N = R11;
-defvar T0_N = R12;
-defvar T1_N = R13;
-defvar T2_N = R14;
-defvar T3_N = R15;
-defvar V0_N_64 = R2_64;
-defvar V1_N_64 = R3_64;
-defvar A4_N_64 = R8_64;
-defvar A5_N_64 = R9_64;
-defvar A6_N_64 = R10_64;
-defvar A7_N_64 = R11_64;
-defvar T0_N_64 = R12_64;
-defvar T1_N_64 = R13_64;
-defvar T2_N_64 = R14_64;
-defvar T3_N_64 = R15_64;
-
-// P32/P64 names.
-defvar T4_P = R2;
-defvar T5_P = R3;
-defvar A4_P = R8;
-defvar A5_P = R9;
-defvar A6_P = R10;
-defvar A7_P = R11;
-defvar T0_P = R12;
-defvar T1_P = R13;
-defvar T2_P = R14;
-defvar T3_P = R15;
-defvar T4_P_64 = R2_64;
-defvar T5_P_64 = R3_64;
-defvar A4_P_64 = R8_64;
-defvar A5_P_64 = R9_64;
-defvar A6_P_64 = R10_64;
-defvar A7_P_64 = R11_64;
-defvar T0_P_64 = R12_64;
-defvar T1_P_64 = R13_64;
-defvar T2_P_64 = R14_64;
-defvar T3_P_64 = R15_64;
-
-// O32-role aliases for the remaining registers; ABI-independent names
-// above. MipsMCTargetDesc.h has the matching C++ aliases. To be removed
-// in favour of MipsABIInfo accessors or plain R<n> names.
-defvar ZERO = R0;
-defvar AT = R1;
-defvar A0 = R4;
-defvar A1 = R5;
-defvar A2 = R6;
-defvar A3 = R7;
-defvar S0 = R16;
-defvar S1 = R17;
-defvar S2 = R18;
-defvar S3 = R19;
-defvar S4 = R20;
-defvar S5 = R21;
-defvar S6 = R22;
-defvar S7 = R23;
-defvar T8 = R24;
-defvar T9 = R25;
-defvar K0 = R26;
-defvar K1 = R27;
-defvar GP = R28;
-defvar SP = R29;
-defvar FP = R30;
-defvar RA = R31;
-defvar ZERO_64 = R0_64;
-defvar AT_64 = R1_64;
-defvar A0_64 = R4_64;
-defvar A1_64 = R5_64;
-defvar A2_64 = R6_64;
-defvar A3_64 = R7_64;
-defvar S0_64 = R16_64;
-defvar S1_64 = R17_64;
-defvar S2_64 = R18_64;
-defvar S3_64 = R19_64;
-defvar S4_64 = R20_64;
-defvar S5_64 = R21_64;
-defvar S6_64 = R22_64;
-defvar S7_64 = R23_64;
-defvar T8_64 = R24_64;
-defvar T9_64 = R25_64;
-defvar K0_64 = R26_64;
-defvar K1_64 = R27_64;
-defvar GP_64 = R28_64;
-defvar SP_64 = R29_64;
-defvar FP_64 = R30_64;
-defvar RA_64 = R31_64;
-
//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//
@@ -429,104 +307,104 @@ defvar RA_64 = R31_64;
class GPR32Class<list<ValueType> regTypes> :
RegisterClass<"Mips", regTypes, 32, (add
// Reserved
- ZERO, AT,
+ R0, R1,
// Return Values and Arguments
- V0, V1, A0, A1, A2, A3,
+ R2, R3, R4, R5, R6, R7,
// Not preserved across procedure calls
- T0, T1, T2, T3, T4, T5, T6, T7,
+ R8, R9, R10, R11, R12, R13, R14, R15,
// Callee save
- S0, S1, S2, S3, S4, S5, S6, S7,
+ R16, R17, R18, R19, R20, R21, R22, R23,
// Not preserved across procedure calls
- T8, T9,
+ R24, R25,
// Reserved
- K0, K1, GP, SP, FP, RA)>;
+ R26, R27, R28, R29, R30, R31)>;
def GPR32 : GPR32Class<[i32]>;
def GPR32ZERO : RegisterClass<"Mips", [i32], 32, (add
// Reserved
- ZERO)>;
+ R0)>;
def GPR32NONZERO : RegisterClass<"Mips", [i32], 32, (add
// Reserved
- AT,
+ R1,
// Return Values and Arguments
- V0, V1, A0, A1, A2, A3,
+ R2, R3, R4, R5, R6, R7,
// Not preserved across procedure calls
- T0, T1, T2, T3, T4, T5, T6, T7,
+ R8, R9, R10, R11, R12, R13, R14, R15,
// Callee save
- S0, S1, S2, S3, S4, S5, S6, S7,
+ R16, R17, R18, R19, R20, R21, R22, R23,
// Not preserved across procedure calls
- T8, T9,
+ R24, R25,
// Reserved
- K0, K1, GP, SP, FP, RA)>;
+ R26, R27, R28, R29, R30, R31)>;
def DSPR : GPR32Class<[v4i8, v2i16, i32]>;
def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
// Callee save
- S0, S1,
+ R16, R17,
// Return Values and Arguments
- V0, V1, A0, A1, A2, A3)>;
+ R2, R3, R4, R5, R6, R7)>;
def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
// Reserved
- ZERO,
+ R0,
// Callee save
- S1,
+ R17,
// Return Values and Arguments
- V0, V1, A0, A1, A2, A3)>;
+ R2, R3, R4, R5, R6, R7)>;
def GPRMM16MoveP : RegisterClass<"Mips", [i32], 32, (add
// Reserved
- ZERO,
+ R0,
// Callee save
- S1,
+ R17,
// Return Values and Arguments
- V0, V1,
+ R2, R3,
// Callee save
- S0, S2, S3, S4)>;
+ R16, R18, R19, R20)>;
def GPRMM16MovePPairFirst : RegisterClass<"Mips", [i32], 32, (add
// Arguments
- A0, A1, A2)>;
+ R4, R5, R6)>;
def GPRMM16MovePPairSecond : RegisterClass<"Mips", [i32], 32, (add
// Arguments
- A1, A2, A3,
+ R5, R6, R7,
// Callee save
- S5, S6)>;
+ R21, R22)>;
def GPR64 : RegisterClass<"Mips", [i64], 64, (add
// Reserved
- ZERO_64, AT_64,
+ R0_64, R1_64,
// Return Values and Arguments
- V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
+ R2_64, R3_64, R4_64, R5_64, R6_64, R7_64,
// Not preserved across procedure calls
- T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
+ R8_64, R9_64, R10_64, R11_64, R12_64, R13_64, R14_64, R15_64,
// Callee save
- S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
+ R16_64, R17_64, R18_64, R19_64, R20_64, R21_64, R22_64, R23_64,
// Not preserved across procedure calls
- T8_64, T9_64,
+ R24_64, R25_64,
// Reserved
- K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
+ R26_64, R27_64, R28_64, R29_64, R30_64, R31_64)>;
def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
// Return Values and Arguments
- V0, V1, A0, A1, A2, A3,
+ R2, R3, R4, R5, R6, R7,
// Callee save
- S0, S1)>;
+ R16, R17)>;
def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
// Return Values and Arguments
- V0, V1, A0, A1, A2, A3,
+ R2, R3, R4, R5, R6, R7,
// Callee save
- S0, S1,
- SP)>;
+ R16, R17,
+ R29)>;
-def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
+def CPURAReg : RegisterClass<"Mips", [i32], 32, (add R31)>, Unallocatable;
-def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
+def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add R29)>, Unallocatable;
// 64bit fp:
// * FGR64 - 32 64-bit registers
@@ -634,10 +512,10 @@ def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>,
// Stack pointer and global pointer classes for instructions that are limited
// to a single register such as lwgp/lwsp in microMIPS.
-def SP32 : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
-def SP64 : RegisterClass<"Mips", [i64], 64, (add SP_64)>, Unallocatable;
-def GP32 : RegisterClass<"Mips", [i32], 32, (add GP)>, Unallocatable;
-def GP64 : RegisterClass<"Mips", [i64], 64, (add GP_64)>, Unallocatable;
+def SP32 : RegisterClass<"Mips", [i32], 32, (add R29)>, Unallocatable;
+def SP64 : RegisterClass<"Mips", [i64], 64, (add R29_64)>, Unallocatable;
+def GP32 : RegisterClass<"Mips", [i32], 32, (add R28)>, Unallocatable;
+def GP64 : RegisterClass<"Mips", [i64], 64, (add R28_64)>, Unallocatable;
// Octeon multiplier and product registers
def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>,
diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
index d4891152337ad..7a932043996d9 100644
--- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -301,7 +301,7 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
// implicit operand, so other passes (like ShrinkWrapping) are aware that
// stack is used.
if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
- && I->getOperand(3).getReg() == Mips::SP) {
+ && I->getOperand(3).getReg() == Mips::R29) {
Register DstReg = I->getOperand(0).getReg();
Register LoReg = I->getOperand(1).getReg();
Register HiReg = I->getOperand(2).getReg();
@@ -358,7 +358,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
// implicit operand, so other passes (like ShrinkWrapping) are aware that
// stack is used.
if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
- && I->getOperand(3).getReg() == Mips::SP) {
+ && I->getOperand(3).getReg() == Mips::R29) {
Register DstReg = I->getOperand(0).getReg();
Register SrcReg = Op1.getReg();
unsigned N = Op2.getImm();
@@ -544,13 +544,13 @@ void MipsSEFrameLowering::emitInterruptPrologueStub(
if (IntKind == "eic") {
// Coprocessor registers are always live per se.
MBB.addLiveIn(Mips::COP013);
- BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)
+ BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::R26)
.addReg(Mips::COP013)
.addImm(0)
.setMIFlag(MachineInstr::FrameSetup);
- BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)
- .addReg(Mips::K0)
+ BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::R26)
+ .addReg(Mips::R26)
.addImm(10)
.addImm(6)
.setMIFlag(MachineInstr::FrameSetup);
@@ -558,34 +558,34 @@ void MipsSEFrameLowering::emitInterruptPrologueStub(
// Fetch and spill EPC
MBB.addLiveIn(Mips::COP014);
- BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
+ BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::R27)
.addReg(Mips::COP014)
.addImm(0)
.setMIFlag(MachineInstr::FrameSetup);
- STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
+ STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::R27, false,
MipsFI->getISRRegFI(0), PtrRC, 0);
// Fetch and Spill Status
MBB.addLiveIn(Mips::COP012);
- BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
+ BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::R27)
.addReg(Mips::COP012)
.addImm(0)
.setMIFlag(MachineInstr::FrameSetup);
- STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
+ STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::R27, false,
MipsFI->getISRRegFI(1), PtrRC, 0);
// Build the configuration for disabling lower priority interrupts. Non EIC
// interrupts need to be masked off with zero, EIC from the Cause register.
unsigned InsPosition = 8;
unsigned InsSize = 0;
- unsigned SrcReg = Mips::ZERO;
+ unsigned SrcReg = Mips::R0;
// If the interrupt we're tied to is the EIC, switch the source for the
// masking off interrupts to the cause register.
if (IntKind == "eic") {
- SrcReg = Mips::K0;
+ SrcReg = Mips::R26;
InsPosition = 10;
InsSize = 6;
} else
@@ -601,33 +601,33 @@ void MipsSEFrameLowering::emitInterruptPrologueStub(
.Default(0);
assert(InsSize != 0 && "Unknown interrupt type!");
- BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
+ BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::R27)
.addReg(SrcReg)
.addImm(InsPosition)
.addImm(InsSize)
- .addReg(Mips::K1)
+ .addReg(Mips::R27)
.setMIFlag(MachineInstr::FrameSetup);
// Mask off KSU, ERL, EXL
- BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
- .addReg(Mips::ZERO)
+ BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::R27)
+ .addReg(Mips::R0)
.addImm(1)
.addImm(4)
- .addReg(Mips::K1)
+ .addReg(Mips::R27)
.setMIFlag(MachineInstr::FrameSetup);
// Disable the FPU as we are not spilling those register sets.
if (!STI.useSoftFloat())
- BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
- .addReg(Mips::ZERO)
+ BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::R27)
+ .addReg(Mips::R0)
.addImm(29)
.addImm(1)
- .addReg(Mips::K1)
+ .addReg(Mips::R27)
.setMIFlag(MachineInstr::FrameSetup);
// Set the new status
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
- .addReg(Mips::K1)
+ .addReg(Mips::R27)
.addImm(0)
.setMIFlag(MachineInstr::FrameSetup);
}
@@ -699,21 +699,21 @@ void MipsSEFrameLowering::emitInterruptEpilogueStub(
const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
// Disable Interrupts.
- BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
+ BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::R0);
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
// Restore EPC
STI.getInstrInfo()->loadRegFromStackSlot(
- MBB, MBBI, Mips::K1, MipsFI->getISRRegFI(0), PtrRC, Register());
+ MBB, MBBI, Mips::R27, MipsFI->getISRRegFI(0), PtrRC, Register());
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
- .addReg(Mips::K1)
+ .addReg(Mips::R27)
.addImm(0);
// Restore Status
STI.getInstrInfo()->loadRegFromStackSlot(
- MBB, MBBI, Mips::K1, MipsFI->getISRRegFI(1), PtrRC, Register());
+ MBB, MBBI, Mips::R27, MipsFI->getISRRegFI(1), PtrRC, Register());
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
- .addReg(Mips::K1)
+ .addReg(Mips::R27)
.addImm(0);
}
@@ -746,7 +746,7 @@ bool MipsSEFrameLowering::spillCalleeSavedRegisters(
// It's killed at the spill, unless the register is RA and return address
// is taken.
MCRegister Reg = I.getReg();
- bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
+ bool IsRAAndRetAddrIsTaken = (Reg == Mips::R31 || Reg == Mips::R31_64)
&& MF->getFrameInfo().isReturnAddressTaken();
if (!IsRAAndRetAddrIsTaken)
MBB.addLiveIn(Reg);
@@ -762,12 +762,12 @@ bool MipsSEFrameLowering::spillCalleeSavedRegisters(
unsigned Op = 0;
if (!STI.getABI().ArePtrs64bit()) {
Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;
- Reg = Mips::K0;
+ Reg = Mips::R26;
} else {
Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64;
- Reg = Mips::K0_64;
+ Reg = Mips::R26_64;
}
- BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
+ BuildMI(MBB, MI, DL, TII.get(Op), Mips::R26)
.setMIFlag(MachineInstr::FrameSetup);
}
@@ -807,7 +807,7 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
MipsABIInfo ABI = STI.getABI();
- unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
+ unsigned RA = ABI.IsN64() ? Mips::R31_64 : Mips::R31;
unsigned FP = ABI.GetFramePtr();
unsigned BP = ABI.GetBasePtr();
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index 392b9b4f9059a..3613e74729a67 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -80,17 +80,17 @@ bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
// Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
if ((MI.getOpcode() == Mips::ADDiu) &&
- (MI.getOperand(1).getReg() == Mips::ZERO) &&
+ (MI.getOperand(1).getReg() == Mips::R0) &&
(MI.getOperand(2).isImm()) &&
(MI.getOperand(2).getImm() == 0)) {
DstReg = MI.getOperand(0).getReg();
- ZeroReg = Mips::ZERO;
+ ZeroReg = Mips::R0;
} else if ((MI.getOpcode() == Mips::DADDiu) &&
- (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
+ (MI.getOperand(1).getReg() == Mips::R0_64) &&
(MI.getOperand(2).isImm()) &&
(MI.getOperand(2).getImm() == 0)) {
DstReg = MI.getOperand(0).getReg();
- ZeroReg = Mips::ZERO_64;
+ ZeroReg = Mips::R0_64;
}
if (!DstReg)
@@ -125,24 +125,24 @@ void MipsSEDAGToDAGISel::emitMCountABI(MachineInstr &MI, MachineBasicBlock &MBB,
if (!Subtarget->isABI_O32()) { // N32, N64
// Save current return address.
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR64))
- .addDef(Mips::AT_64)
- .addUse(Mips::RA_64, RegState::Undef)
- .addUse(Mips::ZERO_64);
+ .addDef(Mips::R1_64)
+ .addUse(Mips::R31_64, RegState::Undef)
+ .addUse(Mips::R0_64);
// Stops instruction above from being removed later on.
- MIB.addUse(Mips::AT_64, RegState::Implicit);
+ MIB.addUse(Mips::R1_64, RegState::Implicit);
} else { // O32
// Save current return address.
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR))
- .addDef(Mips::AT)
- .addUse(Mips::RA, RegState::Undef)
- .addUse(Mips::ZERO);
+ .addDef(Mips::R1)
+ .addUse(Mips::R31, RegState::Undef)
+ .addUse(Mips::R0);
// _mcount pops 2 words from stack.
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu))
- .addDef(Mips::SP)
- .addUse(Mips::SP)
+ .addDef(Mips::R29)
+ .addUse(Mips::R29)
.addImm(-8);
// Stops first instruction above from being removed later on.
- MIB.addUse(Mips::AT, RegState::Implicit);
+ MIB.addUse(Mips::R1, RegState::Implicit);
}
}
@@ -163,14 +163,14 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
case Mips::BuildPairF64_64:
case Mips::ExtractElementF64_64:
if (!Subtarget->useOddSPReg() || !Subtarget->hasMTHC1()) {
- MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
+ MI.addOperand(MachineOperand::CreateReg(Mips::R29, false, true));
break;
}
[[fallthrough]];
case Mips::BuildPairF64:
case Mips::ExtractElementF64:
if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
- MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
+ MI.addOperand(MachineOperand::CreateReg(Mips::R29, false, true));
break;
case Mips::JAL:
case Mips::JAL_MM:
@@ -246,7 +246,7 @@ void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
// Hence take an extremely conservative view and presume it's sticky. We
// therefore need to clear it.
- SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
+ SDValue Zero = CurDAG->getRegister(Mips::R0, MVT::i32);
SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
SDNode *DSPCtrlFinal =
@@ -752,17 +752,17 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
if (Node->getValueType(0) == MVT::f64 && CN->isPosZero()) {
if (Subtarget->isGP64bit()) {
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
- Mips::ZERO_64, MVT::i64);
+ Mips::R0_64, MVT::i64);
ReplaceNode(Node,
CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
} else if (Subtarget->isFP64bit()) {
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
- Mips::ZERO, MVT::i32);
+ Mips::R0, MVT::i32);
ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
MVT::f64, Zero, Zero));
} else {
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
- Mips::ZERO, MVT::i32);
+ Mips::R0, MVT::i32);
ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL,
MVT::f64, Zero, Zero));
}
@@ -798,7 +798,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
else
RegOpnd =
CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
- CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
+ CurDAG->getRegister(Mips::R0_64, MVT::i64),
ImmOpnd);
// The remaining instructions in the sequence are handled here.
@@ -1031,10 +1031,10 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
if (PtrVT == MVT::i32) {
RdhwrOpc = Mips::RDHWR;
- DestReg = Mips::V1;
+ DestReg = Mips::R3;
} else {
RdhwrOpc = Mips::RDHWR64;
- DestReg = Mips::V1_N_64;
+ DestReg = Mips::R3_64;
}
SDNode *Rdhwr =
@@ -1124,7 +1124,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
SDValue ZeroVal = CurDAG->getRegister(
- Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
+ Is32BitSplat ? Mips::R0 : Mips::R0_64, SplatMVT);
const unsigned FILLOp =
SplatBitSize == 16
@@ -1147,7 +1147,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
// of the SplatValue here.
const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
- SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
+ SDValue ZeroVal = CurDAG->getRegister(Mips::R0, MVT::i32);
SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
@@ -1170,7 +1170,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
// zero/sign extension.
const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
- SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
+ SDValue ZeroVal = CurDAG->getRegister(Mips::R0, MVT::i32);
SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
@@ -1224,7 +1224,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
- SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
+ SDValue ZeroVal = CurDAG->getRegister(Mips::R0, MVT::i32);
// Independent of whether we're targeting MIPS64 or not, the basic
// operations are the same. Also, directly use the $zero register if
@@ -1281,7 +1281,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
CurDAG->getTargetConstant(0, DL, MVT::i32));
} else if (ABI.IsN64() || ABI.IsN32()) {
- SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
+ SDValue Zero64Val = CurDAG->getRegister(Mips::R0_64, MVT::i64);
const bool HiResNonZero = Highest || Higher;
const bool ResNonZero = Hi || Lo;
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
index b3de06a2844bb..e0dc415ba602c 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -3285,13 +3285,13 @@ MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
// Fill $FBB.
Register VR2 = RegInfo.createVirtualRegister(RC);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
- .addReg(Mips::ZERO).addImm(0);
+ .addReg(Mips::R0).addImm(0);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
// Fill $TBB.
Register VR1 = RegInfo.createVirtualRegister(RC);
BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
- .addReg(Mips::ZERO).addImm(1);
+ .addReg(Mips::R0).addImm(1);
// Insert phi function to $Sink.
BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
@@ -3354,13 +3354,13 @@ MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
// Fill $FBB.
Register RD1 = RegInfo.createVirtualRegister(RC);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
- .addReg(Mips::ZERO).addImm(0);
+ .addReg(Mips::R0).addImm(0);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
// Fill $TBB.
Register RD2 = RegInfo.createVirtualRegister(RC);
BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
- .addReg(Mips::ZERO).addImm(1);
+ .addReg(Mips::R0).addImm(1);
// Insert phi function to $Sink.
BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
@@ -3634,7 +3634,7 @@ MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
Register LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
LaneTmp2)
- .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
+ .addReg(Subtarget.isABI_N64() ? Mips::R0_64 : Mips::R0)
.addReg(LaneReg);
BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
.addReg(WdTmp2)
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index 60febefb08548..d58aeb2348f91 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -150,7 +150,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
if (isMicroMips)
Opc = Mips::MOVE16_MM;
else
- Opc = Mips::OR, ZeroReg = Mips::ZERO;
+ Opc = Mips::OR, ZeroReg = Mips::R0;
} else if (Mips::CCRRegClass.contains(SrcReg))
Opc = Mips::CFC1;
else if (Mips::FGR32RegClass.contains(SrcReg))
@@ -213,7 +213,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Opc = Mips::FMOV_D64;
else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
if (Mips::GPR64RegClass.contains(SrcReg))
- Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
+ Opc = Mips::OR64, ZeroReg = Mips::R0_64;
else if (Mips::HI64RegClass.contains(SrcReg))
Opc = Mips::MFHI64, SrcReg = 0;
else if (Mips::LO64RegClass.contains(SrcReg))
@@ -278,11 +278,11 @@ static bool isORCopyInst(const MachineInstr &MI) {
break;
case Mips::OR_MM:
case Mips::OR:
- if (MI.getOperand(2).getReg() == Mips::ZERO)
+ if (MI.getOperand(2).getReg() == Mips::R0)
return true;
break;
case Mips::OR64:
- if (MI.getOperand(2).getReg() == Mips::ZERO_64)
+ if (MI.getOperand(2).getReg() == Mips::R0_64)
return true;
break;
}
@@ -356,17 +356,17 @@ void MipsSEInstrInfo::storeRegToStack(MachineBasicBlock &MBB,
const Function &Func = MBB.getParent()->getFunction();
if (Func.hasFnAttribute("interrupt")) {
if (Mips::HI32RegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
- SrcReg = Mips::K0;
+ BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::R26);
+ SrcReg = Mips::R26;
} else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
- SrcReg = Mips::K0_64;
+ BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::R26_64);
+ SrcReg = Mips::R26_64;
} else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
- SrcReg = Mips::K0;
+ BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::R26);
+ SrcReg = Mips::R26;
} else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
- SrcReg = Mips::K0_64;
+ BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::R26_64);
+ SrcReg = Mips::R26_64;
}
}
@@ -441,13 +441,13 @@ void MipsSEInstrInfo::loadRegFromStack(MachineBasicBlock &MBB,
else {
// Load HI/LO through K0. Notably the DestReg is encoded into the
// instruction itself.
- unsigned Reg = Mips::K0;
+ unsigned Reg = Mips::R26;
unsigned LdOp = Mips::MTLO;
if (DestReg == Mips::HI0)
LdOp = Mips::MTHI;
if (Subtarget.getABI().ArePtrs64bit()) {
- Reg = Mips::K0_64;
+ Reg = Mips::R26_64;
if (DestReg == Mips::HI0_64)
LdOp = Mips::MTHI64;
else
@@ -688,7 +688,7 @@ unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
unsigned Size = STI.isABI_N64() ? 64 : 32;
unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
- unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
+ unsigned ZEROReg = STI.isABI_N64() ? Mips::R0_64 : Mips::R0;
const TargetRegisterClass *RC = STI.isABI_N64() ?
&Mips::GPR64RegClass : &Mips::GPR32RegClass;
bool LastInstrIsADDiu = NewImm;
@@ -754,10 +754,10 @@ void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
MachineInstrBuilder MIB;
if (Subtarget.isGP64bit())
MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
- .addReg(Mips::RA_64, RegState::Undef);
+ .addReg(Mips::R31_64, RegState::Undef);
else
MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
- .addReg(Mips::RA, RegState::Undef);
+ .addReg(Mips::R31, RegState::Undef);
// Retain any imp-use flags.
for (auto & MO : I->operands()) {
@@ -953,10 +953,10 @@ void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
// indirect jump to TargetReg
MipsABIInfo ABI = Subtarget.getABI();
unsigned ADDU = ABI.GetPtrAdduOp();
- unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
- unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
+ unsigned SP = Subtarget.isGP64bit() ? Mips::R29_64 : Mips::R29;
+ unsigned RA = Subtarget.isGP64bit() ? Mips::R31_64 : Mips::R31;
unsigned T9 = ABI.getTempReg(9, Subtarget.isGP64bit());
- unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
+ unsigned ZERO = Subtarget.isGP64bit() ? Mips::R0_64 : Mips::R0;
Register OffsetReg = I->getOperand(0).getReg();
Register TargetReg = I->getOperand(1).getReg();
diff --git a/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp b/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
index f9666d98e1e81..8448dbd9779b3 100644
--- a/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
@@ -7,6 +7,7 @@
//===----------------------------------------------------------------------===//
#include "../Error.h"
#include "../Target.h"
+#include "MCTargetDesc/MipsABIInfo.h"
#include "MCTargetDesc/MipsBaseInfo.h"
#include "Mips.h"
#include "MipsRegisterInfo.h"
@@ -78,12 +79,12 @@ static std::vector<MCInst> loadImmediate(MCRegister Reg, bool IsGPR32,
unsigned ZeroReg;
unsigned ORi, LUi, SLL;
if (IsGPR32) {
- ZeroReg = Mips::ZERO;
+ ZeroReg = Mips::R0;
ORi = Mips::ORi;
SLL = Mips::SLL;
LUi = Mips::LUi;
} else {
- ZeroReg = Mips::ZERO_64;
+ ZeroReg = Mips::R0_64;
ORi = Mips::ORi64;
SLL = Mips::SLL64_64;
LUi = Mips::LUi64;
@@ -136,7 +137,9 @@ static std::vector<MCInst> loadImmediate(MCRegister Reg, bool IsGPR32,
MCRegister
ExegesisMipsTarget::getScratchMemoryRegister(const Triple &TT) const {
- return TT.isArch64Bit() ? Mips::A0_64 : Mips::A0;
+ const MipsABIInfo ABI =
+ TT.isArch64Bit() ? MipsABIInfo::N64() : MipsABIInfo::O32();
+ return ABI.getArgReg(0);
}
void ExegesisMipsTarget::fillMemoryOperands(InstructionTemplate &IT,
diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp
index 83ea6c0ba8e4f..645e5e68fe601 100644
--- a/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp
@@ -54,13 +54,13 @@ TEST_F(MipsBenchmarkResultTest, WriteToAndReadFromDisk) {
Benchmark ToDisk;
ToDisk.Key.Instructions.push_back(MCInstBuilder(Mips::XOR)
- .addReg(Mips::T0)
- .addReg(Mips::T1)
- .addReg(Mips::T2));
+ .addReg(Mips::R8)
+ .addReg(Mips::R9)
+ .addReg(Mips::R10));
ToDisk.Key.Config = "config";
ToDisk.Key.RegisterInitialValues = {
- RegisterValue{Mips::T1, APInt(8, "123", 10)},
- RegisterValue{Mips::T2, APInt(8, "456", 10)}};
+ RegisterValue{Mips::R9, APInt(8, "123", 10)},
+ RegisterValue{Mips::R10, APInt(8, "456", 10)}};
ToDisk.Mode = Benchmark::Latency;
ToDisk.CpuName = "cpu_name";
ToDisk.LLVMTriple = "llvm_triple";
diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/RegisterAliasingTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/RegisterAliasingTest.cpp
index 62a7ee5407707..13d01b92a752e 100644
--- a/llvm/unittests/tools/llvm-exegesis/Mips/RegisterAliasingTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/Mips/RegisterAliasingTest.cpp
@@ -25,14 +25,14 @@ class MipsRegisterAliasingTest : public MipsTestBase {};
TEST_F(MipsRegisterAliasingTest, TrackSimpleRegister) {
const auto &RegInfo = State.getRegInfo();
- const RegisterAliasingTracker tracker(RegInfo, Mips::T0_64);
+ const RegisterAliasingTracker tracker(RegInfo, Mips::R8_64);
std::set<MCPhysReg> ActualAliasedRegisters;
for (unsigned I : tracker.aliasedBits().set_bits())
ActualAliasedRegisters.insert(static_cast<MCPhysReg>(I));
- const std::set<MCPhysReg> ExpectedAliasedRegisters = {Mips::T0, Mips::T0_64};
+ const std::set<MCPhysReg> ExpectedAliasedRegisters = {Mips::R8, Mips::R8_64};
ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters);
for (MCPhysReg aliased : ExpectedAliasedRegisters) {
- ASSERT_THAT(tracker.getOrigin(aliased), Mips::T0_64);
+ ASSERT_THAT(tracker.getOrigin(aliased), Mips::R8_64);
}
}
@@ -49,10 +49,10 @@ TEST_F(MipsRegisterAliasingTest, TrackRegisterClass) {
Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID));
BitVector sum(RegInfo.getNumRegs());
- sum |= RegisterAliasingTracker(RegInfo, Mips::ZERO_64).aliasedBits();
- sum |= RegisterAliasingTracker(RegInfo, Mips::V0_64).aliasedBits();
- sum |= RegisterAliasingTracker(RegInfo, Mips::V1_64).aliasedBits();
- sum |= RegisterAliasingTracker(RegInfo, Mips::S1_64).aliasedBits();
+ sum |= RegisterAliasingTracker(RegInfo, Mips::R0_64).aliasedBits();
+ sum |= RegisterAliasingTracker(RegInfo, Mips::R2_64).aliasedBits();
+ sum |= RegisterAliasingTracker(RegInfo, Mips::R3_64).aliasedBits();
+ sum |= RegisterAliasingTracker(RegInfo, Mips::R17_64).aliasedBits();
ASSERT_THAT(RegClassTracker.aliasedBits(), sum);
}
@@ -62,7 +62,7 @@ TEST_F(MipsRegisterAliasingTest, TrackRegisterClassCache) {
const auto &RegInfo = State.getRegInfo();
const BitVector NoReservedReg(RegInfo.getNumRegs());
RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
- ASSERT_THAT(&Cache.getRegister(Mips::T0), &Cache.getRegister(Mips::T0));
+ ASSERT_THAT(&Cache.getRegister(Mips::R8), &Cache.getRegister(Mips::R8));
ASSERT_THAT(&Cache.getRegisterClass(Mips::ACC64RegClassID),
&Cache.getRegisterClass(Mips::ACC64RegClassID));
diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp
index d18ece99d4a6b..6c2f56f5cd3ad 100644
--- a/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp
@@ -42,7 +42,7 @@ Matcher<MCInst> OpcodeIs(unsigned Opcode) {
}
Matcher<MCInst> IsLoadLow16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) {
- const unsigned ZeroReg = IsGPR32 ? Mips::ZERO : Mips::ZERO_64;
+ const unsigned ZeroReg = IsGPR32 ? Mips::R0 : Mips::R0_64;
const unsigned ORi = IsGPR32 ? Mips::ORi : Mips::ORi64;
return AllOf(OpcodeIs(ORi),
ElementsAre(IsReg(Reg), IsReg(ZeroReg), IsImm(Value)));
@@ -69,25 +69,25 @@ class MipsTargetTest : public MipsTestBase {
TEST_F(MipsTargetTest, SetGPR32RegTo16BitValue) {
const uint16_t Value = 0xFFFFU;
- const unsigned Reg = Mips::T0;
+ const unsigned Reg = Mips::R8;
EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
ElementsAre(IsLoadLow16BitImm(Reg, Value, true)));
}
TEST_F(MipsTargetTest, SetGPR64RegTo16BitValue) {
const uint16_t Value = 0xFFFFU;
- const unsigned Reg = Mips::T0_64;
+ const unsigned Reg = Mips::R8_64;
EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
ElementsAre(IsLoadLow16BitImm(Reg, Value, false)));
}
TEST_F(MipsTargetTest, SetGPR32RegTo32BitValue) {
const uint32_t Value0 = 0xFFFF0000UL;
- const unsigned Reg0 = Mips::T0;
+ const unsigned Reg0 = Mips::R8;
EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)),
ElementsAre(IsLoadHigh16BitImm(Reg0, 0xFFFFU, true)));
const uint32_t Value1 = 0xFFFFFFFFUL;
- const unsigned Reg1 = Mips::T1;
+ const unsigned Reg1 = Mips::R9;
EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)),
ElementsAre(IsLoadHigh16BitImm(Reg1, 0xFFFFU, true),
IsLoadLow16BitImm(Reg1, 0xFFFFU, true)));
@@ -95,21 +95,21 @@ TEST_F(MipsTargetTest, SetGPR32RegTo32BitValue) {
TEST_F(MipsTargetTest, SetGPR64RegTo32BitValue) {
const uint32_t Value0 = 0x7FFF0000UL;
- const unsigned Reg0 = Mips::T0_64;
+ const unsigned Reg0 = Mips::R8_64;
EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)),
ElementsAre(IsLoadHigh16BitImm(Reg0, 0x7FFFU, false)));
const uint32_t Value1 = 0x7FFFFFFFUL;
- const unsigned Reg1 = Mips::T1_64;
+ const unsigned Reg1 = Mips::R9_64;
EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)),
ElementsAre(IsLoadHigh16BitImm(Reg1, 0x7FFFU, false),
IsLoadLow16BitImm(Reg1, 0xFFFFU, false)));
const uint32_t Value2 = 0xFFFF0000UL;
- const unsigned Reg2 = Mips::T2_64;
+ const unsigned Reg2 = Mips::R10_64;
EXPECT_THAT(setRegTo(Reg2, APInt(32, Value2)),
ElementsAre(IsLoadLow16BitImm(Reg2, 0xFFFFU, false),
IsShift(Reg2, 16, false)));
const uint32_t Value3 = 0xFFFFFFFFUL;
- const unsigned Reg3 = Mips::T3_64;
+ const unsigned Reg3 = Mips::R11_64;
EXPECT_THAT(setRegTo(Reg3, APInt(32, Value3)),
ElementsAre(IsLoadLow16BitImm(Reg3, 0xFFFFU, false),
IsShift(Reg3, 16, false),
>From dbd7d39033b81fc357b0012aa88f10d5b273b2e0 Mon Sep 17 00:00:00 2001
From: Anton Rapetov <willir29 at gmail.com>
Date: Sun, 11 Oct 2026 13:04:15 -0400
Subject: [PATCH 7/7] [Mips] clang-format changed lines
Apply clang-format 23.1.3 (the version used by the PR formatting check)
to the lines modified by the GPR rename. NFC.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
---
.../Target/Mips/AsmParser/MipsAsmParser.cpp | 354 ++++++++++++------
.../Target/Mips/MCTargetDesc/MipsABIInfo.cpp | 20 +-
.../Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 26 +-
.../Target/Mips/MicroMipsSizeReduction.cpp | 14 +-
llvm/lib/Target/Mips/Mips16FrameLowering.cpp | 9 +-
llvm/lib/Target/Mips/Mips16InstrInfo.cpp | 7 +-
llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 54 +--
llvm/lib/Target/Mips/MipsBranchExpansion.cpp | 3 +-
llvm/lib/Target/Mips/MipsCallLowering.cpp | 4 +-
llvm/lib/Target/Mips/MipsISelLowering.cpp | 6 +-
llvm/lib/Target/Mips/MipsInstrInfo.cpp | 14 +-
llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 17 +-
llvm/lib/Target/Mips/MipsSEFrameLowering.cpp | 12 +-
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 17 +-
llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 12 +-
llvm/tools/llvm-exegesis/lib/Mips/Target.cpp | 2 +-
.../Mips/BenchmarkResultTest.cpp | 7 +-
17 files changed, 350 insertions(+), 228 deletions(-)
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 52847a1ea9010..32199fde69fad 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1339,20 +1339,21 @@ class MipsOperand : public MCParsedAsmOperand {
}
template <unsigned Bits> bool isMemWithUimmOffsetSP() const {
- return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
- && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::R29);
+ return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff()) &&
+ getMemBase()->isRegIdx() &&
+ (getMemBase()->getGPR32Reg() == Mips::R29);
}
template <unsigned Bits> bool isMemWithUimmWordAlignedOffsetSP() const {
- return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
- && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
- && (getMemBase()->getGPR32Reg() == Mips::R29);
+ return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff()) &&
+ (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx() &&
+ (getMemBase()->getGPR32Reg() == Mips::R29);
}
template <unsigned Bits> bool isMemWithSimmWordAlignedOffsetGP() const {
- return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
- && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
- && (getMemBase()->getGPR32Reg() == Mips::R28);
+ return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff()) &&
+ (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx() &&
+ (getMemBase()->getGPR32Reg() == Mips::R28);
}
template <unsigned Bits, unsigned ShiftLeftAmount>
@@ -2087,8 +2088,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
// of the assembler. We ought to leave it to those later stages.
const MCSymbol *JalSym = getSingleMCSymbol(JalExpr);
- if (expandLoadAddress(getABI().getTempReg(9), MCRegister(), Inst.getOperand(0),
- !isGP64bit(), IDLoc, Out, STI))
+ if (expandLoadAddress(getABI().getTempReg(9), MCRegister(),
+ Inst.getOperand(0), !isGP64bit(), IDLoc, Out, STI))
return true;
MCInst JalrInst;
@@ -2147,10 +2148,12 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
MCOperand &DstReg = Inst.getOperand(0);
MCOperand &BaseReg = Inst.getOperand(1);
if (isInt<9>(MemOffset) && (MemOffset % 4 == 0) &&
- getContext().getRegisterInfo()->getRegClass(
- Mips::GPRMM16RegClassID).contains(DstReg.getReg()) &&
+ getContext()
+ .getRegisterInfo()
+ ->getRegClass(Mips::GPRMM16RegClassID)
+ .contains(DstReg.getReg()) &&
(BaseReg.getReg() == Mips::R28 ||
- BaseReg.getReg() == Mips::R28_64)) {
+ BaseReg.getReg() == Mips::R28_64)) {
TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::R28, MemOffset,
IDLoc, STI);
@@ -2972,8 +2975,8 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
// constant then we must use R_MIPS_CALL16 instead of R_MIPS_GOT16
// or R_MIPS_CALL16 instead of R_MIPS_GOT_DISP in 64-bit case.
if ((DstReg == getABI().getTempReg(9, false) ||
- DstReg == getABI().getTempReg(9, true)) && !UseSrcReg &&
- Res.getConstant() == 0 && !IsLocalSym) {
+ DstReg == getABI().getTempReg(9, true)) &&
+ !UseSrcReg && Res.getConstant() == 0 && !IsLocalSym) {
if (UseXGOT) {
const MCExpr *CallHiExpr =
MCSpecifierExpr::create(SymExpr, Mips::S_CALL_HI16, getContext());
@@ -3258,38 +3261,70 @@ static MCRegister nextReg(MCRegister Reg) {
return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1;
switch (Reg.id()) {
default: llvm_unreachable("Unknown register in assembly macro expansion!");
- case Mips::R0: return Mips::R1;
- case Mips::R1: return Mips::R2;
- case Mips::R2: return Mips::R3;
- case Mips::R3: return Mips::R4;
- case Mips::R4: return Mips::R5;
- case Mips::R5: return Mips::R6;
- case Mips::R6: return Mips::R7;
- case Mips::R7: return Mips::R8;
- case Mips::R8: return Mips::R9;
- case Mips::R9: return Mips::R10;
- case Mips::R10: return Mips::R11;
- case Mips::R11: return Mips::R12;
- case Mips::R12: return Mips::R13;
- case Mips::R13: return Mips::R14;
- case Mips::R14: return Mips::R15;
- case Mips::R15: return Mips::R16;
- case Mips::R16: return Mips::R17;
- case Mips::R17: return Mips::R18;
- case Mips::R18: return Mips::R19;
- case Mips::R19: return Mips::R20;
- case Mips::R20: return Mips::R21;
- case Mips::R21: return Mips::R22;
- case Mips::R22: return Mips::R23;
- case Mips::R23: return Mips::R24;
- case Mips::R24: return Mips::R25;
- case Mips::R25: return Mips::R26;
- case Mips::R26: return Mips::R27;
- case Mips::R27: return Mips::R28;
- case Mips::R28: return Mips::R29;
- case Mips::R29: return Mips::R30;
- case Mips::R30: return Mips::R31;
- case Mips::R31: return Mips::R0;
+ case Mips::R0:
+ return Mips::R1;
+ case Mips::R1:
+ return Mips::R2;
+ case Mips::R2:
+ return Mips::R3;
+ case Mips::R3:
+ return Mips::R4;
+ case Mips::R4:
+ return Mips::R5;
+ case Mips::R5:
+ return Mips::R6;
+ case Mips::R6:
+ return Mips::R7;
+ case Mips::R7:
+ return Mips::R8;
+ case Mips::R8:
+ return Mips::R9;
+ case Mips::R9:
+ return Mips::R10;
+ case Mips::R10:
+ return Mips::R11;
+ case Mips::R11:
+ return Mips::R12;
+ case Mips::R12:
+ return Mips::R13;
+ case Mips::R13:
+ return Mips::R14;
+ case Mips::R14:
+ return Mips::R15;
+ case Mips::R15:
+ return Mips::R16;
+ case Mips::R16:
+ return Mips::R17;
+ case Mips::R17:
+ return Mips::R18;
+ case Mips::R18:
+ return Mips::R19;
+ case Mips::R19:
+ return Mips::R20;
+ case Mips::R20:
+ return Mips::R21;
+ case Mips::R21:
+ return Mips::R22;
+ case Mips::R22:
+ return Mips::R23;
+ case Mips::R23:
+ return Mips::R24;
+ case Mips::R24:
+ return Mips::R25;
+ case Mips::R25:
+ return Mips::R26;
+ case Mips::R26:
+ return Mips::R27;
+ case Mips::R27:
+ return Mips::R28;
+ case Mips::R28:
+ return Mips::R29;
+ case Mips::R29:
+ return Mips::R30;
+ case Mips::R30:
+ return Mips::R31;
+ case Mips::R31:
+ return Mips::R0;
case Mips::D0: return Mips::F1;
case Mips::D1: return Mips::F3;
case Mips::D2: return Mips::F5;
@@ -3300,12 +3335,18 @@ static MCRegister nextReg(MCRegister Reg) {
case Mips::D7: return Mips::F15;
case Mips::D8: return Mips::F17;
case Mips::D9: return Mips::F19;
- case Mips::D10: return Mips::F21;
- case Mips::D11: return Mips::F23;
- case Mips::D12: return Mips::F25;
- case Mips::D13: return Mips::F27;
- case Mips::D14: return Mips::F29;
- case Mips::D15: return Mips::F31;
+ case Mips::D10:
+ return Mips::F21;
+ case Mips::D11:
+ return Mips::F23;
+ case Mips::D12:
+ return Mips::F25;
+ case Mips::D13:
+ return Mips::F27;
+ case Mips::D14:
+ return Mips::F29;
+ case Mips::D15:
+ return Mips::F31;
}
}
@@ -3424,8 +3465,8 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
}
if (Lo_32(ImmOp64) == 0) {
- if (TmpReg != Mips::R0 && loadImmediate(ImmOp32, TmpReg, MCRegister(),
- true, false, IDLoc, Out, STI))
+ if (TmpReg != Mips::R0 && loadImmediate(ImmOp32, TmpReg, MCRegister(), true,
+ false, IDLoc, Out, STI))
return true;
TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
return false;
@@ -3675,7 +3716,7 @@ bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
TOut.emitRRI(Mips::SLL, Mips::R0, Mips::R0, 0, IDLoc, STI);
} else
TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::R0, MemOffsetOp, IDLoc,
- STI);
+ STI);
} else {
warnIfNoMacro(IDLoc);
@@ -5567,78 +5608,144 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
// operand.
static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg().id()) {
- case Mips::F0: return Mips::R0;
- case Mips::F1: return Mips::R1;
- case Mips::F2: return Mips::R2;
- case Mips::F3: return Mips::R3;
- case Mips::F4: return Mips::R4;
- case Mips::F5: return Mips::R5;
- case Mips::F6: return Mips::R6;
- case Mips::F7: return Mips::R7;
- case Mips::F8: return Mips::R8;
- case Mips::F9: return Mips::R9;
- case Mips::F10: return Mips::R10;
- case Mips::F11: return Mips::R11;
- case Mips::F12: return Mips::R12;
- case Mips::F13: return Mips::R13;
- case Mips::F14: return Mips::R14;
- case Mips::F15: return Mips::R15;
- case Mips::F16: return Mips::R16;
- case Mips::F17: return Mips::R17;
- case Mips::F18: return Mips::R18;
- case Mips::F19: return Mips::R19;
- case Mips::F20: return Mips::R20;
- case Mips::F21: return Mips::R21;
- case Mips::F22: return Mips::R22;
- case Mips::F23: return Mips::R23;
- case Mips::F24: return Mips::R24;
- case Mips::F25: return Mips::R25;
- case Mips::F26: return Mips::R26;
- case Mips::F27: return Mips::R27;
- case Mips::F28: return Mips::R28;
- case Mips::F29: return Mips::R29;
- case Mips::F30: return Mips::R30;
- case Mips::F31: return Mips::R31;
- default: llvm_unreachable("Unknown register for mttc1 alias!");
+ case Mips::F0:
+ return Mips::R0;
+ case Mips::F1:
+ return Mips::R1;
+ case Mips::F2:
+ return Mips::R2;
+ case Mips::F3:
+ return Mips::R3;
+ case Mips::F4:
+ return Mips::R4;
+ case Mips::F5:
+ return Mips::R5;
+ case Mips::F6:
+ return Mips::R6;
+ case Mips::F7:
+ return Mips::R7;
+ case Mips::F8:
+ return Mips::R8;
+ case Mips::F9:
+ return Mips::R9;
+ case Mips::F10:
+ return Mips::R10;
+ case Mips::F11:
+ return Mips::R11;
+ case Mips::F12:
+ return Mips::R12;
+ case Mips::F13:
+ return Mips::R13;
+ case Mips::F14:
+ return Mips::R14;
+ case Mips::F15:
+ return Mips::R15;
+ case Mips::F16:
+ return Mips::R16;
+ case Mips::F17:
+ return Mips::R17;
+ case Mips::F18:
+ return Mips::R18;
+ case Mips::F19:
+ return Mips::R19;
+ case Mips::F20:
+ return Mips::R20;
+ case Mips::F21:
+ return Mips::R21;
+ case Mips::F22:
+ return Mips::R22;
+ case Mips::F23:
+ return Mips::R23;
+ case Mips::F24:
+ return Mips::R24;
+ case Mips::F25:
+ return Mips::R25;
+ case Mips::F26:
+ return Mips::R26;
+ case Mips::F27:
+ return Mips::R27;
+ case Mips::F28:
+ return Mips::R28;
+ case Mips::F29:
+ return Mips::R29;
+ case Mips::F30:
+ return Mips::R30;
+ case Mips::F31:
+ return Mips::R31;
+ default:
+ llvm_unreachable("Unknown register for mttc1 alias!");
}
}
// Map the coprocessor operand the corresponding gpr register operand.
static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg().id()) {
- case Mips::COP00: return Mips::R0;
- case Mips::COP01: return Mips::R1;
- case Mips::COP02: return Mips::R2;
- case Mips::COP03: return Mips::R3;
- case Mips::COP04: return Mips::R4;
- case Mips::COP05: return Mips::R5;
- case Mips::COP06: return Mips::R6;
- case Mips::COP07: return Mips::R7;
- case Mips::COP08: return Mips::R8;
- case Mips::COP09: return Mips::R9;
- case Mips::COP010: return Mips::R10;
- case Mips::COP011: return Mips::R11;
- case Mips::COP012: return Mips::R12;
- case Mips::COP013: return Mips::R13;
- case Mips::COP014: return Mips::R14;
- case Mips::COP015: return Mips::R15;
- case Mips::COP016: return Mips::R16;
- case Mips::COP017: return Mips::R17;
- case Mips::COP018: return Mips::R18;
- case Mips::COP019: return Mips::R19;
- case Mips::COP020: return Mips::R20;
- case Mips::COP021: return Mips::R21;
- case Mips::COP022: return Mips::R22;
- case Mips::COP023: return Mips::R23;
- case Mips::COP024: return Mips::R24;
- case Mips::COP025: return Mips::R25;
- case Mips::COP026: return Mips::R26;
- case Mips::COP027: return Mips::R27;
- case Mips::COP028: return Mips::R28;
- case Mips::COP029: return Mips::R29;
- case Mips::COP030: return Mips::R30;
- case Mips::COP031: return Mips::R31;
- default: llvm_unreachable("Unknown register for mttc0 alias!");
+ case Mips::COP00:
+ return Mips::R0;
+ case Mips::COP01:
+ return Mips::R1;
+ case Mips::COP02:
+ return Mips::R2;
+ case Mips::COP03:
+ return Mips::R3;
+ case Mips::COP04:
+ return Mips::R4;
+ case Mips::COP05:
+ return Mips::R5;
+ case Mips::COP06:
+ return Mips::R6;
+ case Mips::COP07:
+ return Mips::R7;
+ case Mips::COP08:
+ return Mips::R8;
+ case Mips::COP09:
+ return Mips::R9;
+ case Mips::COP010:
+ return Mips::R10;
+ case Mips::COP011:
+ return Mips::R11;
+ case Mips::COP012:
+ return Mips::R12;
+ case Mips::COP013:
+ return Mips::R13;
+ case Mips::COP014:
+ return Mips::R14;
+ case Mips::COP015:
+ return Mips::R15;
+ case Mips::COP016:
+ return Mips::R16;
+ case Mips::COP017:
+ return Mips::R17;
+ case Mips::COP018:
+ return Mips::R18;
+ case Mips::COP019:
+ return Mips::R19;
+ case Mips::COP020:
+ return Mips::R20;
+ case Mips::COP021:
+ return Mips::R21;
+ case Mips::COP022:
+ return Mips::R22;
+ case Mips::COP023:
+ return Mips::R23;
+ case Mips::COP024:
+ return Mips::R24;
+ case Mips::COP025:
+ return Mips::R25;
+ case Mips::COP026:
+ return Mips::R26;
+ case Mips::COP027:
+ return Mips::R27;
+ case Mips::COP028:
+ return Mips::R28;
+ case Mips::COP029:
+ return Mips::R29;
+ case Mips::COP030:
+ return Mips::R30;
+ case Mips::COP031:
+ return Mips::R31;
+ default:
+ llvm_unreachable("Unknown register for mttc0 alias!");
}
}
@@ -6770,7 +6877,8 @@ ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) {
} else {
MCRegister TmpReg = PrevReg + 1;
while (TmpReg <= Reg) {
- if ((((TmpReg < Mips::R16) || (TmpReg > Mips::R23)) && !isGP64bit()) ||
+ if ((((TmpReg < Mips::R16) || (TmpReg > Mips::R23)) &&
+ !isGP64bit()) ||
(((TmpReg < Mips::R16_64) || (TmpReg > Mips::R23_64)) &&
isGP64bit()))
return Error(E, "invalid register operand");
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 68c8470d87080..bb78a0934276d 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -28,11 +28,11 @@ cl::opt<bool>
namespace {
static constexpr MCPhysReg O32IntRegs[] = {Mips::R4, Mips::R5, Mips::R6,
Mips::R7};
-static constexpr MCPhysReg NABIIntRegs[] = {Mips::R4, Mips::R5, Mips::R6,
- Mips::R7, Mips::R8, Mips::R9,
+static constexpr MCPhysReg NABIIntRegs[] = {Mips::R4, Mips::R5, Mips::R6,
+ Mips::R7, Mips::R8, Mips::R9,
Mips::R10, Mips::R11};
static constexpr MCPhysReg Mips64IntRegs[] = {
- Mips::R4_64, Mips::R5_64, Mips::R6_64, Mips::R7_64,
+ Mips::R4_64, Mips::R5_64, Mips::R6_64, Mips::R7_64,
Mips::R8_64, Mips::R9_64, Mips::R10_64, Mips::R11_64};
struct GPR {
@@ -41,10 +41,11 @@ struct GPR {
};
static constexpr GPR OABITempRegs[] = {
- {Mips::R8, Mips::R8_64}, {Mips::R9, Mips::R9_64}, {Mips::R10, Mips::R10_64},
- {Mips::R11, Mips::R11_64}, {Mips::R12, Mips::R12_64}, {Mips::R13, Mips::R13_64},
- {Mips::R14, Mips::R14_64}, {Mips::R15, Mips::R15_64}, {Mips::R24, Mips::R24_64},
- {Mips::R25, Mips::R25_64},
+ {Mips::R8, Mips::R8_64}, {Mips::R9, Mips::R9_64},
+ {Mips::R10, Mips::R10_64}, {Mips::R11, Mips::R11_64},
+ {Mips::R12, Mips::R12_64}, {Mips::R13, Mips::R13_64},
+ {Mips::R14, Mips::R14_64}, {Mips::R15, Mips::R15_64},
+ {Mips::R24, Mips::R24_64}, {Mips::R25, Mips::R25_64},
};
static constexpr GPR NABITempRegs[] = {
@@ -74,8 +75,9 @@ static constexpr GPR PABITempRegs[] = {
};
static constexpr GPR SavedRegs[] = {
- {Mips::R16, Mips::R16_64}, {Mips::R17, Mips::R17_64}, {Mips::R18, Mips::R18_64},
- {Mips::R19, Mips::R19_64}, {Mips::R20, Mips::R20_64}, {Mips::R21, Mips::R21_64},
+ {Mips::R16, Mips::R16_64}, {Mips::R17, Mips::R17_64},
+ {Mips::R18, Mips::R18_64}, {Mips::R19, Mips::R19_64},
+ {Mips::R20, Mips::R20_64}, {Mips::R21, Mips::R21_64},
{Mips::R22, Mips::R22_64}, {Mips::R23, Mips::R23_64},
};
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 10e0fa5e3e226..ed8d91c717388 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -816,7 +816,7 @@ getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
// Register is encoded in bits 9-5, offset is encoded in bits 4-0.
assert(MI.getOperand(OpNo).isReg() &&
(MI.getOperand(OpNo).getReg() == Mips::R29 ||
- MI.getOperand(OpNo).getReg() == Mips::R29_64) &&
+ MI.getOperand(OpNo).getReg() == Mips::R29_64) &&
"Unexpected base register!");
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
Fixups, STI) >> 2;
@@ -1108,14 +1108,22 @@ MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
switch (Op.getReg().id()) {
default:
llvm_unreachable("Unknown register for movep!");
- case Mips::R0: return 0;
- case Mips::R17: return 1;
- case Mips::R2: return 2;
- case Mips::R3: return 3;
- case Mips::R16: return 4;
- case Mips::R18: return 5;
- case Mips::R19: return 6;
- case Mips::R20: return 7;
+ case Mips::R0:
+ return 0;
+ case Mips::R17:
+ return 1;
+ case Mips::R2:
+ return 2;
+ case Mips::R3:
+ return 3;
+ case Mips::R16:
+ return 4;
+ case Mips::R18:
+ return 5;
+ case Mips::R19:
+ return 6;
+ case Mips::R20:
+ return 7;
}
}
diff --git a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
index 8168decac7e87..691fcb1d39a08 100644
--- a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
+++ b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
@@ -377,11 +377,12 @@ static bool CheckXWPInstr(MachineInstr *MI, bool ReduceToLwp,
// Returns true if the registers Reg1 and Reg2 are consecutive
static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) {
constexpr std::array<unsigned, 31> Registers = {
- {Mips::R1, Mips::R2, Mips::R3, Mips::R4, Mips::R5, Mips::R6, Mips::R7,
- Mips::R8, Mips::R9, Mips::R10, Mips::R11, Mips::R12, Mips::R13, Mips::R14,
- Mips::R15, Mips::R16, Mips::R17, Mips::R18, Mips::R19, Mips::R20, Mips::R21,
- Mips::R22, Mips::R23, Mips::R24, Mips::R25, Mips::R26, Mips::R27, Mips::R28,
- Mips::R29, Mips::R30, Mips::R31}};
+ {Mips::R1, Mips::R2, Mips::R3, Mips::R4, Mips::R5, Mips::R6,
+ Mips::R7, Mips::R8, Mips::R9, Mips::R10, Mips::R11, Mips::R12,
+ Mips::R13, Mips::R14, Mips::R15, Mips::R16, Mips::R17, Mips::R18,
+ Mips::R19, Mips::R20, Mips::R21, Mips::R22, Mips::R23, Mips::R24,
+ Mips::R25, Mips::R26, Mips::R27, Mips::R28, Mips::R29, Mips::R30,
+ Mips::R31}};
for (uint8_t i = 0; i < Registers.size() - 1; i++) {
if (Registers[i] == Reg1) {
@@ -601,8 +602,7 @@ static bool IsMovepDestinationRegPair(unsigned R0, unsigned R1) {
(R0 == Mips::R4 && R1 == Mips::R6) ||
(R0 == Mips::R4 && R1 == Mips::R7) ||
(R0 == Mips::R5 && R1 == Mips::R6) ||
- (R0 == Mips::R5 && R1 == Mips::R7) ||
- (R0 == Mips::R6 && R1 == Mips::R7))
+ (R0 == Mips::R5 && R1 == Mips::R7) || (R0 == Mips::R6 && R1 == Mips::R7))
return true;
return false;
diff --git a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp
index b6bff54c31a6d..66ea18ae13389 100644
--- a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp
+++ b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp
@@ -65,7 +65,8 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
if (hasFP(MF))
BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::R16)
- .addReg(Mips::R29).setMIFlag(MachineInstr::FrameSetup);
+ .addReg(Mips::R29)
+ .setMIFlag(MachineInstr::FrameSetup);
}
void Mips16FrameLowering::emitEpilogue(MachineFunction &MF,
@@ -82,7 +83,7 @@ void Mips16FrameLowering::emitEpilogue(MachineFunction &MF,
if (hasFP(MF))
BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::R29)
- .addReg(Mips::R16);
+ .addReg(Mips::R16);
// Adjust stack.
// assumes stacksize multiple of 8
@@ -106,8 +107,8 @@ bool Mips16FrameLowering::spillCalleeSavedRegisters(
// It's killed at the spill, unless the register is RA and return address
// is taken.
MCRegister Reg = I.getReg();
- bool IsRAAndRetAddrIsTaken = (Reg == Mips::R31)
- && MF->getFrameInfo().isReturnAddressTaken();
+ bool IsRAAndRetAddrIsTaken =
+ (Reg == Mips::R31) && MF->getFrameInfo().isReturnAddressTaken();
if (!IsRAAndRetAddrIsTaken)
MBB.addLiveIn(Reg);
}
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index a2224de2ce3e9..fa5870eb2ee6f 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -282,8 +282,8 @@ void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
MIB3.addReg(Reg1);
MIB3.addReg(Reg2, RegState::Kill);
- MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
- Mips::R29);
+ MachineInstrBuilder MIB4 =
+ BuildMI(MBB, I, DL, get(Mips::Move32R16), Mips::R29);
MIB4.addReg(Reg1, RegState::Kill);
}
@@ -406,8 +406,7 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
BuildMI(MBB, II, DL, get(Mips::AdduRxRyRz16), Reg)
.addReg(SpReg, RegState::Kill)
.addReg(Reg);
- }
- else
+ } else
BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
.addReg(Reg, RegState::Kill);
if (FirstRegSaved || SecondRegSaved) {
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index 03234f3d06b50..361e778e991cf 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -911,21 +911,27 @@ void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
EmitInstrRegReg(STI, MovOpc, ABI.getArgReg(0), Mips::F12);
break;
case FFSig:
- EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12, Mips::F14, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12,
+ Mips::F14, LE);
break;
case FDSig:
EmitInstrRegReg(STI, MovOpc, ABI.getArgReg(0), Mips::F12);
- EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(2), ABI.getArgReg(3), Mips::F14, Mips::F15, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(2), ABI.getArgReg(3), Mips::F14,
+ Mips::F15, LE);
break;
case DSig:
- EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12, Mips::F13, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12,
+ Mips::F13, LE);
break;
case DDSig:
- EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12, Mips::F13, LE);
- EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(2), ABI.getArgReg(3), Mips::F14, Mips::F15, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12,
+ Mips::F13, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(2), ABI.getArgReg(3), Mips::F14,
+ Mips::F15, LE);
break;
case DFSig:
- EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12, Mips::F13, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F12,
+ Mips::F13, LE);
EmitInstrRegReg(STI, MovOpc, ABI.getArgReg(2), Mips::F14);
break;
case NoSig:
@@ -945,14 +951,18 @@ void MipsAsmPrinter::EmitSwapFPIntRetval(
EmitInstrRegReg(STI, MovOpc, ABI.getReturnReg(0), Mips::F0);
break;
case DRet:
- EmitMovFPIntPair(STI, MovOpc, ABI.getReturnReg(0), ABI.getReturnReg(1), Mips::F0, Mips::F1, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getReturnReg(0), ABI.getReturnReg(1),
+ Mips::F0, Mips::F1, LE);
break;
case CFRet:
- EmitMovFPIntPair(STI, MovOpc, ABI.getReturnReg(0), ABI.getReturnReg(1), Mips::F0, Mips::F1, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getReturnReg(0), ABI.getReturnReg(1),
+ Mips::F0, Mips::F1, LE);
break;
case CDRet:
- EmitMovFPIntPair(STI, MovOpc, ABI.getReturnReg(0), ABI.getReturnReg(1), Mips::F0, Mips::F1, LE);
- EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F2, Mips::F3, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getReturnReg(0), ABI.getReturnReg(1),
+ Mips::F0, Mips::F1, LE);
+ EmitMovFPIntPair(STI, MovOpc, ABI.getArgReg(0), ABI.getArgReg(1), Mips::F2,
+ Mips::F3, LE);
break;
case NoFPRet:
break;
@@ -1196,25 +1206,23 @@ void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
// Emit "B .tmpN" instruction, which jumps over the nop sled to the actual
// start of function
const MCExpr *TargetExpr = MCSymbolRefExpr::create(Target, OutContext);
- EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)
- .addReg(Mips::R0)
- .addReg(Mips::R0)
- .addExpr(TargetExpr));
+ EmitToStreamer(
+ *OutStreamer,
+ MCInstBuilder(Mips::BEQ).addReg(Mips::R0).addReg(Mips::R0).addExpr(
+ TargetExpr));
for (int8_t I = 0; I < NoopsInSledCount; I++)
- EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)
- .addReg(Mips::R0)
- .addReg(Mips::R0)
- .addImm(0));
+ EmitToStreamer(
+ *OutStreamer,
+ MCInstBuilder(Mips::SLL).addReg(Mips::R0).addReg(Mips::R0).addImm(0));
OutStreamer->emitLabel(Target);
if (!Subtarget->isGP64bit()) {
- EmitToStreamer(*OutStreamer,
- MCInstBuilder(Mips::ADDiu)
- .addReg(Mips::R25)
- .addReg(Mips::R25)
- .addImm(0x34));
+ EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::ADDiu)
+ .addReg(Mips::R25)
+ .addReg(Mips::R25)
+ .addImm(0x34));
}
recordSled(CurSled, MI, Kind, 2);
diff --git a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
index bd8772e7cf12a..f4f480829d112 100644
--- a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
+++ b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
@@ -521,7 +521,8 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
bool hasDelaySlot = buildProperJumpMI(BalTgtMBB, Pos, DL);
if (!hasDelaySlot) {
- BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::R29)
+ BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu),
+ Mips::R29)
.addReg(Mips::R29)
.addImm(8);
}
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp
index 1ff75d20856f1..d678d7fe4dca4 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -475,8 +475,8 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
if (IsCalleeGlobalPIC) {
MIRBuilder.buildCopy(
- Register(Mips::R28),
- MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel(MF));
+ Register(Mips::R28),
+ MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel(MF));
MIB.addUse(Mips::R28, RegState::Implicit);
}
MIRBuilder.insertInstr(MIB);
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 30319a44d2728..0b8bfda3aedf9 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -1882,7 +1882,8 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
}
BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
- .addReg(Mips::R0).addImm(MaskImm);
+ .addReg(Mips::R0)
+ .addImm(MaskImm);
BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
.addReg(MaskUpper).addReg(ShiftAmt);
BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::R0).addReg(Mask);
@@ -2070,7 +2071,8 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
}
BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
- .addReg(Mips::R0).addImm(MaskImm);
+ .addReg(Mips::R0)
+ .addImm(MaskImm);
BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
.addReg(MaskUpper).addReg(ShiftAmt);
BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::R0).addReg(Mask);
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index 40660862605b5..6ec5840490bd0 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -62,10 +62,7 @@ bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
}
MCInst MipsInstrInfo::getNop() const {
- return MCInstBuilder(Mips::SLL)
- .addReg(Mips::R0)
- .addReg(Mips::R0)
- .addImm(0);
+ return MCInstBuilder(Mips::SLL).addReg(Mips::R0).addReg(Mips::R0).addImm(0);
}
/// insertNoop - If data hazard condition is found insert the target nop
@@ -86,9 +83,7 @@ MachineInstrBuilder MipsInstrInfo::insertNop(MachineBasicBlock &MBB,
Subtarget.hasMips32r6() ? Mips::SLL_MMR6 : Mips::SLL_MM;
const unsigned Opc =
Subtarget.inMicroMipsMode() ? MMOpc : (unsigned)Mips::SLL;
- return BuildMI(MBB, MI, DL, get(Opc), Mips::R0)
- .addReg(Mips::R0)
- .addImm(0);
+ return BuildMI(MBB, MI, DL, get(Opc), Mips::R0).addReg(Mips::R0).addImm(0);
}
MachineMemOperand *
@@ -503,9 +498,8 @@ unsigned MipsInstrInfo::getEquivalentCompactForm(
(I->getOperand(0).isReg() &&
(I->getOperand(0).getReg() == Mips::R0 ||
I->getOperand(0).getReg() == Mips::R0_64)) &&
- (I->getOperand(1).isReg() &&
- (I->getOperand(1).getReg() == Mips::R0 ||
- I->getOperand(1).getReg() == Mips::R0_64)))
+ (I->getOperand(1).isReg() && (I->getOperand(1).getReg() == Mips::R0 ||
+ I->getOperand(1).getReg() == Mips::R0_64)))
return 0;
if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index 774584ab7fe2d..ca57663d7539c 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -39,7 +39,8 @@ using namespace llvm;
#include "MipsGenRegisterInfo.inc"
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &STI)
- : MipsGenRegisterInfo(Mips::R31), ArePtrs64bit(STI.getABI().ArePtrs64bit()) {
+ : MipsGenRegisterInfo(Mips::R31),
+ ArePtrs64bit(STI.getABI().ArePtrs64bit()) {
MIPS_MC::initLLVMToCVRegMapping(this);
}
@@ -162,13 +163,11 @@ const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
BitVector MipsRegisterInfo::
getReservedRegs(const MachineFunction &MF) const {
- static const MCPhysReg ReservedGPR32[] = {
- Mips::R0, Mips::R26, Mips::R27, Mips::R29
- };
+ static const MCPhysReg ReservedGPR32[] = {Mips::R0, Mips::R26, Mips::R27,
+ Mips::R29};
- static const MCPhysReg ReservedGPR64[] = {
- Mips::R0_64, Mips::R26_64, Mips::R27_64, Mips::R29_64
- };
+ static const MCPhysReg ReservedGPR64[] = {Mips::R0_64, Mips::R26_64,
+ Mips::R27_64, Mips::R29_64};
BitVector Reserved(getNumRegs());
const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
@@ -299,8 +298,8 @@ getFrameRegister(const MachineFunction &MF) const {
if (Subtarget.inMips16Mode())
return TFI->hasFP(MF) ? Mips::R16 : Mips::R29;
else
- return TFI->hasFP(MF) ? (IsN64 ? Mips::R30_64 : Mips::R30) :
- (IsN64 ? Mips::R29_64 : Mips::R29);
+ return TFI->hasFP(MF) ? (IsN64 ? Mips::R30_64 : Mips::R30)
+ : (IsN64 ? Mips::R29_64 : Mips::R29);
}
bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
index 7a932043996d9..f0587a035cd7f 100644
--- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -300,8 +300,8 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
// For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as
// implicit operand, so other passes (like ShrinkWrapping) are aware that
// stack is used.
- if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
- && I->getOperand(3).getReg() == Mips::R29) {
+ if (I->getNumOperands() == 4 && I->getOperand(3).isReg() &&
+ I->getOperand(3).getReg() == Mips::R29) {
Register DstReg = I->getOperand(0).getReg();
Register LoReg = I->getOperand(1).getReg();
Register HiReg = I->getOperand(2).getReg();
@@ -357,8 +357,8 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
// For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as
// implicit operand, so other passes (like ShrinkWrapping) are aware that
// stack is used.
- if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
- && I->getOperand(3).getReg() == Mips::R29) {
+ if (I->getNumOperands() == 4 && I->getOperand(3).isReg() &&
+ I->getOperand(3).getReg() == Mips::R29) {
Register DstReg = I->getOperand(0).getReg();
Register SrcReg = Op1.getReg();
unsigned N = Op2.getImm();
@@ -746,8 +746,8 @@ bool MipsSEFrameLowering::spillCalleeSavedRegisters(
// It's killed at the spill, unless the register is RA and return address
// is taken.
MCRegister Reg = I.getReg();
- bool IsRAAndRetAddrIsTaken = (Reg == Mips::R31 || Reg == Mips::R31_64)
- && MF->getFrameInfo().isReturnAddressTaken();
+ bool IsRAAndRetAddrIsTaken = (Reg == Mips::R31 || Reg == Mips::R31_64) &&
+ MF->getFrameInfo().isReturnAddressTaken();
if (!IsRAAndRetAddrIsTaken)
MBB.addLiveIn(Reg);
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index 3613e74729a67..6105d10d0e932 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -80,15 +80,13 @@ bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
// Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
if ((MI.getOpcode() == Mips::ADDiu) &&
- (MI.getOperand(1).getReg() == Mips::R0) &&
- (MI.getOperand(2).isImm()) &&
+ (MI.getOperand(1).getReg() == Mips::R0) && (MI.getOperand(2).isImm()) &&
(MI.getOperand(2).getImm() == 0)) {
DstReg = MI.getOperand(0).getReg();
ZeroReg = Mips::R0;
} else if ((MI.getOpcode() == Mips::DADDiu) &&
(MI.getOperand(1).getReg() == Mips::R0_64) &&
- (MI.getOperand(2).isImm()) &&
- (MI.getOperand(2).getImm() == 0)) {
+ (MI.getOperand(2).isImm()) && (MI.getOperand(2).getImm() == 0)) {
DstReg = MI.getOperand(0).getReg();
ZeroReg = Mips::R0_64;
}
@@ -796,10 +794,9 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
if (Inst->Opc == Mips::LUi64)
RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
else
- RegOpnd =
- CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
- CurDAG->getRegister(Mips::R0_64, MVT::i64),
- ImmOpnd);
+ RegOpnd = CurDAG->getMachineNode(
+ Inst->Opc, DL, MVT::i64, CurDAG->getRegister(Mips::R0_64, MVT::i64),
+ ImmOpnd);
// The remaining instructions in the sequence are handled here.
for (++Inst; Inst != Seq.end(); ++Inst) {
@@ -1123,8 +1120,8 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
- SDValue ZeroVal = CurDAG->getRegister(
- Is32BitSplat ? Mips::R0 : Mips::R0_64, SplatMVT);
+ SDValue ZeroVal =
+ CurDAG->getRegister(Is32BitSplat ? Mips::R0 : Mips::R0_64, SplatMVT);
const unsigned FILLOp =
SplatBitSize == 16
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
index e0dc415ba602c..4da70c6c24713 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -3285,13 +3285,15 @@ MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
// Fill $FBB.
Register VR2 = RegInfo.createVirtualRegister(RC);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
- .addReg(Mips::R0).addImm(0);
+ .addReg(Mips::R0)
+ .addImm(0);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
// Fill $TBB.
Register VR1 = RegInfo.createVirtualRegister(RC);
BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
- .addReg(Mips::R0).addImm(1);
+ .addReg(Mips::R0)
+ .addImm(1);
// Insert phi function to $Sink.
BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
@@ -3354,13 +3356,15 @@ MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
// Fill $FBB.
Register RD1 = RegInfo.createVirtualRegister(RC);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
- .addReg(Mips::R0).addImm(0);
+ .addReg(Mips::R0)
+ .addImm(0);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
// Fill $TBB.
Register RD2 = RegInfo.createVirtualRegister(RC);
BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
- .addReg(Mips::R0).addImm(1);
+ .addReg(Mips::R0)
+ .addImm(1);
// Insert phi function to $Sink.
BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
diff --git a/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp b/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
index 8448dbd9779b3..65a55abbb9976 100644
--- a/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
@@ -5,8 +5,8 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
-#include "../Error.h"
#include "../Target.h"
+#include "../Error.h"
#include "MCTargetDesc/MipsABIInfo.h"
#include "MCTargetDesc/MipsBaseInfo.h"
#include "Mips.h"
diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp
index 645e5e68fe601..1dcab6ca39154 100644
--- a/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp
@@ -53,10 +53,9 @@ TEST_F(MipsBenchmarkResultTest, WriteToAndReadFromDisk) {
Benchmark ToDisk;
- ToDisk.Key.Instructions.push_back(MCInstBuilder(Mips::XOR)
- .addReg(Mips::R8)
- .addReg(Mips::R9)
- .addReg(Mips::R10));
+ ToDisk.Key.Instructions.push_back(
+ MCInstBuilder(Mips::XOR).addReg(Mips::R8).addReg(Mips::R9).addReg(
+ Mips::R10));
ToDisk.Key.Config = "config";
ToDisk.Key.RegisterInitialValues = {
RegisterValue{Mips::R9, APInt(8, "123", 10)},
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