[llvm] [SelectionDAG] Make `AND`/`OR` demanded-bit simplification symmetric (PR #230700)
Alan Li via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 10 19:43:35 PDT 2026
https://github.com/lialan updated https://github.com/llvm/llvm-project/pull/230700
>From 7e4deb5a8fcc5e4813d3c56e064b3b155e32c4fb Mon Sep 17 00:00:00 2001
From: Alan Li <me at alanli.org>
Date: Fri, 9 Oct 2026 13:43:16 -0700
Subject: [PATCH 1/4] fix(SelectionDAG): simplify commuted demanded bits
AND/OR demanded-bit simplification uses RHS known bits to simplify the
LHS, but does not retry the RHS using LHS known bits, making
optimizations depend on operand order.
Retry the RHS when the LHS reduces its demanded bits. Add AArch64
and AMDGPU codegen coverage.
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 18 +
llvm/test/CodeGen/AArch64/andorxor.ll | 78 +++
llvm/test/CodeGen/AArch64/reduce-and.ll | 18 +-
.../AArch64/vecreduce-and-legalization.ll | 6 +-
llvm/test/CodeGen/AMDGPU/and.ll | 44 ++
.../AMDGPU/float-to-arbitrary-fp-fp8-hw.ll | 191 +++---
.../CodeGen/AMDGPU/float-to-arbitrary-fp.ll | 15 +-
llvm/test/CodeGen/AMDGPU/or.ll | 46 ++
llvm/test/CodeGen/AMDGPU/permute.ll | 16 +-
.../test/CodeGen/AMDGPU/setcc-multiple-use.ll | 7 +-
.../CodeGen/LoongArch/ir-instruction/and.ll | 2 +-
llvm/test/CodeGen/RISCV/and-add-lsr.ll | 22 +-
llvm/test/CodeGen/RISCV/pr148084.ll | 16 +-
.../CodeGen/RISCV/signed-truncation-check.ll | 2 +-
llvm/test/CodeGen/X86/apx/ccmp.ll | 22 +-
llvm/test/CodeGen/X86/atomic-rm-bit-test.ll | 256 ++++-----
llvm/test/CodeGen/X86/avx512-cmp.ll | 2 +-
llvm/test/CodeGen/X86/bswap_tree2.ll | 2 -
.../test/CodeGen/X86/float-to-arbitrary-fp.ll | 544 +++++++++---------
llvm/test/CodeGen/X86/movmsk-cmp.ll | 16 +-
llvm/test/CodeGen/X86/pr34137.ll | 6 +-
llvm/test/CodeGen/X86/setcc-logic.ll | 19 +-
llvm/test/CodeGen/X86/test-shrink-bug.ll | 2 +-
llvm/test/CodeGen/X86/vector-bo-select.ll | 23 +-
24 files changed, 752 insertions(+), 621 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 2bf2eeb828825..1c7af4e103673 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1660,6 +1660,14 @@ bool TargetLowering::SimplifyDemandedBits(
Known2, TLO, Depth + 1))
return true;
+ // Retry the RHS with the demand reduced by the unchanged LHS.
+ APInt RHSDemandedBits = ~Known2.Zero & DemandedBits;
+ if (RHSDemandedBits != DemandedBits) {
+ if (SimplifyDemandedBits(Op1, RHSDemandedBits, DemandedElts, Known, TLO,
+ Depth + 1))
+ return true;
+ }
+
// If all of the demanded bits are known one on one side, return the other.
// These bits cannot contribute to the result of the 'and'.
if (DemandedBits.isSubsetOf(Known2.Zero | Known.One))
@@ -1709,6 +1717,16 @@ bool TargetLowering::SimplifyDemandedBits(
return true;
}
+ // Retry the RHS with the demand reduced by the unchanged LHS.
+ APInt RHSDemandedBits = ~Known2.One & DemandedBits;
+ if (RHSDemandedBits != DemandedBits) {
+ if (SimplifyDemandedBits(Op1, RHSDemandedBits, DemandedElts, Known, TLO,
+ Depth + 1)) {
+ Op->dropFlags(SDNodeFlags::Disjoint);
+ return true;
+ }
+ }
+
// If all of the demanded bits are known zero on one side, return the other.
// These bits cannot contribute to the result of the 'or'.
if (DemandedBits.isSubsetOf(Known2.One | Known.Zero))
diff --git a/llvm/test/CodeGen/AArch64/andorxor.ll b/llvm/test/CodeGen/AArch64/andorxor.ll
index adf560cc97362..f6c2b57266d66 100644
--- a/llvm/test/CodeGen/AArch64/andorxor.ll
+++ b/llvm/test/CodeGen/AArch64/andorxor.ll
@@ -1474,3 +1474,81 @@ entry:
%s = xor <4 x i128> %d, %e
ret <4 x i128> %s
}
+
+; Propagate demanded bits from the LHS to simplify the RHS.
+
+define i32 @and_hidden_bits_rhs(i32 %x, i32 %y) {
+; CHECK-SD-LABEL: and_hidden_bits_rhs:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and w0, w0, w1, lsr #24
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: and_hidden_bits_rhs:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: orr w8, w0, #0xff00
+; CHECK-GI-NEXT: and w0, w8, w1, lsr #24
+; CHECK-GI-NEXT: ret
+ %bounded = lshr i32 %y, 24
+ %inner = or i32 %x, 65280
+ %result = and i32 %bounded, %inner
+ ret i32 %result
+}
+
+define i32 @or_hidden_bits_rhs(i32 %x, i32 %y) {
+; CHECK-SD-LABEL: or_hidden_bits_rhs:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: orn w0, w0, w1, lsr #24
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: or_hidden_bits_rhs:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w0, #0xff
+; CHECK-GI-NEXT: orn w0, w8, w1, lsr #24
+; CHECK-GI-NEXT: ret
+ %shift = lshr i32 %y, 24
+ %bounded = xor i32 %shift, -1
+ %inner = and i32 %x, 255
+ %result = or i32 %bounded, %inner
+ ret i32 %result
+}
+
+define <4 x i32> @and_hidden_bits_rhs_v4i32(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-SD-LABEL: and_hidden_bits_rhs_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushr v1.4s, v1.4s, #24
+; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: and_hidden_bits_rhs_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v2.2d, #0x00ff000000ff00
+; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #24
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %bounded = lshr <4 x i32> %y, <i32 24, i32 24, i32 24, i32 24>
+ %inner = or <4 x i32> %x, <i32 65280, i32 65280, i32 65280, i32 65280>
+ %result = and <4 x i32> %bounded, %inner
+ ret <4 x i32> %result
+}
+
+define <4 x i32> @or_hidden_bits_rhs_v4i32(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-SD-LABEL: or_hidden_bits_rhs_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushr v1.4s, v1.4s, #24
+; CHECK-SD-NEXT: orn v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: or_hidden_bits_rhs_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v2.2d, #0x0000ff000000ff
+; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #24
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: orn v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %shift = lshr <4 x i32> %y, <i32 24, i32 24, i32 24, i32 24>
+ %bounded = xor <4 x i32> %shift, <i32 -1, i32 -1, i32 -1, i32 -1>
+ %inner = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
+ %result = or <4 x i32> %bounded, %inner
+ ret <4 x i32> %result
+}
diff --git a/llvm/test/CodeGen/AArch64/reduce-and.ll b/llvm/test/CodeGen/AArch64/reduce-and.ll
index c6229007bec3c..6ec166311dc19 100644
--- a/llvm/test/CodeGen/AArch64/reduce-and.ll
+++ b/llvm/test/CodeGen/AArch64/reduce-and.ll
@@ -252,9 +252,9 @@ define i8 @test_redand_v8i8(<8 x i8> %a) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmov x8, d0
; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
-; CHECK-SD-NEXT: and x8, x8, x8, lsr #16
-; CHECK-SD-NEXT: lsr x9, x8, #8
-; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: and w8, w8, w9
+; CHECK-SD-NEXT: and w0, w8, w8, lsr #8
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_redand_v8i8:
@@ -287,9 +287,9 @@ define i8 @test_redand_v16i8(<16 x i8> %a) {
; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x8, d0
; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
-; CHECK-SD-NEXT: and x8, x8, x8, lsr #16
-; CHECK-SD-NEXT: lsr x9, x8, #8
-; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: and w8, w8, w9
+; CHECK-SD-NEXT: and w0, w8, w8, lsr #8
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_redand_v16i8:
@@ -324,9 +324,9 @@ define i8 @test_redand_v32i8(<32 x i8> %a) {
; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x8, d0
; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
-; CHECK-SD-NEXT: and x8, x8, x8, lsr #16
-; CHECK-SD-NEXT: lsr x9, x8, #8
-; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: and w8, w8, w9
+; CHECK-SD-NEXT: and w0, w8, w8, lsr #8
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_redand_v32i8:
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
index 7fbe6e55cc968..159abaa707eab 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
@@ -107,9 +107,9 @@ define i8 @test_v9i8(<9 x i8> %a) nounwind {
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
-; CHECK-NEXT: and x8, x8, x8, lsr #16
-; CHECK-NEXT: lsr x9, x8, #8
-; CHECK-NEXT: and w0, w8, w9
+; CHECK-NEXT: lsr x9, x8, #16
+; CHECK-NEXT: and w8, w8, w9
+; CHECK-NEXT: and w0, w8, w8, lsr #8
; CHECK-NEXT: ret
%b = call i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)
ret i8 %b
diff --git a/llvm/test/CodeGen/AMDGPU/and.ll b/llvm/test/CodeGen/AMDGPU/and.ll
index 545b75a47ee9d..8cd270f6f7739 100644
--- a/llvm/test/CodeGen/AMDGPU/and.ll
+++ b/llvm/test/CodeGen/AMDGPU/and.ll
@@ -1621,4 +1621,48 @@ define amdgpu_kernel void @s_and_inline_high_imm_f32_neg_4.0_i64(ptr addrspace(1
store i64 %and, ptr addrspace(1) %out, align 8
ret void
}
+
+; Propagate demanded bits from the LHS to simplify the RHS.
+
+define i32 @s_and_hidden_bits_rhs(i32 inreg %x, i32 inreg %y) {
+; GFX6-LABEL: s_and_hidden_bits_rhs:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_lshr_b32 s4, s17, 24
+; GFX6-NEXT: s_and_b32 s4, s4, s16
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: s_and_hidden_bits_rhs:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_lshr_b32 s4, s17, 24
+; GFX8-NEXT: s_and_b32 s4, s4, s16
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+ %bounded = lshr i32 %y, 24
+ %inner = or i32 %x, 65280
+ %result = and i32 %bounded, %inner
+ ret i32 %result
+}
+
+define i32 @v_and_hidden_bits_rhs(i32 %x, i32 %y) {
+; GFX6-LABEL: v_and_hidden_bits_rhs:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; GFX6-NEXT: v_and_b32_e32 v0, v1, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_and_hidden_bits_rhs:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+ %bounded = lshr i32 %y, 24
+ %inner = or i32 %x, 65280
+ %result = and i32 %bounded, %inner
+ ret i32 %result
+}
+
attributes #0 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
index a6e5d0ebd943e..0298b67ee3c71 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
@@ -1155,8 +1155,8 @@ define i8 @to_fp8_f64(double %x) {
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
; GFX950-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[6:7]
-; GFX950-NEXT: v_and_b32_e32 v14, 0xfffff, v11
-; GFX950-NEXT: v_or_b32_e32 v13, 0x100000, v14
+; GFX950-NEXT: v_and_b32_e32 v12, 0xfffff, v11
+; GFX950-NEXT: v_or_b32_e32 v13, 0x100000, v12
; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
; GFX950-NEXT: v_cndmask_b32_e32 v6, 63, v6, vcc
; GFX950-NEXT: v_cmp_lt_u64_e32 vcc, 1, v[6:7]
@@ -1170,11 +1170,11 @@ define i8 @to_fp8_f64(double %x) {
; GFX950-NEXT: v_and_b32_e32 v8, v10, v8
; GFX950-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
; GFX950-NEXT: v_lshrrev_b64 v[8:9], v6, v[12:13]
-; GFX950-NEXT: v_and_b32_e32 v16, 1, v8
-; GFX950-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; GFX950-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX950-NEXT: v_and_b32_e32 v15, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_or_b32_e32 v14, v14, v15
; GFX950-NEXT: v_lshrrev_b64 v[12:13], v4, v[12:13]
-; GFX950-NEXT: v_and_b32_e32 v4, v12, v15
+; GFX950-NEXT: v_and_b32_e32 v4, v12, v14
; GFX950-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GFX950-NEXT: s_movk_i32 s1, 0x80
; GFX950-NEXT: s_mov_b32 s0, 0
@@ -1188,13 +1188,12 @@ define i8 @to_fp8_f64(double %x) {
; GFX950-NEXT: v_or3_b32 v9, v8, v6, v4
; GFX950-NEXT: v_mov_b32_e32 v6, v10
; GFX950-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX950-NEXT: v_bfe_u32 v6, v14, 18, 1
-; GFX950-NEXT: v_mov_b32_e32 v7, v5
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX950-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX950-NEXT: v_lshrrev_b32_e32 v6, 17, v11
-; GFX950-NEXT: v_and_b32_e32 v4, v6, v4
; GFX950-NEXT: v_bfe_u32 v6, v11, 18, 2
+; GFX950-NEXT: v_lshrrev_b32_e32 v7, 17, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_and_or_b32 v4, v6, 1, v4
+; GFX950-NEXT: v_and_b32_e32 v4, v7, v4
+; GFX950-NEXT: v_mov_b32_e32 v7, v5
; GFX950-NEXT: v_lshl_add_u64 v[4:5], v[6:7], 0, v[4:5]
; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[4:5]
; GFX950-NEXT: v_mov_b32_e32 v7, s0
@@ -1239,43 +1238,43 @@ define i8 @to_fp8_f64(double %x) {
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
; GFX1200-NEXT: v_frexp_mant_f64_e32 v[2:3], v[0:1]
+; GFX1200-NEXT: s_mov_b32 s0, 0xfffff
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX1200-NEXT: v_sub_co_u32 v4, vcc_lo, 37, v12
-; GFX1200-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_and_b32 v9, 0xfffff, v3
+; GFX1200-NEXT: v_bfe_u32 v10, v3, 18, 2
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_and_or_b32 v9, v3, s0, 0x100000
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_sub_co_ci_u32_e64 v5, null, 0, v13, vcc_lo
-; GFX1200-NEXT: v_lshrrev_b32_e32 v15, 17, v3
-; GFX1200-NEXT: v_bfe_u32 v17, v3, 18, 2
-; GFX1200-NEXT: v_bfe_u32 v11, v9, 18, 1
-; GFX1200-NEXT: v_cmp_gt_u64_e32 vcc_lo, 63, v[4:5]
-; GFX1200-NEXT: v_or_b32_e32 v9, 0x100000, v9
; GFX1200-NEXT: v_and_b32_e32 v7, 0x1ffff, v3
+; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 17, v3
+; GFX1200-NEXT: v_mov_b32_e32 v6, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_cmp_gt_u64_e32 vcc_lo, 63, v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_dual_cndmask_b32 v5, 0, v5 :: v_dual_cndmask_b32 v4, 63, v4
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_u64_e32 vcc_lo, 1, v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v8, 1, v4, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_add_nc_u32_e32 v14, -1, v8
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX1200-NEXT: v_lshlrev_b64_e64 v[6:7], v14, 1
-; GFX1200-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_add_co_u32 v11, vcc_lo, v6, -1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_and_or_b32 v11, v10, 1, v11
+; GFX1200-NEXT: v_add_co_u32 v15, vcc_lo, v6, -1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_add_co_ci_u32_e64 v16, null, -1, v7, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b32_e32 v10, v15, v10
-; GFX1200-NEXT: v_mov_b32_e32 v8, v2
-; GFX1200-NEXT: v_and_b32_e32 v2, v2, v11
+; GFX1200-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_and_b32 v11, v3, v11
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b32_e32 v2, v2, v15
; GFX1200-NEXT: v_and_b32_e32 v3, v9, v16
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_add_co_u32 v10, s0, v17, v10
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_add_co_u32 v10, s0, v10, v11
; GFX1200-NEXT: v_lshrrev_b64 v[6:7], v4, v[8:9]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
@@ -1349,67 +1348,66 @@ define i8 @to_fp8_f64(double %x) {
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
; GFX1250-NEXT: v_frexp_mant_f64_e32 v[4:5], v[0:1]
-; GFX1250-NEXT: s_mov_b32 s0, 0
-; GFX1250-NEXT: s_mov_b32 s1, 0xfffff
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_ashrrev_i32 v3, 31, v2 :: v_dual_bitop2_b32 v15, s1, v5 bitop3:0x40
+; GFX1250-NEXT: s_mov_b32 s0, 0xfffff
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250-NEXT: v_and_or_b32 v11, v5, s0, 0x100000
+; GFX1250-NEXT: s_mov_b32 s0, 0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_mov_b32_e32 v10, v4
; GFX1250-NEXT: v_sub_nc_u64_e32 v[6:7], 37, v[2:3]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_or_b32_e32 v11, 0x100000, v15
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cmp_gt_u64_e32 vcc_lo, 63, v[6:7]
; GFX1250-NEXT: v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 63, v6
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cmp_lt_u64_e32 vcc_lo, 1, v[6:7]
; GFX1250-NEXT: v_cndmask_b32_e32 v8, 1, v6, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_add_nc_u32_e32 v14, -1, v8
; GFX1250-NEXT: v_lshrrev_b64 v[12:13], v6, v[10:11]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_lshlrev_b64_e64 v[8:9], v14, 1
-; GFX1250-NEXT: v_and_b32_e32 v16, 1, v12
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_and_b32_e32 v15, 1, v12
; GFX1250-NEXT: v_add_nc_u64_e32 v[8:9], -1, v[8:9]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_and_b32_e32 v9, v11, v9
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_and_b32_e32 v8, v4, v8
; GFX1250-NEXT: v_lshrrev_b64 v[10:11], v14, v[10:11]
; GFX1250-NEXT: v_lshrrev_b32_e32 v14, 17, v5
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[8:9]
+; GFX1250-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1250-NEXT: v_or_b32_e32 v11, v8, v15
; GFX1250-NEXT: v_mov_b32_e32 v8, v4
-; GFX1250-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_or_b32_e32 v4, v17, v16
-; GFX1250-NEXT: v_and_b32_e32 v4, v10, v4
+; GFX1250-NEXT: v_bfe_u32 v4, v5, 18, 2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_and_b32_e32 v10, v10, v11
; GFX1250-NEXT: v_and_b32_e32 v9, 0x1ffff, v5
-; GFX1250-NEXT: v_bfe_u32 v10, v15, 18, 1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[8:9]
; GFX1250-NEXT: v_mov_b32_e32 v9, 0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_mov_b32_e32 v5, v9
; GFX1250-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
-; GFX1250-NEXT: v_mov_b32_e32 v7, v9
-; GFX1250-NEXT: v_bfe_u32 v6, v5, 18, 2
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_cndmask_b32 v8, 0, v4, vcc_lo :: v_dual_bitop2_b32 v10, v11, v10 bitop3:0x54
-; GFX1250-NEXT: v_add_nc_u64_e32 v[4:5], v[12:13], v[8:9]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e32 v8, 0, v10, vcc_lo
+; GFX1250-NEXT: v_and_or_b32 v10, v4, 1, v11
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_add_nc_u64_e32 v[6:7], v[12:13], v[8:9]
; GFX1250-NEXT: v_dual_lshrrev_b32 v10, 24, v1 :: v_dual_bitop2_b32 v8, v14, v10 bitop3:0x40
-; GFX1250-NEXT: v_add_nc_u64_e32 v[6:7], v[6:7], v[8:9]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_add_nc_u64_e32 v[4:5], v[4:5], v[8:9]
; GFX1250-NEXT: v_mov_b32_e32 v9, s0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_cmp_lt_i64_e64 s0, 3, v[4:5]
-; GFX1250-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[6:7]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_cndmask_b32_e64 v4, v4, 0, s0
+; GFX1250-NEXT: v_cmp_lt_i64_e64 s0, 3, v[6:7]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[4:5]
+; GFX1250-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
; GFX1250-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1250-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
-; GFX1250-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], v[2:3], v[8:9]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[6:7]
+; GFX1250-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[4:5]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], 14, v[2:3]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_lshlrev_b64_e32 v[8:9], 2, v[2:3]
; GFX1250-NEXT: v_cndmask_b32_e64 v9, 0, 4, s0
; GFX1250-NEXT: v_cmp_eq_u64_e64 s0, 30, v[2:3]
@@ -1418,17 +1416,17 @@ define i8 @to_fp8_f64(double %x) {
; GFX1250-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: s_or_b32 vcc_lo, s1, s0
-; GFX1250-NEXT: v_and_b32_e32 v5, 0x80, v10
-; GFX1250-NEXT: v_or_b32_e32 v8, v8, v5
-; GFX1250-NEXT: v_or3_b32 v4, v5, v9, v4
-; GFX1250-NEXT: v_or_b32_e32 v3, 0x7c, v5
+; GFX1250-NEXT: v_and_b32_e32 v7, 0x80, v10
+; GFX1250-NEXT: v_or_b32_e32 v8, v8, v7
+; GFX1250-NEXT: v_or3_b32 v6, v7, v9, v6
+; GFX1250-NEXT: v_or_b32_e32 v3, 0x7c, v7
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_or_b32_e32 v8, v8, v6
-; GFX1250-NEXT: v_cndmask_b32_e64 v2, v8, v4, s2
+; GFX1250-NEXT: v_or_b32_e32 v8, v8, v4
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, v8, v6, s2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX1250-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
-; GFX1250-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX1250-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
@@ -1445,44 +1443,42 @@ define i8 @to_fp8_f64(double %x) {
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
; GFX1310-NEXT: v_frexp_mant_f64_e32 v[2:3], v[0:1]
+; GFX1310-NEXT: s_mov_b32 s0, 0xfffff
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX1310-NEXT: v_sub_co_u32 v4, vcc_lo, 37, v12
-; GFX1310-NEXT: v_bfe_u32 v17, v3, 18, 2
-; GFX1310-NEXT: v_and_b32_e32 v7, 0x1ffff, v3
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_and_or_b32 v9, v3, s0, 0x100000
+; GFX1310-NEXT: v_bfe_u32 v10, v3, 18, 2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1310-NEXT: v_sub_co_ci_u32_e64 v5, null, 0, v13, vcc_lo
-; GFX1310-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_lshrrev_b32 v15, 17, v3
+; GFX1310-NEXT: s_mov_b32 s0, 0x1ffff
+; GFX1310-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_bitop2_b32 v7, s0, v3 bitop3:0x40
; GFX1310-NEXT: v_cmp_gt_u64_e32 vcc_lo, 63, v[4:5]
; GFX1310-NEXT: v_dual_cndmask_b32 v5, 0, v5 :: v_dual_cndmask_b32 v4, 63, v4
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_lt_u64_e32 vcc_lo, 1, v[4:5]
-; GFX1310-NEXT: s_mov_b32 s0, 0xfffff
-; GFX1310-NEXT: v_dual_cndmask_b32 v8, 1, v4, vcc_lo :: v_dual_bitop2_b32 v9, s0, v3 bitop3:0x40
+; GFX1310-NEXT: v_cndmask_b32_e32 v8, 1, v4, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_add_nc_u32_e32 v14, -1, v8
-; GFX1310-NEXT: v_bfe_u32 v11, v9, 18, 1
-; GFX1310-NEXT: s_mov_b32 s0, 0x100000
-; GFX1310-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_bitop2_b32 v9, s0, v9 bitop3:0x54
-; GFX1310-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1310-NEXT: v_dual_add_nc_u32 v14, -1, v8 :: v_dual_mov_b32 v8, v2
+; GFX1310-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_lshlrev_b64_e64 v[6:7], v14, 1
-; GFX1310-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX1310-NEXT: v_and_or_b32 v11, v10, 1, v11
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1310-NEXT: v_add_co_u32 v11, vcc_lo, v6, -1
+; GFX1310-NEXT: v_add_co_u32 v15, vcc_lo, v6, -1
; GFX1310-NEXT: v_add_co_ci_u32_e64 v16, null, -1, v7, vcc_lo
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_and_b32_e32 v10, v15, v10
-; GFX1310-NEXT: v_and_b32_e32 v2, v2, v11
; GFX1310-NEXT: v_lshrrev_b64 v[6:7], v4, v[8:9]
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_lshrrev_b32_e32 v3, 17, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_and_b32_e32 v2, v2, v15
+; GFX1310-NEXT: v_and_b32_e32 v15, 1, v6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_and_b32_e32 v11, v3, v11
; GFX1310-NEXT: v_and_b32_e32 v3, v9, v16
-; GFX1310-NEXT: v_add_co_u32 v10, s0, v17, v10
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_add_co_ci_u32_e64 v11, null, 0, 0, s0
+; GFX1310-NEXT: v_add_co_u32 v10, s0, v10, v11
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
-; GFX1310-NEXT: v_and_b32_e32 v15, 1, v6
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v11, null, 0, 0, s0
; GFX1310-NEXT: v_lshrrev_b64 v[2:3], v14, v[8:9]
; GFX1310-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[10:11]
@@ -3449,3 +3445,6 @@ define i8 @to_e5m3fnu_f32_rtz(float %x) {
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E5M3FNU", metadata !"round.towardzero", i1 false)
ret i8 %r
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1250-FAKE16: {{.*}}
+; GFX1250-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
index abbecb8005493..ce517b23aaefc 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
@@ -1337,7 +1337,6 @@ define i8 @to_f8e5m2_from_f64(double %x) {
; CHECK-NEXT: v_sub_co_u32_e32 v4, vcc, 37, v12
; CHECK-NEXT: v_subb_co_u32_e32 v5, vcc, 0, v13, vcc
; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[4:5]
-; CHECK-NEXT: v_and_b32_e32 v15, 0xfffff, v3
; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v4, 63, v4, vcc
; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 1, v[4:5]
@@ -1345,8 +1344,9 @@ define i8 @to_f8e5m2_from_f64(double %x) {
; CHECK-NEXT: v_add_u32_e32 v14, -1, v6
; CHECK-NEXT: v_lshlrev_b64 v[6:7], v14, 1
; CHECK-NEXT: v_add_co_u32_e32 v8, vcc, -1, v6
+; CHECK-NEXT: v_and_b32_e32 v6, 0xfffff, v3
; CHECK-NEXT: v_addc_co_u32_e32 v9, vcc, -1, v7, vcc
-; CHECK-NEXT: v_or_b32_e32 v7, 0x100000, v15
+; CHECK-NEXT: v_or_b32_e32 v7, 0x100000, v6
; CHECK-NEXT: v_mov_b32_e32 v6, v2
; CHECK-NEXT: v_and_b32_e32 v9, v7, v9
; CHECK-NEXT: v_and_b32_e32 v8, v2, v8
@@ -1369,13 +1369,12 @@ define i8 @to_f8e5m2_from_f64(double %x) {
; CHECK-NEXT: v_and_b32_e32 v5, 0x1ffff, v3
; CHECK-NEXT: v_mov_b32_e32 v4, v2
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; CHECK-NEXT: v_bfe_u32 v4, v15, 18, 1
+; CHECK-NEXT: v_bfe_u32 v4, v3, 18, 2
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_or_b32_e32 v2, v2, v4
-; CHECK-NEXT: v_lshrrev_b32_e32 v4, 17, v3
-; CHECK-NEXT: v_and_b32_e32 v2, v4, v2
-; CHECK-NEXT: v_bfe_u32 v3, v3, 18, 2
-; CHECK-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; CHECK-NEXT: v_and_or_b32 v2, v4, 1, v2
+; CHECK-NEXT: v_lshrrev_b32_e32 v3, 17, v3
+; CHECK-NEXT: v_and_b32_e32 v2, v3, v2
+; CHECK-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
; CHECK-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc
; CHECK-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[2:3]
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/or.ll b/llvm/test/CodeGen/AMDGPU/or.ll
index 327fec4f2d476..853b553c8ed98 100644
--- a/llvm/test/CodeGen/AMDGPU/or.ll
+++ b/llvm/test/CodeGen/AMDGPU/or.ll
@@ -621,3 +621,49 @@ define amdgpu_kernel void @s_or_i1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c
store i1 %or, ptr addrspace(1) %out
ret void
}
+
+; Propagate demanded bits from the LHS to simplify the RHS.
+
+define i32 @s_or_hidden_bits_rhs(i32 inreg %x, i32 inreg %y) {
+; GFX6-LABEL: s_or_hidden_bits_rhs:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_lshr_b32 s4, s17, 24
+; GFX6-NEXT: s_orn2_b32 s4, s16, s4
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: s_or_hidden_bits_rhs:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_lshr_b32 s4, s17, 24
+; GFX8-NEXT: s_orn2_b32 s4, s16, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+ %shift = lshr i32 %y, 24
+ %bounded = xor i32 %shift, -1
+ %inner = and i32 %x, 255
+ %result = or i32 %bounded, %inner
+ ret i32 %result
+}
+
+define i32 @v_or_hidden_bits_rhs(i32 %x, i32 %y) {
+; GFX6-LABEL: v_or_hidden_bits_rhs:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; GFX6-NEXT: v_bfi_b32 v0, v1, v0, -1
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_or_hidden_bits_rhs:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; GFX8-NEXT: v_bfi_b32 v0, v1, v0, -1
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+ %shift = lshr i32 %y, 24
+ %bounded = xor i32 %shift, -1
+ %inner = and i32 %x, 255
+ %result = or i32 %bounded, %inner
+ ret i32 %result
+}
diff --git a/llvm/test/CodeGen/AMDGPU/permute.ll b/llvm/test/CodeGen/AMDGPU/permute.ll
index 2dc526c2a0a45..f952cda718321 100644
--- a/llvm/test/CodeGen/AMDGPU/permute.ll
+++ b/llvm/test/CodeGen/AMDGPU/permute.ll
@@ -199,16 +199,14 @@ define amdgpu_kernel void @and_or_or_and(ptr addrspace(1) nocapture %arg, i32 %a
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GCN-NEXT: v_mov_b32_e32 v3, 0xffff0500
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: flat_load_dword v2, v[0:1]
-; GCN-NEXT: s_and_b32 s0, s2, 0xff00
-; GCN-NEXT: s_or_b32 s0, s0, 0xffff0000
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_and_b32_e32 v2, 0xff00ff, v2
-; GCN-NEXT: v_or_b32_e32 v2, s0, v2
+; GCN-NEXT: v_perm_b32 v2, s2, v2, v3
; GCN-NEXT: flat_store_dword v[0:1], v2
; GCN-NEXT: s_endpgm
bb:
@@ -285,7 +283,8 @@ define amdgpu_kernel void @known_ffff0500(ptr addrspace(1) nocapture %arg, i32 %
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: v_mov_b32_e32 v5, 0xffff8004
+; GCN-NEXT: v_mov_b32_e32 v5, 0xffff0500
+; GCN-NEXT: v_mov_b32_e32 v6, 0xffff8004
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0
@@ -294,14 +293,11 @@ define amdgpu_kernel void @known_ffff0500(ptr addrspace(1) nocapture %arg, i32 %
; GCN-NEXT: s_bitset1_b32 s2, 15
; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v2, s0
-; GCN-NEXT: s_and_b32 s0, s2, 0xff00
-; GCN-NEXT: s_or_b32 s0, s0, 0xffff0000
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_or_b32_e32 v4, 4, v4
-; GCN-NEXT: v_and_b32_e32 v4, 0xff00ff, v4
-; GCN-NEXT: v_or_b32_e32 v4, s0, v4
+; GCN-NEXT: v_perm_b32 v4, s2, v4, v5
; GCN-NEXT: flat_store_dword v[0:1], v4
-; GCN-NEXT: flat_store_dword v[2:3], v5
+; GCN-NEXT: flat_store_dword v[2:3], v6
; GCN-NEXT: s_endpgm
bb:
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll b/llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll
index 3fbeecfbf9213..cda1c07d05886 100644
--- a/llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll
+++ b/llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll
@@ -14,10 +14,11 @@ define i32 @f() {
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: ds_read_b32 v0, v0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_and_b32_e32 v0, v0, v1
; CHECK-NEXT: s_setpc_b64 s[30:31]
bb:
%i = load i32, ptr addrspace(3) zeroinitializer, align 16
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/and.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/and.ll
index c88e15d93806c..2286bf7bb28a0 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/and.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/and.ll
@@ -611,7 +611,7 @@ define i32 @and_add_lsr(i32 %x, i32 %y) {
;
; LA64-LABEL: and_add_lsr:
; LA64: # %bb.0:
-; LA64-NEXT: addi.w $a0, $a0, -1
+; LA64-NEXT: addi.d $a0, $a0, -1
; LA64-NEXT: bstrpick.d $a1, $a1, 31, 20
; LA64-NEXT: and $a0, $a1, $a0
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/and-add-lsr.ll b/llvm/test/CodeGen/RISCV/and-add-lsr.ll
index 22ac9a2705aea..89af3264b665c 100644
--- a/llvm/test/CodeGen/RISCV/and-add-lsr.ll
+++ b/llvm/test/CodeGen/RISCV/and-add-lsr.ll
@@ -14,7 +14,7 @@ define i32 @and_add_lsr(i32 %x, i32 %y) {
;
; RV64I-LABEL: and_add_lsr:
; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a0, a0, -1
+; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: srliw a1, a1, 20
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
@@ -28,20 +28,16 @@ define i32 @and_add_lsr(i32 %x, i32 %y) {
define <2 x i32> @and_add_lsr_vec(<2 x i32> %x, <2 x i32> %y) {
; RV32I-LABEL: and_add_lsr_vec:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV32I-NEXT: vadd.vx v8, v8, a0
+; RV32I-NEXT: vadd.vi v8, v8, -1
; RV32I-NEXT: vsrl.vi v9, v9, 20
; RV32I-NEXT: vand.vv v8, v9, v8
; RV32I-NEXT: ret
;
; RV64I-LABEL: and_add_lsr_vec:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64I-NEXT: vadd.vx v8, v8, a0
+; RV64I-NEXT: vadd.vi v8, v8, -1
; RV64I-NEXT: vsrl.vi v9, v9, 20
; RV64I-NEXT: vand.vv v8, v9, v8
; RV64I-NEXT: ret
@@ -55,20 +51,16 @@ define <2 x i32> @and_add_lsr_vec(<2 x i32> %x, <2 x i32> %y) {
define <vscale x 2 x i32> @and_add_lsr_vec2(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
; RV32I-LABEL: and_add_lsr_vec2:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV32I-NEXT: vadd.vx v8, v8, a0
+; RV32I-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; RV32I-NEXT: vadd.vi v8, v8, -1
; RV32I-NEXT: vsrl.vi v9, v9, 20
; RV32I-NEXT: vand.vv v8, v9, v8
; RV32I-NEXT: ret
;
; RV64I-LABEL: and_add_lsr_vec2:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV64I-NEXT: vadd.vx v8, v8, a0
+; RV64I-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; RV64I-NEXT: vadd.vi v8, v8, -1
; RV64I-NEXT: vsrl.vi v9, v9, 20
; RV64I-NEXT: vand.vv v8, v9, v8
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/pr148084.ll b/llvm/test/CodeGen/RISCV/pr148084.ll
index 157e0aee81518..d2c6bc85f9b88 100644
--- a/llvm/test/CodeGen/RISCV/pr148084.ll
+++ b/llvm/test/CodeGen/RISCV/pr148084.ll
@@ -166,20 +166,18 @@ define fastcc i16 @search_tx_type() #0 {
; CHECK-NEXT: sgtz a1, a1
; CHECK-NEXT: slli a1, a1, 15
; CHECK-NEXT: bset a3, zero, a2
-; CHECK-NEXT: and a4, a3, a1
-; CHECK-NEXT: lui a3, 16
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: bnez a4, .LBB0_54
+; CHECK-NEXT: and a3, a3, a1
+; CHECK-NEXT: bnez a3, .LBB0_54
; CHECK-NEXT: # %bb.53: # %bb
-; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: lui a2, 16
+; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: j .LBB0_55
; CHECK-NEXT: .LBB0_54:
-; CHECK-NEXT: li a4, -2
-; CHECK-NEXT: rol a2, a4, a2
+; CHECK-NEXT: li a3, -2
+; CHECK-NEXT: rol a2, a3, a2
; CHECK-NEXT: .LBB0_55: # %bb
; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: xor a1, a1, a3
-; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: andn a0, a0, a1
; CHECK-NEXT: # %bb.56: # %get_tx_mask.exit
; CHECK-NEXT: seqz a1, a0
; CHECK-NEXT: addi a1, a1, -1
diff --git a/llvm/test/CodeGen/RISCV/signed-truncation-check.ll b/llvm/test/CodeGen/RISCV/signed-truncation-check.ll
index 42f233d5fa163..0252df003187b 100644
--- a/llvm/test/CodeGen/RISCV/signed-truncation-check.ll
+++ b/llvm/test/CodeGen/RISCV/signed-truncation-check.ll
@@ -462,7 +462,7 @@ define i1 @add_ugecmp_i64_i8(i64 %x) nounwind {
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: sltiu a1, a2, -256
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: xori a1, a1, 1
+; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
diff --git a/llvm/test/CodeGen/X86/apx/ccmp.ll b/llvm/test/CodeGen/X86/apx/ccmp.ll
index 8629b179a1797..39c8b532d085a 100644
--- a/llvm/test/CodeGen/X86/apx/ccmp.ll
+++ b/llvm/test/CodeGen/X86/apx/ccmp.ll
@@ -435,8 +435,12 @@ define void @ccmp64rr_of(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: ccmp64rr_of:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7]
-; CHECK-NEXT: ccmpbq {dfv=of} %rsi, %rdi # encoding: [0x62,0xf4,0xc4,0x02,0x39,0xf7]
-; CHECK-NEXT: jno .LBB6_1 # encoding: [0x71,A]
+; CHECK-NEXT: setb %al # encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7]
+; CHECK-NEXT: seto %cl # encoding: [0x0f,0x90,0xc1]
+; CHECK-NEXT: notb %cl # encoding: [0xf6,0xd1]
+; CHECK-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; CHECK-NEXT: jne .LBB6_1 # encoding: [0x75,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB6_1, kind: FK_PCRel_1
; CHECK-NEXT: # %bb.2: # %if.then
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
@@ -449,8 +453,12 @@ define void @ccmp64rr_of(i64 %a, i64 %b, i64 %c) {
; NDD-LABEL: ccmp64rr_of:
; NDD: # %bb.0: # %bb
; NDD-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7]
-; NDD-NEXT: ccmpbq {dfv=of} %rsi, %rdi # encoding: [0x62,0xf4,0xc4,0x02,0x39,0xf7]
-; NDD-NEXT: jno .LBB6_1 # encoding: [0x71,A]
+; NDD-NEXT: setb %al # encoding: [0x0f,0x92,0xc0]
+; NDD-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7]
+; NDD-NEXT: seto %cl # encoding: [0x0f,0x90,0xc1]
+; NDD-NEXT: notb %cl # EVEX TO LEGACY Compression encoding: [0xf6,0xd1]
+; NDD-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; NDD-NEXT: jne .LBB6_1 # encoding: [0x75,A]
; NDD-NEXT: # fixup A - offset: 1, value: .LBB6_1, kind: FK_PCRel_1
; NDD-NEXT: # %bb.2: # %if.then
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
@@ -465,7 +473,8 @@ define void @ccmp64rr_of(i64 %a, i64 %b, i64 %c) {
; PREFER_NO_LEGACY_SETCC-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7]
; PREFER_NO_LEGACY_SETCC-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
; PREFER_NO_LEGACY_SETCC-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7]
-; PREFER_NO_LEGACY_SETCC-NEXT: setzuno %cl # encoding: [0x62,0xf4,0x7f,0x18,0x41,0xc1]
+; PREFER_NO_LEGACY_SETCC-NEXT: setzuo %cl # encoding: [0x62,0xf4,0x7f,0x18,0x40,0xc1]
+; PREFER_NO_LEGACY_SETCC-NEXT: notb %cl # encoding: [0xf6,0xd1]
; PREFER_NO_LEGACY_SETCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
; PREFER_NO_LEGACY_SETCC-NEXT: jne .LBB6_1 # encoding: [0x75,A]
; PREFER_NO_LEGACY_SETCC-NEXT: # fixup A - offset: 1, value: .LBB6_1, kind: FK_PCRel_1
@@ -482,7 +491,8 @@ define void @ccmp64rr_of(i64 %a, i64 %b, i64 %c) {
; PREFER_LEGACY_SETCC-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7]
; PREFER_LEGACY_SETCC-NEXT: setb %al # encoding: [0x0f,0x92,0xc0]
; PREFER_LEGACY_SETCC-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7]
-; PREFER_LEGACY_SETCC-NEXT: setno %cl # encoding: [0x0f,0x91,0xc1]
+; PREFER_LEGACY_SETCC-NEXT: seto %cl # encoding: [0x0f,0x90,0xc1]
+; PREFER_LEGACY_SETCC-NEXT: notb %cl # encoding: [0xf6,0xd1]
; PREFER_LEGACY_SETCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
; PREFER_LEGACY_SETCC-NEXT: jne .LBB6_1 # encoding: [0x75,A]
; PREFER_LEGACY_SETCC-NEXT: # fixup A - offset: 1, value: .LBB6_1, kind: FK_PCRel_1
diff --git a/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll b/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll
index 71887e369bd18..169fdf90a6470 100644
--- a/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll
+++ b/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll
@@ -1286,11 +1286,10 @@ define zeroext i16 @atomic_shl1_mask01_xor_16_gpr_valz(ptr %v, i16 zeroext %c) n
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB22_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %ecx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: testl %ecx, %esi
-; X86-NEXT: sete %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: testl %eax, %esi
+; X86-NEXT: sete %cl
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
@@ -1312,11 +1311,10 @@ define zeroext i16 @atomic_shl1_mask01_xor_16_gpr_valz(ptr %v, i16 zeroext %c) n
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB22_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %ecx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: testl %ecx, %edx
-; X64-NEXT: sete %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: testl %eax, %edx
+; X64-NEXT: sete %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
entry:
%0 = and i16 %c, 15
@@ -1335,51 +1333,49 @@ define zeroext i16 @atomic_blsi_xor_16_gpr_valz(ptr %v, i16 zeroext %c) nounwind
; X86-LABEL: atomic_blsi_xor_16_gpr_valz:
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: negl %ecx
-; X86-NEXT: andl %eax, %ecx
-; X86-NEXT: movzwl (%edx), %eax
+; X86-NEXT: movl %eax, %edx
+; X86-NEXT: negl %edx
+; X86-NEXT: andl %eax, %edx
+; X86-NEXT: movzwl (%ecx), %eax
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB23_1: # %atomicrmw.start
; X86-NEXT: # =>This Inner Loop Header: Depth=1
; X86-NEXT: movl %eax, %esi
-; X86-NEXT: xorl %ecx, %esi
+; X86-NEXT: xorl %edx, %esi
; X86-NEXT: # kill: def $ax killed $ax killed $eax
-; X86-NEXT: lock cmpxchgw %si, (%edx)
+; X86-NEXT: lock cmpxchgw %si, (%ecx)
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB23_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %edx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: testl %edx, %ecx
-; X86-NEXT: sete %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: testl %eax, %edx
+; X86-NEXT: sete %cl
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
; X64-LABEL: atomic_blsi_xor_16_gpr_valz:
; X64: # %bb.0: # %entry
-; X64-NEXT: movl %esi, %ecx
-; X64-NEXT: negl %ecx
-; X64-NEXT: andl %esi, %ecx
+; X64-NEXT: movl %esi, %edx
+; X64-NEXT: negl %edx
+; X64-NEXT: andl %esi, %edx
; X64-NEXT: movzwl (%rdi), %eax
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB23_1: # %atomicrmw.start
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: movl %eax, %edx
-; X64-NEXT: xorl %ecx, %edx
+; X64-NEXT: movl %eax, %ecx
+; X64-NEXT: xorl %edx, %ecx
; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: lock cmpxchgw %dx, (%rdi)
+; X64-NEXT: lock cmpxchgw %cx, (%rdi)
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB23_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: testl %edx, %ecx
-; X64-NEXT: sete %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: testl %eax, %edx
+; X64-NEXT: sete %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
entry:
%conv = zext i16 %c to i32
@@ -1679,11 +1675,10 @@ define zeroext i16 @atomic_shl1_mask01_xor_16_gpr_valnz(ptr %v, i16 zeroext %c)
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB28_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %ecx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: testl %ecx, %esi
-; X86-NEXT: setne %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: testl %eax, %esi
+; X86-NEXT: setne %cl
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
@@ -1705,11 +1700,10 @@ define zeroext i16 @atomic_shl1_mask01_xor_16_gpr_valnz(ptr %v, i16 zeroext %c)
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB28_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %ecx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: testl %ecx, %edx
-; X64-NEXT: setne %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: testl %eax, %edx
+; X64-NEXT: setne %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
entry:
%0 = and i16 %c, 15
@@ -1728,51 +1722,49 @@ define zeroext i16 @atomic_blsi_xor_16_gpr_valnz(ptr %v, i16 zeroext %c) nounwin
; X86-LABEL: atomic_blsi_xor_16_gpr_valnz:
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: negl %ecx
-; X86-NEXT: andl %eax, %ecx
-; X86-NEXT: movzwl (%edx), %eax
+; X86-NEXT: movl %eax, %edx
+; X86-NEXT: negl %edx
+; X86-NEXT: andl %eax, %edx
+; X86-NEXT: movzwl (%ecx), %eax
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB29_1: # %atomicrmw.start
; X86-NEXT: # =>This Inner Loop Header: Depth=1
; X86-NEXT: movl %eax, %esi
-; X86-NEXT: xorl %ecx, %esi
+; X86-NEXT: xorl %edx, %esi
; X86-NEXT: # kill: def $ax killed $ax killed $eax
-; X86-NEXT: lock cmpxchgw %si, (%edx)
+; X86-NEXT: lock cmpxchgw %si, (%ecx)
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB29_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %edx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: testl %edx, %ecx
-; X86-NEXT: setne %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: testl %eax, %edx
+; X86-NEXT: setne %cl
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
; X64-LABEL: atomic_blsi_xor_16_gpr_valnz:
; X64: # %bb.0: # %entry
-; X64-NEXT: movl %esi, %ecx
-; X64-NEXT: negl %ecx
-; X64-NEXT: andl %esi, %ecx
+; X64-NEXT: movl %esi, %edx
+; X64-NEXT: negl %edx
+; X64-NEXT: andl %esi, %edx
; X64-NEXT: movzwl (%rdi), %eax
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB29_1: # %atomicrmw.start
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: movl %eax, %edx
-; X64-NEXT: xorl %ecx, %edx
+; X64-NEXT: movl %eax, %ecx
+; X64-NEXT: xorl %edx, %ecx
; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: lock cmpxchgw %dx, (%rdi)
+; X64-NEXT: lock cmpxchgw %cx, (%rdi)
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB29_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: testl %edx, %ecx
-; X64-NEXT: setne %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: testl %eax, %edx
+; X64-NEXT: setne %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
entry:
%conv = zext i16 %c to i32
@@ -2141,14 +2133,14 @@ define zeroext i16 @atomic_shl1_mask01_xor_16_gpr_brz(ptr %v, i16 zeroext %c) no
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB34_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %ecx
-; X86-NEXT: movw $123, %ax
-; X86-NEXT: testl %ecx, %esi
+; X86-NEXT: movw $123, %cx
+; X86-NEXT: testl %eax, %esi
; X86-NEXT: jne .LBB34_4
; X86-NEXT: # %bb.3: # %if.then
; X86-NEXT: movzwl %bx, %eax
-; X86-NEXT: movzwl (%edx,%eax,2), %eax
+; X86-NEXT: movzwl (%edx,%eax,2), %ecx
; X86-NEXT: .LBB34_4: # %return
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %ebx
; X86-NEXT: retl
@@ -2172,15 +2164,16 @@ define zeroext i16 @atomic_shl1_mask01_xor_16_gpr_brz(ptr %v, i16 zeroext %c) no
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB34_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %ecx
-; X64-NEXT: movw $123, %ax
-; X64-NEXT: testl %ecx, %esi
+; X64-NEXT: movw $123, %cx
+; X64-NEXT: testl %eax, %esi
; X64-NEXT: je .LBB34_3
; X64-NEXT: # %bb.4: # %return
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
; X64-NEXT: .LBB34_3: # %if.then
; X64-NEXT: movzwl %dx, %eax
-; X64-NEXT: movzwl (%rdi,%rax,2), %eax
+; X64-NEXT: movzwl (%rdi,%rax,2), %ecx
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
entry:
%0 = and i16 %c, 15
@@ -2209,59 +2202,60 @@ define zeroext i16 @atomic_blsi_xor_16_gpr_brz(ptr %v, i16 zeroext %c) nounwind
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movl %ecx, %esi
-; X86-NEXT: negl %esi
-; X86-NEXT: andl %ecx, %esi
-; X86-NEXT: movzwl (%edx), %eax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: negl %edi
+; X86-NEXT: andl %edx, %edi
+; X86-NEXT: movzwl (%esi), %eax
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB35_1: # %atomicrmw.start
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: movl %eax, %edi
-; X86-NEXT: xorl %esi, %edi
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: xorl %edi, %ecx
; X86-NEXT: # kill: def $ax killed $ax killed $eax
-; X86-NEXT: lock cmpxchgw %di, (%edx)
+; X86-NEXT: lock cmpxchgw %cx, (%esi)
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB35_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %edi
-; X86-NEXT: movw $123, %ax
-; X86-NEXT: testl %edi, %esi
+; X86-NEXT: movw $123, %cx
+; X86-NEXT: testl %eax, %edi
; X86-NEXT: jne .LBB35_4
; X86-NEXT: # %bb.3: # %if.then
-; X86-NEXT: movzwl %cx, %eax
-; X86-NEXT: movzwl (%edx,%eax,2), %eax
+; X86-NEXT: movzwl %dx, %eax
+; X86-NEXT: movzwl (%esi,%eax,2), %ecx
; X86-NEXT: .LBB35_4: # %return
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
;
; X64-LABEL: atomic_blsi_xor_16_gpr_brz:
; X64: # %bb.0: # %entry
-; X64-NEXT: movl %esi, %ecx
-; X64-NEXT: negl %ecx
-; X64-NEXT: andl %esi, %ecx
+; X64-NEXT: movl %esi, %edx
+; X64-NEXT: negl %edx
+; X64-NEXT: andl %esi, %edx
; X64-NEXT: movzwl (%rdi), %eax
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB35_1: # %atomicrmw.start
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: movl %eax, %edx
-; X64-NEXT: xorl %ecx, %edx
+; X64-NEXT: movl %eax, %ecx
+; X64-NEXT: xorl %edx, %ecx
; X64-NEXT: # kill: def $ax killed $ax killed $eax
-; X64-NEXT: lock cmpxchgw %dx, (%rdi)
+; X64-NEXT: lock cmpxchgw %cx, (%rdi)
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB35_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
-; X64-NEXT: movw $123, %ax
-; X64-NEXT: testl %edx, %ecx
+; X64-NEXT: movw $123, %cx
+; X64-NEXT: testl %eax, %edx
; X64-NEXT: je .LBB35_3
; X64-NEXT: # %bb.4: # %return
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
; X64-NEXT: .LBB35_3: # %if.then
; X64-NEXT: movzwl %si, %eax
-; X64-NEXT: movzwl (%rdi,%rax,2), %eax
+; X64-NEXT: movzwl (%rdi,%rax,2), %ecx
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
entry:
%conv = zext i16 %c to i32
@@ -2893,11 +2887,10 @@ define zeroext i16 @atomic_shl1_mask01_and_16_gpr_valnz(ptr %v, i16 zeroext %c)
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB46_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %ecx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: testl %ecx, %esi
-; X86-NEXT: setne %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: testl %eax, %esi
+; X86-NEXT: setne %cl
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -2922,11 +2915,10 @@ define zeroext i16 @atomic_shl1_mask01_and_16_gpr_valnz(ptr %v, i16 zeroext %c)
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB46_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %ecx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: testl %ecx, %edx
-; X64-NEXT: setne %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: testl %eax, %edx
+; X64-NEXT: setne %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
entry:
%0 = and i16 %c, 15
@@ -2947,56 +2939,54 @@ define zeroext i16 @atomic_blsi_and_16_gpr_valnz(ptr %v, i16 zeroext %c) nounwin
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: negl %ecx
-; X86-NEXT: andl %eax, %ecx
-; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %eax, %edx
+; X86-NEXT: negl %edx
+; X86-NEXT: andl %eax, %edx
+; X86-NEXT: movl %edx, %esi
; X86-NEXT: notl %esi
-; X86-NEXT: movzwl (%edx), %eax
+; X86-NEXT: movzwl (%ecx), %eax
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB47_1: # %atomicrmw.start
; X86-NEXT: # =>This Inner Loop Header: Depth=1
; X86-NEXT: movl %eax, %edi
; X86-NEXT: andl %esi, %edi
; X86-NEXT: # kill: def $ax killed $ax killed $eax
-; X86-NEXT: lock cmpxchgw %di, (%edx)
+; X86-NEXT: lock cmpxchgw %di, (%ecx)
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB47_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %edx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: testl %edx, %ecx
-; X86-NEXT: setne %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: testl %eax, %edx
+; X86-NEXT: setne %cl
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
;
; X64-LABEL: atomic_blsi_and_16_gpr_valnz:
; X64: # %bb.0: # %entry
-; X64-NEXT: movl %esi, %ecx
-; X64-NEXT: negl %ecx
-; X64-NEXT: andl %esi, %ecx
-; X64-NEXT: movl %ecx, %edx
-; X64-NEXT: notl %edx
+; X64-NEXT: movl %esi, %edx
+; X64-NEXT: negl %edx
+; X64-NEXT: andl %esi, %edx
+; X64-NEXT: movl %edx, %ecx
+; X64-NEXT: notl %ecx
; X64-NEXT: movzwl (%rdi), %eax
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB47_1: # %atomicrmw.start
; X64-NEXT: # =>This Inner Loop Header: Depth=1
; X64-NEXT: movl %eax, %esi
-; X64-NEXT: andl %edx, %esi
+; X64-NEXT: andl %ecx, %esi
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: lock cmpxchgw %si, (%rdi)
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB47_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: testl %edx, %ecx
-; X64-NEXT: setne %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %ecx, %ecx
+; X64-NEXT: testl %eax, %edx
+; X64-NEXT: setne %cl
+; X64-NEXT: movl %ecx, %eax
; X64-NEXT: retq
entry:
%conv = zext i16 %c to i32
@@ -3382,7 +3372,6 @@ define zeroext i16 @atomic_shl1_mask01_and_16_gpr_brnz(ptr %v, i16 zeroext %c) n
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB52_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %eax
; X86-NEXT: testl %eax, %esi
; X86-NEXT: je .LBB52_3
; X86-NEXT: # %bb.4: # %if.then
@@ -3418,7 +3407,6 @@ define zeroext i16 @atomic_shl1_mask01_and_16_gpr_brnz(ptr %v, i16 zeroext %c) n
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB52_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %eax
; X64-NEXT: testl %eax, %esi
; X64-NEXT: je .LBB52_3
; X64-NEXT: # %bb.4: # %if.then
@@ -3475,7 +3463,6 @@ define zeroext i16 @atomic_blsi_and_16_gpr_brnz(ptr %v, i16 zeroext %c) nounwind
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB53_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %eax
; X86-NEXT: testl %eax, %esi
; X86-NEXT: je .LBB53_3
; X86-NEXT: # %bb.4: # %if.then
@@ -3508,7 +3495,6 @@ define zeroext i16 @atomic_blsi_and_16_gpr_brnz(ptr %v, i16 zeroext %c) nounwind
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB53_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %eax
; X64-NEXT: testl %eax, %ecx
; X64-NEXT: je .LBB53_3
; X64-NEXT: # %bb.4: # %if.then
diff --git a/llvm/test/CodeGen/X86/avx512-cmp.ll b/llvm/test/CodeGen/X86/avx512-cmp.ll
index ac099b5c6718e..56de8299c2e06 100644
--- a/llvm/test/CodeGen/X86/avx512-cmp.ll
+++ b/llvm/test/CodeGen/X86/avx512-cmp.ll
@@ -155,7 +155,7 @@ B:
define i32 @test10(i64 %b, i64 %c, i1 %d) {
; ALL-LABEL: test10:
; ALL: ## %bb.0:
-; ALL-NEXT: xorb $1, %dl
+; ALL-NEXT: notb %dl
; ALL-NEXT: cmpq %rsi, %rdi
; ALL-NEXT: sete %al
; ALL-NEXT: testb %dl, %al
diff --git a/llvm/test/CodeGen/X86/bswap_tree2.ll b/llvm/test/CodeGen/X86/bswap_tree2.ll
index 98b51460207c3..17f4899fb74d2 100644
--- a/llvm/test/CodeGen/X86/bswap_tree2.ll
+++ b/llvm/test/CodeGen/X86/bswap_tree2.ll
@@ -11,7 +11,6 @@
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, %ecx
-; CHECK-NEXT: andl $16711935, %ecx # imm = 0xFF00FF
; CHECK-NEXT: shll $8, %ecx
; CHECK-NEXT: orl $-16777216, %eax # imm = 0xFF000000
; CHECK-NEXT: shrl $8, %eax
@@ -21,7 +20,6 @@
; CHECK64-LABEL: test1:
; CHECK64: # %bb.0:
; CHECK64-NEXT: movl %edi, %eax
-; CHECK64-NEXT: andl $16711935, %eax # imm = 0xFF00FF
; CHECK64-NEXT: shll $8, %eax
; CHECK64-NEXT: orl $-16777216, %edi # imm = 0xFF000000
; CHECK64-NEXT: shrl $8, %edi
diff --git a/llvm/test/CodeGen/X86/float-to-arbitrary-fp.ll b/llvm/test/CodeGen/X86/float-to-arbitrary-fp.ll
index b3f9e68fc3368..3db623dce4074 100644
--- a/llvm/test/CodeGen/X86/float-to-arbitrary-fp.ll
+++ b/llvm/test/CodeGen/X86/float-to-arbitrary-fp.ll
@@ -72,14 +72,13 @@ define i8 @to_f8e5m2_dynamic(float %x) {
; CHECK-NEXT: leal (%rax,%r8,4), %r8d
; CHECK-NEXT: orl %r10d, %r8d
; CHECK-NEXT: shrl $21, %edi
-; CHECK-NEXT: movl %edi, %r9d
-; CHECK-NEXT: andl $1, %r9d
-; CHECK-NEXT: xorl %r10d, %r10d
+; CHECK-NEXT: xorl %r9d, %r9d
; CHECK-NEXT: testl $1048575, %esi # imm = 0xFFFFF
-; CHECK-NEXT: setne %r10b
-; CHECK-NEXT: orl %r9d, %r10d
+; CHECK-NEXT: setne %r9b
+; CHECK-NEXT: orl %edi, %r9d
; CHECK-NEXT: shrl $20, %esi
-; CHECK-NEXT: andl %r10d, %esi
+; CHECK-NEXT: andl %r9d, %esi
+; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: addl %edi, %esi
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: cmpl $4, %esi
@@ -455,14 +454,13 @@ define <2 x i8> @to_f8e5m2_v2f32(<2 x float> %x) {
; CHECK-NEXT: leal (%r9,%r8,4), %r8d
; CHECK-NEXT: orl %r13d, %r8d
; CHECK-NEXT: shrl $21, %r12d
-; CHECK-NEXT: movl %r12d, %r10d
-; CHECK-NEXT: andl $1, %r10d
-; CHECK-NEXT: xorl %r11d, %r11d
+; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: testl $1048575, %r15d # imm = 0xFFFFF
-; CHECK-NEXT: setne %r11b
-; CHECK-NEXT: orl %r10d, %r11d
+; CHECK-NEXT: setne %r10b
+; CHECK-NEXT: orl %r12d, %r10d
; CHECK-NEXT: shrl $20, %r15d
-; CHECK-NEXT: andl %r11d, %r15d
+; CHECK-NEXT: andl %r10d, %r15d
+; CHECK-NEXT: andl $1, %r15d
; CHECK-NEXT: addl %r12d, %r15d
; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: cmpl $4, %r15d
@@ -515,14 +513,13 @@ define <2 x i8> @to_f8e5m2_v2f32(<2 x float> %x) {
; CHECK-NEXT: leal (%rdi,%r10,4), %r10d
; CHECK-NEXT: orl %ecx, %r10d
; CHECK-NEXT: shrl $21, %esi
-; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: andl $1, %ecx
-; CHECK-NEXT: xorl %r11d, %r11d
+; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl $1048575, %edx # imm = 0xFFFFF
-; CHECK-NEXT: setne %r11b
-; CHECK-NEXT: orl %ecx, %r11d
+; CHECK-NEXT: setne %cl
+; CHECK-NEXT: orl %esi, %ecx
; CHECK-NEXT: shrl $20, %edx
-; CHECK-NEXT: andl %r11d, %edx
+; CHECK-NEXT: andl %ecx, %edx
+; CHECK-NEXT: andl $1, %edx
; CHECK-NEXT: addl %esi, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl $4, %edx
@@ -687,14 +684,13 @@ define <2 x i8> @to_f8e4m3fn_v2f32(<2 x float> %x) {
; CHECK-NEXT: leal (%r9,%r8,8), %r8d
; CHECK-NEXT: orl %r13d, %r8d
; CHECK-NEXT: shrl $20, %r12d
-; CHECK-NEXT: movl %r12d, %r10d
-; CHECK-NEXT: andl $1, %r10d
-; CHECK-NEXT: xorl %r11d, %r11d
+; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: testl $524287, %r15d # imm = 0x7FFFF
-; CHECK-NEXT: setne %r11b
-; CHECK-NEXT: orl %r10d, %r11d
+; CHECK-NEXT: setne %r10b
+; CHECK-NEXT: orl %r12d, %r10d
; CHECK-NEXT: shrl $19, %r15d
-; CHECK-NEXT: andl %r11d, %r15d
+; CHECK-NEXT: andl %r10d, %r15d
+; CHECK-NEXT: andl $1, %r15d
; CHECK-NEXT: addl %r12d, %r15d
; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: cmpl $8, %r15d
@@ -727,14 +723,13 @@ define <2 x i8> @to_f8e4m3fn_v2f32(<2 x float> %x) {
; CHECK-NEXT: leal (%rdi,%r10,8), %r10d
; CHECK-NEXT: orl %ecx, %r10d
; CHECK-NEXT: shrl $20, %esi
-; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: andl $1, %ecx
-; CHECK-NEXT: xorl %r11d, %r11d
+; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl $524287, %edx # imm = 0x7FFFF
-; CHECK-NEXT: setne %r11b
-; CHECK-NEXT: orl %ecx, %r11d
+; CHECK-NEXT: setne %cl
+; CHECK-NEXT: orl %esi, %ecx
; CHECK-NEXT: shrl $19, %edx
-; CHECK-NEXT: andl %r11d, %edx
+; CHECK-NEXT: andl %ecx, %edx
+; CHECK-NEXT: andl $1, %edx
; CHECK-NEXT: addl %esi, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl $8, %edx
@@ -912,7 +907,7 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl $8, %r14d
; CHECK-NEXT: cmovgel %eax, %r14d
-; CHECK-NEXT: movl $0, %ebp
+; CHECK-NEXT: movl $0, %ebx
; CHECK-NEXT: setge %cl
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movd %xmm1, %eax
@@ -922,19 +917,17 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK-NEXT: orl %r14d, %ecx
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r11 # 8-byte Reload
; CHECK-NEXT: shrl $20, %r11d
-; CHECK-NEXT: movl %r11d, %edx
-; CHECK-NEXT: movq %r11, %rbx
-; CHECK-NEXT: andl $1, %edx
-; CHECK-NEXT: xorl %r11d, %r11d
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: testl $524287, %r13d # imm = 0x7FFFF
-; CHECK-NEXT: setne %r11b
-; CHECK-NEXT: orl %edx, %r11d
+; CHECK-NEXT: setne %dl
+; CHECK-NEXT: orl %r11d, %edx
; CHECK-NEXT: shrl $19, %r13d
-; CHECK-NEXT: andl %r11d, %r13d
-; CHECK-NEXT: addl %ebx, %r13d
+; CHECK-NEXT: andl %edx, %r13d
+; CHECK-NEXT: andl $1, %r13d
+; CHECK-NEXT: addl %r11d, %r13d
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: cmpl $8, %r13d
-; CHECK-NEXT: cmovgel %ebp, %r13d
+; CHECK-NEXT: cmovgel %ebx, %r13d
; CHECK-NEXT: setge %dl
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Reload
; CHECK-NEXT: leal (%rbx,%rdx), %r11d
@@ -953,8 +946,8 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK-NEXT: addl (%rsp), %r12d # 4-byte Folded Reload
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl $8, %r12d
-; CHECK-NEXT: movl $0, %r13d
-; CHECK-NEXT: cmovgel %r13d, %r12d
+; CHECK-NEXT: movl $0, %ebp
+; CHECK-NEXT: cmovgel %ebp, %r12d
; CHECK-NEXT: setge %cl
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movd %xmm1, %edx
@@ -964,18 +957,18 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK-NEXT: orl %r12d, %ecx
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Reload
; CHECK-NEXT: shrl $20, %r14d
-; CHECK-NEXT: movl %r14d, %ebx
-; CHECK-NEXT: andl $1, %ebx
-; CHECK-NEXT: xorl %ebp, %ebp
+; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: testl $524287, %r15d # imm = 0x7FFFF
-; CHECK-NEXT: setne %bpl
-; CHECK-NEXT: orl %ebx, %ebp
+; CHECK-NEXT: setne %bl
+; CHECK-NEXT: orl %r14d, %ebx
; CHECK-NEXT: shrl $19, %r15d
-; CHECK-NEXT: andl %ebp, %r15d
+; CHECK-NEXT: andl %ebx, %r15d
+; CHECK-NEXT: andl $1, %r15d
; CHECK-NEXT: addl %r14d, %r15d
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: cmpl $8, %r15d
-; CHECK-NEXT: cmovgel %r13d, %r15d
+; CHECK-NEXT: cmovgel %ebp, %r15d
+; CHECK-NEXT: movl $0, %r13d
; CHECK-NEXT: setge %bl
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Reload
; CHECK-NEXT: leal (%r12,%rbx), %r14d
@@ -1001,14 +994,13 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK-NEXT: leal (%rcx,%r9,8), %r9d
; CHECK-NEXT: orl %r10d, %r9d
; CHECK-NEXT: shrl $20, %r8d
-; CHECK-NEXT: movl %r8d, %r10d
-; CHECK-NEXT: andl $1, %r10d
-; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: testl $524287, %edi # imm = 0x7FFFF
-; CHECK-NEXT: setne %bl
-; CHECK-NEXT: orl %r10d, %ebx
+; CHECK-NEXT: setne %r10b
+; CHECK-NEXT: orl %r8d, %r10d
; CHECK-NEXT: shrl $19, %edi
-; CHECK-NEXT: andl %ebx, %edi
+; CHECK-NEXT: andl %r10d, %edi
+; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: addl %r8d, %edi
; CHECK-NEXT: xorl %r8d, %r8d
; CHECK-NEXT: cmpl $8, %edi
@@ -1235,16 +1227,14 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: orl %ebx, %r8d
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r11 # 8-byte Reload
; CHECK-NEXT: shrl $20, %r11d
-; CHECK-NEXT: movl %r11d, %r10d
-; CHECK-NEXT: movq %r11, %rbx
-; CHECK-NEXT: andl $1, %r10d
-; CHECK-NEXT: xorl %r11d, %r11d
+; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: testl $524287, %r12d # imm = 0x7FFFF
-; CHECK-NEXT: setne %r11b
-; CHECK-NEXT: orl %r10d, %r11d
+; CHECK-NEXT: setne %r10b
+; CHECK-NEXT: orl %r11d, %r10d
; CHECK-NEXT: shrl $19, %r12d
-; CHECK-NEXT: andl %r11d, %r12d
-; CHECK-NEXT: addl %ebx, %r12d
+; CHECK-NEXT: andl %r10d, %r12d
+; CHECK-NEXT: andl $1, %r12d
+; CHECK-NEXT: addl %r11d, %r12d
; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: cmpl $8, %r12d
; CHECK-NEXT: cmovgel %eax, %r12d
@@ -1276,16 +1266,14 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: orl %r14d, %r11d
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Reload
; CHECK-NEXT: shrl $20, %r14d
-; CHECK-NEXT: movl %r14d, %ebx
-; CHECK-NEXT: movq %r14, %r12
-; CHECK-NEXT: andl $1, %ebx
-; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: testl $524287, %r13d # imm = 0x7FFFF
-; CHECK-NEXT: setne %r14b
-; CHECK-NEXT: orl %ebx, %r14d
+; CHECK-NEXT: setne %bl
+; CHECK-NEXT: orl %r14d, %ebx
; CHECK-NEXT: shrl $19, %r13d
-; CHECK-NEXT: andl %r14d, %r13d
-; CHECK-NEXT: addl %r12d, %r13d
+; CHECK-NEXT: andl %ebx, %r13d
+; CHECK-NEXT: andl $1, %r13d
+; CHECK-NEXT: addl %r14d, %r13d
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: cmpl $8, %r13d
; CHECK-NEXT: cmovgel %eax, %r13d
@@ -1298,10 +1286,10 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: leal 6(%r12,%rbx), %ebx
; CHECK-NEXT: testl %ebx, %ebx
; CHECK-NEXT: cmovlel %r11d, %r13d
-; CHECK-NEXT: movzbl %r9b, %r11d
; CHECK-NEXT: ucomiss %xmm0, %xmm1
; CHECK-NEXT: cmovnel %r13d, %r10d
; CHECK-NEXT: cmovpl %r13d, %r10d
+; CHECK-NEXT: movzbl %r9b, %r11d
; CHECK-NEXT: cmovpl %r8d, %r10d
; CHECK-NEXT: movzbl %r10b, %r9d
; CHECK-NEXT: shll $8, %r9d
@@ -1319,14 +1307,13 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: orl %ebp, %r11d
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Reload
; CHECK-NEXT: shrl $20, %r14d
-; CHECK-NEXT: movl %r14d, %ebx
-; CHECK-NEXT: andl $1, %ebx
-; CHECK-NEXT: xorl %ebp, %ebp
+; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: testl $524287, %r15d # imm = 0x7FFFF
-; CHECK-NEXT: setne %bpl
-; CHECK-NEXT: orl %ebx, %ebp
+; CHECK-NEXT: setne %bl
+; CHECK-NEXT: orl %r14d, %ebx
; CHECK-NEXT: shrl $19, %r15d
-; CHECK-NEXT: andl %ebp, %r15d
+; CHECK-NEXT: andl %ebx, %r15d
+; CHECK-NEXT: andl $1, %r15d
; CHECK-NEXT: addl %r14d, %r15d
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: cmpl $8, %r15d
@@ -1359,14 +1346,13 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: leal (%rdi,%r9,8), %r9d
; CHECK-NEXT: orl %ecx, %r9d
; CHECK-NEXT: shrl $20, %esi
-; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: andl $1, %ecx
-; CHECK-NEXT: xorl %r11d, %r11d
+; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl $524287, %edx # imm = 0x7FFFF
-; CHECK-NEXT: setne %r11b
-; CHECK-NEXT: orl %ecx, %r11d
+; CHECK-NEXT: setne %cl
+; CHECK-NEXT: orl %esi, %ecx
; CHECK-NEXT: shrl $19, %edx
-; CHECK-NEXT: andl %r11d, %edx
+; CHECK-NEXT: andl %ecx, %edx
+; CHECK-NEXT: andl $1, %edx
; CHECK-NEXT: addl %esi, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl $8, %edx
@@ -1437,13 +1423,12 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: callq frexpf at PLT
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %ecx
; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: movl $8, %ebx
; CHECK-NEXT: movl $8, %eax
; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: cmpl $31, %eax
; CHECK-NEXT: movl $31, %ecx
; CHECK-NEXT: cmovael %ecx, %eax
-; CHECK-NEXT: movl $31, %r14d
+; CHECK-NEXT: movl $31, %ebp
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: adcl $-1, %ecx
@@ -1451,26 +1436,26 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: movl %r12d, %edx
; CHECK-NEXT: andl $8388607, %edx # imm = 0x7FFFFF
; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: leal 8388608(%rdx), %r15d
-; CHECK-NEXT: movl %r15d, %edx
+; CHECK-NEXT: leal 8388608(%rdx), %ebx
+; CHECK-NEXT: movl %ebx, %edx
; CHECK-NEXT: shrl %cl, %edx
; CHECK-NEXT: movl $1, %esi
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK-NEXT: shll %cl, %esi
; CHECK-NEXT: decl %esi
; CHECK-NEXT: xorl %edi, %edi
-; CHECK-NEXT: testl %esi, %r15d
+; CHECK-NEXT: testl %esi, %ebx
; CHECK-NEXT: setne %dil
; CHECK-NEXT: movl %eax, %ecx
-; CHECK-NEXT: shrl %cl, %r15d
-; CHECK-NEXT: movl %r15d, (%rsp) # 4-byte Spill
-; CHECK-NEXT: andl $1, %r15d
-; CHECK-NEXT: orl %edi, %r15d
-; CHECK-NEXT: andl %edx, %r15d
+; CHECK-NEXT: shrl %cl, %ebx
+; CHECK-NEXT: movl %ebx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: andl $1, %ebx
+; CHECK-NEXT: orl %edi, %ebx
+; CHECK-NEXT: andl %edx, %ebx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl $1, %eax
-; CHECK-NEXT: cmovbl %ecx, %r15d
-; CHECK-NEXT: xorl %ebp, %ebp
+; CHECK-NEXT: cmovbl %ecx, %ebx
+; CHECK-NEXT: xorl %r15d, %r15d
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq frexpf at PLT
@@ -1479,7 +1464,8 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: movl $8, %eax
; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: cmpl $31, %eax
-; CHECK-NEXT: cmovael %r14d, %eax
+; CHECK-NEXT: cmovael %ebp, %eax
+; CHECK-NEXT: movl $31, %ebp
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: adcl $-1, %ecx
@@ -1504,7 +1490,7 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: orl %edi, %r13d
; CHECK-NEXT: andl %edx, %r13d
; CHECK-NEXT: cmpl $1, %eax
-; CHECK-NEXT: cmovbl %ebp, %r13d
+; CHECK-NEXT: cmovbl %r15d, %r13d
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -1515,14 +1501,12 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: movl $8, %eax
; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: cmpl $31, %eax
-; CHECK-NEXT: movl $31, %ecx
-; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: cmovael %ebp, %eax
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: adcl $-1, %ecx
-; CHECK-NEXT: movd %xmm0, %edx
-; CHECK-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
-; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
+; CHECK-NEXT: movd %xmm0, %r15d
+; CHECK-NEXT: movl %r15d, %edx
; CHECK-NEXT: andl $8388607, %edx # imm = 0x7FFFFF
; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: leal 8388608(%rdx), %ebp
@@ -1551,12 +1535,14 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: callq frexpf at PLT
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: subl %eax, %ebx
-; CHECK-NEXT: cmpl $31, %ebx
+; CHECK-NEXT: movl $8, %edx
+; CHECK-NEXT: subl %eax, %edx
+; CHECK-NEXT: cmpl $31, %edx
; CHECK-NEXT: movl $31, %eax
-; CHECK-NEXT: cmovael %eax, %ebx
-; CHECK-NEXT: cmpl $1, %ebx
-; CHECK-NEXT: movl %ebx, %ecx
+; CHECK-NEXT: cmovael %eax, %edx
+; CHECK-NEXT: cmpl $1, %edx
+; CHECK-NEXT: movl %edx, %ecx
+; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: adcl $-1, %ecx
; CHECK-NEXT: movd %xmm0, %edx
; CHECK-NEXT: movl %edx, %esi
@@ -1565,55 +1551,55 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: movl %edi, %r8d
; CHECK-NEXT: shrl %cl, %r8d
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
-; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: shll %cl, %eax
-; CHECK-NEXT: decl %eax
+; CHECK-NEXT: movl $1, %r9d
+; CHECK-NEXT: shll %cl, %r9d
+; CHECK-NEXT: decl %r9d
+; CHECK-NEXT: movl %r9d, %ecx
; CHECK-NEXT: xorl %r9d, %r9d
-; CHECK-NEXT: testl %eax, %edi
+; CHECK-NEXT: testl %ecx, %edi
; CHECK-NEXT: setne %r9b
-; CHECK-NEXT: movl %ebx, %ecx
+; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl %cl, %edi
; CHECK-NEXT: movl %edi, %ecx
; CHECK-NEXT: andl $1, %ecx
; CHECK-NEXT: orl %r9d, %ecx
; CHECK-NEXT: andl %r8d, %ecx
-; CHECK-NEXT: cmpl $1, %ebx
+; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: movl $0, %eax
; CHECK-NEXT: cmovbl %eax, %ecx
-; CHECK-NEXT: addl (%rsp), %r15d # 4-byte Folded Reload
+; CHECK-NEXT: addl {{[-0-9]+}}(%r{{[sb]}}p), %ebx # 4-byte Folded Reload
; CHECK-NEXT: xorl %r8d, %r8d
-; CHECK-NEXT: cmpl $4, %r15d
-; CHECK-NEXT: cmovgel %eax, %r15d
+; CHECK-NEXT: cmpl $4, %ebx
+; CHECK-NEXT: cmovgel %eax, %ebx
; CHECK-NEXT: setge %r8b
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; CHECK-NEXT: movd %xmm2, %r9d
; CHECK-NEXT: shrl $24, %r9d
; CHECK-NEXT: andl $-128, %r9d
; CHECK-NEXT: leal (%r9,%r8,4), %r8d
-; CHECK-NEXT: orl %r15d, %r8d
-; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r11 # 8-byte Reload
-; CHECK-NEXT: shrl $21, %r11d
-; CHECK-NEXT: movl %r11d, %r10d
-; CHECK-NEXT: movq %r11, %rbx
-; CHECK-NEXT: andl $1, %r10d
-; CHECK-NEXT: xorl %r11d, %r11d
+; CHECK-NEXT: orl %ebx, %r8d
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: shrl $21, %eax
+; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: testl $1048575, %r12d # imm = 0xFFFFF
-; CHECK-NEXT: setne %r11b
-; CHECK-NEXT: orl %r10d, %r11d
+; CHECK-NEXT: setne %r10b
+; CHECK-NEXT: orl %eax, %r10d
; CHECK-NEXT: shrl $20, %r12d
-; CHECK-NEXT: andl %r11d, %r12d
-; CHECK-NEXT: addl %ebx, %r12d
+; CHECK-NEXT: andl %r10d, %r12d
+; CHECK-NEXT: andl $1, %r12d
+; CHECK-NEXT: addl %eax, %r12d
; CHECK-NEXT: xorl %r11d, %r11d
; CHECK-NEXT: cmpl $4, %r12d
+; CHECK-NEXT: movl $0, %eax
; CHECK-NEXT: cmovgel %eax, %r12d
; CHECK-NEXT: setge %r11b
-; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r15 # 8-byte Reload
-; CHECK-NEXT: leal (%r15,%r11), %r10d
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: leal (%rax,%r11), %r10d
; CHECK-NEXT: leal 56(,%r10,4), %ebx
; CHECK-NEXT: movl %r9d, %r10d
; CHECK-NEXT: orl %r12d, %r10d
; CHECK-NEXT: orl %ebx, %r10d
-; CHECK-NEXT: leal 14(%r15,%r11), %r11d
+; CHECK-NEXT: leal 14(%rax,%r11), %r11d
; CHECK-NEXT: testl %r11d, %r11d
; CHECK-NEXT: cmovlel %r8d, %r10d
; CHECK-NEXT: cmpl $4, %r12d
@@ -1645,6 +1631,7 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: addl {{[-0-9]+}}(%r{{[sb]}}p), %r13d # 4-byte Folded Reload
; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: cmpl $4, %r13d
+; CHECK-NEXT: movl $0, %eax
; CHECK-NEXT: cmovgel %eax, %r13d
; CHECK-NEXT: setge %r10b
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
@@ -1653,31 +1640,29 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: andl $-128, %r11d
; CHECK-NEXT: leal (%r11,%r10,4), %r10d
; CHECK-NEXT: orl %r13d, %r10d
-; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r15 # 8-byte Reload
-; CHECK-NEXT: shrl $21, %r15d
-; CHECK-NEXT: movl %r15d, %ebx
-; CHECK-NEXT: movq %r15, %r12
-; CHECK-NEXT: andl $1, %ebx
-; CHECK-NEXT: xorl %r15d, %r15d
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Reload
+; CHECK-NEXT: shrl $21, %r12d
+; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: testl $1048575, %r14d # imm = 0xFFFFF
-; CHECK-NEXT: setne %r15b
-; CHECK-NEXT: orl %ebx, %r15d
+; CHECK-NEXT: setne %bl
+; CHECK-NEXT: orl %r12d, %ebx
; CHECK-NEXT: shrl $20, %r14d
-; CHECK-NEXT: andl %r15d, %r14d
+; CHECK-NEXT: andl %ebx, %r14d
+; CHECK-NEXT: andl $1, %r14d
; CHECK-NEXT: addl %r12d, %r14d
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: cmpl $4, %r14d
; CHECK-NEXT: cmovgel %eax, %r14d
; CHECK-NEXT: setge %bl
-; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Reload
-; CHECK-NEXT: leal (%r13,%rbx), %r15d
-; CHECK-NEXT: leal 56(,%r15,4), %r15d
-; CHECK-NEXT: movl %r11d, %r12d
-; CHECK-NEXT: orl %r14d, %r12d
-; CHECK-NEXT: orl %r15d, %r12d
-; CHECK-NEXT: leal 14(%r13,%rbx), %ebx
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: leal (%rax,%rbx), %r12d
+; CHECK-NEXT: leal 56(,%r12,4), %r12d
+; CHECK-NEXT: movl %r11d, %r13d
+; CHECK-NEXT: orl %r14d, %r13d
+; CHECK-NEXT: orl %r12d, %r13d
+; CHECK-NEXT: leal 14(%rax,%rbx), %ebx
; CHECK-NEXT: testl %ebx, %ebx
-; CHECK-NEXT: cmovlel %r10d, %r12d
+; CHECK-NEXT: cmovlel %r10d, %r13d
; CHECK-NEXT: cmpl $4, %r14d
; CHECK-NEXT: setge %r10b
; CHECK-NEXT: cmpl $30, %ebx
@@ -1688,10 +1673,10 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: orb %r14b, %r10b
; CHECK-NEXT: testb %r10b, %r10b
; CHECK-NEXT: leal 124(%r11), %r10d
-; CHECK-NEXT: cmovnel %r10d, %r12d
+; CHECK-NEXT: cmovnel %r10d, %r13d
; CHECK-NEXT: ucomiss %xmm0, %xmm4
-; CHECK-NEXT: cmovnel %r12d, %r11d
-; CHECK-NEXT: cmovpl %r12d, %r11d
+; CHECK-NEXT: cmovnel %r13d, %r11d
+; CHECK-NEXT: cmovpl %r13d, %r11d
; CHECK-NEXT: movaps %xmm4, %xmm3
; CHECK-NEXT: andps %xmm1, %xmm3
; CHECK-NEXT: ucomiss %xmm2, %xmm3
@@ -1702,6 +1687,7 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: addl {{[-0-9]+}}(%r{{[sb]}}p), %ebp # 4-byte Folded Reload
; CHECK-NEXT: xorl %r11d, %r11d
; CHECK-NEXT: cmpl $4, %ebp
+; CHECK-NEXT: movl $0, %eax
; CHECK-NEXT: cmovgel %eax, %ebp
; CHECK-NEXT: setge %r11b
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
@@ -1712,33 +1698,28 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: orl %ebp, %r11d
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Reload
; CHECK-NEXT: shrl $21, %r14d
-; CHECK-NEXT: movl %r14d, %ebp
-; CHECK-NEXT: movq %r14, %r15
-; CHECK-NEXT: andl $1, %ebp
-; CHECK-NEXT: xorl %r14d, %r14d
-; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %r12d # 4-byte Reload
-; CHECK-NEXT: testl $1048575, %r12d # imm = 0xFFFFF
-; CHECK-NEXT: setne %r14b
-; CHECK-NEXT: orl %ebp, %r14d
-; CHECK-NEXT: movl %r12d, %ebp
-; CHECK-NEXT: shrl $20, %ebp
-; CHECK-NEXT: andl %r14d, %ebp
-; CHECK-NEXT: addl %r15d, %ebp
+; CHECK-NEXT: xorl %ebp, %ebp
+; CHECK-NEXT: testl $1048575, %r15d # imm = 0xFFFFF
+; CHECK-NEXT: setne %bpl
+; CHECK-NEXT: orl %r14d, %ebp
+; CHECK-NEXT: shrl $20, %r15d
+; CHECK-NEXT: andl %ebp, %r15d
+; CHECK-NEXT: andl $1, %r15d
+; CHECK-NEXT: addl %r14d, %r15d
; CHECK-NEXT: xorl %r14d, %r14d
-; CHECK-NEXT: cmpl $4, %ebp
-; CHECK-NEXT: cmovgel %eax, %ebp
-; CHECK-NEXT: movl %ebp, %r13d
+; CHECK-NEXT: cmpl $4, %r15d
+; CHECK-NEXT: cmovgel %eax, %r15d
; CHECK-NEXT: setge %r14b
-; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Reload
-; CHECK-NEXT: leal (%r12,%r14), %r15d
-; CHECK-NEXT: leal 56(,%r15,4), %ebp
-; CHECK-NEXT: movl %ebx, %r15d
-; CHECK-NEXT: orl %r13d, %r15d
-; CHECK-NEXT: orl %ebp, %r15d
-; CHECK-NEXT: leal 14(%r12,%r14), %ebp
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Reload
+; CHECK-NEXT: leal (%r13,%r14), %r12d
+; CHECK-NEXT: leal 56(,%r12,4), %ebp
+; CHECK-NEXT: movl %ebx, %r12d
+; CHECK-NEXT: orl %r15d, %r12d
+; CHECK-NEXT: orl %ebp, %r12d
+; CHECK-NEXT: leal 14(%r13,%r14), %ebp
; CHECK-NEXT: testl %ebp, %ebp
-; CHECK-NEXT: cmovlel %r11d, %r15d
-; CHECK-NEXT: cmpl $4, %r13d
+; CHECK-NEXT: cmovlel %r11d, %r12d
+; CHECK-NEXT: cmpl $4, %r15d
; CHECK-NEXT: setge %r11b
; CHECK-NEXT: cmpl $30, %ebp
; CHECK-NEXT: sete %r14b
@@ -1748,10 +1729,10 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: orb %r14b, %r11b
; CHECK-NEXT: testb %r11b, %r11b
; CHECK-NEXT: leal 124(%rbx), %r11d
-; CHECK-NEXT: cmovnel %r11d, %r15d
+; CHECK-NEXT: cmovnel %r11d, %r12d
; CHECK-NEXT: ucomiss %xmm0, %xmm4
-; CHECK-NEXT: cmovnel %r15d, %ebx
-; CHECK-NEXT: cmovpl %r15d, %ebx
+; CHECK-NEXT: cmovnel %r12d, %ebx
+; CHECK-NEXT: cmovpl %r12d, %ebx
; CHECK-NEXT: movaps %xmm4, %xmm3
; CHECK-NEXT: andps %xmm1, %xmm3
; CHECK-NEXT: ucomiss %xmm2, %xmm3
@@ -1771,14 +1752,13 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: leal (%rdi,%rbx,4), %ebx
; CHECK-NEXT: orl %ecx, %ebx
; CHECK-NEXT: shrl $21, %esi
-; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: andl $1, %ecx
-; CHECK-NEXT: xorl %ebp, %ebp
+; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl $1048575, %edx # imm = 0xFFFFF
-; CHECK-NEXT: setne %bpl
-; CHECK-NEXT: orl %ecx, %ebp
+; CHECK-NEXT: setne %cl
+; CHECK-NEXT: orl %esi, %ecx
; CHECK-NEXT: shrl $20, %edx
-; CHECK-NEXT: andl %ebp, %edx
+; CHECK-NEXT: andl %ecx, %edx
+; CHECK-NEXT: andl $1, %edx
; CHECK-NEXT: addl %esi, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl $4, %edx
@@ -1887,30 +1867,28 @@ define <2 x i8> @to_f8e4m3fn_v2f16(<2 x half> %x) {
; CHECK-NEXT: movl %r13d, %eax
; CHECK-NEXT: andl $1023, %eax # imm = 0x3FF
; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT: leal 1024(%rax), %edi
-; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: leal 1024(%rax), %r12d
+; CHECK-NEXT: movl %r12d, %eax
; CHECK-NEXT: movl %r14d, %ecx
; CHECK-NEXT: shrl %cl, %eax
; CHECK-NEXT: movl $1, %r15d
; CHECK-NEXT: movl $1, %edx
; CHECK-NEXT: shll %cl, %edx
; CHECK-NEXT: decl %edx
-; CHECK-NEXT: xorl %esi, %esi
-; CHECK-NEXT: movl %edi, %r14d
-; CHECK-NEXT: testw %dx, %r14w
-; CHECK-NEXT: setne %sil
+; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: testw %dx, %r12w
+; CHECK-NEXT: setne %r14b
; CHECK-NEXT: movl %ebp, %ecx
-; CHECK-NEXT: shrl %cl, %r14d
-; CHECK-NEXT: movl %r14d, %r12d
-; CHECK-NEXT: andl $1, %r12d
-; CHECK-NEXT: orl %esi, %r12d
-; CHECK-NEXT: andl %eax, %r12d
+; CHECK-NEXT: shrl %cl, %r12d
+; CHECK-NEXT: orl %r12d, %r14d
+; CHECK-NEXT: andl %eax, %r14d
+; CHECK-NEXT: andl $1, %r14d
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpw $1, %bp
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: psrld $16, %xmm0
; CHECK-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; CHECK-NEXT: cmovbl %eax, %r12d
+; CHECK-NEXT: cmovbl %eax, %r14d
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: movd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
@@ -1928,36 +1906,35 @@ define <2 x i8> @to_f8e4m3fn_v2f16(<2 x half> %x) {
; CHECK-NEXT: pextrw $0, %xmm0, %eax
; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: andl $1023, %edx # imm = 0x3FF
-; CHECK-NEXT: leal 1024(%rdx), %esi
-; CHECK-NEXT: movl %esi, %edi
+; CHECK-NEXT: leal 1024(%rdx), %edi
+; CHECK-NEXT: movl %edi, %r8d
; CHECK-NEXT: movl %ebp, %ecx
-; CHECK-NEXT: shrl %cl, %edi
+; CHECK-NEXT: shrl %cl, %r8d
; CHECK-NEXT: shll %cl, %r15d
; CHECK-NEXT: decl %r15d
-; CHECK-NEXT: xorl %r8d, %r8d
-; CHECK-NEXT: testw %r15w, %si
-; CHECK-NEXT: setne %r8b
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: testw %r15w, %di
+; CHECK-NEXT: setne %sil
; CHECK-NEXT: movl %ebx, %ecx
-; CHECK-NEXT: shrl %cl, %esi
-; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: andl $1, %ecx
-; CHECK-NEXT: orl %r8d, %ecx
-; CHECK-NEXT: andl %edi, %ecx
+; CHECK-NEXT: shrl %cl, %edi
+; CHECK-NEXT: orl %edi, %esi
+; CHECK-NEXT: andl %r8d, %esi
+; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: cmpw $1, %bx
; CHECK-NEXT: movl $0, %r8d
-; CHECK-NEXT: cmovbl %r8d, %ecx
-; CHECK-NEXT: addl %r14d, %r12d
-; CHECK-NEXT: xorl %edi, %edi
-; CHECK-NEXT: cmpw $8, %r12w
-; CHECK-NEXT: cmovgel %r8d, %r12d
+; CHECK-NEXT: cmovbl %r8d, %esi
+; CHECK-NEXT: addl %r12d, %r14d
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpw $8, %r14w
+; CHECK-NEXT: cmovgel %r8d, %r14d
; CHECK-NEXT: movl $0, %r11d
-; CHECK-NEXT: setge %dil
+; CHECK-NEXT: setge %cl
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: pextrw $0, %xmm0, %r8d
; CHECK-NEXT: shrl $8, %r8d
; CHECK-NEXT: andl $128, %r8d
-; CHECK-NEXT: leal (%r8,%rdi,8), %edi
-; CHECK-NEXT: orl %r12d, %edi
+; CHECK-NEXT: leal (%r8,%rcx,8), %ecx
+; CHECK-NEXT: orl %r14d, %ecx
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Reload
; CHECK-NEXT: shrl $7, %r10d
; CHECK-NEXT: movl %r10d, %r9d
@@ -1981,58 +1958,58 @@ define <2 x i8> @to_f8e4m3fn_v2f16(<2 x half> %x) {
; CHECK-NEXT: orl %r10d, %r13d
; CHECK-NEXT: leal 6(%rbx,%r9), %r9d
; CHECK-NEXT: testw %r9w, %r9w
-; CHECK-NEXT: cmovlel %edi, %r13d
+; CHECK-NEXT: cmovlel %ecx, %r13d
; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm0, %xmm1
; CHECK-NEXT: cmovnel %r13d, %r8d
; CHECK-NEXT: cmovpl %r13d, %r8d
-; CHECK-NEXT: movl $127, %edi
-; CHECK-NEXT: cmovpl %edi, %r8d
+; CHECK-NEXT: movl $127, %ecx
+; CHECK-NEXT: cmovpl %ecx, %r8d
; CHECK-NEXT: movzbl %r8b, %r8d
-; CHECK-NEXT: addl %esi, %ecx
+; CHECK-NEXT: addl %edi, %esi
; CHECK-NEXT: xorl %r9d, %r9d
-; CHECK-NEXT: cmpw $8, %cx
-; CHECK-NEXT: cmovgel %r11d, %ecx
+; CHECK-NEXT: cmpw $8, %si
+; CHECK-NEXT: cmovgel %r11d, %esi
; CHECK-NEXT: setge %r9b
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; CHECK-NEXT: pextrw $0, %xmm1, %esi
-; CHECK-NEXT: shrl $8, %esi
-; CHECK-NEXT: andl $128, %esi
-; CHECK-NEXT: leal (%rsi,%r9,8), %r9d
-; CHECK-NEXT: orl %ecx, %r9d
+; CHECK-NEXT: pextrw $0, %xmm1, %edi
+; CHECK-NEXT: shrl $8, %edi
+; CHECK-NEXT: andl $128, %edi
+; CHECK-NEXT: leal (%rdi,%r9,8), %r9d
+; CHECK-NEXT: orl %esi, %r9d
; CHECK-NEXT: shrl $7, %edx
-; CHECK-NEXT: movl %edx, %ecx
-; CHECK-NEXT: andl $1, %ecx
+; CHECK-NEXT: movl %edx, %esi
+; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: xorl %r10d, %r10d
; CHECK-NEXT: testb $63, %al
; CHECK-NEXT: setne %r10b
-; CHECK-NEXT: orl %ecx, %r10d
+; CHECK-NEXT: orl %esi, %r10d
; CHECK-NEXT: shrl $6, %eax
; CHECK-NEXT: andl %r10d, %eax
; CHECK-NEXT: addl %edx, %eax
-; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: cmpw $8, %ax
; CHECK-NEXT: cmovgel %r11d, %eax
-; CHECK-NEXT: setge %cl
+; CHECK-NEXT: setge %dl
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Reload
-; CHECK-NEXT: leal (%r10,%rcx), %edx
-; CHECK-NEXT: leal 48(,%rdx,8), %edx
+; CHECK-NEXT: leal (%r10,%rdx), %esi
+; CHECK-NEXT: leal 48(,%rsi,8), %esi
+; CHECK-NEXT: orl %edi, %eax
; CHECK-NEXT: orl %esi, %eax
-; CHECK-NEXT: orl %edx, %eax
-; CHECK-NEXT: leal 6(%r10,%rcx), %ecx
-; CHECK-NEXT: testw %cx, %cx
+; CHECK-NEXT: leal 6(%r10,%rdx), %edx
+; CHECK-NEXT: testw %dx, %dx
; CHECK-NEXT: cmovlel %r9d, %eax
; CHECK-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm0, %xmm1
-; CHECK-NEXT: cmovnel %eax, %esi
-; CHECK-NEXT: cmovpl %eax, %esi
-; CHECK-NEXT: cmovpl %edi, %esi
-; CHECK-NEXT: shll $8, %esi
-; CHECK-NEXT: orl %r8d, %esi
-; CHECK-NEXT: movd %esi, %xmm0
+; CHECK-NEXT: cmovnel %eax, %edi
+; CHECK-NEXT: cmovpl %eax, %edi
+; CHECK-NEXT: cmovpl %ecx, %edi
+; CHECK-NEXT: shll $8, %edi
+; CHECK-NEXT: orl %r8d, %edi
+; CHECK-NEXT: movd %edi, %xmm0
; CHECK-NEXT: addq $88, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 56
; CHECK-NEXT: popq %rbx
@@ -2088,35 +2065,34 @@ define i8 @to_f8e5m2_from_f16(half %x) {
; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: andl $1023, %edx # imm = 0x3FF
; CHECK-NEXT: leal 1024(%rdx), %esi
-; CHECK-NEXT: movl %esi, %edi
+; CHECK-NEXT: movl %esi, %r8d
; CHECK-NEXT: movl %ebp, %ecx
-; CHECK-NEXT: shrl %cl, %edi
-; CHECK-NEXT: movl $1, %r8d
-; CHECK-NEXT: shll %cl, %r8d
-; CHECK-NEXT: decl %r8d
-; CHECK-NEXT: xorl %r9d, %r9d
-; CHECK-NEXT: testw %r8w, %si
-; CHECK-NEXT: setne %r9b
+; CHECK-NEXT: shrl %cl, %r8d
+; CHECK-NEXT: movl $1, %r9d
+; CHECK-NEXT: shll %cl, %r9d
+; CHECK-NEXT: decl %r9d
+; CHECK-NEXT: xorl %edi, %edi
+; CHECK-NEXT: testw %r9w, %si
+; CHECK-NEXT: setne %dil
; CHECK-NEXT: movl %ebx, %ecx
; CHECK-NEXT: shrl %cl, %esi
-; CHECK-NEXT: movl %esi, %r8d
-; CHECK-NEXT: andl $1, %r8d
-; CHECK-NEXT: orl %r9d, %r8d
-; CHECK-NEXT: andl %edi, %r8d
+; CHECK-NEXT: orl %esi, %edi
+; CHECK-NEXT: andl %r8d, %edi
+; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpw $1, %bx
-; CHECK-NEXT: cmovbl %ecx, %r8d
-; CHECK-NEXT: addl %esi, %r8d
+; CHECK-NEXT: cmovbl %ecx, %edi
+; CHECK-NEXT: addl %esi, %edi
; CHECK-NEXT: xorl %esi, %esi
-; CHECK-NEXT: cmpw $4, %r8w
-; CHECK-NEXT: cmovgel %ecx, %r8d
+; CHECK-NEXT: cmpw $4, %di
+; CHECK-NEXT: cmovgel %ecx, %edi
; CHECK-NEXT: setge %sil
; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: pextrw $0, %xmm1, %ebx
; CHECK-NEXT: shrl $8, %ebx
; CHECK-NEXT: andl $128, %ebx
; CHECK-NEXT: leal (%rbx,%rsi,4), %esi
-; CHECK-NEXT: orl %r8d, %esi
+; CHECK-NEXT: orl %edi, %esi
; CHECK-NEXT: shrl $8, %edx
; CHECK-NEXT: movl %edx, %edi
; CHECK-NEXT: andl $1, %edi
@@ -2235,14 +2211,13 @@ define i8 @to_f8e5m2_from_bf16(bfloat %x) {
; CHECK-NEXT: leal (%rax,%r8,4), %r8d
; CHECK-NEXT: orl %r10d, %r8d
; CHECK-NEXT: shrl $21, %edi
-; CHECK-NEXT: movl %edi, %r9d
-; CHECK-NEXT: andl $1, %r9d
-; CHECK-NEXT: xorl %r10d, %r10d
+; CHECK-NEXT: xorl %r9d, %r9d
; CHECK-NEXT: testl $1048575, %esi # imm = 0xFFFFF
-; CHECK-NEXT: setne %r10b
-; CHECK-NEXT: orl %r9d, %r10d
+; CHECK-NEXT: setne %r9b
+; CHECK-NEXT: orl %edi, %r9d
; CHECK-NEXT: shrl $20, %esi
-; CHECK-NEXT: andl %r10d, %esi
+; CHECK-NEXT: andl %r9d, %esi
+; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: addl %edi, %esi
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: cmpl $4, %esi
@@ -2325,11 +2300,11 @@ define i8 @to_f8e5m2_from_f64(double %x) {
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrq %cl, %r10
; CHECK-NEXT: movl %r10d, %ebx
-; CHECK-NEXT: andl $1, %ebx
; CHECK-NEXT: orl %r11d, %ebx
; CHECK-NEXT: movl %edx, %ecx
; CHECK-NEXT: shrq %cl, %r9
; CHECK-NEXT: andl %ebx, %r9d
+; CHECK-NEXT: andl $1, %r9d
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpq $1, %rax
; CHECK-NEXT: cmovbq %rcx, %r9
@@ -2345,15 +2320,14 @@ define i8 @to_f8e5m2_from_f64(double %x) {
; CHECK-NEXT: leal (%rax,%rdx,4), %edx
; CHECK-NEXT: orq %r9, %rdx
; CHECK-NEXT: shrq $50, %r8
-; CHECK-NEXT: movl %r8d, %r9d
-; CHECK-NEXT: andl $1, %r9d
-; CHECK-NEXT: xorl %r10d, %r10d
-; CHECK-NEXT: movq %rdi, %r11
-; CHECK-NEXT: shlq $15, %r11
-; CHECK-NEXT: setne %r10b
-; CHECK-NEXT: orl %r9d, %r10d
+; CHECK-NEXT: xorl %r9d, %r9d
+; CHECK-NEXT: movq %rdi, %r10
+; CHECK-NEXT: shlq $15, %r10
+; CHECK-NEXT: setne %r9b
+; CHECK-NEXT: orl %r8d, %r9d
; CHECK-NEXT: shrq $49, %rdi
-; CHECK-NEXT: andl %r10d, %edi
+; CHECK-NEXT: andl %r9d, %edi
+; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: addq %r8, %rdi
; CHECK-NEXT: xorl %r8d, %r8d
; CHECK-NEXT: cmpq $4, %rdi
@@ -2451,14 +2425,13 @@ define i8 @to_f8e5m3fnu_dynamic(float %x) {
; CHECK-NEXT: shll $3, %eax
; CHECK-NEXT: orl %r10d, %eax
; CHECK-NEXT: shrl $20, %edi
-; CHECK-NEXT: movl %edi, %r8d
-; CHECK-NEXT: andl $1, %r8d
-; CHECK-NEXT: xorl %r9d, %r9d
+; CHECK-NEXT: xorl %r8d, %r8d
; CHECK-NEXT: testl $524287, %esi # imm = 0x7FFFF
-; CHECK-NEXT: setne %r9b
-; CHECK-NEXT: orl %r8d, %r9d
+; CHECK-NEXT: setne %r8b
+; CHECK-NEXT: orl %edi, %r8d
; CHECK-NEXT: shrl $19, %esi
-; CHECK-NEXT: andl %r9d, %esi
+; CHECK-NEXT: andl %r8d, %esi
+; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: addl %edi, %esi
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: cmpl $8, %esi
@@ -2535,14 +2508,13 @@ define i8 @to_f8e5m3fnu_saturate(float %x) {
; CHECK-NEXT: shll $3, %eax
; CHECK-NEXT: orl %r10d, %eax
; CHECK-NEXT: shrl $20, %edi
-; CHECK-NEXT: movl %edi, %r8d
-; CHECK-NEXT: andl $1, %r8d
-; CHECK-NEXT: xorl %r9d, %r9d
+; CHECK-NEXT: xorl %r8d, %r8d
; CHECK-NEXT: testl $524287, %esi # imm = 0x7FFFF
-; CHECK-NEXT: setne %r9b
-; CHECK-NEXT: orl %r8d, %r9d
+; CHECK-NEXT: setne %r8b
+; CHECK-NEXT: orl %edi, %r8d
; CHECK-NEXT: shrl $19, %esi
-; CHECK-NEXT: andl %r9d, %esi
+; CHECK-NEXT: andl %r8d, %esi
+; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: addl %edi, %esi
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: cmpl $8, %esi
diff --git a/llvm/test/CodeGen/X86/movmsk-cmp.ll b/llvm/test/CodeGen/X86/movmsk-cmp.ll
index 09854d197dcd8..ffb43cab4ca28 100644
--- a/llvm/test/CodeGen/X86/movmsk-cmp.ll
+++ b/llvm/test/CodeGen/X86/movmsk-cmp.ll
@@ -3713,8 +3713,6 @@ define i1 @movmsk_v16i8(<16 x i8> %x, <16 x i8> %y) {
; SSE-NEXT: shrl $15, %ecx
; SSE-NEXT: movl %eax, %edx
; SSE-NEXT: shrl $8, %edx
-; SSE-NEXT: andl $1, %edx
-; SSE-NEXT: andl $8, %eax
; SSE-NEXT: shrl $3, %eax
; SSE-NEXT: xorl %edx, %eax
; SSE-NEXT: andl %ecx, %eax
@@ -3729,8 +3727,6 @@ define i1 @movmsk_v16i8(<16 x i8> %x, <16 x i8> %y) {
; AVX1OR2-NEXT: shrl $15, %ecx
; AVX1OR2-NEXT: movl %eax, %edx
; AVX1OR2-NEXT: shrl $8, %edx
-; AVX1OR2-NEXT: andl $1, %edx
-; AVX1OR2-NEXT: andl $8, %eax
; AVX1OR2-NEXT: shrl $3, %eax
; AVX1OR2-NEXT: xorl %edx, %eax
; AVX1OR2-NEXT: andl %ecx, %eax
@@ -4483,7 +4479,7 @@ define i32 @pr67287(<2 x i64> %broadcast.splatinsert25) {
; SSE2-NEXT: testl %eax, %eax
; SSE2-NEXT: sete %al
; SSE2-NEXT: movd %xmm1, %ecx
-; SSE2-NEXT: xorb $1, %cl
+; SSE2-NEXT: notb %cl
; SSE2-NEXT: testb %cl, %al
; SSE2-NEXT: jne .LBB97_2
; SSE2-NEXT: # %bb.1:
@@ -4501,7 +4497,7 @@ define i32 @pr67287(<2 x i64> %broadcast.splatinsert25) {
; SSE41-NEXT: testl %eax, %eax
; SSE41-NEXT: sete %al
; SSE41-NEXT: movd %xmm0, %ecx
-; SSE41-NEXT: xorb $1, %cl
+; SSE41-NEXT: notb %cl
; SSE41-NEXT: testb %cl, %al
; SSE41-NEXT: jne .LBB97_2
; SSE41-NEXT: # %bb.1:
@@ -4518,7 +4514,7 @@ define i32 @pr67287(<2 x i64> %broadcast.splatinsert25) {
; AVX1-NEXT: vtestpd %xmm0, %xmm0
; AVX1-NEXT: sete %al
; AVX1-NEXT: vmovd %xmm0, %ecx
-; AVX1-NEXT: xorb $1, %cl
+; AVX1-NEXT: notb %cl
; AVX1-NEXT: testb %cl, %al
; AVX1-NEXT: jne .LBB97_2
; AVX1-NEXT: # %bb.1:
@@ -4535,7 +4531,7 @@ define i32 @pr67287(<2 x i64> %broadcast.splatinsert25) {
; AVX2-NEXT: vtestpd %xmm0, %xmm0
; AVX2-NEXT: sete %al
; AVX2-NEXT: vmovd %xmm0, %ecx
-; AVX2-NEXT: xorb $1, %cl
+; AVX2-NEXT: notb %cl
; AVX2-NEXT: testb %cl, %al
; AVX2-NEXT: jne .LBB97_2
; AVX2-NEXT: # %bb.1:
@@ -4553,7 +4549,7 @@ define i32 @pr67287(<2 x i64> %broadcast.splatinsert25) {
; KNL-NEXT: kmovw %k0, %ecx
; KNL-NEXT: testb $3, %cl
; KNL-NEXT: sete %cl
-; KNL-NEXT: xorb $1, %al
+; KNL-NEXT: notb %al
; KNL-NEXT: testb %al, %cl
; KNL-NEXT: jne .LBB97_2
; KNL-NEXT: # %bb.1:
@@ -4571,7 +4567,7 @@ define i32 @pr67287(<2 x i64> %broadcast.splatinsert25) {
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: kmovd %k0, %ecx
-; SKX-NEXT: xorb $1, %cl
+; SKX-NEXT: notb %cl
; SKX-NEXT: testb %cl, %al
; SKX-NEXT: jne .LBB97_2
; SKX-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/X86/pr34137.ll b/llvm/test/CodeGen/X86/pr34137.ll
index 09a5cbb02cc26..643863d61aad3 100644
--- a/llvm/test/CodeGen/X86/pr34137.ll
+++ b/llvm/test/CodeGen/X86/pr34137.ll
@@ -15,10 +15,10 @@ define void @pr34127() {
; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movzwl var_3(%rip), %ecx
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: testl %eax, %ecx
+; CHECK-NEXT: testw %ax, %cx
; CHECK-NEXT: sete %dl
-; CHECK-NEXT: andl %ecx, %edx
-; CHECK-NEXT: movq %rdx, var_212(%rip)
+; CHECK-NEXT: andl %edx, %ecx
+; CHECK-NEXT: movq %rcx, var_212(%rip)
; CHECK-NEXT: movw $0, (%rax)
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/setcc-logic.ll b/llvm/test/CodeGen/X86/setcc-logic.ll
index 1390c666bb4ec..4ca4c12b93120 100644
--- a/llvm/test/CodeGen/X86/setcc-logic.ll
+++ b/llvm/test/CodeGen/X86/setcc-logic.ll
@@ -804,12 +804,10 @@ define i1 @or_cmp_ne(i32 %x) {
define i1 @not_pow2(i8 %x) {
; CHECK-LABEL: not_pow2:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: andb $8, %al
; CHECK-NEXT: testb $3, %dil
-; CHECK-NEXT: setne %cl
-; CHECK-NEXT: shrb $3, %al
-; CHECK-NEXT: andb %cl, %al
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: shrb $3, %dil
+; CHECK-NEXT: andb %dil, %al
; CHECK-NEXT: retq
%a1 = and i8 %x, 3
%a2 = and i8 %x, 8
@@ -823,7 +821,7 @@ define i1 @diff_vars(i8 %x, i8 %y) {
; CHECK-LABEL: diff_vars:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %esi, %eax
-; CHECK-NEXT: andb $8, %al
+; CHECK-NEXT: andb $4, %dil
; CHECK-NEXT: shrb $2, %dil
; CHECK-NEXT: shrb $3, %al
; CHECK-NEXT: andb %dil, %al
@@ -842,7 +840,6 @@ define i1 @nonzero_rhs(i8 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: andb $4, %al
-; CHECK-NEXT: andb $8, %dil
; CHECK-NEXT: cmpb $1, %al
; CHECK-NEXT: setne %al
; CHECK-NEXT: shrb $3, %dil
@@ -859,12 +856,10 @@ define i1 @nonzero_rhs(i8 %x) {
define i1 @mixed_cc(i8 %x) {
; CHECK-LABEL: mixed_cc:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
-; CHECK-NEXT: andb $8, %al
; CHECK-NEXT: testb $4, %dil
-; CHECK-NEXT: sete %cl
-; CHECK-NEXT: shrb $3, %al
-; CHECK-NEXT: andb %cl, %al
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: shrb $3, %dil
+; CHECK-NEXT: andb %dil, %al
; CHECK-NEXT: retq
%a1 = and i8 %x, 4
%a2 = and i8 %x, 8
diff --git a/llvm/test/CodeGen/X86/test-shrink-bug.ll b/llvm/test/CodeGen/X86/test-shrink-bug.ll
index 1d5da42a8c09b..8a6899b8aa032 100644
--- a/llvm/test/CodeGen/X86/test-shrink-bug.ll
+++ b/llvm/test/CodeGen/X86/test-shrink-bug.ll
@@ -67,7 +67,7 @@ define dso_local void @fail(i16 %a, <2 x i8> %b) {
; CHECK-X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; CHECK-X64-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-X64-NEXT: pextrw $1, %xmm0, %eax
-; CHECK-X64-NEXT: xorb $1, %al
+; CHECK-X64-NEXT: notb %al
; CHECK-X64-NEXT: testl $263, %edi # imm = 0x107
; CHECK-X64-NEXT: setne %cl
; CHECK-X64-NEXT: testb %al, %cl
diff --git a/llvm/test/CodeGen/X86/vector-bo-select.ll b/llvm/test/CodeGen/X86/vector-bo-select.ll
index ac27c26768c92..cdbc80dfbe6dd 100644
--- a/llvm/test/CodeGen/X86/vector-bo-select.ll
+++ b/llvm/test/CodeGen/X86/vector-bo-select.ll
@@ -9,10 +9,11 @@ define <4 x float> @fadd_v4f32(<4 x i1> %b, <4 x float> noundef %x, <4 x float>
; SSE2-LABEL: fadd_v4f32:
; SSE2: # %bb.0:
; SSE2-NEXT: pslld $31, %xmm0
-; SSE2-NEXT: psrad $31, %xmm0
-; SSE2-NEXT: pand %xmm0, %xmm2
+; SSE2-NEXT: movdqa %xmm0, %xmm3
+; SSE2-NEXT: psrad $31, %xmm3
+; SSE2-NEXT: pand %xmm2, %xmm3
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE2-NEXT: por %xmm2, %xmm0
+; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -62,17 +63,19 @@ define <8 x float> @fadd_v8f32_commute(<8 x i1> %b, <8 x float> noundef %x, <8 x
; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: punpckhwd {{.*#+}} xmm5 = xmm5[4,4,5,5,6,6,7,7]
; SSE2-NEXT: pslld $31, %xmm5
-; SSE2-NEXT: psrad $31, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; SSE2-NEXT: pand %xmm5, %xmm4
-; SSE2-NEXT: pandn %xmm6, %xmm5
-; SSE2-NEXT: por %xmm4, %xmm5
+; SSE2-NEXT: movdqa %xmm5, %xmm7
+; SSE2-NEXT: pandn %xmm6, %xmm7
+; SSE2-NEXT: psrad $31, %xmm5
+; SSE2-NEXT: pand %xmm4, %xmm5
+; SSE2-NEXT: por %xmm7, %xmm5
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE2-NEXT: pslld $31, %xmm0
+; SSE2-NEXT: movdqa %xmm0, %xmm4
+; SSE2-NEXT: pandn %xmm6, %xmm4
; SSE2-NEXT: psrad $31, %xmm0
-; SSE2-NEXT: pand %xmm0, %xmm3
-; SSE2-NEXT: pandn %xmm6, %xmm0
-; SSE2-NEXT: por %xmm3, %xmm0
+; SSE2-NEXT: pand %xmm3, %xmm0
+; SSE2-NEXT: por %xmm4, %xmm0
; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: addps %xmm2, %xmm5
; SSE2-NEXT: movaps %xmm5, %xmm1
>From 97f631aebff8c80b18e4405bda26fa665e9c5e34 Mon Sep 17 00:00:00 2001
From: Alan Li <me at alanli.org>
Date: Sat, 10 Oct 2026 12:06:45 -0700
Subject: [PATCH 2/4] fix(SelectionDAG): isolate retry known bits
The LHS demanded-bits query already excludes bits masked by the RHS.
Its returned facts cannot safely reduce the RHS demand in turn.
Query LHS known bits independently, and preserve the original RHS facts
when a reduced-demand retry does not simplify. Defer the retry until
existing folds fail and skip constant or shared RHS operands.
Refresh the affected X86 atomic codegen checks.
Refs #230700
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 50 +++--
llvm/test/CodeGen/X86/atomic-rm-bit-test.ll | 172 ++++++++----------
2 files changed, 111 insertions(+), 111 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 1c7af4e103673..0991df43d06c1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1660,14 +1660,6 @@ bool TargetLowering::SimplifyDemandedBits(
Known2, TLO, Depth + 1))
return true;
- // Retry the RHS with the demand reduced by the unchanged LHS.
- APInt RHSDemandedBits = ~Known2.Zero & DemandedBits;
- if (RHSDemandedBits != DemandedBits) {
- if (SimplifyDemandedBits(Op1, RHSDemandedBits, DemandedElts, Known, TLO,
- Depth + 1))
- return true;
- }
-
// If all of the demanded bits are known one on one side, return the other.
// These bits cannot contribute to the result of the 'and'.
if (DemandedBits.isSubsetOf(Known2.Zero | Known.One))
@@ -1699,6 +1691,21 @@ bool TargetLowering::SimplifyDemandedBits(
}
}
+ // Try reducing the RHS demand using independent LHS known bits. Known2
+ // may only be valid for the demand already reduced by the RHS.
+ if (Op1.hasOneUse() && !isConstOrConstSplat(Op1, DemandedElts)) {
+ KnownBits LHSKnown =
+ TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1);
+ APInt RHSDemandedBits = ~LHSKnown.Zero & DemandedBits;
+ if (RHSDemandedBits != DemandedBits) {
+ // A failed retry must not replace Known with reduced-demand facts.
+ KnownBits RetryKnown;
+ if (SimplifyDemandedBits(Op1, RHSDemandedBits, DemandedElts, RetryKnown,
+ TLO, Depth + 1))
+ return true;
+ }
+ }
+
Known &= Known2;
break;
}
@@ -1717,16 +1724,6 @@ bool TargetLowering::SimplifyDemandedBits(
return true;
}
- // Retry the RHS with the demand reduced by the unchanged LHS.
- APInt RHSDemandedBits = ~Known2.One & DemandedBits;
- if (RHSDemandedBits != DemandedBits) {
- if (SimplifyDemandedBits(Op1, RHSDemandedBits, DemandedElts, Known, TLO,
- Depth + 1)) {
- Op->dropFlags(SDNodeFlags::Disjoint);
- return true;
- }
- }
-
// If all of the demanded bits are known zero on one side, return the other.
// These bits cannot contribute to the result of the 'or'.
if (DemandedBits.isSubsetOf(Known2.One | Known.Zero))
@@ -1769,6 +1766,23 @@ bool TargetLowering::SimplifyDemandedBits(
}
}
+ // Try reducing the RHS demand using independent LHS known bits. Known2
+ // may only be valid for the demand already reduced by the RHS.
+ if (Op1.hasOneUse() && !isConstOrConstSplat(Op1, DemandedElts)) {
+ KnownBits LHSKnown =
+ TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1);
+ APInt RHSDemandedBits = ~LHSKnown.One & DemandedBits;
+ if (RHSDemandedBits != DemandedBits) {
+ // A failed retry must not replace Known with reduced-demand facts.
+ KnownBits RetryKnown;
+ if (SimplifyDemandedBits(Op1, RHSDemandedBits, DemandedElts, RetryKnown,
+ TLO, Depth + 1)) {
+ Op->dropFlags(SDNodeFlags::Disjoint);
+ return true;
+ }
+ }
+ }
+
Known |= Known2;
break;
}
diff --git a/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll b/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll
index 169fdf90a6470..c86dd4db55f4a 100644
--- a/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll
+++ b/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll
@@ -1085,11 +1085,10 @@ define zeroext i16 @atomic_shl1_small_mask_xor_16_gpr_valz(ptr %v, i16 zeroext %
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB19_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %edx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: btl %ecx, %edx
-; X86-NEXT: setae %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: btl %ecx, %eax
+; X86-NEXT: setae %dl
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -1112,11 +1111,10 @@ define zeroext i16 @atomic_shl1_small_mask_xor_16_gpr_valz(ptr %v, i16 zeroext %
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB19_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: btl %ecx, %edx
-; X64-NEXT: setae %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: btl %ecx, %eax
+; X64-NEXT: setae %dl
+; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
entry:
%0 = and i16 %c, 7
@@ -1218,12 +1216,11 @@ define zeroext i16 @atomic_shl1_mask1_xor_16_gpr_valz(ptr %v, i16 zeroext %c) no
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB21_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %edx
; X86-NEXT: andl $15, %ecx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: btl %ecx, %edx
-; X86-NEXT: setae %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: btl %ecx, %eax
+; X86-NEXT: setae %dl
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -1244,12 +1241,11 @@ define zeroext i16 @atomic_shl1_mask1_xor_16_gpr_valz(ptr %v, i16 zeroext %c) no
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB21_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
; X64-NEXT: andl $15, %ecx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: btl %ecx, %edx
-; X64-NEXT: setae %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: btl %ecx, %eax
+; X64-NEXT: setae %dl
+; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
entry:
%conv = zext i16 %c to i32
@@ -1474,11 +1470,10 @@ define zeroext i16 @atomic_shl1_small_mask_xor_16_gpr_valnz(ptr %v, i16 zeroext
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB25_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %edx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: btl %ecx, %edx
-; X86-NEXT: setb %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: btl %ecx, %eax
+; X86-NEXT: setb %dl
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -1501,11 +1496,10 @@ define zeroext i16 @atomic_shl1_small_mask_xor_16_gpr_valnz(ptr %v, i16 zeroext
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB25_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: btl %ecx, %edx
-; X64-NEXT: setb %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: btl %ecx, %eax
+; X64-NEXT: setb %dl
+; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
entry:
%0 = and i16 %c, 7
@@ -1607,12 +1601,11 @@ define zeroext i16 @atomic_shl1_mask1_xor_16_gpr_valnz(ptr %v, i16 zeroext %c) n
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB27_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %edx
; X86-NEXT: andl $15, %ecx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: btl %ecx, %edx
-; X86-NEXT: setb %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: btl %ecx, %eax
+; X86-NEXT: setb %dl
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -1633,12 +1626,11 @@ define zeroext i16 @atomic_shl1_mask1_xor_16_gpr_valnz(ptr %v, i16 zeroext %c) n
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB27_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
; X64-NEXT: andl $15, %ecx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: btl %ecx, %edx
-; X64-NEXT: setb %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: btl %ecx, %eax
+; X64-NEXT: setb %dl
+; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
entry:
%conv = zext i16 %c to i32
@@ -1863,31 +1855,31 @@ define zeroext i16 @atomic_shl1_small_mask_xor_16_gpr_brz(ptr %v, i16 zeroext %c
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: andl $7, %ecx
-; X86-NEXT: movl $1, %esi
-; X86-NEXT: shll %cl, %esi
-; X86-NEXT: movzwl (%edx), %eax
-; X86-NEXT: movzwl %si, %esi
+; X86-NEXT: movl $1, %edx
+; X86-NEXT: shll %cl, %edx
+; X86-NEXT: movzwl (%esi), %eax
+; X86-NEXT: movzwl %dx, %edx
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB31_1: # %atomicrmw.start
; X86-NEXT: # =>This Inner Loop Header: Depth=1
; X86-NEXT: movl %eax, %edi
-; X86-NEXT: xorl %esi, %edi
+; X86-NEXT: xorl %edx, %edi
; X86-NEXT: # kill: def $ax killed $ax killed $eax
-; X86-NEXT: lock cmpxchgw %di, (%edx)
+; X86-NEXT: lock cmpxchgw %di, (%esi)
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB31_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %esi
-; X86-NEXT: movw $123, %ax
-; X86-NEXT: btl %ecx, %esi
+; X86-NEXT: movw $123, %dx
+; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jb .LBB31_4
; X86-NEXT: # %bb.3: # %if.then
; X86-NEXT: movzwl %cx, %eax
-; X86-NEXT: movzwl (%edx,%eax,2), %eax
+; X86-NEXT: movzwl (%esi,%eax,2), %edx
; X86-NEXT: .LBB31_4: # %return
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -1910,15 +1902,16 @@ define zeroext i16 @atomic_shl1_small_mask_xor_16_gpr_brz(ptr %v, i16 zeroext %c
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB31_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
-; X64-NEXT: movw $123, %ax
-; X64-NEXT: btl %ecx, %edx
+; X64-NEXT: movw $123, %dx
+; X64-NEXT: btl %ecx, %eax
; X64-NEXT: jae .LBB31_3
; X64-NEXT: # %bb.4: # %return
+; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
; X64-NEXT: .LBB31_3: # %if.then
; X64-NEXT: movzwl %cx, %eax
-; X64-NEXT: movzwl (%rdi,%rax,2), %eax
+; X64-NEXT: movzwl (%rdi,%rax,2), %edx
+; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
entry:
%0 = and i16 %c, 7
@@ -2031,30 +2024,30 @@ define zeroext i16 @atomic_shl1_mask1_xor_16_gpr_brz(ptr %v, i16 zeroext %c) nou
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movl $1, %esi
-; X86-NEXT: shll %cl, %esi
-; X86-NEXT: movzwl (%edx), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl $1, %edx
+; X86-NEXT: shll %cl, %edx
+; X86-NEXT: movzwl (%esi), %eax
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB33_1: # %atomicrmw.start
; X86-NEXT: # =>This Inner Loop Header: Depth=1
; X86-NEXT: movl %eax, %edi
-; X86-NEXT: xorl %esi, %edi
+; X86-NEXT: xorl %edx, %edi
; X86-NEXT: # kill: def $ax killed $ax killed $eax
-; X86-NEXT: lock cmpxchgw %di, (%edx)
+; X86-NEXT: lock cmpxchgw %di, (%esi)
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB33_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %esi
; X86-NEXT: movl %ecx, %edi
; X86-NEXT: andl $15, %edi
-; X86-NEXT: movw $123, %ax
-; X86-NEXT: btl %edi, %esi
+; X86-NEXT: movw $123, %dx
+; X86-NEXT: btl %edi, %eax
; X86-NEXT: jb .LBB33_4
; X86-NEXT: # %bb.3: # %if.then
; X86-NEXT: movzwl %cx, %eax
-; X86-NEXT: movzwl (%edx,%eax,2), %eax
+; X86-NEXT: movzwl (%esi,%eax,2), %edx
; X86-NEXT: .LBB33_4: # %return
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -2075,17 +2068,18 @@ define zeroext i16 @atomic_shl1_mask1_xor_16_gpr_brz(ptr %v, i16 zeroext %c) nou
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB33_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
; X64-NEXT: movl %ecx, %esi
; X64-NEXT: andl $15, %esi
-; X64-NEXT: movw $123, %ax
-; X64-NEXT: btl %esi, %edx
+; X64-NEXT: movw $123, %dx
+; X64-NEXT: btl %esi, %eax
; X64-NEXT: jae .LBB33_3
; X64-NEXT: # %bb.4: # %return
+; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
; X64-NEXT: .LBB33_3: # %if.then
; X64-NEXT: movzwl %cx, %eax
-; X64-NEXT: movzwl (%rdi,%rax,2), %eax
+; X64-NEXT: movzwl (%rdi,%rax,2), %edx
+; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
entry:
%conv = zext i16 %c to i32
@@ -2684,11 +2678,10 @@ define zeroext i16 @atomic_shl1_small_mask_and_16_gpr_valnz(ptr %v, i16 zeroext
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB43_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %edx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: btl %ecx, %edx
-; X86-NEXT: setb %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: btl %ecx, %eax
+; X86-NEXT: setb %dl
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -2710,11 +2703,10 @@ define zeroext i16 @atomic_shl1_small_mask_and_16_gpr_valnz(ptr %v, i16 zeroext
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB43_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: btl %ecx, %edx
-; X64-NEXT: setb %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: btl %ecx, %eax
+; X64-NEXT: setb %dl
+; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
entry:
%0 = and i16 %c, 7
@@ -2815,12 +2807,11 @@ define zeroext i16 @atomic_shl1_mask1_and_16_gpr_valnz(ptr %v, i16 zeroext %c) n
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB45_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %edx
; X86-NEXT: andl $15, %ecx
-; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: btl %ecx, %edx
-; X86-NEXT: setb %al
-; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: btl %ecx, %eax
+; X86-NEXT: setb %dl
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: retl
@@ -2841,12 +2832,11 @@ define zeroext i16 @atomic_shl1_mask1_and_16_gpr_valnz(ptr %v, i16 zeroext %c) n
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB45_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %edx
; X64-NEXT: andl $15, %ecx
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: btl %ecx, %edx
-; X64-NEXT: setb %al
-; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: btl %ecx, %eax
+; X64-NEXT: setb %dl
+; X64-NEXT: movl %edx, %eax
; X64-NEXT: retq
entry:
%conv = zext i16 %c to i32
@@ -3111,7 +3101,6 @@ define zeroext i16 @atomic_shl1_small_mask_and_16_gpr_brnz(ptr %v, i16 zeroext %
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB49_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %eax
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: jae .LBB49_3
; X86-NEXT: # %bb.4: # %if.then
@@ -3142,7 +3131,6 @@ define zeroext i16 @atomic_shl1_small_mask_and_16_gpr_brnz(ptr %v, i16 zeroext %
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB49_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %eax
; X64-NEXT: btl %ecx, %eax
; X64-NEXT: jae .LBB49_3
; X64-NEXT: # %bb.4: # %if.then
@@ -3278,7 +3266,6 @@ define zeroext i16 @atomic_shl1_mask1_and_16_gpr_brnz(ptr %v, i16 zeroext %c) no
; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: jne .LBB51_1
; X86-NEXT: # %bb.2: # %atomicrmw.end
-; X86-NEXT: movzwl %ax, %eax
; X86-NEXT: movl %ecx, %esi
; X86-NEXT: andl $15, %esi
; X86-NEXT: btl %esi, %eax
@@ -3310,7 +3297,6 @@ define zeroext i16 @atomic_shl1_mask1_and_16_gpr_brnz(ptr %v, i16 zeroext %c) no
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: jne .LBB51_1
; X64-NEXT: # %bb.2: # %atomicrmw.end
-; X64-NEXT: movzwl %ax, %eax
; X64-NEXT: movl %ecx, %edx
; X64-NEXT: andl $15, %edx
; X64-NEXT: btl %edx, %eax
>From 9048ff1dcf3d3c1ad0f280d53f984624dcb8f98b Mon Sep 17 00:00:00 2001
From: Alan Li <me at alanli.org>
Date: Sat, 10 Oct 2026 15:11:19 -0700
Subject: [PATCH 3/4] fix(SelectionDAG): validate identity fold demands
KnownBits returned for the LHS may only be valid for the demand
already reduced by the RHS. Check the full result demand before
folding AND/OR to the LHS.
Share the masked-bit check between both operations. Drop Disjoint
when the query rewrites an OR operand.
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 92 ++++++++++++-------
1 file changed, 59 insertions(+), 33 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 0991df43d06c1..4ac1af3cf385e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1355,6 +1355,50 @@ bool TargetLowering::SimplifyDemandedBits(
return false;
}
+ // Before folding to the LHS, recheck bits excluded from its earlier demand
+ // using the full result demand. Mask identifies these excluded bits.
+ // KnownMask selects the Zero/One member of the recomputed LHS known bits
+ // that must cover Mask & DemandedBits.
+ auto TryFoldToLHS = [&](const APInt &Mask,
+ const APInt KnownBits::*KnownMask) {
+ SDValue LHS = Op.getOperand(0);
+ APInt MaskedBits = Mask & DemandedBits;
+ if (MaskedBits.isZero())
+ return TLO.CombineTo(Op, LHS);
+
+ KnownBits LHSKnown(BitWidth);
+ if (SimplifyDemandedBits(LHS, DemandedBits, DemandedElts, LHSKnown, TLO,
+ Depth + 1))
+ return true;
+
+ return MaskedBits.isSubsetOf(LHSKnown.*KnownMask) && TLO.CombineTo(Op, LHS);
+ };
+
+ // Try reducing the RHS demand using LHS known bits.
+ // KnownMask selects the LHS Zero/One bits that make RHS bits irrelevant.
+ auto TryReduceRHSDemand = [&](const KnownBits &LHSKnown,
+ const APInt KnownBits::*KnownMask) {
+ SDValue RHS = Op.getOperand(1);
+ if (!RHS.hasOneUse() || isConstOrConstSplat(RHS, DemandedElts))
+ return false;
+
+ // Reuse LHS facts if the RHS did not reduce its earlier demand. Otherwise,
+ // query independent facts to avoid using bits outside that demand.
+ KnownBits FullDemandKnown =
+ DemandedBits.intersects(Known.*KnownMask)
+ ? TLO.DAG.computeKnownBits(Op.getOperand(0), DemandedElts,
+ Depth + 1)
+ : LHSKnown;
+ APInt RHSDemandedBits = ~(FullDemandKnown.*KnownMask) & DemandedBits;
+ if (RHSDemandedBits == DemandedBits)
+ return false;
+
+ // A failed retry must not replace Known with reduced-demand facts.
+ KnownBits RetryKnown;
+ return SimplifyDemandedBits(RHS, RHSDemandedBits, DemandedElts, RetryKnown,
+ TLO, Depth + 1);
+ };
+
KnownBits Known2;
switch (Op.getOpcode()) {
case ISD::SCALAR_TO_VECTOR: {
@@ -1662,8 +1706,10 @@ bool TargetLowering::SimplifyDemandedBits(
// If all of the demanded bits are known one on one side, return the other.
// These bits cannot contribute to the result of the 'and'.
- if (DemandedBits.isSubsetOf(Known2.Zero | Known.One))
- return TLO.CombineTo(Op, Op0);
+ if (DemandedBits.isSubsetOf(Known2.Zero | Known.One)) {
+ if (TryFoldToLHS(Known.Zero, &KnownBits::Zero))
+ return true;
+ }
if (DemandedBits.isSubsetOf(Known.Zero | Known2.One))
return TLO.CombineTo(Op, Op1);
// If all of the demanded bits in the inputs are known zeros, return zero.
@@ -1691,20 +1737,8 @@ bool TargetLowering::SimplifyDemandedBits(
}
}
- // Try reducing the RHS demand using independent LHS known bits. Known2
- // may only be valid for the demand already reduced by the RHS.
- if (Op1.hasOneUse() && !isConstOrConstSplat(Op1, DemandedElts)) {
- KnownBits LHSKnown =
- TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1);
- APInt RHSDemandedBits = ~LHSKnown.Zero & DemandedBits;
- if (RHSDemandedBits != DemandedBits) {
- // A failed retry must not replace Known with reduced-demand facts.
- KnownBits RetryKnown;
- if (SimplifyDemandedBits(Op1, RHSDemandedBits, DemandedElts, RetryKnown,
- TLO, Depth + 1))
- return true;
- }
- }
+ if (TryReduceRHSDemand(Known2, &KnownBits::Zero))
+ return true;
Known &= Known2;
break;
@@ -1726,8 +1760,12 @@ bool TargetLowering::SimplifyDemandedBits(
// If all of the demanded bits are known zero on one side, return the other.
// These bits cannot contribute to the result of the 'or'.
- if (DemandedBits.isSubsetOf(Known2.One | Known.Zero))
- return TLO.CombineTo(Op, Op0);
+ if (DemandedBits.isSubsetOf(Known2.One | Known.Zero)) {
+ if (TryFoldToLHS(Known.One, &KnownBits::One)) {
+ Op->dropFlags(SDNodeFlags::Disjoint);
+ return true;
+ }
+ }
if (DemandedBits.isSubsetOf(Known.One | Known2.Zero))
return TLO.CombineTo(Op, Op1);
// If the RHS is a constant, see if we can simplify it.
@@ -1766,21 +1804,9 @@ bool TargetLowering::SimplifyDemandedBits(
}
}
- // Try reducing the RHS demand using independent LHS known bits. Known2
- // may only be valid for the demand already reduced by the RHS.
- if (Op1.hasOneUse() && !isConstOrConstSplat(Op1, DemandedElts)) {
- KnownBits LHSKnown =
- TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1);
- APInt RHSDemandedBits = ~LHSKnown.One & DemandedBits;
- if (RHSDemandedBits != DemandedBits) {
- // A failed retry must not replace Known with reduced-demand facts.
- KnownBits RetryKnown;
- if (SimplifyDemandedBits(Op1, RHSDemandedBits, DemandedElts, RetryKnown,
- TLO, Depth + 1)) {
- Op->dropFlags(SDNodeFlags::Disjoint);
- return true;
- }
- }
+ if (TryReduceRHSDemand(Known2, &KnownBits::One)) {
+ Op->dropFlags(SDNodeFlags::Disjoint);
+ return true;
}
Known |= Known2;
>From 6d003135b69f752d47bbdca9931b2489af2aec8d Mon Sep 17 00:00:00 2001
From: Alan Li <me at alanli.org>
Date: Sat, 10 Oct 2026 18:49:25 -0700
Subject: [PATCH 4/4] perf(SelectionDAG): reduce KnownBits temporaries
Let SimplifyDemandedBits initialize the fold-check result. Build the
RHS demand in one APInt instead of copying both KnownBits masks.
---
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 4ac1af3cf385e..8628faad486aa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1366,7 +1366,7 @@ bool TargetLowering::SimplifyDemandedBits(
if (MaskedBits.isZero())
return TLO.CombineTo(Op, LHS);
- KnownBits LHSKnown(BitWidth);
+ KnownBits LHSKnown;
if (SimplifyDemandedBits(LHS, DemandedBits, DemandedElts, LHSKnown, TLO,
Depth + 1))
return true;
@@ -1384,12 +1384,16 @@ bool TargetLowering::SimplifyDemandedBits(
// Reuse LHS facts if the RHS did not reduce its earlier demand. Otherwise,
// query independent facts to avoid using bits outside that demand.
- KnownBits FullDemandKnown =
+ SDValue LHS = Op.getOperand(0);
+ // Keep only the selected mask, then compute DemandedBits & ~Mask in place.
+ // This avoids copying the unused KnownBits mask and extra APInt
+ // temporaries, which can allocate memory for masks wider than one word.
+ APInt RHSDemandedBits =
DemandedBits.intersects(Known.*KnownMask)
- ? TLO.DAG.computeKnownBits(Op.getOperand(0), DemandedElts,
- Depth + 1)
- : LHSKnown;
- APInt RHSDemandedBits = ~(FullDemandKnown.*KnownMask) & DemandedBits;
+ ? TLO.DAG.computeKnownBits(LHS, DemandedElts, Depth + 1).*KnownMask
+ : LHSKnown.*KnownMask;
+ RHSDemandedBits.flipAllBits();
+ RHSDemandedBits &= DemandedBits;
if (RHSDemandedBits == DemandedBits)
return false;
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