[llvm] [ISel] Add extension attribute on Memset libcall arg. (PR #229883)
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 8 14:47:14 PDT 2026
https://github.com/JonPsson1 updated https://github.com/llvm/llvm-project/pull/229883
>From 4ea9f528333a9bbec3c4ef412a6b7ec6fed2cbaa Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: Wed, 7 Oct 2026 19:24:48 +0200
Subject: [PATCH 1/5] [ISel] Add ext attributes on Memset libcall.
---
.../include/llvm/Analysis/TargetLibraryInfo.h | 10 ++++
llvm/include/llvm/CodeGen/TargetLowering.h | 2 +
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 +-
.../CodeGen/SelectionDAG/TargetLowering.cpp | 11 ++++
llvm/test/CodeGen/AArch64/aarch64-mops.ll | 6 +-
.../AArch64/memset-vs-memset-inline.ll | 34 ++++++++++-
.../ARM/subtarget-features-long-calls.ll | 58 ++++++++++++++++++-
.../CodeGen/PowerPC/aix-llvm-intrinsic.ll | 5 +-
llvm/test/CodeGen/PowerPC/milicode32.ll | 2 +
.../CodeGen/WebAssembly/disable-feature.ll | 2 +
.../CodeGen/WebAssembly/mem-intrinsics.ll | 20 +++++--
llvm/test/CodeGen/X86/memset-2.ll | 3 +-
llvm/test/CodeGen/X86/memset-nonzero.ll | 1 +
.../CodeGen/X86/memset-vs-memset-inline.ll | 1 +
14 files changed, 146 insertions(+), 14 deletions(-)
diff --git a/llvm/include/llvm/Analysis/TargetLibraryInfo.h b/llvm/include/llvm/Analysis/TargetLibraryInfo.h
index b006cceb429086..3606f6854adbdf 100644
--- a/llvm/include/llvm/Analysis/TargetLibraryInfo.h
+++ b/llvm/include/llvm/Analysis/TargetLibraryInfo.h
@@ -544,6 +544,16 @@ class TargetLibraryInfo {
Impl->ShouldSignExtI32Param, Signed);
}
+ Attribute::AttrKind getExtAttrForParam(Type *Ty, bool Signed = true) const {
+ if (Ty->isIntegerTy()) {
+ if (Ty->getPrimitiveSizeInBits() == 8)
+ return getExtAttrForI8Param(Signed);
+ else if (Ty->getPrimitiveSizeInBits() == 32)
+ return getExtAttrForI32Param(Signed);
+ }
+ return Attribute::None;
+ }
+
/// Returns extension attribute kind to be used for i32 return values
/// corresponding to C-level int or unsigned int. May be zeroext, signext,
/// or none.
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 70718b14666534..6b6928d62cd78b 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -365,6 +365,8 @@ class LLVM_ABI TargetLoweringBase {
ArgListEntry(SDValue Node, Type *Ty) : ArgListEntry(nullptr, Node, Ty) {}
+ ArgListEntry(SDValue Node, Type *Ty, Attribute::AttrKind Attr);
+
LLVM_ABI void setAttributes(const CallBase *Call, unsigned ArgIdx);
LLVM_ABI void setAttributes(const AttributeList &Attrs, unsigned ArgIdx);
};
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 77922d8fb13442..ce7a293a1da343 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10497,9 +10497,12 @@ SDValue SelectionDAG::getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst,
RTLIB::LibcallImpl MemsetImpl = Libcalls->getLibcallImpl(RTLIB::MEMSET);
TargetLowering::ArgListTy Args;
+ Type *SrcTy = Src.getValueType().getTypeForEVT(Ctx);
Args.emplace_back(Dst, PointerType::getUnqual(Ctx));
- Args.emplace_back(Src, Src.getValueType().getTypeForEVT(Ctx));
+ Args.emplace_back(Src, SrcTy,
+ LibInfo->getExtAttrForParam(SrcTy, /*Signed=*/false));
Args.emplace_back(Size, DL.getIntPtrType(Ctx));
+
CLI.setLibCallee(Libcalls->getLibcallImplCallingConv(MemsetImpl),
Dst.getValueType().getTypeForEVT(Ctx),
getExternalSymbol(MemsetImpl, TLI->getPointerTy(DL)),
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index fcf989694c3c56..91ac9f40806502 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -179,6 +179,17 @@ static void setArgListEntryAttributes(TargetLoweringBase::ArgListEntry &Entry,
Entry.IndirectType = Src.getParamStructRetType(ArgIdx);
}
+TargetLoweringBase::ArgListEntry::
+ArgListEntry(SDValue Node, Type *Ty, Attribute::AttrKind Attr)
+ : ArgListEntry(nullptr, Node, Ty) {
+ if (Attr == Attribute::SExt)
+ IsSExt = true;
+ else if (Attr == Attribute::ZExt)
+ IsZExt = true;
+ else if (Attr != Attribute::None)
+ llvm_unreachable("Unexpected attribute left unhandled.");
+}
+
void TargetLoweringBase::ArgListEntry::setAttributes(const CallBase *Call,
unsigned ArgIdx) {
setArgListEntryAttributes(*this, *Call, ArgIdx);
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops.ll b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
index f673c9b68800f2..be5c96f50f76d9 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
@@ -666,6 +666,7 @@ define void @memset_10000(ptr %dst, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
+; SDAG-WITHOUT-MOPS-O2-NEXT: and w1, w1, #0xff
; SDAG-WITHOUT-MOPS-O2-NEXT: mov w2, #10000 // =0x2710
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -732,6 +733,7 @@ define void @memset_10000_volatile(ptr %dst, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
+; SDAG-WITHOUT-MOPS-O2-NEXT: and w1, w1, #0xff
; SDAG-WITHOUT-MOPS-O2-NEXT: mov w2, #10000 // =0x2710
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -801,7 +803,7 @@ define void @memset_size(ptr %dst, i64 %size, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x8, x1
-; SDAG-WITHOUT-MOPS-O2-NEXT: mov w1, w2
+; SDAG-WITHOUT-MOPS-O2-NEXT: and w1, w2, #0xff
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x2, x8
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -870,7 +872,7 @@ define void @memset_size_volatile(ptr %dst, i64 %size, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x8, x1
-; SDAG-WITHOUT-MOPS-O2-NEXT: mov w1, w2
+; SDAG-WITHOUT-MOPS-O2-NEXT: and w1, w2, #0xff
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x2, x8
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll b/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
index a970a8f8fc9c07..230cf9f864e74c 100644
--- a/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
+++ b/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
@@ -17,7 +17,8 @@ define void @test1(ptr %a, i8 %value) nounwind {
define void @regular_memset_calls_external_function(ptr %a, i8 %value) nounwind {
; CHECK-LABEL: regular_memset_calls_external_function:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w2, #1024
+; CHECK-NEXT: and w1, w1, #0xff
+; CHECK-NEXT: mov w2, #1024 // =0x400
; CHECK-NEXT: b memset
tail call void @llvm.memset.p0.i64(ptr %a, i8 %value, i64 1024, i1 0)
ret void
@@ -29,6 +30,37 @@ define void @inlined_set_doesnt_call_external_function(ptr %a, i8 %value) nounwi
; CHECK-NEXT: dup v0.16b, w1
; CHECK-NEXT: stp q0, q0, [x0]
; CHECK-NEXT: stp q0, q0, [x0, #32]
+; CHECK-NEXT: stp q0, q0, [x0, #64]
+; CHECK-NEXT: stp q0, q0, [x0, #96]
+; CHECK-NEXT: stp q0, q0, [x0, #128]
+; CHECK-NEXT: stp q0, q0, [x0, #160]
+; CHECK-NEXT: stp q0, q0, [x0, #192]
+; CHECK-NEXT: stp q0, q0, [x0, #224]
+; CHECK-NEXT: stp q0, q0, [x0, #256]
+; CHECK-NEXT: stp q0, q0, [x0, #288]
+; CHECK-NEXT: stp q0, q0, [x0, #320]
+; CHECK-NEXT: stp q0, q0, [x0, #352]
+; CHECK-NEXT: stp q0, q0, [x0, #384]
+; CHECK-NEXT: stp q0, q0, [x0, #416]
+; CHECK-NEXT: stp q0, q0, [x0, #448]
+; CHECK-NEXT: stp q0, q0, [x0, #480]
+; CHECK-NEXT: stp q0, q0, [x0, #512]
+; CHECK-NEXT: stp q0, q0, [x0, #544]
+; CHECK-NEXT: stp q0, q0, [x0, #576]
+; CHECK-NEXT: stp q0, q0, [x0, #608]
+; CHECK-NEXT: stp q0, q0, [x0, #640]
+; CHECK-NEXT: stp q0, q0, [x0, #672]
+; CHECK-NEXT: stp q0, q0, [x0, #704]
+; CHECK-NEXT: stp q0, q0, [x0, #736]
+; CHECK-NEXT: stp q0, q0, [x0, #768]
+; CHECK-NEXT: stp q0, q0, [x0, #800]
+; CHECK-NEXT: stp q0, q0, [x0, #832]
+; CHECK-NEXT: stp q0, q0, [x0, #864]
+; CHECK-NEXT: stp q0, q0, [x0, #896]
+; CHECK-NEXT: stp q0, q0, [x0, #928]
+; CHECK-NEXT: stp q0, q0, [x0, #960]
+; CHECK-NEXT: stp q0, q0, [x0, #992]
+; CHECK-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 1024, i1 0)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll b/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
index 24fc8b7ee2e9b7..f509f90ce6e055 100644
--- a/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
+++ b/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
@@ -3,7 +3,7 @@
; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=+long-calls | FileCheck -check-prefix=LONGCALL %s
; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=-long-calls | FileCheck -check-prefix=NO-LONGCALL %s
; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 | FileCheck -check-prefix=NO-OPTION %s
-; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=+long-calls | FileCheck -check-prefix=LONGCALL %s
+; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=+long-calls | FileCheck -check-prefix=LONGCALL-O0 %s
; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=-long-calls | FileCheck -check-prefix=NO-LONGCALL %s
; RUN: llc -mtriple=arm-linux-gnueabi -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=+long-calls,+execute-only | FileCheck -check-prefix=XO-LONGCALL %s
; RUN: llc -mtriple=arm-linux-gnueabi -mcpu=cortex-a8 -relocation-model=pic %s -o - -mattr=+long-calls | FileCheck -check-prefix=PIC-LONGCALL %s
@@ -40,6 +40,18 @@ define i32 @caller0() #0 {
; NO-LONGCALL-NEXT: movs r0, #0
; NO-LONGCALL-NEXT: pop {r7, pc}
;
+; LONGCALL-O0-LABEL: caller0:
+; LONGCALL-O0: @ %bb.0: @ %entry
+; LONGCALL-O0-NEXT: push {r7, lr}
+; LONGCALL-O0-NEXT: ldr r0, .LCPI0_0
+; LONGCALL-O0-NEXT: blx r0
+; LONGCALL-O0-NEXT: movs r0, #0
+; LONGCALL-O0-NEXT: pop {r7, pc}
+; LONGCALL-O0-NEXT: .p2align 2
+; LONGCALL-O0-NEXT: @ %bb.1:
+; LONGCALL-O0-NEXT: .LCPI0_0:
+; LONGCALL-O0-NEXT: .long callee0
+;
; XO-LONGCALL-LABEL: caller0:
; XO-LONGCALL: @ %bb.0: @ %entry
; XO-LONGCALL-NEXT: .save {r11, lr}
@@ -97,6 +109,18 @@ define i32 @caller1() {
; NO-LONGCALL-NEXT: movs r0, #0
; NO-LONGCALL-NEXT: pop {r7, pc}
;
+; LONGCALL-O0-LABEL: caller1:
+; LONGCALL-O0: @ %bb.0: @ %entry
+; LONGCALL-O0-NEXT: push {r7, lr}
+; LONGCALL-O0-NEXT: ldr r0, .LCPI1_0
+; LONGCALL-O0-NEXT: blx r0
+; LONGCALL-O0-NEXT: movs r0, #0
+; LONGCALL-O0-NEXT: pop {r7, pc}
+; LONGCALL-O0-NEXT: .p2align 2
+; LONGCALL-O0-NEXT: @ %bb.1:
+; LONGCALL-O0-NEXT: .LCPI1_0:
+; LONGCALL-O0-NEXT: .long callee0
+;
; XO-LONGCALL-LABEL: caller1:
; XO-LONGCALL: @ %bb.0: @ %entry
; XO-LONGCALL-NEXT: .save {r11, lr}
@@ -144,6 +168,10 @@ define dso_local void @global_func() {
; NO-LONGCALL: @ %bb.0: @ %entry
; NO-LONGCALL-NEXT: bx lr
;
+; LONGCALL-O0-LABEL: global_func:
+; LONGCALL-O0: @ %bb.0: @ %entry
+; LONGCALL-O0-NEXT: bx lr
+;
; XO-LONGCALL-LABEL: global_func:
; XO-LONGCALL: @ %bb.0: @ %entry
; XO-LONGCALL-NEXT: bx lr
@@ -175,6 +203,17 @@ define void @test_global() {
; NO-LONGCALL-NEXT: bl global_func
; NO-LONGCALL-NEXT: pop {r7, pc}
;
+; LONGCALL-O0-LABEL: test_global:
+; LONGCALL-O0: @ %bb.0: @ %entry
+; LONGCALL-O0-NEXT: push {r7, lr}
+; LONGCALL-O0-NEXT: ldr r0, .LCPI3_0
+; LONGCALL-O0-NEXT: blx r0
+; LONGCALL-O0-NEXT: pop {r7, pc}
+; LONGCALL-O0-NEXT: .p2align 2
+; LONGCALL-O0-NEXT: @ %bb.1:
+; LONGCALL-O0-NEXT: .LCPI3_0:
+; LONGCALL-O0-NEXT: .long global_func
+;
; XO-LONGCALL-LABEL: test_global:
; XO-LONGCALL: @ %bb.0: @ %entry
; XO-LONGCALL-NEXT: .save {r11, lr}
@@ -208,6 +247,7 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; NO-OPTION-LABEL: test_memset:
; NO-OPTION: @ %bb.0: @ %entry
; NO-OPTION-NEXT: push {r7, lr}
+; NO-OPTION-NEXT: uxtb r1, r1
; NO-OPTION-NEXT: bl memset
; NO-OPTION-NEXT: pop {r7, pc}
;
@@ -215,6 +255,7 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; LONGCALL: @ %bb.0: @ %entry
; LONGCALL-NEXT: push {r7, lr}
; LONGCALL-NEXT: ldr r3, .LCPI4_0
+; LONGCALL-NEXT: uxtb r1, r1
; LONGCALL-NEXT: blx r3
; LONGCALL-NEXT: pop {r7, pc}
; LONGCALL-NEXT: .p2align 2
@@ -225,14 +266,28 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; NO-LONGCALL-LABEL: test_memset:
; NO-LONGCALL: @ %bb.0: @ %entry
; NO-LONGCALL-NEXT: push {r7, lr}
+; NO-LONGCALL-NEXT: uxtb r1, r1
; NO-LONGCALL-NEXT: bl memset
; NO-LONGCALL-NEXT: pop {r7, pc}
;
+; LONGCALL-O0-LABEL: test_memset:
+; LONGCALL-O0: @ %bb.0: @ %entry
+; LONGCALL-O0-NEXT: push {r7, lr}
+; LONGCALL-O0-NEXT: uxtb r1, r1
+; LONGCALL-O0-NEXT: ldr r3, .LCPI4_0
+; LONGCALL-O0-NEXT: blx r3
+; LONGCALL-O0-NEXT: pop {r7, pc}
+; LONGCALL-O0-NEXT: .p2align 2
+; LONGCALL-O0-NEXT: @ %bb.1:
+; LONGCALL-O0-NEXT: .LCPI4_0:
+; LONGCALL-O0-NEXT: .long memset
+;
; XO-LONGCALL-LABEL: test_memset:
; XO-LONGCALL: @ %bb.0: @ %entry
; XO-LONGCALL-NEXT: .save {r11, lr}
; XO-LONGCALL-NEXT: push {r11, lr}
; XO-LONGCALL-NEXT: movw r3, :lower16:memset
+; XO-LONGCALL-NEXT: uxtb r1, r1
; XO-LONGCALL-NEXT: movt r3, :upper16:memset
; XO-LONGCALL-NEXT: blx r3
; XO-LONGCALL-NEXT: pop {r11, pc}
@@ -242,6 +297,7 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; PIC-LONGCALL-NEXT: .save {r11, lr}
; PIC-LONGCALL-NEXT: push {r11, lr}
; PIC-LONGCALL-NEXT: ldr r3, .LCPI4_0
+; PIC-LONGCALL-NEXT: uxtb r1, r1
; PIC-LONGCALL-NEXT: .LPC4_0:
; PIC-LONGCALL-NEXT: ldr r3, [pc, r3]
; PIC-LONGCALL-NEXT: blx r3
diff --git a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
index d6c3e63fb9a9e6..354c53e8d97b34 100644
--- a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
@@ -82,8 +82,9 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
; CHECKRELOC64-NEXT: 8: e8 62 00 00 ld 3, 0(2)
; CHECKRELOC64-NEXT: 000000000000000a: R_TOC (idx: [[#NFA+13]]) s[TC]
; CHECKRELOC64-NEXT: c: f8 01 00 80 std 0, 128(1)
-; CHECKRELOC-NEXT: 10: 80 83 00 04 lwz 4, 4(3)
-; CHECKRELOC-NEXT: 14: 7c 85 23 78 mr 5, 4
+; CHECKRELOC-NEXT: 10: 80 a3 00 04 lwz 5, 4(3)
+; CHECKRELOC32-NEXT: 14: 54 a4 06 3e clrlwi 4, 5, 24
+; CHECKRELOC64-NEXT: 14: 78 a4 06 20 clrldi 4, 5, 56
; CHECKRELOC-NEXT: 18: 4b ff ff e9 bl 0x0
; CHECKRELOC32-NEXT: 00000018: R_RBR (idx: [[#NFA+1]]) .___memset[PR]
; CHECKRELOC64-NEXT: 0000000000000018: R_RBR (idx: [[#NFA+1]]) .___memset64[PR]
diff --git a/llvm/test/CodeGen/PowerPC/milicode32.ll b/llvm/test/CodeGen/PowerPC/milicode32.ll
index f2caec7e0045f7..ad84bf80a33609 100644
--- a/llvm/test/CodeGen/PowerPC/milicode32.ll
+++ b/llvm/test/CodeGen/PowerPC/milicode32.ll
@@ -244,6 +244,7 @@ define ptr @test_memset(ptr noundef %dst, i32 noundef signext %value, i32 nounde
; CHECK-AIX-32-P9: # %bb.0: # %entry
; CHECK-AIX-32-P9-NEXT: mflr r0
; CHECK-AIX-32-P9-NEXT: stwu r1, -64(r1)
+; CHECK-AIX-32-P9-NEXT: clrlwi r4, r4, 24
; CHECK-AIX-32-P9-NEXT: stw r0, 72(r1)
; CHECK-AIX-32-P9-NEXT: stw r31, 60(r1) # 4-byte Folded Spill
; CHECK-AIX-32-P9-NEXT: mr r31, r3
@@ -260,6 +261,7 @@ define ptr @test_memset(ptr noundef %dst, i32 noundef signext %value, i32 nounde
; CHECK-LINUX32-P9: # %bb.0: # %entry
; CHECK-LINUX32-P9-NEXT: mflr r0
; CHECK-LINUX32-P9-NEXT: stwu r1, -16(r1)
+; CHECK-LINUX32-P9-NEXT: clrlwi r4, r4, 24
; CHECK-LINUX32-P9-NEXT: stw r0, 20(r1)
; CHECK-LINUX32-P9-NEXT: stw r30, 8(r1) # 4-byte Folded Spill
; CHECK-LINUX32-P9-NEXT: mr r30, r3
diff --git a/llvm/test/CodeGen/WebAssembly/disable-feature.ll b/llvm/test/CodeGen/WebAssembly/disable-feature.ll
index 5f7275f3699ede..e8f72ac574a4e7 100644
--- a/llvm/test/CodeGen/WebAssembly/disable-feature.ll
+++ b/llvm/test/CodeGen/WebAssembly/disable-feature.ll
@@ -39,6 +39,8 @@ define void @lower_bulk_memory(i8 %val) #0 {
; CHECK-NEXT: i32.const 12
; CHECK-NEXT: i32.add
; CHECK-NEXT: local.get 0
+; CHECK-NEXT: i32.const 255
+; CHECK-NEXT: i32.and
; CHECK-NEXT: i32.const 100
; CHECK-NEXT: call memset
; CHECK-NEXT: drop
diff --git a/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
index 51e6c2836a20ff..e3c74d175a4509 100644
--- a/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
+++ b/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
@@ -54,8 +54,10 @@ define ptr @set_yes(ptr %dst, i8 %src, i32 %len) {
; CHECK-LABEL: set_yes:
; CHECK: .functype set_yes (i32, i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: call $push0=, memset, $0, $1, $2
-; CHECK-NEXT: return $pop0
+; CHECK-NEXT: i32.const $push0=, 255
+; CHECK-NEXT: i32.and $push1=, $1, $pop0
+; CHECK-NEXT: call $push2=, memset, $0, $pop1, $2
+; CHECK-NEXT: return $pop2
call void @llvm.memset.p0.i32(ptr %dst, i8 %src, i32 %len, i1 false)
ret ptr %dst
}
@@ -64,7 +66,9 @@ define void @set_no(ptr %dst, i8 %src, i32 %len) {
; CHECK-LABEL: set_no:
; CHECK: .functype set_no (i32, i32, i32) -> ()
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: call $drop=, memset, $0, $1, $2
+; CHECK-NEXT: i32.const $push0=, 255
+; CHECK-NEXT: i32.and $push1=, $1, $pop0
+; CHECK-NEXT: call $drop=, memset, $0, $pop1, $2
; CHECK-NEXT: return
call void @llvm.memset.p0.i32(ptr %dst, i8 %src, i32 %len, i1 false)
ret void
@@ -115,7 +119,9 @@ define ptr @drop_result(ptr %arg, i8 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: br_if 1, $4 # 1: down to label0
; CHECK-NEXT: # %bb.2: # %bb7
-; CHECK-NEXT: call $drop=, memset, $0, $1, $2
+; CHECK-NEXT: i32.const $push0=, 255
+; CHECK-NEXT: i32.and $push1=, $1, $pop0
+; CHECK-NEXT: call $drop=, memset, $0, $pop1, $2
; CHECK-NEXT: call block_tail_dup
; CHECK-NEXT: return $0
; CHECK-NEXT: .LBB7_3: # %bb9
@@ -163,8 +169,10 @@ define ptr @tail_dup_to_reuse_result(ptr %arg, i8 %arg1, i32 %arg2, i32 %arg3, i
; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: br_if 1, $4 # 1: down to label2
; CHECK-NEXT: # %bb.2: # %bb7
-; CHECK-NEXT: call $push0=, memset, $0, $1, $2
-; CHECK-NEXT: return $pop0
+; CHECK-NEXT: i32.const $push0=, 255
+; CHECK-NEXT: i32.and $push1=, $1, $pop0
+; CHECK-NEXT: call $push2=, memset, $0, $pop1, $2
+; CHECK-NEXT: return $pop2
; CHECK-NEXT: .LBB8_3: # %bb9
; CHECK-NEXT: end_block # label3:
; CHECK-NEXT: call $0=, def
diff --git a/llvm/test/CodeGen/X86/memset-2.ll b/llvm/test/CodeGen/X86/memset-2.ll
index a4fbbc57004708..d75838dd1972db 100644
--- a/llvm/test/CodeGen/X86/memset-2.ll
+++ b/llvm/test/CodeGen/X86/memset-2.ll
@@ -20,8 +20,9 @@ define fastcc void @t2(ptr nocapture %s, i8 signext %c) nounwind {
; CHECK-LABEL: t2:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: subl $16, %esp
+; CHECK-NEXT: movzbl %dl, %eax
; CHECK-NEXT: pushl $76
-; CHECK-NEXT: pushl %edx
+; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: calll _memset
; CHECK-NEXT: addl $16, %esp
diff --git a/llvm/test/CodeGen/X86/memset-nonzero.ll b/llvm/test/CodeGen/X86/memset-nonzero.ll
index d07b0f64d68c18..af8ab4e724d1e1 100644
--- a/llvm/test/CodeGen/X86/memset-nonzero.ll
+++ b/llvm/test/CodeGen/X86/memset-nonzero.ll
@@ -525,6 +525,7 @@ define void @memset_128_nonconst_bytes(ptr %x, i8 %c) {
define void @memset_256_nonconst_bytes(ptr %x, i8 %c) {
; SSE-LABEL: memset_256_nonconst_bytes:
; SSE: # %bb.0:
+; SSE-NEXT: movzbl %sil, %esi
; SSE-NEXT: movl $256, %edx # imm = 0x100
; SSE-NEXT: jmp memset at PLT # TAILCALL
;
diff --git a/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll b/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll
index e34682aa0fcb42..6a1b336c65f2dc 100644
--- a/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll
+++ b/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll
@@ -19,6 +19,7 @@ define void @test1(ptr %a, i8 %value) nounwind {
define void @regular_memset_calls_external_function(ptr %a, i8 %value) nounwind {
; CHECK-LABEL: regular_memset_calls_external_function:
; CHECK: # %bb.0:
+; CHECK-NEXT: movzbl %sil, %esi
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: jmp memset at PLT # TAILCALL
tail call void @llvm.memset.p0.i64(ptr %a, i8 %value, i64 1024, i1 0)
>From 7f0bf16a76a16bb647372b1264b970b9f0a6e469 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: Wed, 7 Oct 2026 21:07:58 +0200
Subject: [PATCH 2/5] Tests updates.
---
llvm/test/CodeGen/AArch64/aarch64-mops.ll | 6 +++---
llvm/test/CodeGen/RISCV/memset.ll | 7 +++++++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops.ll b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
index be5c96f50f76d9..a7144d062d8aaa 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
@@ -2892,9 +2892,9 @@ define void @memset_size_i32(ptr %dst, i32 %size, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
-; SDAG-WITHOUT-MOPS-O2-NEXT: mov w8, w2
-; SDAG-WITHOUT-MOPS-O2-NEXT: mov w2, w1
-; SDAG-WITHOUT-MOPS-O2-NEXT: mov w1, w8
+; SDAG-WITHOUT-MOPS-O2-NEXT: mov w8, w1
+; SDAG-WITHOUT-MOPS-O2-NEXT: and w1, w2, #0xff
+; SDAG-WITHOUT-MOPS-O2-NEXT: mov x2, x8
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; SDAG-WITHOUT-MOPS-O2-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/memset.ll b/llvm/test/CodeGen/RISCV/memset.ll
index 359b7d8ac3a43f..aec21e68c6a79a 100644
--- a/llvm/test/CodeGen/RISCV/memset.ll
+++ b/llvm/test/CodeGen/RISCV/memset.ll
@@ -7,6 +7,7 @@ define void @memset_i32_var(ptr %dest, i8 %val, i32 %n) nounwind {
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: zext.b a1, a1
; RV32-NEXT: call memset
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
@@ -16,6 +17,7 @@ define void @memset_i32_var(ptr %dest, i8 %val, i32 %n) nounwind {
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: zext.b a1, a1
; RV64-NEXT: slli a2, a2, 32
; RV64-NEXT: srli a2, a2, 32
; RV64-NEXT: call memset
@@ -32,6 +34,7 @@ define void @memset_i32_2147483648(ptr %dest, i8 %val) nounwind {
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: zext.b a1, a1
; RV32-NEXT: lui a2, 524288
; RV32-NEXT: call memset
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -42,6 +45,7 @@ define void @memset_i32_2147483648(ptr %dest, i8 %val) nounwind {
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: zext.b a1, a1
; RV64-NEXT: li a2, 1
; RV64-NEXT: slli a2, a2, 31
; RV64-NEXT: call memset
@@ -86,6 +90,7 @@ define void @memset_i64_var(ptr %dest, i8 %val, i64 %n) nounwind {
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: zext.b a1, a1
; RV32-NEXT: call memset
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
@@ -95,6 +100,7 @@ define void @memset_i64_var(ptr %dest, i8 %val, i64 %n) nounwind {
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: zext.b a1, a1
; RV64-NEXT: call memset
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16
@@ -113,6 +119,7 @@ define void @memset_i64_4294967296(ptr %dest, i8 %val) nounwind {
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: zext.b a1, a1
; RV64-NEXT: li a2, 1
; RV64-NEXT: slli a2, a2, 32
; RV64-NEXT: call memset
>From d0beb8fcd9e7a9ae8a3567d384bd42523c986e09 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <Jonas.Paulsson2 at ibm.com>
Date: Wed, 7 Oct 2026 12:24:26 -0700
Subject: [PATCH 3/5] clang-format
---
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 91ac9f40806502..a7f2a8ad55543b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -179,9 +179,9 @@ static void setArgListEntryAttributes(TargetLoweringBase::ArgListEntry &Entry,
Entry.IndirectType = Src.getParamStructRetType(ArgIdx);
}
-TargetLoweringBase::ArgListEntry::
-ArgListEntry(SDValue Node, Type *Ty, Attribute::AttrKind Attr)
- : ArgListEntry(nullptr, Node, Ty) {
+TargetLoweringBase::ArgListEntry::ArgListEntry(SDValue Node, Type *Ty,
+ Attribute::AttrKind Attr)
+ : ArgListEntry(nullptr, Node, Ty) {
if (Attr == Attribute::SExt)
IsSExt = true;
else if (Attr == Attribute::ZExt)
>From d356707e2c83019a7fd8087ea2f98b26d9b97db2 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: Thu, 8 Oct 2026 03:52:49 +0200
Subject: [PATCH 4/5] Fix: Size parameter is signed int.
---
.../include/llvm/Analysis/TargetLibraryInfo.h | 10 ------
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 ++-
llvm/test/CodeGen/AArch64/aarch64-mops.ll | 14 ++++----
.../AArch64/memset-vs-memset-inline.ll | 2 +-
.../ARM/subtarget-features-long-calls.ll | 12 +++----
.../CodeGen/PowerPC/aix-llvm-intrinsic.ll | 3 +-
llvm/test/CodeGen/PowerPC/milicode32.ll | 4 +--
llvm/test/CodeGen/PowerPC/milicode64.ll | 6 ++--
llvm/test/CodeGen/RISCV/memset.ll | 21 +++++++----
llvm/test/CodeGen/RISCV/xqcilsm-memset.ll | 22 ++++++------
.../CodeGen/WebAssembly/disable-feature.ll | 6 ++--
.../CodeGen/WebAssembly/mem-intrinsics.ll | 36 +++++++++++--------
llvm/test/CodeGen/X86/memset-2.ll | 3 +-
llvm/test/CodeGen/X86/memset-nonzero.ll | 2 +-
.../CodeGen/X86/memset-vs-memset-inline.ll | 2 +-
llvm/test/CodeGen/X86/optimize-max-0.ll | 6 ++--
16 files changed, 79 insertions(+), 75 deletions(-)
diff --git a/llvm/include/llvm/Analysis/TargetLibraryInfo.h b/llvm/include/llvm/Analysis/TargetLibraryInfo.h
index 3606f6854adbdf..b006cceb429086 100644
--- a/llvm/include/llvm/Analysis/TargetLibraryInfo.h
+++ b/llvm/include/llvm/Analysis/TargetLibraryInfo.h
@@ -544,16 +544,6 @@ class TargetLibraryInfo {
Impl->ShouldSignExtI32Param, Signed);
}
- Attribute::AttrKind getExtAttrForParam(Type *Ty, bool Signed = true) const {
- if (Ty->isIntegerTy()) {
- if (Ty->getPrimitiveSizeInBits() == 8)
- return getExtAttrForI8Param(Signed);
- else if (Ty->getPrimitiveSizeInBits() == 32)
- return getExtAttrForI32Param(Signed);
- }
- return Attribute::None;
- }
-
/// Returns extension attribute kind to be used for i32 return values
/// corresponding to C-level int or unsigned int. May be zeroext, signext,
/// or none.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index ce7a293a1da343..dc1b981b8f12f7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10497,10 +10497,9 @@ SDValue SelectionDAG::getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst,
RTLIB::LibcallImpl MemsetImpl = Libcalls->getLibcallImpl(RTLIB::MEMSET);
TargetLowering::ArgListTy Args;
- Type *SrcTy = Src.getValueType().getTypeForEVT(Ctx);
Args.emplace_back(Dst, PointerType::getUnqual(Ctx));
- Args.emplace_back(Src, SrcTy,
- LibInfo->getExtAttrForParam(SrcTy, /*Signed=*/false));
+ Args.emplace_back(Src, Src.getValueType().getTypeForEVT(Ctx),
+ LibInfo->getExtAttrForI8Param());
Args.emplace_back(Size, DL.getIntPtrType(Ctx));
CLI.setLibCallee(Libcalls->getLibcallImplCallingConv(MemsetImpl),
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops.ll b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
index a7144d062d8aaa..5dc25d160c6818 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
@@ -666,7 +666,7 @@ define void @memset_10000(ptr %dst, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
-; SDAG-WITHOUT-MOPS-O2-NEXT: and w1, w1, #0xff
+; SDAG-WITHOUT-MOPS-O2-NEXT: sxtb w1, w1
; SDAG-WITHOUT-MOPS-O2-NEXT: mov w2, #10000 // =0x2710
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -733,7 +733,7 @@ define void @memset_10000_volatile(ptr %dst, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
-; SDAG-WITHOUT-MOPS-O2-NEXT: and w1, w1, #0xff
+; SDAG-WITHOUT-MOPS-O2-NEXT: sxtb w1, w1
; SDAG-WITHOUT-MOPS-O2-NEXT: mov w2, #10000 // =0x2710
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -803,7 +803,7 @@ define void @memset_size(ptr %dst, i64 %size, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x8, x1
-; SDAG-WITHOUT-MOPS-O2-NEXT: and w1, w2, #0xff
+; SDAG-WITHOUT-MOPS-O2-NEXT: sxtb w1, w2
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x2, x8
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -872,7 +872,7 @@ define void @memset_size_volatile(ptr %dst, i64 %size, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x8, x1
-; SDAG-WITHOUT-MOPS-O2-NEXT: and w1, w2, #0xff
+; SDAG-WITHOUT-MOPS-O2-NEXT: sxtb w1, w2
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x2, x8
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -2892,9 +2892,9 @@ define void @memset_size_i32(ptr %dst, i32 %size, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
-; SDAG-WITHOUT-MOPS-O2-NEXT: mov w8, w1
-; SDAG-WITHOUT-MOPS-O2-NEXT: and w1, w2, #0xff
-; SDAG-WITHOUT-MOPS-O2-NEXT: mov x2, x8
+; SDAG-WITHOUT-MOPS-O2-NEXT: sxtb w8, w2
+; SDAG-WITHOUT-MOPS-O2-NEXT: mov w2, w1
+; SDAG-WITHOUT-MOPS-O2-NEXT: mov w1, w8
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; SDAG-WITHOUT-MOPS-O2-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll b/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
index 230cf9f864e74c..4cac6835147168 100644
--- a/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
+++ b/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
@@ -17,7 +17,7 @@ define void @test1(ptr %a, i8 %value) nounwind {
define void @regular_memset_calls_external_function(ptr %a, i8 %value) nounwind {
; CHECK-LABEL: regular_memset_calls_external_function:
; CHECK: // %bb.0:
-; CHECK-NEXT: and w1, w1, #0xff
+; CHECK-NEXT: sxtb w1, w1
; CHECK-NEXT: mov w2, #1024 // =0x400
; CHECK-NEXT: b memset
tail call void @llvm.memset.p0.i64(ptr %a, i8 %value, i64 1024, i1 0)
diff --git a/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll b/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
index f509f90ce6e055..6286196941d92b 100644
--- a/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
+++ b/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
@@ -247,7 +247,7 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; NO-OPTION-LABEL: test_memset:
; NO-OPTION: @ %bb.0: @ %entry
; NO-OPTION-NEXT: push {r7, lr}
-; NO-OPTION-NEXT: uxtb r1, r1
+; NO-OPTION-NEXT: sxtb r1, r1
; NO-OPTION-NEXT: bl memset
; NO-OPTION-NEXT: pop {r7, pc}
;
@@ -255,7 +255,7 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; LONGCALL: @ %bb.0: @ %entry
; LONGCALL-NEXT: push {r7, lr}
; LONGCALL-NEXT: ldr r3, .LCPI4_0
-; LONGCALL-NEXT: uxtb r1, r1
+; LONGCALL-NEXT: sxtb r1, r1
; LONGCALL-NEXT: blx r3
; LONGCALL-NEXT: pop {r7, pc}
; LONGCALL-NEXT: .p2align 2
@@ -266,14 +266,14 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; NO-LONGCALL-LABEL: test_memset:
; NO-LONGCALL: @ %bb.0: @ %entry
; NO-LONGCALL-NEXT: push {r7, lr}
-; NO-LONGCALL-NEXT: uxtb r1, r1
+; NO-LONGCALL-NEXT: sxtb r1, r1
; NO-LONGCALL-NEXT: bl memset
; NO-LONGCALL-NEXT: pop {r7, pc}
;
; LONGCALL-O0-LABEL: test_memset:
; LONGCALL-O0: @ %bb.0: @ %entry
; LONGCALL-O0-NEXT: push {r7, lr}
-; LONGCALL-O0-NEXT: uxtb r1, r1
+; LONGCALL-O0-NEXT: sxtb r1, r1
; LONGCALL-O0-NEXT: ldr r3, .LCPI4_0
; LONGCALL-O0-NEXT: blx r3
; LONGCALL-O0-NEXT: pop {r7, pc}
@@ -287,7 +287,7 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; XO-LONGCALL-NEXT: .save {r11, lr}
; XO-LONGCALL-NEXT: push {r11, lr}
; XO-LONGCALL-NEXT: movw r3, :lower16:memset
-; XO-LONGCALL-NEXT: uxtb r1, r1
+; XO-LONGCALL-NEXT: sxtb r1, r1
; XO-LONGCALL-NEXT: movt r3, :upper16:memset
; XO-LONGCALL-NEXT: blx r3
; XO-LONGCALL-NEXT: pop {r11, pc}
@@ -297,7 +297,7 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; PIC-LONGCALL-NEXT: .save {r11, lr}
; PIC-LONGCALL-NEXT: push {r11, lr}
; PIC-LONGCALL-NEXT: ldr r3, .LCPI4_0
-; PIC-LONGCALL-NEXT: uxtb r1, r1
+; PIC-LONGCALL-NEXT: sxtb r1, r1
; PIC-LONGCALL-NEXT: .LPC4_0:
; PIC-LONGCALL-NEXT: ldr r3, [pc, r3]
; PIC-LONGCALL-NEXT: blx r3
diff --git a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
index 354c53e8d97b34..595f8a52f06c01 100644
--- a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
@@ -83,8 +83,7 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
; CHECKRELOC64-NEXT: 000000000000000a: R_TOC (idx: [[#NFA+13]]) s[TC]
; CHECKRELOC64-NEXT: c: f8 01 00 80 std 0, 128(1)
; CHECKRELOC-NEXT: 10: 80 a3 00 04 lwz 5, 4(3)
-; CHECKRELOC32-NEXT: 14: 54 a4 06 3e clrlwi 4, 5, 24
-; CHECKRELOC64-NEXT: 14: 78 a4 06 20 clrldi 4, 5, 56
+; CHECKRELOC-NEXT: 14: 7c a4 07 74 extsb 4, 5
; CHECKRELOC-NEXT: 18: 4b ff ff e9 bl 0x0
; CHECKRELOC32-NEXT: 00000018: R_RBR (idx: [[#NFA+1]]) .___memset[PR]
; CHECKRELOC64-NEXT: 0000000000000018: R_RBR (idx: [[#NFA+1]]) .___memset64[PR]
diff --git a/llvm/test/CodeGen/PowerPC/milicode32.ll b/llvm/test/CodeGen/PowerPC/milicode32.ll
index ad84bf80a33609..bcec84306425d9 100644
--- a/llvm/test/CodeGen/PowerPC/milicode32.ll
+++ b/llvm/test/CodeGen/PowerPC/milicode32.ll
@@ -244,7 +244,7 @@ define ptr @test_memset(ptr noundef %dst, i32 noundef signext %value, i32 nounde
; CHECK-AIX-32-P9: # %bb.0: # %entry
; CHECK-AIX-32-P9-NEXT: mflr r0
; CHECK-AIX-32-P9-NEXT: stwu r1, -64(r1)
-; CHECK-AIX-32-P9-NEXT: clrlwi r4, r4, 24
+; CHECK-AIX-32-P9-NEXT: extsb r4, r4
; CHECK-AIX-32-P9-NEXT: stw r0, 72(r1)
; CHECK-AIX-32-P9-NEXT: stw r31, 60(r1) # 4-byte Folded Spill
; CHECK-AIX-32-P9-NEXT: mr r31, r3
@@ -261,7 +261,7 @@ define ptr @test_memset(ptr noundef %dst, i32 noundef signext %value, i32 nounde
; CHECK-LINUX32-P9: # %bb.0: # %entry
; CHECK-LINUX32-P9-NEXT: mflr r0
; CHECK-LINUX32-P9-NEXT: stwu r1, -16(r1)
-; CHECK-LINUX32-P9-NEXT: clrlwi r4, r4, 24
+; CHECK-LINUX32-P9-NEXT: extsb r4, r4
; CHECK-LINUX32-P9-NEXT: stw r0, 20(r1)
; CHECK-LINUX32-P9-NEXT: stw r30, 8(r1) # 4-byte Folded Spill
; CHECK-LINUX32-P9-NEXT: mr r30, r3
diff --git a/llvm/test/CodeGen/PowerPC/milicode64.ll b/llvm/test/CodeGen/PowerPC/milicode64.ll
index 8f4c6b495117ad..a4e67173a3d7be 100644
--- a/llvm/test/CodeGen/PowerPC/milicode64.ll
+++ b/llvm/test/CodeGen/PowerPC/milicode64.ll
@@ -302,7 +302,7 @@ define ptr @test_memset(ptr noundef %dst, i32 noundef signext %value, i64 nounde
; CHECK-LE-P9-NEXT: mflr r0
; CHECK-LE-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-LE-P9-NEXT: stdu r1, -48(r1)
-; CHECK-LE-P9-NEXT: clrldi r4, r4, 56
+; CHECK-LE-P9-NEXT: extsb r4, r4
; CHECK-LE-P9-NEXT: std r0, 64(r1)
; CHECK-LE-P9-NEXT: mr r30, r3
; CHECK-LE-P9-NEXT: bl memset
@@ -318,7 +318,7 @@ define ptr @test_memset(ptr noundef %dst, i32 noundef signext %value, i64 nounde
; CHECK-BE-P9: # %bb.0: # %entry
; CHECK-BE-P9-NEXT: mflr r0
; CHECK-BE-P9-NEXT: stdu r1, -128(r1)
-; CHECK-BE-P9-NEXT: clrldi r4, r4, 56
+; CHECK-BE-P9-NEXT: extsb r4, r4
; CHECK-BE-P9-NEXT: std r0, 144(r1)
; CHECK-BE-P9-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; CHECK-BE-P9-NEXT: mr r30, r3
@@ -335,7 +335,7 @@ define ptr @test_memset(ptr noundef %dst, i32 noundef signext %value, i64 nounde
; CHECK-AIX-64-P9: # %bb.0: # %entry
; CHECK-AIX-64-P9-NEXT: mflr r0
; CHECK-AIX-64-P9-NEXT: stdu r1, -128(r1)
-; CHECK-AIX-64-P9-NEXT: clrldi r4, r4, 56
+; CHECK-AIX-64-P9-NEXT: extsb r4, r4
; CHECK-AIX-64-P9-NEXT: std r0, 144(r1)
; CHECK-AIX-64-P9-NEXT: std r31, 120(r1) # 8-byte Folded Spill
; CHECK-AIX-64-P9-NEXT: mr r31, r3
diff --git a/llvm/test/CodeGen/RISCV/memset.ll b/llvm/test/CodeGen/RISCV/memset.ll
index aec21e68c6a79a..eb6cbc88446000 100644
--- a/llvm/test/CodeGen/RISCV/memset.ll
+++ b/llvm/test/CodeGen/RISCV/memset.ll
@@ -7,7 +7,8 @@ define void @memset_i32_var(ptr %dest, i8 %val, i32 %n) nounwind {
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: zext.b a1, a1
+; RV32-NEXT: slli a1, a1, 24
+; RV32-NEXT: srai a1, a1, 24
; RV32-NEXT: call memset
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
@@ -17,8 +18,9 @@ define void @memset_i32_var(ptr %dest, i8 %val, i32 %n) nounwind {
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: zext.b a1, a1
+; RV64-NEXT: slli a1, a1, 56
; RV64-NEXT: slli a2, a2, 32
+; RV64-NEXT: srai a1, a1, 56
; RV64-NEXT: srli a2, a2, 32
; RV64-NEXT: call memset
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -34,7 +36,8 @@ define void @memset_i32_2147483648(ptr %dest, i8 %val) nounwind {
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: zext.b a1, a1
+; RV32-NEXT: slli a1, a1, 24
+; RV32-NEXT: srai a1, a1, 24
; RV32-NEXT: lui a2, 524288
; RV32-NEXT: call memset
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -45,8 +48,9 @@ define void @memset_i32_2147483648(ptr %dest, i8 %val) nounwind {
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: zext.b a1, a1
+; RV64-NEXT: slli a1, a1, 56
; RV64-NEXT: li a2, 1
+; RV64-NEXT: srai a1, a1, 56
; RV64-NEXT: slli a2, a2, 31
; RV64-NEXT: call memset
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -90,7 +94,8 @@ define void @memset_i64_var(ptr %dest, i8 %val, i64 %n) nounwind {
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: zext.b a1, a1
+; RV32-NEXT: slli a1, a1, 24
+; RV32-NEXT: srai a1, a1, 24
; RV32-NEXT: call memset
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
@@ -100,7 +105,8 @@ define void @memset_i64_var(ptr %dest, i8 %val, i64 %n) nounwind {
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: zext.b a1, a1
+; RV64-NEXT: slli a1, a1, 56
+; RV64-NEXT: srai a1, a1, 56
; RV64-NEXT: call memset
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16
@@ -119,8 +125,9 @@ define void @memset_i64_4294967296(ptr %dest, i8 %val) nounwind {
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: zext.b a1, a1
+; RV64-NEXT: slli a1, a1, 56
; RV64-NEXT: li a2, 1
+; RV64-NEXT: srai a1, a1, 56
; RV64-NEXT: slli a2, a2, 32
; RV64-NEXT: call memset
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll b/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
index c0883adbd692af..91df1dbac2b5f9 100644
--- a/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
+++ b/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
@@ -37,7 +37,7 @@ entry:
define void @test2(ptr nocapture %p) nounwind {
; RV32I-LABEL: test2:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: li a1, 165
+; RV32I-NEXT: li a1, -91
; RV32I-NEXT: li a2, 128
; RV32I-NEXT: tail memset
;
@@ -56,7 +56,7 @@ entry:
define void @test2a(ptr nocapture %p) nounwind {
; RV32I-LABEL: test2a:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: li a1, 165
+; RV32I-NEXT: li a1, -91
; RV32I-NEXT: li a2, 188
; RV32I-NEXT: tail memset
;
@@ -76,13 +76,13 @@ entry:
define void @test2b(ptr nocapture %p) nounwind {
; RV32I-LABEL: test2b:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: li a1, 165
+; RV32I-NEXT: li a1, -91
; RV32I-NEXT: li a2, 192
; RV32I-NEXT: tail memset
;
; RV32IXQCILSM-LABEL: test2b:
; RV32IXQCILSM: # %bb.0: # %entry
-; RV32IXQCILSM-NEXT: li a1, 165
+; RV32IXQCILSM-NEXT: li a1, -91
; RV32IXQCILSM-NEXT: li a2, 192
; RV32IXQCILSM-NEXT: tail memset
entry:
@@ -93,7 +93,7 @@ entry:
define void @test2c(ptr nocapture %p) nounwind {
; RV32I-LABEL: test2c:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: li a1, 165
+; RV32I-NEXT: li a1, -91
; RV32I-NEXT: li a2, 128
; RV32I-NEXT: tail memset
;
@@ -196,7 +196,7 @@ entry:
define void @test4a(ptr nocapture %s) nounwind {
; RV32I-LABEL: test4a:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: li a1, 166
+; RV32I-NEXT: li a1, -90
; RV32I-NEXT: li a2, 64
; RV32I-NEXT: tail memset
;
@@ -551,7 +551,7 @@ define void @test7b() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
-; RV32I-NEXT: li a1, 255
+; RV32I-NEXT: li a1, -1
; RV32I-NEXT: li a2, 68
; RV32I-NEXT: tail memset
;
@@ -573,7 +573,7 @@ define void @test7c() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
-; RV32I-NEXT: li a1, 128
+; RV32I-NEXT: li a1, -128
; RV32I-NEXT: li a2, 128
; RV32I-NEXT: tail memset
;
@@ -620,7 +620,7 @@ define void @test7e() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
-; RV32I-NEXT: li a1, 239
+; RV32I-NEXT: li a1, -17
; RV32I-NEXT: li a2, 100
; RV32I-NEXT: tail memset
;
@@ -818,7 +818,7 @@ define void @test15a() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
-; RV32I-NEXT: li a1, 165
+; RV32I-NEXT: li a1, -91
; RV32I-NEXT: li a2, 192
; RV32I-NEXT: tail memset
;
@@ -826,7 +826,7 @@ define void @test15a() nounwind {
; RV32IXQCILSM: # %bb.0: # %entry
; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
-; RV32IXQCILSM-NEXT: li a1, 165
+; RV32IXQCILSM-NEXT: li a1, -91
; RV32IXQCILSM-NEXT: li a2, 192
; RV32IXQCILSM-NEXT: tail memset
entry:
diff --git a/llvm/test/CodeGen/WebAssembly/disable-feature.ll b/llvm/test/CodeGen/WebAssembly/disable-feature.ll
index e8f72ac574a4e7..0d182ba4e1a0bd 100644
--- a/llvm/test/CodeGen/WebAssembly/disable-feature.ll
+++ b/llvm/test/CodeGen/WebAssembly/disable-feature.ll
@@ -39,8 +39,10 @@ define void @lower_bulk_memory(i8 %val) #0 {
; CHECK-NEXT: i32.const 12
; CHECK-NEXT: i32.add
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: i32.const 255
-; CHECK-NEXT: i32.and
+; CHECK-NEXT: i32.const 24
+; CHECK-NEXT: i32.shl
+; CHECK-NEXT: i32.const 24
+; CHECK-NEXT: i32.shr_s
; CHECK-NEXT: i32.const 100
; CHECK-NEXT: call memset
; CHECK-NEXT: drop
diff --git a/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
index e3c74d175a4509..49607a31c55d02 100644
--- a/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
+++ b/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
@@ -54,10 +54,12 @@ define ptr @set_yes(ptr %dst, i8 %src, i32 %len) {
; CHECK-LABEL: set_yes:
; CHECK: .functype set_yes (i32, i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: i32.const $push0=, 255
-; CHECK-NEXT: i32.and $push1=, $1, $pop0
-; CHECK-NEXT: call $push2=, memset, $0, $pop1, $2
-; CHECK-NEXT: return $pop2
+; CHECK-NEXT: i32.const $push0=, 24
+; CHECK-NEXT: i32.shl $push1=, $1, $pop0
+; CHECK-NEXT: i32.const $push4=, 24
+; CHECK-NEXT: i32.shr_s $push2=, $pop1, $pop4
+; CHECK-NEXT: call $push3=, memset, $0, $pop2, $2
+; CHECK-NEXT: return $pop3
call void @llvm.memset.p0.i32(ptr %dst, i8 %src, i32 %len, i1 false)
ret ptr %dst
}
@@ -66,9 +68,11 @@ define void @set_no(ptr %dst, i8 %src, i32 %len) {
; CHECK-LABEL: set_no:
; CHECK: .functype set_no (i32, i32, i32) -> ()
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: i32.const $push0=, 255
-; CHECK-NEXT: i32.and $push1=, $1, $pop0
-; CHECK-NEXT: call $drop=, memset, $0, $pop1, $2
+; CHECK-NEXT: i32.const $push0=, 24
+; CHECK-NEXT: i32.shl $push1=, $1, $pop0
+; CHECK-NEXT: i32.const $push3=, 24
+; CHECK-NEXT: i32.shr_s $push2=, $pop1, $pop3
+; CHECK-NEXT: call $drop=, memset, $0, $pop2, $2
; CHECK-NEXT: return
call void @llvm.memset.p0.i32(ptr %dst, i8 %src, i32 %len, i1 false)
ret void
@@ -119,9 +123,11 @@ define ptr @drop_result(ptr %arg, i8 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: br_if 1, $4 # 1: down to label0
; CHECK-NEXT: # %bb.2: # %bb7
-; CHECK-NEXT: i32.const $push0=, 255
-; CHECK-NEXT: i32.and $push1=, $1, $pop0
-; CHECK-NEXT: call $drop=, memset, $0, $pop1, $2
+; CHECK-NEXT: i32.const $push0=, 24
+; CHECK-NEXT: i32.shl $push1=, $1, $pop0
+; CHECK-NEXT: i32.const $push3=, 24
+; CHECK-NEXT: i32.shr_s $push2=, $pop1, $pop3
+; CHECK-NEXT: call $drop=, memset, $0, $pop2, $2
; CHECK-NEXT: call block_tail_dup
; CHECK-NEXT: return $0
; CHECK-NEXT: .LBB7_3: # %bb9
@@ -169,10 +175,12 @@ define ptr @tail_dup_to_reuse_result(ptr %arg, i8 %arg1, i32 %arg2, i32 %arg3, i
; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: br_if 1, $4 # 1: down to label2
; CHECK-NEXT: # %bb.2: # %bb7
-; CHECK-NEXT: i32.const $push0=, 255
-; CHECK-NEXT: i32.and $push1=, $1, $pop0
-; CHECK-NEXT: call $push2=, memset, $0, $pop1, $2
-; CHECK-NEXT: return $pop2
+; CHECK-NEXT: i32.const $push0=, 24
+; CHECK-NEXT: i32.shl $push1=, $1, $pop0
+; CHECK-NEXT: i32.const $push4=, 24
+; CHECK-NEXT: i32.shr_s $push2=, $pop1, $pop4
+; CHECK-NEXT: call $push3=, memset, $0, $pop2, $2
+; CHECK-NEXT: return $pop3
; CHECK-NEXT: .LBB8_3: # %bb9
; CHECK-NEXT: end_block # label3:
; CHECK-NEXT: call $0=, def
diff --git a/llvm/test/CodeGen/X86/memset-2.ll b/llvm/test/CodeGen/X86/memset-2.ll
index d75838dd1972db..a4fbbc57004708 100644
--- a/llvm/test/CodeGen/X86/memset-2.ll
+++ b/llvm/test/CodeGen/X86/memset-2.ll
@@ -20,9 +20,8 @@ define fastcc void @t2(ptr nocapture %s, i8 signext %c) nounwind {
; CHECK-LABEL: t2:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: subl $16, %esp
-; CHECK-NEXT: movzbl %dl, %eax
; CHECK-NEXT: pushl $76
-; CHECK-NEXT: pushl %eax
+; CHECK-NEXT: pushl %edx
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: calll _memset
; CHECK-NEXT: addl $16, %esp
diff --git a/llvm/test/CodeGen/X86/memset-nonzero.ll b/llvm/test/CodeGen/X86/memset-nonzero.ll
index af8ab4e724d1e1..d5b1ab6fd06570 100644
--- a/llvm/test/CodeGen/X86/memset-nonzero.ll
+++ b/llvm/test/CodeGen/X86/memset-nonzero.ll
@@ -525,7 +525,7 @@ define void @memset_128_nonconst_bytes(ptr %x, i8 %c) {
define void @memset_256_nonconst_bytes(ptr %x, i8 %c) {
; SSE-LABEL: memset_256_nonconst_bytes:
; SSE: # %bb.0:
-; SSE-NEXT: movzbl %sil, %esi
+; SSE-NEXT: movsbl %sil, %esi
; SSE-NEXT: movl $256, %edx # imm = 0x100
; SSE-NEXT: jmp memset at PLT # TAILCALL
;
diff --git a/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll b/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll
index 6a1b336c65f2dc..4f3e975708ed3f 100644
--- a/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll
+++ b/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll
@@ -19,7 +19,7 @@ define void @test1(ptr %a, i8 %value) nounwind {
define void @regular_memset_calls_external_function(ptr %a, i8 %value) nounwind {
; CHECK-LABEL: regular_memset_calls_external_function:
; CHECK: # %bb.0:
-; CHECK-NEXT: movzbl %sil, %esi
+; CHECK-NEXT: movsbl %sil, %esi
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: jmp memset at PLT # TAILCALL
tail call void @llvm.memset.p0.i64(ptr %a, i8 %value, i64 1024, i1 0)
diff --git a/llvm/test/CodeGen/X86/optimize-max-0.ll b/llvm/test/CodeGen/X86/optimize-max-0.ll
index b6af7e1641a9c6..afbc519d8bf062 100644
--- a/llvm/test/CodeGen/X86/optimize-max-0.ll
+++ b/llvm/test/CodeGen/X86/optimize-max-0.ll
@@ -212,7 +212,7 @@ define void @foo(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind {
; CHECK-NEXT: sarl %eax
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: pushl $128
+; CHECK-NEXT: pushl $-128
; CHECK-NEXT: pushl %edx
; CHECK-NEXT: calll _memset
; CHECK-NEXT: addl $44, %esp
@@ -612,7 +612,7 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind {
; CHECK-NEXT: shrl %ecx
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %ecx
-; CHECK-NEXT: pushl $128
+; CHECK-NEXT: pushl $-128
; CHECK-NEXT: pushl %edx
; CHECK-NEXT: jmp LBB1_23
; CHECK-NEXT: LBB1_19: ## %bb29
@@ -647,7 +647,7 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind {
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: pushl $128
+; CHECK-NEXT: pushl $-128
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: LBB1_23: ## %bb33
; CHECK-NEXT: calll _memset
>From 196081a02f02ca731607ef32609c4e22ac626adb Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: Thu, 8 Oct 2026 23:36:32 +0200
Subject: [PATCH 5/5] Any-extend i8 Src to i32 and treat as int.
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 +-
llvm/test/CodeGen/AArch64/aarch64-mops.ll | 8 +--
.../AArch64/memset-vs-memset-inline.ll | 1 -
.../ARM/subtarget-features-long-calls.ll | 58 +------------------
llvm/test/CodeGen/MSP430/memset.ll | 3 +-
.../CodeGen/PowerPC/aix-llvm-intrinsic.ll | 6 +-
llvm/test/CodeGen/PowerPC/milicode32.ll | 2 -
llvm/test/CodeGen/RISCV/memset.ll | 6 --
llvm/test/CodeGen/RISCV/xqcilsm-memset.ll | 22 +++----
.../CodeGen/WebAssembly/disable-feature.ll | 4 --
.../CodeGen/WebAssembly/mem-intrinsics.ll | 28 ++-------
llvm/test/CodeGen/X86/memset-nonzero.ll | 1 -
.../CodeGen/X86/memset-vs-memset-inline.ll | 1 -
llvm/test/CodeGen/X86/optimize-max-0.ll | 6 +-
14 files changed, 32 insertions(+), 118 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index dc1b981b8f12f7..af43aab6916575 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10498,8 +10498,8 @@ SDValue SelectionDAG::getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst,
TargetLowering::ArgListTy Args;
Args.emplace_back(Dst, PointerType::getUnqual(Ctx));
- Args.emplace_back(Src, Src.getValueType().getTypeForEVT(Ctx),
- LibInfo->getExtAttrForI8Param());
+ Args.emplace_back(getAnyExtOrTrunc(Src, dl, MVT::i32),
+ Type::getInt32Ty(Ctx), LibInfo->getExtAttrForI32Param());
Args.emplace_back(Size, DL.getIntPtrType(Ctx));
CLI.setLibCallee(Libcalls->getLibcallImplCallingConv(MemsetImpl),
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops.ll b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
index 5dc25d160c6818..f673c9b68800f2 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
@@ -666,7 +666,6 @@ define void @memset_10000(ptr %dst, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
-; SDAG-WITHOUT-MOPS-O2-NEXT: sxtb w1, w1
; SDAG-WITHOUT-MOPS-O2-NEXT: mov w2, #10000 // =0x2710
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -733,7 +732,6 @@ define void @memset_10000_volatile(ptr %dst, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
-; SDAG-WITHOUT-MOPS-O2-NEXT: sxtb w1, w1
; SDAG-WITHOUT-MOPS-O2-NEXT: mov w2, #10000 // =0x2710
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -803,7 +801,7 @@ define void @memset_size(ptr %dst, i64 %size, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x8, x1
-; SDAG-WITHOUT-MOPS-O2-NEXT: sxtb w1, w2
+; SDAG-WITHOUT-MOPS-O2-NEXT: mov w1, w2
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x2, x8
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -872,7 +870,7 @@ define void @memset_size_volatile(ptr %dst, i64 %size, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x8, x1
-; SDAG-WITHOUT-MOPS-O2-NEXT: sxtb w1, w2
+; SDAG-WITHOUT-MOPS-O2-NEXT: mov w1, w2
; SDAG-WITHOUT-MOPS-O2-NEXT: mov x2, x8
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
; SDAG-WITHOUT-MOPS-O2-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -2892,7 +2890,7 @@ define void @memset_size_i32(ptr %dst, i32 %size, i32 %value) {
; SDAG-WITHOUT-MOPS-O2-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_def_cfa_offset 16
; SDAG-WITHOUT-MOPS-O2-NEXT: .cfi_offset w30, -16
-; SDAG-WITHOUT-MOPS-O2-NEXT: sxtb w8, w2
+; SDAG-WITHOUT-MOPS-O2-NEXT: mov w8, w2
; SDAG-WITHOUT-MOPS-O2-NEXT: mov w2, w1
; SDAG-WITHOUT-MOPS-O2-NEXT: mov w1, w8
; SDAG-WITHOUT-MOPS-O2-NEXT: bl memset
diff --git a/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll b/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
index 4cac6835147168..0a730617c5e196 100644
--- a/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
+++ b/llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
@@ -17,7 +17,6 @@ define void @test1(ptr %a, i8 %value) nounwind {
define void @regular_memset_calls_external_function(ptr %a, i8 %value) nounwind {
; CHECK-LABEL: regular_memset_calls_external_function:
; CHECK: // %bb.0:
-; CHECK-NEXT: sxtb w1, w1
; CHECK-NEXT: mov w2, #1024 // =0x400
; CHECK-NEXT: b memset
tail call void @llvm.memset.p0.i64(ptr %a, i8 %value, i64 1024, i1 0)
diff --git a/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll b/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
index 6286196941d92b..24fc8b7ee2e9b7 100644
--- a/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
+++ b/llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
@@ -3,7 +3,7 @@
; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=+long-calls | FileCheck -check-prefix=LONGCALL %s
; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=-long-calls | FileCheck -check-prefix=NO-LONGCALL %s
; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 | FileCheck -check-prefix=NO-OPTION %s
-; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=+long-calls | FileCheck -check-prefix=LONGCALL-O0 %s
+; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=+long-calls | FileCheck -check-prefix=LONGCALL %s
; RUN: llc -mtriple=thumb-- -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=-long-calls | FileCheck -check-prefix=NO-LONGCALL %s
; RUN: llc -mtriple=arm-linux-gnueabi -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=+long-calls,+execute-only | FileCheck -check-prefix=XO-LONGCALL %s
; RUN: llc -mtriple=arm-linux-gnueabi -mcpu=cortex-a8 -relocation-model=pic %s -o - -mattr=+long-calls | FileCheck -check-prefix=PIC-LONGCALL %s
@@ -40,18 +40,6 @@ define i32 @caller0() #0 {
; NO-LONGCALL-NEXT: movs r0, #0
; NO-LONGCALL-NEXT: pop {r7, pc}
;
-; LONGCALL-O0-LABEL: caller0:
-; LONGCALL-O0: @ %bb.0: @ %entry
-; LONGCALL-O0-NEXT: push {r7, lr}
-; LONGCALL-O0-NEXT: ldr r0, .LCPI0_0
-; LONGCALL-O0-NEXT: blx r0
-; LONGCALL-O0-NEXT: movs r0, #0
-; LONGCALL-O0-NEXT: pop {r7, pc}
-; LONGCALL-O0-NEXT: .p2align 2
-; LONGCALL-O0-NEXT: @ %bb.1:
-; LONGCALL-O0-NEXT: .LCPI0_0:
-; LONGCALL-O0-NEXT: .long callee0
-;
; XO-LONGCALL-LABEL: caller0:
; XO-LONGCALL: @ %bb.0: @ %entry
; XO-LONGCALL-NEXT: .save {r11, lr}
@@ -109,18 +97,6 @@ define i32 @caller1() {
; NO-LONGCALL-NEXT: movs r0, #0
; NO-LONGCALL-NEXT: pop {r7, pc}
;
-; LONGCALL-O0-LABEL: caller1:
-; LONGCALL-O0: @ %bb.0: @ %entry
-; LONGCALL-O0-NEXT: push {r7, lr}
-; LONGCALL-O0-NEXT: ldr r0, .LCPI1_0
-; LONGCALL-O0-NEXT: blx r0
-; LONGCALL-O0-NEXT: movs r0, #0
-; LONGCALL-O0-NEXT: pop {r7, pc}
-; LONGCALL-O0-NEXT: .p2align 2
-; LONGCALL-O0-NEXT: @ %bb.1:
-; LONGCALL-O0-NEXT: .LCPI1_0:
-; LONGCALL-O0-NEXT: .long callee0
-;
; XO-LONGCALL-LABEL: caller1:
; XO-LONGCALL: @ %bb.0: @ %entry
; XO-LONGCALL-NEXT: .save {r11, lr}
@@ -168,10 +144,6 @@ define dso_local void @global_func() {
; NO-LONGCALL: @ %bb.0: @ %entry
; NO-LONGCALL-NEXT: bx lr
;
-; LONGCALL-O0-LABEL: global_func:
-; LONGCALL-O0: @ %bb.0: @ %entry
-; LONGCALL-O0-NEXT: bx lr
-;
; XO-LONGCALL-LABEL: global_func:
; XO-LONGCALL: @ %bb.0: @ %entry
; XO-LONGCALL-NEXT: bx lr
@@ -203,17 +175,6 @@ define void @test_global() {
; NO-LONGCALL-NEXT: bl global_func
; NO-LONGCALL-NEXT: pop {r7, pc}
;
-; LONGCALL-O0-LABEL: test_global:
-; LONGCALL-O0: @ %bb.0: @ %entry
-; LONGCALL-O0-NEXT: push {r7, lr}
-; LONGCALL-O0-NEXT: ldr r0, .LCPI3_0
-; LONGCALL-O0-NEXT: blx r0
-; LONGCALL-O0-NEXT: pop {r7, pc}
-; LONGCALL-O0-NEXT: .p2align 2
-; LONGCALL-O0-NEXT: @ %bb.1:
-; LONGCALL-O0-NEXT: .LCPI3_0:
-; LONGCALL-O0-NEXT: .long global_func
-;
; XO-LONGCALL-LABEL: test_global:
; XO-LONGCALL: @ %bb.0: @ %entry
; XO-LONGCALL-NEXT: .save {r11, lr}
@@ -247,7 +208,6 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; NO-OPTION-LABEL: test_memset:
; NO-OPTION: @ %bb.0: @ %entry
; NO-OPTION-NEXT: push {r7, lr}
-; NO-OPTION-NEXT: sxtb r1, r1
; NO-OPTION-NEXT: bl memset
; NO-OPTION-NEXT: pop {r7, pc}
;
@@ -255,7 +215,6 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; LONGCALL: @ %bb.0: @ %entry
; LONGCALL-NEXT: push {r7, lr}
; LONGCALL-NEXT: ldr r3, .LCPI4_0
-; LONGCALL-NEXT: sxtb r1, r1
; LONGCALL-NEXT: blx r3
; LONGCALL-NEXT: pop {r7, pc}
; LONGCALL-NEXT: .p2align 2
@@ -266,28 +225,14 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; NO-LONGCALL-LABEL: test_memset:
; NO-LONGCALL: @ %bb.0: @ %entry
; NO-LONGCALL-NEXT: push {r7, lr}
-; NO-LONGCALL-NEXT: sxtb r1, r1
; NO-LONGCALL-NEXT: bl memset
; NO-LONGCALL-NEXT: pop {r7, pc}
;
-; LONGCALL-O0-LABEL: test_memset:
-; LONGCALL-O0: @ %bb.0: @ %entry
-; LONGCALL-O0-NEXT: push {r7, lr}
-; LONGCALL-O0-NEXT: sxtb r1, r1
-; LONGCALL-O0-NEXT: ldr r3, .LCPI4_0
-; LONGCALL-O0-NEXT: blx r3
-; LONGCALL-O0-NEXT: pop {r7, pc}
-; LONGCALL-O0-NEXT: .p2align 2
-; LONGCALL-O0-NEXT: @ %bb.1:
-; LONGCALL-O0-NEXT: .LCPI4_0:
-; LONGCALL-O0-NEXT: .long memset
-;
; XO-LONGCALL-LABEL: test_memset:
; XO-LONGCALL: @ %bb.0: @ %entry
; XO-LONGCALL-NEXT: .save {r11, lr}
; XO-LONGCALL-NEXT: push {r11, lr}
; XO-LONGCALL-NEXT: movw r3, :lower16:memset
-; XO-LONGCALL-NEXT: sxtb r1, r1
; XO-LONGCALL-NEXT: movt r3, :upper16:memset
; XO-LONGCALL-NEXT: blx r3
; XO-LONGCALL-NEXT: pop {r11, pc}
@@ -297,7 +242,6 @@ define void @test_memset(ptr %dst, i8 %val, i32 %len) {
; PIC-LONGCALL-NEXT: .save {r11, lr}
; PIC-LONGCALL-NEXT: push {r11, lr}
; PIC-LONGCALL-NEXT: ldr r3, .LCPI4_0
-; PIC-LONGCALL-NEXT: sxtb r1, r1
; PIC-LONGCALL-NEXT: .LPC4_0:
; PIC-LONGCALL-NEXT: ldr r3, [pc, r3]
; PIC-LONGCALL-NEXT: blx r3
diff --git a/llvm/test/CodeGen/MSP430/memset.ll b/llvm/test/CodeGen/MSP430/memset.ll
index ad0b0edef69aa6..e28a85a99b1b79 100644
--- a/llvm/test/CodeGen/MSP430/memset.ll
+++ b/llvm/test/CodeGen/MSP430/memset.ll
@@ -11,7 +11,8 @@ entry:
%0 = load ptr, ptr @buf, align 2
; CHECK: mov &buf, r12
; CHECK-NEXT: mov #5, r13
-; CHECK-NEXT: mov #128, r14
+; CHECK-NEXT: clr r14
+; CHECK-NEXT: mov #128, r15
; CHECK-NEXT: call #memset
call void @llvm.memset.p0.i16(ptr %0, i8 5, i16 128, i1 false)
ret void
diff --git a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
index 595f8a52f06c01..54296957ae17b3 100644
--- a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
@@ -78,12 +78,14 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
; CHECKRELOC32-NEXT: 8: 80 62 00 00 lwz 3, 0(2)
; CHECKRELOC32-NEXT: 0000000a: R_TOC (idx: [[#NFA+13]]) s[TC]
; CHECKRELOC32-NEXT: c: 90 01 00 48 stw 0, 72(1)
+; CHECKRELOC32-NEXT: 10: 80 83 00 04 lwz 4, 4(3)
+; CHECKRELOC32-NEXT: 14: 7c 85 23 78 mr 5, 4
; CHECKRELOC64-NEXT: 4: f8 21 ff 91 stdu 1, -112(1)
; CHECKRELOC64-NEXT: 8: e8 62 00 00 ld 3, 0(2)
; CHECKRELOC64-NEXT: 000000000000000a: R_TOC (idx: [[#NFA+13]]) s[TC]
; CHECKRELOC64-NEXT: c: f8 01 00 80 std 0, 128(1)
-; CHECKRELOC-NEXT: 10: 80 a3 00 04 lwz 5, 4(3)
-; CHECKRELOC-NEXT: 14: 7c a4 07 74 extsb 4, 5
+; CHECKRELOC64-NEXT: 10: e8 83 00 06 lwa 4, 4(3)
+; CHECKRELOC64-NEXT: 14: 78 85 00 20 clrldi 5, 4, 32
; CHECKRELOC-NEXT: 18: 4b ff ff e9 bl 0x0
; CHECKRELOC32-NEXT: 00000018: R_RBR (idx: [[#NFA+1]]) .___memset[PR]
; CHECKRELOC64-NEXT: 0000000000000018: R_RBR (idx: [[#NFA+1]]) .___memset64[PR]
diff --git a/llvm/test/CodeGen/PowerPC/milicode32.ll b/llvm/test/CodeGen/PowerPC/milicode32.ll
index bcec84306425d9..f2caec7e0045f7 100644
--- a/llvm/test/CodeGen/PowerPC/milicode32.ll
+++ b/llvm/test/CodeGen/PowerPC/milicode32.ll
@@ -244,7 +244,6 @@ define ptr @test_memset(ptr noundef %dst, i32 noundef signext %value, i32 nounde
; CHECK-AIX-32-P9: # %bb.0: # %entry
; CHECK-AIX-32-P9-NEXT: mflr r0
; CHECK-AIX-32-P9-NEXT: stwu r1, -64(r1)
-; CHECK-AIX-32-P9-NEXT: extsb r4, r4
; CHECK-AIX-32-P9-NEXT: stw r0, 72(r1)
; CHECK-AIX-32-P9-NEXT: stw r31, 60(r1) # 4-byte Folded Spill
; CHECK-AIX-32-P9-NEXT: mr r31, r3
@@ -261,7 +260,6 @@ define ptr @test_memset(ptr noundef %dst, i32 noundef signext %value, i32 nounde
; CHECK-LINUX32-P9: # %bb.0: # %entry
; CHECK-LINUX32-P9-NEXT: mflr r0
; CHECK-LINUX32-P9-NEXT: stwu r1, -16(r1)
-; CHECK-LINUX32-P9-NEXT: extsb r4, r4
; CHECK-LINUX32-P9-NEXT: stw r0, 20(r1)
; CHECK-LINUX32-P9-NEXT: stw r30, 8(r1) # 4-byte Folded Spill
; CHECK-LINUX32-P9-NEXT: mr r30, r3
diff --git a/llvm/test/CodeGen/RISCV/memset.ll b/llvm/test/CodeGen/RISCV/memset.ll
index eb6cbc88446000..e130226865ff78 100644
--- a/llvm/test/CodeGen/RISCV/memset.ll
+++ b/llvm/test/CodeGen/RISCV/memset.ll
@@ -7,8 +7,6 @@ define void @memset_i32_var(ptr %dest, i8 %val, i32 %n) nounwind {
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: slli a1, a1, 24
-; RV32-NEXT: srai a1, a1, 24
; RV32-NEXT: call memset
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
@@ -36,8 +34,6 @@ define void @memset_i32_2147483648(ptr %dest, i8 %val) nounwind {
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: slli a1, a1, 24
-; RV32-NEXT: srai a1, a1, 24
; RV32-NEXT: lui a2, 524288
; RV32-NEXT: call memset
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -94,8 +90,6 @@ define void @memset_i64_var(ptr %dest, i8 %val, i64 %n) nounwind {
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: slli a1, a1, 24
-; RV32-NEXT: srai a1, a1, 24
; RV32-NEXT: call memset
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll b/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
index 91df1dbac2b5f9..c0883adbd692af 100644
--- a/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
+++ b/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
@@ -37,7 +37,7 @@ entry:
define void @test2(ptr nocapture %p) nounwind {
; RV32I-LABEL: test2:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: li a1, -91
+; RV32I-NEXT: li a1, 165
; RV32I-NEXT: li a2, 128
; RV32I-NEXT: tail memset
;
@@ -56,7 +56,7 @@ entry:
define void @test2a(ptr nocapture %p) nounwind {
; RV32I-LABEL: test2a:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: li a1, -91
+; RV32I-NEXT: li a1, 165
; RV32I-NEXT: li a2, 188
; RV32I-NEXT: tail memset
;
@@ -76,13 +76,13 @@ entry:
define void @test2b(ptr nocapture %p) nounwind {
; RV32I-LABEL: test2b:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: li a1, -91
+; RV32I-NEXT: li a1, 165
; RV32I-NEXT: li a2, 192
; RV32I-NEXT: tail memset
;
; RV32IXQCILSM-LABEL: test2b:
; RV32IXQCILSM: # %bb.0: # %entry
-; RV32IXQCILSM-NEXT: li a1, -91
+; RV32IXQCILSM-NEXT: li a1, 165
; RV32IXQCILSM-NEXT: li a2, 192
; RV32IXQCILSM-NEXT: tail memset
entry:
@@ -93,7 +93,7 @@ entry:
define void @test2c(ptr nocapture %p) nounwind {
; RV32I-LABEL: test2c:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: li a1, -91
+; RV32I-NEXT: li a1, 165
; RV32I-NEXT: li a2, 128
; RV32I-NEXT: tail memset
;
@@ -196,7 +196,7 @@ entry:
define void @test4a(ptr nocapture %s) nounwind {
; RV32I-LABEL: test4a:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: li a1, -90
+; RV32I-NEXT: li a1, 166
; RV32I-NEXT: li a2, 64
; RV32I-NEXT: tail memset
;
@@ -551,7 +551,7 @@ define void @test7b() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
-; RV32I-NEXT: li a1, -1
+; RV32I-NEXT: li a1, 255
; RV32I-NEXT: li a2, 68
; RV32I-NEXT: tail memset
;
@@ -573,7 +573,7 @@ define void @test7c() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
-; RV32I-NEXT: li a1, -128
+; RV32I-NEXT: li a1, 128
; RV32I-NEXT: li a2, 128
; RV32I-NEXT: tail memset
;
@@ -620,7 +620,7 @@ define void @test7e() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
-; RV32I-NEXT: li a1, -17
+; RV32I-NEXT: li a1, 239
; RV32I-NEXT: li a2, 100
; RV32I-NEXT: tail memset
;
@@ -818,7 +818,7 @@ define void @test15a() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
-; RV32I-NEXT: li a1, -91
+; RV32I-NEXT: li a1, 165
; RV32I-NEXT: li a2, 192
; RV32I-NEXT: tail memset
;
@@ -826,7 +826,7 @@ define void @test15a() nounwind {
; RV32IXQCILSM: # %bb.0: # %entry
; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
-; RV32IXQCILSM-NEXT: li a1, -91
+; RV32IXQCILSM-NEXT: li a1, 165
; RV32IXQCILSM-NEXT: li a2, 192
; RV32IXQCILSM-NEXT: tail memset
entry:
diff --git a/llvm/test/CodeGen/WebAssembly/disable-feature.ll b/llvm/test/CodeGen/WebAssembly/disable-feature.ll
index 0d182ba4e1a0bd..5f7275f3699ede 100644
--- a/llvm/test/CodeGen/WebAssembly/disable-feature.ll
+++ b/llvm/test/CodeGen/WebAssembly/disable-feature.ll
@@ -39,10 +39,6 @@ define void @lower_bulk_memory(i8 %val) #0 {
; CHECK-NEXT: i32.const 12
; CHECK-NEXT: i32.add
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: i32.const 24
-; CHECK-NEXT: i32.shl
-; CHECK-NEXT: i32.const 24
-; CHECK-NEXT: i32.shr_s
; CHECK-NEXT: i32.const 100
; CHECK-NEXT: call memset
; CHECK-NEXT: drop
diff --git a/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
index 49607a31c55d02..51e6c2836a20ff 100644
--- a/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
+++ b/llvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
@@ -54,12 +54,8 @@ define ptr @set_yes(ptr %dst, i8 %src, i32 %len) {
; CHECK-LABEL: set_yes:
; CHECK: .functype set_yes (i32, i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: i32.const $push0=, 24
-; CHECK-NEXT: i32.shl $push1=, $1, $pop0
-; CHECK-NEXT: i32.const $push4=, 24
-; CHECK-NEXT: i32.shr_s $push2=, $pop1, $pop4
-; CHECK-NEXT: call $push3=, memset, $0, $pop2, $2
-; CHECK-NEXT: return $pop3
+; CHECK-NEXT: call $push0=, memset, $0, $1, $2
+; CHECK-NEXT: return $pop0
call void @llvm.memset.p0.i32(ptr %dst, i8 %src, i32 %len, i1 false)
ret ptr %dst
}
@@ -68,11 +64,7 @@ define void @set_no(ptr %dst, i8 %src, i32 %len) {
; CHECK-LABEL: set_no:
; CHECK: .functype set_no (i32, i32, i32) -> ()
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: i32.const $push0=, 24
-; CHECK-NEXT: i32.shl $push1=, $1, $pop0
-; CHECK-NEXT: i32.const $push3=, 24
-; CHECK-NEXT: i32.shr_s $push2=, $pop1, $pop3
-; CHECK-NEXT: call $drop=, memset, $0, $pop2, $2
+; CHECK-NEXT: call $drop=, memset, $0, $1, $2
; CHECK-NEXT: return
call void @llvm.memset.p0.i32(ptr %dst, i8 %src, i32 %len, i1 false)
ret void
@@ -123,11 +115,7 @@ define ptr @drop_result(ptr %arg, i8 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: br_if 1, $4 # 1: down to label0
; CHECK-NEXT: # %bb.2: # %bb7
-; CHECK-NEXT: i32.const $push0=, 24
-; CHECK-NEXT: i32.shl $push1=, $1, $pop0
-; CHECK-NEXT: i32.const $push3=, 24
-; CHECK-NEXT: i32.shr_s $push2=, $pop1, $pop3
-; CHECK-NEXT: call $drop=, memset, $0, $pop2, $2
+; CHECK-NEXT: call $drop=, memset, $0, $1, $2
; CHECK-NEXT: call block_tail_dup
; CHECK-NEXT: return $0
; CHECK-NEXT: .LBB7_3: # %bb9
@@ -175,12 +163,8 @@ define ptr @tail_dup_to_reuse_result(ptr %arg, i8 %arg1, i32 %arg2, i32 %arg3, i
; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: br_if 1, $4 # 1: down to label2
; CHECK-NEXT: # %bb.2: # %bb7
-; CHECK-NEXT: i32.const $push0=, 24
-; CHECK-NEXT: i32.shl $push1=, $1, $pop0
-; CHECK-NEXT: i32.const $push4=, 24
-; CHECK-NEXT: i32.shr_s $push2=, $pop1, $pop4
-; CHECK-NEXT: call $push3=, memset, $0, $pop2, $2
-; CHECK-NEXT: return $pop3
+; CHECK-NEXT: call $push0=, memset, $0, $1, $2
+; CHECK-NEXT: return $pop0
; CHECK-NEXT: .LBB8_3: # %bb9
; CHECK-NEXT: end_block # label3:
; CHECK-NEXT: call $0=, def
diff --git a/llvm/test/CodeGen/X86/memset-nonzero.ll b/llvm/test/CodeGen/X86/memset-nonzero.ll
index d5b1ab6fd06570..d07b0f64d68c18 100644
--- a/llvm/test/CodeGen/X86/memset-nonzero.ll
+++ b/llvm/test/CodeGen/X86/memset-nonzero.ll
@@ -525,7 +525,6 @@ define void @memset_128_nonconst_bytes(ptr %x, i8 %c) {
define void @memset_256_nonconst_bytes(ptr %x, i8 %c) {
; SSE-LABEL: memset_256_nonconst_bytes:
; SSE: # %bb.0:
-; SSE-NEXT: movsbl %sil, %esi
; SSE-NEXT: movl $256, %edx # imm = 0x100
; SSE-NEXT: jmp memset at PLT # TAILCALL
;
diff --git a/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll b/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll
index 4f3e975708ed3f..e34682aa0fcb42 100644
--- a/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll
+++ b/llvm/test/CodeGen/X86/memset-vs-memset-inline.ll
@@ -19,7 +19,6 @@ define void @test1(ptr %a, i8 %value) nounwind {
define void @regular_memset_calls_external_function(ptr %a, i8 %value) nounwind {
; CHECK-LABEL: regular_memset_calls_external_function:
; CHECK: # %bb.0:
-; CHECK-NEXT: movsbl %sil, %esi
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: jmp memset at PLT # TAILCALL
tail call void @llvm.memset.p0.i64(ptr %a, i8 %value, i64 1024, i1 0)
diff --git a/llvm/test/CodeGen/X86/optimize-max-0.ll b/llvm/test/CodeGen/X86/optimize-max-0.ll
index afbc519d8bf062..b6af7e1641a9c6 100644
--- a/llvm/test/CodeGen/X86/optimize-max-0.ll
+++ b/llvm/test/CodeGen/X86/optimize-max-0.ll
@@ -212,7 +212,7 @@ define void @foo(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind {
; CHECK-NEXT: sarl %eax
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: pushl $-128
+; CHECK-NEXT: pushl $128
; CHECK-NEXT: pushl %edx
; CHECK-NEXT: calll _memset
; CHECK-NEXT: addl $44, %esp
@@ -612,7 +612,7 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind {
; CHECK-NEXT: shrl %ecx
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %ecx
-; CHECK-NEXT: pushl $-128
+; CHECK-NEXT: pushl $128
; CHECK-NEXT: pushl %edx
; CHECK-NEXT: jmp LBB1_23
; CHECK-NEXT: LBB1_19: ## %bb29
@@ -647,7 +647,7 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind {
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: pushl $-128
+; CHECK-NEXT: pushl $128
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: LBB1_23: ## %bb33
; CHECK-NEXT: calll _memset
More information about the llvm-commits
mailing list