[llvm] [AMDGPU] Fix long-branch jump clobbers callee-saved registers (PR #229427)

[Jan Patrick Lehr via llvm-commits]

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@@ -121,9 +121,13 @@ bool GCNPreRALongBranchReg::run(MachineFunction &MF) {
   // shift down to a lower unused pair of SGPRs
   // If all registers are used, then findUnusedRegister will return
   // AMDGPU::NoRegister.
+  // Branch relaxation writes the pair after the callee-saved registers have
+  // been determined, so it must not be a register the caller expects to be
+  // preserved.
   constexpr bool ReserveHighestRegister = true;
   Register LongBranchReservedReg = TRI->findUnusedRegister(
-      MRI, &AMDGPU::SGPR_64RegClass, MF, ReserveHighestRegister);
+      MRI, &AMDGPU::SGPR_64RegClass, MF, ReserveHighestRegister,
+      /*ExcludeCalleeSaved=*/true);
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jplehr wrote:

Yes, that is a decision I took, since I am not really familiar with these parts it may be the wrong one.

>From my little understanding it felt that this was the easiest-to-approach and easiest to reason about. By limiting the reserved registers here to only allow for non-CSR we prevent the later rewrite from clobbering CSRs. Since this is pre-RA, I figured it should not make a real difference which registers we take away from the RA (I may be wrong though).

I don't think I understand the ordering point you are making about `SILowerSGPRSpills`. If we have reserved two registers for long-branch and need to spill SGPRs, isn't that a situation where it does not really matter which SGPRs are used for long-branch values?

And, yes, if all fails, there would be an emergency spill which uses the fixed register.

https://github.com/llvm/llvm-project/pull/229427