[llvm] c29426f - [RISCV][Disassembler] Reject GPR pairs with x16-x31 under RVE (#229166)

[via llvm-commits]

Author: Craig Topper
Date: 2026-10-05T19:48:57Z
New Revision: c29426f07918afbd9ab786b09404e8a5e5923efe

URL: https://github.com/llvm/llvm-project/commit/c29426f07918afbd9ab786b09404e8a5e5923efe
DIFF: https://github.com/llvm/llvm-project/commit/c29426f07918afbd9ab786b09404e8a5e5923efe.diff

LOG: [RISCV][Disassembler] Reject GPR pairs with x16-x31 under RVE (#229166)

GPR pairs used by instructions like Zilsd ld/sd must use registers
accessible under RVE. Registers x16-x31 are not available with RVE, so
DecodeGPRPairRegisterClass should fail decoding when RVE is enabled and
the register number is in that range.

Co-authored-by: Claude Sonnet 5 <noreply at anthropic.com>

Added: 
    llvm/test/MC/Disassembler/RISCV/rve-invalid-gpr-pair.txt

Modified: 
    llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index e7a28ee3943f92..076c74a40a7f55 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -190,6 +190,10 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
   if (RegNo >= 32 || RegNo % 2)
     return MCDisassembler::Fail;
 
+  bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
+  if (IsRVE && RegNo >= 16)
+    return MCDisassembler::Fail;
+
   const RISCVDisassembler *Dis =
       static_cast<const RISCVDisassembler *>(Decoder);
   const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();

diff  --git a/llvm/test/MC/Disassembler/RISCV/rve-invalid-gpr-pair.txt b/llvm/test/MC/Disassembler/RISCV/rve-invalid-gpr-pair.txt
new file mode 100644
index 00000000000000..f72a3b6d8fb88d
--- /dev/null
+++ b/llvm/test/MC/Disassembler/RISCV/rve-invalid-gpr-pair.txt
@@ -0,0 +1,33 @@
+# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+e,+zilsd -M no-aliases %s 2>%t.err \
+# RUN:   | FileCheck %s --check-prefixes=CHECK,RVE
+# RUN: FileCheck %s --check-prefix=RVE-ERR < %t.err
+# RUN: llvm-mc -disassemble -triple=riscv32 -mattr=+zilsd -M no-aliases %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK,RVI
+
+# GPR pairs using registers x16-x31 are not valid with RVE.
+
+[0x03,0x37,0x05,0x00]
+# CHECK: ld a4, 0(a0)
+
+[0x03,0x38,0x05,0x00]
+# RVE-ERR: :[[@LINE-1]]:2: warning: invalid instruction encoding
+# RVE-NOT: ld a6, 0(a0)
+# RVI: ld a6, 0(a0)
+
+[0x03,0x3f,0x05,0x00]
+# RVE-ERR: :[[@LINE-1]]:2: warning: invalid instruction encoding
+# RVE-NOT: ld t5, 0(a0)
+# RVI: ld t5, 0(a0)
+
+[0x23,0x30,0xe5,0x00]
+# CHECK: sd a4, 0(a0)
+
+[0x23,0x30,0x05,0x01]
+# RVE-ERR: :[[@LINE-1]]:2: warning: invalid instruction encoding
+# RVE-NOT: sd a6, 0(a0)
+# RVI: sd a6, 0(a0)
+
+[0x23,0x30,0xe5,0x01]
+# RVE-ERR: :[[@LINE-1]]:2: warning: invalid instruction encoding
+# RVE-NOT: sd t5, 0(a0)
+# RVI: sd t5, 0(a0)