[llvm] [Mips][nanoMIPS] Add initial nanoMIPS target support (PR #223032)

[via llvm-commits]

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+//===-- NanoMipsInstrFormats.td - nanoMIPS Instr Formats --*- tablegen -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the formats of the nanoMIPS instruction set.
+//
+//===----------------------------------------------------------------------===//
+
+class InstNM_Enc : Instruction, PredicateControl, ISA_NANOMIPS {
+  let Namespace = "Mips";
+  let DecoderNamespace = "NanoMips";
+
+  let EncodingPredicates = [HasNanoMips];
+  string Arch = "nanomips";
+  let AsmVariantName = "nanomips";
+}
+
+class InstNM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
+             InstrItinClass itin = NoItinerary,
+             bit FastISelIgnore = 1>
+  : InstNM_Enc {
+  let OutOperandList = outs;
+  let InOperandList  = ins;
+  let AsmString = asmstr;
+  let Pattern   = pattern;
+  let FastISelShouldIgnore = FastISelIgnore;
+  bit isCTI = 0; // Any form of Control Transfer Instruction.
+
+  let Itinerary = itin;
+}
+
+class InstSize16 {
+  bits<16> Inst;
+  int Size = 2;
+  bits<16> SoftFail = 0;
+}
+
+class InstSize32 {
+  bits<32> Inst;
+  int Size = 4;
+  bits<32> SoftFail = 0;
+}
+
+class InstSize48 {
+  bits<48> Inst;
+  int Size = 6;
+  bits<48> SoftFail = 0;
+}
+
+class RegConstraint<string C> {
+  string Constraints = C;
+}
+
+class NoEncode<string E> {
+  string DisableEncoding = E;
+}
+
+//===----------------------------------------------------------------------===//
+// Opcode Pools, as specified in the ISA document.
+//===----------------------------------------------------------------------===//
+
+class _Pool_P32<bits<5> psel> : InstSize32 {
+  let Inst{31-26} = {psel{4-2}, 0b0, psel{1-0}};
+}
+
+class _Pool_P_ADDIU<bits<5> psel> : _Pool_P32<0b00000> {
+  let Inst{25-21} = psel;
+}
+
+class _Pool_P32A<bits<3> psel> : _Pool_P32<0b00100> {
+  let Inst{2-0} = psel;
+}
+
+class _Pool_P_GP_W<bits<2> psel> : _Pool_P32<0b01000> {
+  let Inst{1-0} = psel;
+}
+
+class _Pool_P_U12<bits<4> psel> : _Pool_P32<0b10000> {
+  let Inst{15-12} = psel;
+}
+
+class _Pool_P_LUI<bits<1> psel> : _Pool_P32<0b11100> {
+  let Inst{1} = psel;
+}
+
+class _Pool_P48I<bits<5> psel> : InstSize48 {
+  let Inst{47-42} = 0b011000;
+  let Inst{36-32} = psel;
+}
+
+class _Pool_P_GP_BH<bits<3> psel> : _Pool_P32<0b01001> {
+  let Inst{20-18} = psel;
+}
+
+class _Pool_P_LS_U12<bits<4> psel> : _Pool_P32<0b10001> {
+  let Inst{15-12} = psel;
+}
+
+class _Pool_P_LS_S9<bits<3> psel> : _Pool_P32<0b10101> {
+  let Inst{10-8} = psel;
+}
+
+class _Pool_P_BAL<bits<1> psel> : _Pool_P32<0b00110> {
+  let Inst{25} = psel;
+}
+
+class _Pool_P_J<bits<4> psel> : _Pool_P32<0b01010> {
+  let Inst{15-12} = psel;
+}
+
+// Covers both the P.BR1 and P.BR2 pools.
+class _Pool_P_BR12<bits<3> psel> : _Pool_P32<0b10010> {
+  let Inst{29} = psel{2};
+  let Inst{15-14} = psel{1-0};
+}
+
+class _Pool_P_BRI<bits<3> psel> : _Pool_P32<0b11010> {
+  let Inst{20-18} = psel;
+}
+
+class _Pool_P_SHIFT<bits<4> psel> : _Pool_P_U12<0b1100> {
+  bits<5> shift;
+  bits<5> rs;
+  bits<5> rt;
+
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{8-5} = psel;
+  let Inst{4-0} = shift;
+}
+
+class _Pool_P_EXT_INS<bits<4> psel> : _Pool_P_U12<psel> {
+  let Inst{11} = 0;
+  let Inst{5} = 0;
+}
+
+class _Pool_P_LS_E0<bits<4> psel> : _Pool_P_LS_S9<0b010> {
+  let Inst{14-11} = psel;
+}
+
+class _Pool_P16<bits<5> psel> : InstSize16 {
+  let Inst{15-10} = {psel{4-2}, 0b1, psel{1-0}};
+}
+
+class _Pool_P16_MV : _Pool_P16<0b00000>;
+
+class _Pool_P16_SR<bits<1> psel> : _Pool_P16<0b00011> {
+  let Inst{8} = psel;
+}
+
+class _Pool_P16_SHIFT<bits<1> isel> : _Pool_P16<0b00100> {
+  let Inst{3} = isel;
+}
+
+class _Pool_P16_4X4<bits<2> psel> : _Pool_P16<0b00111> {
+  let Inst{8} = psel{1};
+  let Inst{3} = psel{0};
+}
+
+class _Pool_P16C<bits<1> psel> : _Pool_P16<0b01000> {
+  let Inst{0} = psel;
+}
+
+class _Pool_POOL16C_00<bits<2> psel> : _Pool_P16<0b01000> {
+  let Inst{3-2} = psel;
+  let Inst{1-0} = 0b00;
+}
+
+class _Pool_P16_LB<bits<2> psel> : _Pool_P16<0b01011> {
+  let Inst{3-2} = psel;
+}
+
+class _Pool_P16_A1<bits<1> psel> : _Pool_P16<0b01100> {
+  let Inst{6} = psel;
+}
+
+class _Pool_P16_LH<bits<2> psel> : _Pool_P16<0b01111> {
+  let Inst{3} = psel{1};
+  let Inst{0} = psel{0};
+}
+
+class _Pool_P16_A2<bits<1> psel> : _Pool_P16<0b10000> {
+  let Inst{3} = psel;
+}
+
+class _Pool_P16_ADDU<bits<1> psel> : _Pool_P16<0b10100> {
+  let Inst{0} = psel;
+}
+
+class _Pool_P16_BR<bits<4> psel> : _Pool_P16<0b11010> {
+  let Inst{3-0} = psel;
+}
+
+class _Pool_P16_RI<bits<2> psel> : _Pool_P16_MV {
+  let Inst{4-3} = psel;
+  let Inst{9-5} = 0b00000;
+}
+
+class _Pool_P_RI<bits<2> psel> : _Pool_P_ADDIU<0b00000> {
+  let Inst{20-19} = psel;
+}
+
+class _Pool_POOL32A0<bits<1> psel> : _Pool_P32A<0b000> {
+  let Inst{5} = psel;
+}
+
+class _Pool_POOL32A0_0<bits<6> psel> : _Pool_POOL32A0<0b0> {
+  let Inst{9-6} = psel{5-2};
+  let Inst{4-3} = psel{1-0};
+}
+
+class _Pool_P_TRAP<bits<1> isel> : _Pool_POOL32A0_0<0b000000> {
+  let Inst{10} = isel;
+}
+
+class _Pool_P_CMOVE<bits<1> isel> : _Pool_POOL32A0_0<0b100010> {
+  let Inst{10} = isel;
+}
+
+class _Pool_POOL32A7<bits<3> psel> : _Pool_P32A<0b111> {
+  let Inst{5-3} = psel;
+}
+
+class _Pool_POOL32Axf_4<bits<7> isel> : _Pool_POOL32A7<0b111> {
+  let Inst{15-9} = isel;
+  let Inst{8-6} = 0b100;
+}
+
+class _Pool_POOL32Axf_5<bits<2> psel> : _Pool_POOL32A7<0b111> {
+  let Inst{8-6} = 0b101;
+  let Inst{15-14} = psel;
+}
+
+class _Pool_POOL32Axf_5_group0<bits<5> isel> : _Pool_POOL32Axf_5<0b00> {
+  let Inst{13-9} = isel;
+}
+
+class _Pool_POOL32Axf_5_group1<bits<5> isel> : _Pool_POOL32Axf_5<0b01> {
+  let Inst{13-9} = isel;
+}
+
+class _Pool_POOL32Axf_5_group3<bits<5> isel> : _Pool_POOL32Axf_5<0b11> {
+  let Inst{13-9} = isel;
+}
+
+class _Pool_PP_LSX<bit scaled, bits<4> isel> : _Pool_POOL32A7<0b000> {
+  let Inst{6} = scaled;
+  let Inst{10-7} = isel;
+}
+
+class _Pool_POOL32A0_1<bits<6> psel> : _Pool_POOL32A0<0b1> {
+  let Inst{9-6} = psel{5-2};
+  let Inst{4-3} = psel{1-0};
+}
+
+class _Pool_PP_SR<bits<2> isel> : _Pool_P_U12<0b0011> {
+  let Inst{20} = 0;
+  let Inst{1-0} = isel;
+}
+
+//===----------------------------------------------------------------------===//
+// nanoMIPS Instruction Formats
+//===----------------------------------------------------------------------===//
+
+class Arith4x4_Enc<bits<2> isel> :  _Pool_P16_4X4<isel> {
+  bits<5> dst;
+  bits<5> rs;
+  bits<5> rt;
----------------
nrakovic wrote:

Removed in cbd38d7.

https://github.com/llvm/llvm-project/pull/223032