[llvm] ARM: Stop setting kill flags on virtual registers before FinalizeISel (PR #229020)
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Mon Oct 5 02:17:30 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
There is no point in maintaining kill flags before register allocation
anymore.
Co-authored-by: Claude Opus 5.5 <noreply@<!-- -->anthropic.com>
---
Full diff: https://github.com/llvm/llvm-project/pull/229020.diff
2 Files Affected:
- (modified) llvm/lib/Target/ARM/ARMFastISel.cpp (+4-5)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+31-31)
``````````diff
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 6d1c6ea5356b8..a577f52a3343a 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -2811,13 +2811,12 @@ Register ARMFastISel::ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT,
unsigned Opcode = isLsl ? LSLOpc : Opc;
ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
- bool isKill = 1 == Instr;
MachineInstrBuilder MIB = BuildMI(
*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opcode), ResultReg);
if (setsCPSR)
MIB.addReg(ARM::CPSR, RegState::Define | RegState::Dead);
SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
- MIB.addReg(SrcReg, getKillRegState(isKill))
+ MIB.addReg(SrcReg)
.addImm(ImmEnc)
.add(predOps(ARMCC::AL));
if (hasS)
@@ -3158,9 +3157,9 @@ bool ARMFastISel::fastLowerArguments() {
// Without this, EmitLiveInCopies may eliminate the livein if its only
// use is a bitcast (which isn't turned into an instruction).
Register ResultReg = createResultReg(RC);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY),
- ResultReg).addReg(DstReg, getKillRegState(true));
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(DstReg);
updateValueMap(&Arg, ResultReg);
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 1267b7fa380d8..31e1a8fbe3bdc 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10858,16 +10858,16 @@ void ARMTargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI,
// Set the low bit because of thumb mode.
Register NewVReg2 = MRI->createVirtualRegister(TRC);
BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
- .addReg(NewVReg1, RegState::Kill)
+ .addReg(NewVReg1)
.addImm(0x01)
.add(predOps(ARMCC::AL))
.add(condCodeOp());
Register NewVReg3 = MRI->createVirtualRegister(TRC);
BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
- .addReg(NewVReg2, RegState::Kill)
- .addImm(PCLabelId);
+ .addReg(NewVReg2)
+ .addImm(PCLabelId);
BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
- .addReg(NewVReg3, RegState::Kill)
+ .addReg(NewVReg3)
.addFrameIndex(FI)
.addImm(36) // &jbuf[1] :: pc
.addMemOperand(FIMMOSt)
@@ -10887,8 +10887,8 @@ void ARMTargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI,
.add(predOps(ARMCC::AL));
Register NewVReg2 = MRI->createVirtualRegister(TRC);
BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
- .addReg(NewVReg1, RegState::Kill)
- .addImm(PCLabelId);
+ .addReg(NewVReg1)
+ .addImm(PCLabelId);
// Set the low bit because of thumb mode.
Register NewVReg3 = MRI->createVirtualRegister(TRC);
BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
@@ -10898,16 +10898,16 @@ void ARMTargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI,
Register NewVReg4 = MRI->createVirtualRegister(TRC);
BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
.addReg(ARM::CPSR, RegState::Define)
- .addReg(NewVReg2, RegState::Kill)
- .addReg(NewVReg3, RegState::Kill)
+ .addReg(NewVReg2)
+ .addReg(NewVReg3)
.add(predOps(ARMCC::AL));
Register NewVReg5 = MRI->createVirtualRegister(TRC);
BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
.addFrameIndex(FI)
.addImm(36); // &jbuf[1] :: pc
BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
- .addReg(NewVReg4, RegState::Kill)
- .addReg(NewVReg5, RegState::Kill)
+ .addReg(NewVReg4)
+ .addReg(NewVReg5)
.addImm(0)
.addMemOperand(FIMMOSt)
.add(predOps(ARMCC::AL));
@@ -10924,11 +10924,11 @@ void ARMTargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI,
.add(predOps(ARMCC::AL));
Register NewVReg2 = MRI->createVirtualRegister(TRC);
BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
- .addReg(NewVReg1, RegState::Kill)
+ .addReg(NewVReg1)
.addImm(PCLabelId)
.add(predOps(ARMCC::AL));
BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
- .addReg(NewVReg2, RegState::Kill)
+ .addReg(NewVReg2)
.addFrameIndex(FI)
.addImm(36) // &jbuf[1] :: pc
.addMemOperand(FIMMOSt)
@@ -11081,16 +11081,16 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
Register NewVReg4 = MRI->createVirtualRegister(TRC);
BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
- .addReg(NewVReg3, RegState::Kill)
+ .addReg(NewVReg3)
.addReg(NewVReg1)
.addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))
.add(predOps(ARMCC::AL))
.add(condCodeOp());
BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
- .addReg(NewVReg4, RegState::Kill)
- .addReg(NewVReg1)
- .addJumpTableIndex(MJTI);
+ .addReg(NewVReg4)
+ .addReg(NewVReg1)
+ .addJumpTableIndex(MJTI);
} else if (Subtarget->isThumb()) {
Register NewVReg1 = MRI->createVirtualRegister(TRC);
BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
@@ -11144,7 +11144,7 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
Register NewVReg4 = MRI->createVirtualRegister(TRC);
BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
.addReg(ARM::CPSR, RegState::Define)
- .addReg(NewVReg2, RegState::Kill)
+ .addReg(NewVReg2)
.addReg(NewVReg3)
.add(predOps(ARMCC::AL));
@@ -11154,7 +11154,7 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
Register NewVReg5 = MRI->createVirtualRegister(TRC);
BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
- .addReg(NewVReg4, RegState::Kill)
+ .addReg(NewVReg4)
.addImm(0)
.addMemOperand(JTMMOLd)
.add(predOps(ARMCC::AL));
@@ -11164,14 +11164,14 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
NewVReg6 = MRI->createVirtualRegister(TRC);
BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
.addReg(ARM::CPSR, RegState::Define)
- .addReg(NewVReg5, RegState::Kill)
+ .addReg(NewVReg5)
.addReg(NewVReg3)
.add(predOps(ARMCC::AL));
}
BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
- .addReg(NewVReg6, RegState::Kill)
- .addJumpTableIndex(MJTI);
+ .addReg(NewVReg6)
+ .addJumpTableIndex(MJTI);
} else {
Register NewVReg1 = MRI->createVirtualRegister(TRC);
BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
@@ -11221,7 +11221,7 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
.add(predOps(ARMCC::AL));
BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
.addReg(NewVReg1)
- .addReg(VReg1, RegState::Kill)
+ .addReg(VReg1)
.add(predOps(ARMCC::AL));
}
@@ -11246,7 +11246,7 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
MachineMemOperand::MOLoad, 4, Align(4));
Register NewVReg5 = MRI->createVirtualRegister(TRC);
BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
- .addReg(NewVReg3, RegState::Kill)
+ .addReg(NewVReg3)
.addReg(NewVReg4)
.addImm(0)
.addMemOperand(JTMMOLd)
@@ -11254,13 +11254,13 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
if (IsPositionIndependent) {
BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
- .addReg(NewVReg5, RegState::Kill)
- .addReg(NewVReg4)
- .addJumpTableIndex(MJTI);
+ .addReg(NewVReg5)
+ .addReg(NewVReg4)
+ .addJumpTableIndex(MJTI);
} else {
BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
- .addReg(NewVReg5, RegState::Kill)
- .addJumpTableIndex(MJTI);
+ .addReg(NewVReg5)
+ .addJumpTableIndex(MJTI);
}
}
@@ -11767,7 +11767,7 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,
.addExternalSymbol(ChkStk);
BuildMI(*MBB, MI, DL, TII.get(gettBLXrOpcode(*MBB->getParent())))
.add(predOps(ARMCC::AL))
- .addReg(Reg, RegState::Kill)
+ .addReg(Reg)
.setOperandDead(3) // implicit-def $lr
.addReg(ARM::R4, RegState::Implicit | RegState::Kill)
.addReg(ARM::R4, RegState::Implicit | RegState::Define)
@@ -11871,14 +11871,14 @@ static Register genTPEntry(MachineBasicBlock *TpEntry,
Register LsrDestReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
BuildMI(TpEntry, Dl, TII->get(ARM::t2LSRri), LsrDestReg)
- .addUse(AddDestReg, RegState::Kill)
+ .addUse(AddDestReg)
.addImm(4)
.add(predOps(ARMCC::AL))
.addReg(0);
Register TotalIterationsReg = MRI.createVirtualRegister(&ARM::GPRlrRegClass);
BuildMI(TpEntry, Dl, TII->get(ARM::t2WhileLoopSetup), TotalIterationsReg)
- .addUse(LsrDestReg, RegState::Kill);
+ .addUse(LsrDestReg);
BuildMI(TpEntry, Dl, TII->get(ARM::t2WhileLoopStart))
.addUse(TotalIterationsReg)
``````````
</details>
https://github.com/llvm/llvm-project/pull/229020
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