[llvm] [IR][RFC] Add @llvm.mask.beforefirst intrinsic (PR #203874)

[Luke Lau via llvm-commits]

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@@ -0,0 +1,148 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple aarch64 -mattr=+sve | FileCheck %s
+
+define <vscale x 16 x i1> @nxv16i1(<vscale x 16 x i1> %m) {
+; CHECK-LABEL: nxv16i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p1.b
+; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
+; CHECK-NEXT:    ret
+  %x = call <vscale x 16 x i1> @llvm.mask.beforefirst(<vscale x 16 x i1> %m)
+  ret <vscale x 16 x i1> %x
+}
+
+define <vscale x 8 x i1> @nxv8i1(<vscale x 8 x i1> %m) {
+; CHECK-LABEL: nxv8i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p1.h
+; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
+; CHECK-NEXT:    ret
+  %x = call <vscale x 8 x i1> @llvm.mask.beforefirst(<vscale x 8 x i1> %m)
+  ret <vscale x 8 x i1> %x
+}
+
+define <vscale x 4 x i1> @nxv4i1(<vscale x 4 x i1> %m) {
+; CHECK-LABEL: nxv4i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p1.s
+; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
+; CHECK-NEXT:    ret
+  %x = call <vscale x 4 x i1> @llvm.mask.beforefirst(<vscale x 4 x i1> %m)
+  ret <vscale x 4 x i1> %x
+}
+
+define <vscale x 2 x i1> @nxv2i1(<vscale x 2 x i1> %m) {
+; CHECK-LABEL: nxv2i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p1.d
+; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
+; CHECK-NEXT:    ret
+  %x = call <vscale x 2 x i1> @llvm.mask.beforefirst(<vscale x 2 x i1> %m)
+  ret <vscale x 2 x i1> %x
+}
+
+define <16 x i1> @v16i1(<16 x i1> %m) {
+; CHECK-LABEL: v16i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.16b, v0.16b, #7
+; CHECK-NEXT:    adrp x8, .LCPI4_0
+; CHECK-NEXT:    mov w9, #16 // =0x10
+; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
+; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    umaxv b0, v0.16b
+; CHECK-NEXT:    fmov w8, s0
+; CHECK-NEXT:    sub w8, w9, w8, uxtb
+; CHECK-NEXT:    whilelo p0.b, xzr, x8
+; CHECK-NEXT:    mov z0.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+  %x = call <16 x i1> @llvm.mask.beforefirst(<16 x i1> %m)
+  ret <16 x i1> %x
+}
+
+define <8 x i1> @v8i1(<8 x i1> %m) {
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lukel97 wrote:

Getting the equivalent codegen sequence has been moved out of scope of this PR, e.g see https://github.com/llvm/llvm-project/pull/203874#discussion_r4105414743

I plan on focusing on the codegen in follow up PRs before plugging it into the LV. For now this PR is just focusing on having the correct expansion

https://github.com/llvm/llvm-project/pull/203874