[llvm] RISCV: Use hasOneNonDBGUse instead of kill flag for cascaded select (PR #228940)

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Sun Oct 4 14:05:15 PDT 2026


https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/228940

The cascaded select lowering requires the first select's result to only be
used by the second select. Avoid depending on the kill flag which will not be
set in the future.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>

>From 42813c67841c79c5aca3a42c61e5b075fb37b2ef Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sun, 4 Oct 2026 22:39:23 +0200
Subject: [PATCH] RISCV: Use hasOneNonDBGUse instead of kill flag for cascaded
 select

The cascaded select lowering requires the first select's result to only be
used by the second select. Avoid depending on the kill flag which will not be
set in the future.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4b9175b9aad27..1e4fb60a36b9a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -27259,7 +27259,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
       MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
       Next != BB->end() && Next->getOpcode() == MI.getOpcode() &&
       Next->getOperand(5).getReg() == MI.getOperand(0).getReg() &&
-      Next->getOperand(5).isKill())
+      BB->getParent()->getRegInfo().hasOneNonDBGUse(MI.getOperand(0).getReg()))
     return EmitLoweredCascadedSelect(MI, *Next, BB, Subtarget);
 
   Register LHS = MI.getOperand(1).getReg();



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