[llvm] [RISCV] Prefix option names with riscv-, turn disable- to positive options (PR #228922)
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 4 10:25:36 PDT 2026
https://github.com/MaskRay created https://github.com/llvm/llvm-project/pull/228922
Rename the RISCV CodeGen options so that they start with riscv-, and
turn the -disable-* options that default to false into positive options
that default to true.
Preparatory for migrating to LibraryOptions.
Aided by Opus 5.5
>From 42e062d601045dee8bc25039ee3b92bf583231ca Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Sun, 4 Oct 2026 10:11:34 -0700
Subject: [PATCH] [RISCV] Prefix option names with riscv-, turn disable- to
positive options
Rename the RISCV CodeGen options so that they start with riscv-, and
turn the -disable-* options that default to false into positive options
that default to true.
Preparatory for migrating to LibraryOptions.
Aided by Opus 5.5
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
.../Target/RISCV/RISCVInsertReadWriteCSR.cpp | 7 +++----
llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp | 16 ++++++++--------
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 15 +++++++--------
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 14 +++++++-------
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 8 ++++----
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp | 6 +++---
.../CodeGen/RISCV/GlobalISel/sextw-removal.ll | 2 +-
llvm/test/CodeGen/RISCV/imm.ll | 18 +++++++++---------
llvm/test/CodeGen/RISCV/load-store-pair.ll | 10 +++++-----
llvm/test/CodeGen/RISCV/prefer-w-inst.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/frm-insert.ll | 2 +-
llvm/test/CodeGen/RISCV/sextw-removal.ll | 2 +-
14 files changed, 52 insertions(+), 54 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4b9175b9aad27..5769fab65ec06 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -84,7 +84,7 @@ static cl::opt<int>
cl::init(3));
static cl::opt<bool>
- ReassocShlAddiAdd("reassoc-shl-addi-add", cl::Hidden,
+ ReassocShlAddiAdd("riscv-reassoc-shl-addi-add", cl::Hidden,
cl::desc("Swap add and addi in cases where the add may "
"be combined with a shift"),
cl::init(true));
diff --git a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
index 7b9e9fb988bc6..e62085ea1f367 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
@@ -24,9 +24,8 @@ using namespace llvm;
#define RISCV_INSERT_READ_WRITE_CSR_NAME "RISC-V Insert Read/Write CSR Pass"
static cl::opt<bool>
- DisableFRMInsertOpt("riscv-disable-frm-insert-opt", cl::init(false),
- cl::Hidden,
- cl::desc("Disable optimized frm insertion."));
+ EnableFRMInsertOpt("riscv-frm-insert-opt", cl::init(true), cl::Hidden,
+ cl::desc("Enable optimized frm insertion."));
namespace {
@@ -183,7 +182,7 @@ bool RISCVInsertReadWriteCSR::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
for (MachineBasicBlock &MBB : MF) {
- if (DisableFRMInsertOpt)
+ if (!EnableFRMInsertOpt)
Changed |= emitWriteRoundingMode(MBB);
else
Changed |= emitWriteRoundingModeOpt(MBB);
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 18c8611c337f8..6df1870987bca 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -51,12 +51,12 @@ STATISTIC(NumTransformedToWInstrs,
STATISTIC(NumTransformedToNonWInstrs,
"Number of instructions transformed to non-W-ops");
-static cl::opt<bool> DisableSExtWRemoval("riscv-disable-sextw-removal",
- cl::desc("Disable removal of sext.w"),
- cl::init(false), cl::Hidden);
-static cl::opt<bool> DisableStripWSuffix("riscv-disable-strip-w-suffix",
- cl::desc("Disable strip W suffix"),
- cl::init(false), cl::Hidden);
+static cl::opt<bool> EnableSExtWRemoval("riscv-sextw-removal",
+ cl::desc("Enable removal of sext.w"),
+ cl::init(true), cl::Hidden);
+static cl::opt<bool> EnableStripWSuffix("riscv-strip-w-suffix",
+ cl::desc("Enable strip W suffix"),
+ cl::init(true), cl::Hidden);
namespace {
@@ -745,7 +745,7 @@ bool RISCVOptWInstrsImpl::removeSExtWInstrs(MachineFunction &MF,
const RISCVInstrInfo &TII,
const RISCVSubtarget &ST,
MachineRegisterInfo &MRI) {
- if (DisableSExtWRemoval)
+ if (!EnableSExtWRemoval)
return false;
bool MadeChange = false;
@@ -808,7 +808,7 @@ bool RISCVOptWInstrsImpl::canonicalizeWSuffixes(MachineFunction &MF,
const RISCVInstrInfo &TII,
const RISCVSubtarget &ST,
MachineRegisterInfo &MRI) {
- bool ShouldStripW = !(DisableStripWSuffix || ST.preferWInst());
+ bool ShouldStripW = EnableStripWSuffix && !ST.preferWInst();
bool ShouldPreferW = ST.preferWInst();
bool MadeChange = false;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 33738a9661571..36d66042262b2 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -29,13 +29,12 @@
using namespace llvm;
-static cl::opt<bool> DisableCostPerUse("riscv-disable-cost-per-use",
- cl::init(false), cl::Hidden);
+static cl::opt<bool> EnableCostPerUse("riscv-cost-per-use", cl::init(true),
+ cl::Hidden);
static cl::opt<bool>
- DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden,
- cl::init(false),
- cl::desc("Disable two address hints for register "
- "allocation"));
+ EnableRegAllocHints("riscv-regalloc-hints", cl::Hidden, cl::init(true),
+ cl::desc("Enable two address hints for register "
+ "allocation"));
static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
@@ -985,7 +984,7 @@ RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
// Set CostPerUse to 1 only when optimizing for size and RVC exists.
return MF.getFunction().hasOptSize() &&
MF.getSubtarget<RISCVSubtarget>().hasStdExtZca() &&
- !DisableCostPerUse
+ EnableCostPerUse
? 1
: 0;
}
@@ -1047,7 +1046,7 @@ bool RISCVRegisterInfo::getRegAllocationHints(
bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
VirtReg, Order, Hints, MF, VRM, Matrix);
- if (!VRM || DisableRegAllocHints)
+ if (!VRM || !EnableRegAllocHints)
return BaseImplRetVal;
// Add any two address hints after any copy hints.
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 747e10152ddf6..502037c9701b0 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -59,10 +59,10 @@ namespace llvm::RISCVTuneInfoTable {
#include "RISCVGenSearchableTables.inc"
} // namespace llvm::RISCVTuneInfoTable
-static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
- "riscv-disable-using-constant-pool-for-large-ints",
- cl::desc("Disable using constant pool for large integers."),
- cl::init(false), cl::Hidden);
+static cl::opt<bool> RISCVConstantPoolForLargeInts(
+ "riscv-constant-pool-for-large-ints",
+ cl::desc("Enable using constant pool for large integers."), cl::init(true),
+ cl::Hidden);
static cl::opt<unsigned> RISCVMaxBuildIntsCost(
"riscv-max-build-ints-cost",
@@ -77,11 +77,11 @@ static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
static cl::opt<bool> UseMIPSLoadStorePairsOpt(
- "use-riscv-mips-load-store-pairs",
+ "riscv-mips-load-store-pairs",
cl::desc("Enable the load/store pair optimization pass"), cl::init(false),
cl::Hidden);
-static cl::opt<bool> UseMIPSCCMovInsn("use-riscv-mips-ccmov",
+static cl::opt<bool> UseMIPSCCMovInsn("riscv-mips-ccmov",
cl::desc("Use 'mips.ccmov' instruction"),
cl::init(true), cl::Hidden);
@@ -186,7 +186,7 @@ const RISCVRegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
}
bool RISCVSubtarget::useConstantPoolForLargeInts() const {
- return !RISCVDisableUsingConstantPoolForLargeInts;
+ return RISCVConstantPoolForLargeInts;
}
// Returns true if VT is a P extension packed SIMD type.
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 685bb91583cf5..1d98d2e41cdab 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -91,9 +91,9 @@ static cl::opt<bool>
cl::desc("Enable the loop data prefetch pass"),
cl::init(true));
-static cl::opt<bool> DisableVectorMaskMutation(
- "riscv-disable-vector-mask-mutation",
- cl::desc("Disable the vector mask scheduling mutation"), cl::init(false),
+static cl::opt<bool> EnableVectorMaskMutation(
+ "riscv-vector-mask-mutation",
+ cl::desc("Enable the vector mask scheduling mutation"), cl::init(true),
cl::Hidden);
static cl::opt<bool>
@@ -296,7 +296,7 @@ RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
DAG->addMutation(createStoreClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
- if (!DisableVectorMaskMutation && ST.hasVInstructions())
+ if (EnableVectorMaskMutation && ST.hasVInstructions())
DAG->addMutation(createRISCVVectorMaskDAGMutation(DAG->TRI));
return DAG;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 69554ca2b8155..13ec1fdae4a8f 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -47,7 +47,7 @@ static cl::opt<unsigned>
"vectorization while tail-folding."),
cl::init(5), cl::Hidden);
-static cl::opt<bool> EnableOrLikeSelectOpt("enable-riscv-or-like-select",
+static cl::opt<bool> EnableOrLikeSelectOpt("riscv-or-like-select",
cl::init(true), cl::Hidden);
InstructionCost
diff --git a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
index bae193d59f7a4..2564b3dbe9bbd 100644
--- a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
@@ -48,8 +48,8 @@ STATISTIC(NumLDFormed, "Number of LD instructions formed");
STATISTIC(NumSDFormed, "Number of SD instructions formed");
static cl::opt<bool>
- DisableZilsdOpt("disable-riscv-zilsd-opt", cl::Hidden, cl::init(false),
- cl::desc("Disable Zilsd load/store optimization"));
+ EnableZilsdOpt("riscv-zilsd-opt", cl::Hidden, cl::init(true),
+ cl::desc("Enable Zilsd load/store optimization"));
static cl::opt<unsigned> MaxRescheduleDistance(
"riscv-zilsd-max-reschedule-distance", cl::Hidden, cl::init(10),
@@ -130,7 +130,7 @@ INITIALIZE_PASS_END(RISCVPreAllocZilsdOpt, "riscv-prera-zilsd-opt",
bool RISCVPreAllocZilsdOpt::runOnMachineFunction(MachineFunction &MF) {
- if (DisableZilsdOpt || skipFunction(MF.getFunction()))
+ if (!EnableZilsdOpt || skipFunction(MF.getFunction()))
return false;
STI = &MF.getSubtarget<RISCVSubtarget>();
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/sextw-removal.ll b/llvm/test/CodeGen/RISCV/GlobalISel/sextw-removal.ll
index 9d6556c43be7f..8e58fa14bc060 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/sextw-removal.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -global-isel | FileCheck %s
-; RUN: llc < %s -mtriple=riscv64 -global-isel -riscv-disable-sextw-removal \
+; RUN: llc < %s -mtriple=riscv64 -global-isel -riscv-sextw-removal=0 \
; RUN: | FileCheck %s --check-prefix=NOREMOVAL
declare signext i32 @bar(i32 signext)
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index 4fc4dc9867a63..59f5e0daf1678 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -1,24 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -riscv-constant-pool-for-large-ints=0 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -mattr=+xqcili \
+; RUN: llc -mtriple=riscv32 -riscv-constant-pool-for-large-ints=0 -mattr=+xqcili \
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IXQCILI
-; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -riscv-constant-pool-for-large-ints=0 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV64I,RV64-NOPOOL
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV64I,RV64I-POOL
-; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zba \
+; RUN: llc -mtriple=riscv64 -riscv-constant-pool-for-large-ints=0 -mattr=+zba \
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBA
-; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zbb \
+; RUN: llc -mtriple=riscv64 -riscv-constant-pool-for-large-ints=0 -mattr=+zbb \
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBB
-; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zbs \
+; RUN: llc -mtriple=riscv64 -riscv-constant-pool-for-large-ints=0 -mattr=+zbs \
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBS
-; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+xtheadbb \
+; RUN: llc -mtriple=riscv64 -riscv-constant-pool-for-large-ints=0 -mattr=+xtheadbb \
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IXTHEADBB
-; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -riscv-constant-pool-for-large-ints=0 -verify-machineinstrs < %s \
; RUN: -riscv-use-rematerializable-movimm | FileCheck %s -check-prefix=RV32-REMAT
-; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -riscv-constant-pool-for-large-ints=0 -verify-machineinstrs < %s \
; RUN: -riscv-use-rematerializable-movimm | FileCheck %s -check-prefix=RV64-REMAT
; Materializing constants
diff --git a/llvm/test/CodeGen/RISCV/load-store-pair.ll b/llvm/test/CodeGen/RISCV/load-store-pair.ll
index bce20af36228a..0413e9291dc88 100644
--- a/llvm/test/CodeGen/RISCV/load-store-pair.ll
+++ b/llvm/test/CodeGen/RISCV/load-store-pair.ll
@@ -7,15 +7,15 @@
; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64D
-; RUN: llc -mtriple=riscv32 -mattr=+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I_PAIR
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+d,+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+d,+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32D_PAIR
-; RUN: llc -mtriple=riscv64 -mattr=+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I_PAIR
-; RUN: llc -mtriple=riscv64 -mcpu=mips-p8700 -mattr=+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mcpu=mips-p8700 -mattr=+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64P_8700
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+d,+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+d,+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64D_PAIR
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64D_NOPAIR
diff --git a/llvm/test/CodeGen/RISCV/prefer-w-inst.ll b/llvm/test/CodeGen/RISCV/prefer-w-inst.ll
index dcc4f04340055..3d194287793c2 100644
--- a/llvm/test/CodeGen/RISCV/prefer-w-inst.ll
+++ b/llvm/test/CodeGen/RISCV/prefer-w-inst.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=NO-PREFER-W-INST %s
-; RUN: llc -mtriple=riscv64 -mattr=+m -riscv-disable-strip-w-suffix -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+m -riscv-strip-w-suffix=0 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=NO-STRIP %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+prefer-w-inst -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=PREFER-W-INST %s
diff --git a/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll b/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
index 2e484776bfa63..b606c5a525eb9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -target-abi=lp64d < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -target-abi=lp64d \
-; RUN: -riscv-disable-frm-insert-opt < %s | FileCheck %s --check-prefix=UNOPT
+; RUN: -riscv-frm-insert-opt=0 < %s | FileCheck %s --check-prefix=UNOPT
; Test only save/restore frm once.
define <vscale x 1 x float> @test(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll
index f54332133a776..f28718a049621 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zba,+zbb,+zbkb,+f,+zknh,+v -target-abi=lp64f \
; RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zba,+zbb,+zbkb,+f,+zknh,+v -target-abi=lp64f \
-; RUN: -riscv-disable-sextw-removal | FileCheck %s --check-prefix=NOREMOVAL
+; RUN: -riscv-sextw-removal=0 | FileCheck %s --check-prefix=NOREMOVAL
define void @test1(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK-LABEL: test1:
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