[llvm] [CodeGenPrepare] Prefix option names with cgp- (PR #228838)
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 4 09:17:32 PDT 2026
https://github.com/MaskRay updated https://github.com/llvm/llvm-project/pull/228838
>From 656d6beb7a0a6c45fe313b677236a1c3edbb43ed Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Sun, 4 Oct 2026 08:50:36 -0700
Subject: [PATCH] [CodeGenPrepare] Prefix option names with cgp-
Rename the CodeGenPrepare options so that they start with cgp-, and turn
the -disable-* options into positive options that default to true:
```
-addr-sink-* -cgp-addr-sink-*
-cgpp-huge-func -cgp-huge-func
-disable-cgp-X -cgp-X=0
-disable-complex-addr-modes -cgp-complex-addr-modes=0
-disable-preheader-prot -cgp-preheader-prot=0
-enable-andcmp-sinking -cgp-andcmp-sinking
-force-split-store -cgp-force-split-store
-stress-cgp-X -cgp-stress-X
```
The section prefix options (-profile-guided-section-prefix, etc.) are
kept, as they are not specific to CodeGenPrepare.
Aided by Opus 5.5
---
llvm/lib/CodeGen/CodeGenOptions.td | 56 +++++++++----------
llvm/lib/CodeGen/CodeGenPrepare.cpp | 48 ++++++++--------
.../GlobalISel/irtranslator-switch-bittest.ll | 2 +-
llvm/test/CodeGen/AArch64/and-sink.ll | 2 +-
.../CodeGen/AArch64/arm64-andCmpBrToTBZ.ll | 2 +-
.../AArch64/arm64-codegen-prepare-extload.ll | 4 +-
.../CodeGen/AArch64/fast-isel-int-ext2.ll | 2 +-
llvm/test/CodeGen/ARM/constants.ll | 2 +-
llvm/test/CodeGen/ARM/vector-promotion.ll | 2 +-
.../Hexagon/autohvx/lower-insert-elt.ll | 2 +-
llvm/test/CodeGen/Hexagon/postinc-offset.ll | 2 +-
llvm/test/CodeGen/Hexagon/swp-carried-1.ll | 2 +-
llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll | 2 +-
llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll | 2 +-
llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll | 2 +-
llvm/test/CodeGen/Hexagon/swp-lots-deps.ll | 2 +-
llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll | 2 +-
llvm/test/CodeGen/Hexagon/swp-tfri.ll | 2 +-
.../CodeGen/Hexagon/v6-unaligned-spill.ll | 2 +-
llvm/test/CodeGen/Mips/brdelayslot.ll | 2 +-
llvm/test/CodeGen/PowerPC/sink-side-effect.ll | 2 +-
llvm/test/CodeGen/PowerPC/sms-iterator.ll | 2 +-
.../PowerPC/splitstore-check-volatile.ll | 2 +-
.../SystemZ/codegenprepare-splitstore.ll | 2 +-
llvm/test/CodeGen/Thumb/dyn-stackalloc.ll | 4 +-
.../Thumb2/2011-06-07-TwoAddrEarlyClobber.ll | 2 +-
llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll | 2 +-
.../CodeGen/X86/2012-10-18-crash-dagco.ll | 2 +-
llvm/test/CodeGen/X86/MachineSink-PHIUse.ll | 2 +-
llvm/test/CodeGen/X86/and-sink.ll | 2 +-
llvm/test/CodeGen/X86/avx512-i1test.ll | 4 +-
llvm/test/CodeGen/X86/cmov.ll | 2 +-
.../CodeGen/X86/codegen-prepare-extload.ll | 4 +-
.../test/CodeGen/X86/ins_subreg_coalesce-3.ll | 2 +-
.../CodeGen/X86/phi-immediate-factoring.ll | 6 +-
llvm/test/CodeGen/X86/pr3366.ll | 2 +-
llvm/test/CodeGen/X86/sext-i1.ll | 4 +-
llvm/test/CodeGen/X86/sink-blockfreq.ll | 6 +-
llvm/test/CodeGen/X86/split-store.ll | 2 +-
llvm/test/CodeGen/X86/tail-opts.ll | 2 +-
llvm/test/CodeGen/X86/x86-shrink-wrapping.ll | 4 +-
.../CodeGenPrepare/ARM/sink-addrmode.ll | 2 +-
.../ARM/sinkchain-inseltpoison.ll | 2 +-
.../CodeGenPrepare/ARM/sinkchain.ll | 2 +-
.../PowerPC/split-store-alignment.ll | 4 +-
.../CodeGenPrepare/X86/baseoffs-sext-bug.ll | 2 +-
.../CodeGenPrepare/X86/extend-sink-hoist.ll | 2 +-
.../X86/gather-scatter-opt-inseltpoison.ll | 2 +-
.../CodeGenPrepare/X86/nonintegral.ll | 2 +-
.../Transforms/CodeGenPrepare/X86/pr35658.ll | 2 +-
.../CodeGenPrepare/X86/sink-addr-recreate.ll | 2 +-
.../CodeGenPrepare/X86/sink-addr-reuse.ll | 2 +-
.../CodeGenPrepare/X86/sink-addrmode-base.ll | 4 +-
.../X86/sink-addrmode-select.ll | 2 +-
.../X86/sink-addrmode-two-phi.ll | 2 +-
.../X86/split-store-alignment.ll | 2 +-
.../X86/store-extract-division-ub.ll | 2 +-
57 files changed, 119 insertions(+), 119 deletions(-)
diff --git a/llvm/lib/CodeGen/CodeGenOptions.td b/llvm/lib/CodeGen/CodeGenOptions.td
index f2b9d07f4276a..6956c70e0f0ec 100644
--- a/llvm/lib/CodeGen/CodeGenOptions.td
+++ b/llvm/lib/CodeGen/CodeGenOptions.td
@@ -15,37 +15,37 @@ defm : BoolField<"bbsections-guided-section-prefix", "true",
"Use the basic-block-sections profile to determine the text section prefix for hot functions. "
"Functions with basic-block-sections profile will be placed in `.text.hot` regardless of their FDO profile info. "
"Other functions won't be impacted, i.e., their prefixes will be decided by FDO/sampleFDO profiles">;
-defm : BoolField<"addr-sink-combine-base-gv", "true",
+defm : BoolField<"cgp-addr-sink-combine-base-gv", "true",
"Allow combining of BaseGV field in Address sinking">;
-defm : BoolField<"addr-sink-combine-base-offs", "true",
+defm : BoolField<"cgp-addr-sink-combine-base-offs", "true",
"Allow combining of BaseOffs field in Address sinking">;
-defm : BoolField<"addr-sink-combine-base-reg", "true",
+defm : BoolField<"cgp-addr-sink-combine-base-reg", "true",
"Allow combining of BaseReg field in Address sinking">;
-defm : BoolField<"addr-sink-combine-scaled-reg", "true",
+defm : BoolField<"cgp-addr-sink-combine-scaled-reg", "true",
"Allow combining of ScaledReg field in Address sinking">;
-defm : BoolField<"addr-sink-new-phis", "false",
+defm : BoolField<"cgp-addr-sink-new-phis", "false",
"Allow creation of Phis in Address sinking">;
-defm : BoolField<"addr-sink-new-select", "true",
+defm : BoolField<"cgp-addr-sink-new-select", "true",
"Allow creation of selects in Address sinking">;
-defm : OptionalBoolField<"addr-sink-using-gep",
+defm : OptionalBoolField<"cgp-addr-sink-using-gep",
"Address sinking in CGP using GEPs">;
-defm : BoolField<"enable-andcmp-sinking", "true",
+defm : BoolField<"cgp-andcmp-sinking", "true",
"Enable sinking and/cmp into branches">;
-defm : BoolField<"disable-cgp-branch-opts", "false",
- "Disable branch optimizations in CodeGenPrepare">;
-defm : BoolField<"disable-complex-addr-modes", "false",
- "Disables combining addressing modes with different parts in optimizeMemoryInst">;
-defm : BoolField<"disable-cgp-delete-phis", "false",
- "Disable elimination of dead PHI nodes">;
-defm : BoolField<"disable-cgp-ext-ld-promotion", "false",
- "Disable ext(promotable(ld)) -> promoted(ext(ld)) optimization in CodeGenPrepare">;
-defm : BoolField<"force-split-store", "false",
+defm : BoolField<"cgp-branch-opts", "true",
+ "Enable branch optimizations in CodeGenPrepare">;
+defm : BoolField<"cgp-complex-addr-modes", "true",
+ "Enable combining addressing modes with different parts in optimizeMemoryInst">;
+defm : BoolField<"cgp-delete-phis", "true",
+ "Enable elimination of dead PHI nodes">;
+defm : BoolField<"cgp-ext-ld-promotion", "true",
+ "Enable ext(promotable(ld)) -> promoted(ext(ld)) optimization in CodeGenPrepare">;
+defm : BoolField<"cgp-force-split-store", "false",
"Force store splitting no matter what the target query says">;
defm : ValueField<"cgp-freq-ratio-to-skip-merge", "uint64_t", "2",
"Skip merging empty blocks if (frequency of empty block) / (frequency of destination block) is greater than this ratio">;
-defm : BoolField<"disable-cgp-gc-opts", "false",
- "Disable GC optimizations in CodeGenPrepare">;
-defm : ValueField<"cgpp-huge-func", "unsigned", "10000",
+defm : BoolField<"cgp-gc-opts", "true",
+ "Enable GC optimizations in CodeGenPrepare">;
+defm : ValueField<"cgp-huge-func", "unsigned", "10000",
"Least BB number of huge function">;
defm : BoolField<"cgp-icmp-eq2icmp-st", "false",
"Enable ICMP_EQ to ICMP_S(L|G)T conversion">;
@@ -53,17 +53,17 @@ defm : ValueField<"cgp-max-address-users-to-scan", "unsigned", "100",
"Max number of address users to look at">;
defm : BoolField<"cgp-optimize-phi-types", "true",
"Enable converting phi types in CodeGenPrepare">;
-defm : BoolField<"disable-preheader-prot", "false",
- "Disable protection against removing loop preheaders">;
-defm : BoolField<"disable-cgp-select2branch", "false",
- "Disable select to branch conversion">;
+defm : BoolField<"cgp-preheader-prot", "true",
+ "Protect loop preheaders from removal">;
+defm : BoolField<"cgp-select2branch", "true",
+ "Enable select to branch conversion">;
defm : BoolField<"cgp-split-large-offset-gep", "true",
"Enable splitting large offset of GEP">;
-defm : BoolField<"disable-cgp-store-extract", "false",
- "Disable store(extract) optimizations in CodeGenPrepare">;
-defm : BoolField<"stress-cgp-ext-ld-promotion", "false",
+defm : BoolField<"cgp-store-extract", "true",
+ "Enable store(extract) optimizations in CodeGenPrepare">;
+defm : BoolField<"cgp-stress-ext-ld-promotion", "false",
"Stress test ext(promotable(ld)) -> promoted(ext(ld)) optimization in CodeGenPrepare">;
-defm : BoolField<"stress-cgp-store-extract", "false",
+defm : BoolField<"cgp-stress-store-extract", "false",
"Stress test store(extract) optimizations in CodeGenPrepare">;
defm : BoolField<"cgp-type-promotion-merge", "true",
"Enable merging of redundant sexts when one is dominating the other">;
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index 24f91d05d3bad..f6e9f3cd42db7 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -503,7 +503,7 @@ bool CodeGenPrepare::_run(Function &F) {
if (ResetLI)
resetLoopInfo();
- if (!Opts.disable_cgp_branch_opts)
+ if (Opts.cgp_branch_opts)
EverMadeChange |= splitBranchCondition(F);
// Split some critical edges where one of the sources is an indirect branch,
@@ -525,7 +525,7 @@ bool CodeGenPrepare::_run(Function &F) {
// If we are optimzing huge function, we need to consider the build time.
// Because the basic algorithm's complex is near O(N!).
- IsHugeFunc = F.size() > Opts.cgpp_huge_func;
+ IsHugeFunc = F.size() > Opts.cgp_huge_func;
bool MadeChange = true;
bool FuncIterated = false;
@@ -605,7 +605,7 @@ bool CodeGenPrepare::_run(Function &F) {
// LoopInfo is not needed anymore and ConstantFoldTerminator can break it.
LI = nullptr;
- if (!Opts.disable_cgp_branch_opts) {
+ if (Opts.cgp_branch_opts) {
MadeChange = false;
// Use a set vector to get deterministic iteration order. The order the
// blocks are removed may affect whether or not PHI nodes in successors
@@ -646,7 +646,7 @@ bool CodeGenPrepare::_run(Function &F) {
EverMadeChange |= MadeChange;
}
- if (!Opts.disable_cgp_gc_opts) {
+ if (Opts.cgp_gc_opts) {
SmallVector<GCStatepointInst *, 2> Statepoints;
for (BasicBlock &BB : F)
for (Instruction &I : BB)
@@ -813,7 +813,7 @@ bool CodeGenPrepare::eliminateMostlyEmptyBlocks(Function &F, bool &ResetLI) {
// Note that this intentionally skips the entry block.
for (auto &Block : llvm::drop_begin(F)) {
// Delete phi nodes that could block deleting other empty blocks.
- if (!Opts.disable_cgp_delete_phis)
+ if (Opts.cgp_delete_phis)
MadeChange |= DeleteDeadPHIs(&Block, TLInfo, nullptr, &KnownNonDeadPHIs);
}
@@ -839,7 +839,7 @@ bool CodeGenPrepare::isMergingEmptyBlockProfitable(BasicBlock *BB,
// Loop preheaders can be good locations to spill registers. If the
// preheader is deleted and we create a critical edge, registers may be
// spilled in the loop body instead.
- if (!Opts.disable_preheader_prot && isPreheader &&
+ if (Opts.cgp_preheader_prot && isPreheader &&
!(BB->getSinglePredecessor() &&
BB->getSinglePredecessor()->getSingleSuccessor()))
return false;
@@ -4219,14 +4219,14 @@ class AddressingModeCombiner {
// Second Step, fill new nodes by merged values and simplify if possible.
FillPlaceholders(Map, TraverseOrder, ST);
- if (!Opts.addr_sink_new_select && ST.countNewSelectNodes() > 0) {
+ if (!Opts.cgp_addr_sink_new_select && ST.countNewSelectNodes() > 0) {
ST.destroyNewNodes(CommonType);
return nullptr;
}
// Now we'd like to match New Phi nodes to existed ones.
unsigned PhiNotMatchedCount = 0;
- if (!MatchPhiSet(ST, Opts.addr_sink_new_phis, PhiNotMatchedCount)) {
+ if (!MatchPhiSet(ST, Opts.cgp_addr_sink_new_phis, PhiNotMatchedCount)) {
ST.destroyNewNodes(CommonType);
return nullptr;
}
@@ -4419,19 +4419,19 @@ class AddressingModeCombiner {
}
bool addrModeCombiningAllowed() {
- if (Opts.disable_complex_addr_modes)
+ if (!Opts.cgp_complex_addr_modes)
return false;
switch (DifferentField) {
default:
return false;
case ExtAddrMode::BaseRegField:
- return Opts.addr_sink_combine_base_reg;
+ return Opts.cgp_addr_sink_combine_base_reg;
case ExtAddrMode::BaseGVField:
- return Opts.addr_sink_combine_base_gv;
+ return Opts.cgp_addr_sink_combine_base_gv;
case ExtAddrMode::BaseOffsField:
- return Opts.addr_sink_combine_base_offs;
+ return Opts.cgp_addr_sink_combine_base_offs;
case ExtAddrMode::ScaledRegField:
- return Opts.addr_sink_combine_scaled_reg;
+ return Opts.cgp_addr_sink_combine_scaled_reg;
}
}
};
@@ -5888,8 +5888,8 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr,
} else
SunkAddr = Builder.CreatePointerCast(SunkAddr, Addr->getType());
}
- } else if (valueOr(Opts.addr_sink_using_gep, true) ||
- (Opts.addr_sink_using_gep == BoolOrDefault::Default &&
+ } else if (valueOr(Opts.cgp_addr_sink_using_gep, true) ||
+ (Opts.cgp_addr_sink_using_gep == BoolOrDefault::Default &&
SubtargetInfo->addrSinkUsingGEPs())) {
// By default, we use the GEP-based method when AA is used later. This
// prevents new inttoptr/ptrtoint pairs from degrading AA capabilities.
@@ -6588,7 +6588,7 @@ bool CodeGenPrepare::tryToPromoteExts(
// this check inside the for loop is to catch the case where an extension
// is directly fed by a load because in such case the extension can be moved
// up without any promotion on its operands.
- if (!TLI->enableExtLdPromotion() || Opts.disable_cgp_ext_ld_promotion)
+ if (!TLI->enableExtLdPromotion() || !Opts.cgp_ext_ld_promotion)
return false;
// Get the action to perform the promotion.
@@ -6626,7 +6626,7 @@ bool CodeGenPrepare::tryToPromoteExts(
// conservatively ceiling it to 0.
TotalCreatedInstsCost =
std::max((long long)0, (TotalCreatedInstsCost - ExtCost));
- if (!Opts.stress_cgp_ext_ld_promotion &&
+ if (!Opts.cgp_stress_ext_ld_promotion &&
(TotalCreatedInstsCost > 1 ||
!isPromotedInstructionLegal(*TLI, *DL, PromotedVal) ||
(ExtCost == 0 && NewExts.size() > 1))) {
@@ -6647,7 +6647,7 @@ bool CodeGenPrepare::tryToPromoteExts(
// If we have reached to a load, we need this extra profitability check
// as it could potentially be merged into an ext(load).
if (isa<LoadInst>(ExtOperand) &&
- !(Opts.stress_cgp_ext_ld_promotion ||
+ !(Opts.cgp_stress_ext_ld_promotion ||
NewCreatedInstsCost <= ExtCost ||
(ExtOperand->hasOneUse() || hasSameExtUse(ExtOperand, *TLI))))
continue;
@@ -7609,7 +7609,7 @@ bool CodeGenPrepare::optimizeFunnelShift(IntrinsicInst *Fsh) {
/// If we have a SelectInst that will likely profit from branch prediction,
/// turn it into a branch.
bool CodeGenPrepare::optimizeSelectInst(SelectInst *SI) {
- if (Opts.disable_cgp_select2branch)
+ if (!Opts.cgp_select2branch)
return false;
// If the SelectOptimize pass is enabled, selects have already been optimized.
@@ -8366,8 +8366,8 @@ void VectorPromoteHelper::promoteImpl(Instruction *ToBePromoted) {
/// has this feature and this is profitable.
bool CodeGenPrepare::optimizeExtractElementInst(Instruction *Inst) {
unsigned CombineCost = std::numeric_limits<unsigned>::max();
- if (Opts.disable_cgp_store_extract ||
- (!Opts.stress_cgp_store_extract &&
+ if (!Opts.cgp_store_extract ||
+ (!Opts.cgp_stress_store_extract &&
!TLI->canCombineStoreAndExtract(Inst->getOperand(0)->getType(),
Inst->getOperand(1), CombineCost)))
return false;
@@ -8382,7 +8382,7 @@ bool CodeGenPrepare::optimizeExtractElementInst(Instruction *Inst) {
BasicBlock *Parent = Inst->getParent();
LLVM_DEBUG(dbgs() << "Found an interesting transition: " << *Inst << '\n');
VectorPromoteHelper VPH(*DL, *TLI, *TTI, Inst, CombineCost,
- Opts.stress_cgp_store_extract);
+ Opts.cgp_stress_store_extract);
// If the transition has more than one use, assume this is not going to be
// beneficial.
while (Inst->hasOneUse()) {
@@ -8876,7 +8876,7 @@ bool CodeGenPrepare::optimizeInst(Instruction *I, ModifyDT &ModifiedDT) {
}
if (StoreInst *SI = dyn_cast<StoreInst>(I)) {
- if (splitMergedValStore(*SI, *DL, *TLI, Opts.force_split_store))
+ if (splitMergedValStore(*SI, *DL, *TLI, Opts.cgp_force_split_store))
return true;
SI->setMetadata(LLVMContext::MD_invariant_group, nullptr);
unsigned AS = SI->getPointerAddressSpace();
@@ -8898,7 +8898,7 @@ bool CodeGenPrepare::optimizeInst(Instruction *I, ModifyDT &ModifiedDT) {
BinaryOperator *BinOp = dyn_cast<BinaryOperator>(I);
if (BinOp && BinOp->getOpcode() == Instruction::And &&
- Opts.enable_andcmp_sinking &&
+ Opts.cgp_andcmp_sinking &&
sinkAndCmp0Expression(BinOp, *TLI, InsertedInsts))
return true;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
index 66e0fd15ce9c1..1b4c5652212cb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple aarch64 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=ir-translator -global-isel -verify-machineinstrs -disable-cgp-delete-phis %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple aarch64 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=ir-translator -global-isel -verify-machineinstrs -cgp-delete-phis=0 %s -o - 2>&1 | FileCheck %s
define i32 @test_bittest(i16 %p) {
; CHECK-LABEL: name: test_bittest
diff --git a/llvm/test/CodeGen/AArch64/and-sink.ll b/llvm/test/CodeGen/AArch64/and-sink.ll
index c84310629e5fd..dd2cf06668726 100644
--- a/llvm/test/CodeGen/AArch64/and-sink.ll
+++ b/llvm/test/CodeGen/AArch64/and-sink.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -mtriple=aarch64-linux %s | FileCheck --check-prefix=CHECK-CGP %s
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgpp-huge-func=0 -mtriple=aarch64-linux %s | FileCheck --check-prefix=CHECK-CGP %s
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgp-huge-func=0 -mtriple=aarch64-linux %s | FileCheck --check-prefix=CHECK-CGP %s
@A = dso_local global i32 zeroinitializer
@B = dso_local global i32 zeroinitializer
diff --git a/llvm/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll b/llvm/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll
index 4bc3ba0f0a966..d3f29ac828f5a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O1 -mtriple=arm64-apple-ios7.0.0 -enable-andcmp-sinking=true < %s | FileCheck %s
+; RUN: llc -O1 -mtriple=arm64-apple-ios7.0.0 -cgp-andcmp-sinking=1 < %s | FileCheck %s
; ModuleID = 'and-cbz-extr-mr.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll b/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
index 7b4a94a41f7d8..1354ca38f572d 100644
--- a/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -mtriple=aarch64-apple-ios -S | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefixes=OPT,NONSTRESS
-; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -mtriple=aarch64-apple-ios -S -stress-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefixes=OPTALL,OPT,STRESS
-; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -mtriple=aarch64-apple-ios -S -disable-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefixes=OPTALL,DISABLE
+; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -mtriple=aarch64-apple-ios -S -cgp-stress-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefixes=OPTALL,OPT,STRESS
+; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -mtriple=aarch64-apple-ios -S -cgp-ext-ld-promotion=0 | FileCheck -enable-var-scope %s --check-prefixes=OPTALL,DISABLE
; CodeGenPrepare should move the zext into the block with the load
; so that SelectionDAG can select it with the load.
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-int-ext2.ll b/llvm/test/CodeGen/AArch64/fast-isel-int-ext2.ll
index 98e020e01da60..5e6550faab482 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-int-ext2.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-int-ext2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -aarch64-enable-atomic-cfg-tidy=false -disable-cgp-branch-opts -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -aarch64-enable-atomic-cfg-tidy=false -cgp-branch-opts=0 -verify-machineinstrs < %s | FileCheck %s
;
; Test folding of the sign-/zero-extend into the load instruction.
diff --git a/llvm/test/CodeGen/ARM/constants.ll b/llvm/test/CodeGen/ARM/constants.ll
index 75a90bbf0caa6..7f9c6c5f6d02f 100644
--- a/llvm/test/CodeGen/ARM/constants.ll
+++ b/llvm/test/CodeGen/ARM/constants.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=armv4t-unknown-linux-gnueabi -disable-cgp-branch-opts -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=armv4t-unknown-linux-gnueabi -cgp-branch-opts=0 -verify-machineinstrs | FileCheck %s
define i32 @f1() {
; CHECK: f1
diff --git a/llvm/test/CodeGen/ARM/vector-promotion.ll b/llvm/test/CodeGen/ARM/vector-promotion.ll
index 41fff7823f765..25cff4f5e7808 100644
--- a/llvm/test/CodeGen/ARM/vector-promotion.ll
+++ b/llvm/test/CodeGen/ARM/vector-promotion.ll
@@ -1,5 +1,5 @@
; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon -S | FileCheck --check-prefix=IR-BOTH --check-prefix=IR-NORMAL %s
-; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon -S -stress-cgp-store-extract | FileCheck --check-prefix=IR-BOTH --check-prefix=IR-STRESS %s
+; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon -S -cgp-stress-store-extract | FileCheck --check-prefix=IR-BOTH --check-prefix=IR-STRESS %s
; RUN: llc -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon | FileCheck --check-prefix=ASM %s
; IR-BOTH-LABEL: @simpleOneInstructionPromotion
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll b/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
index 607532beb30e3..ca0bcb9e00866 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -disable-cgp-delete-phis < %s | FileCheck %s
+; RUN: llc -mtriple=hexagon -cgp-delete-phis=0 < %s | FileCheck %s
; REQUIRES: asserts
; Check that this testcase compiles successfully.
diff --git a/llvm/test/CodeGen/Hexagon/postinc-offset.ll b/llvm/test/CodeGen/Hexagon/postinc-offset.ll
index d1b103ed1e70a..aee6d52be6f7b 100644
--- a/llvm/test/CodeGen/Hexagon/postinc-offset.ll
+++ b/llvm/test/CodeGen/Hexagon/postinc-offset.ll
@@ -1,4 +1,4 @@
-; RUN: llc -enable-aa-sched-mi -mtriple=hexagon -mcpu=hexagonv5 -rdf-opt=0 -disable-cgp-delete-phis \
+; RUN: llc -enable-aa-sched-mi -mtriple=hexagon -mcpu=hexagonv5 -rdf-opt=0 -cgp-delete-phis=0 \
; RUN: < %s | FileCheck %s
; CHECK: {
diff --git a/llvm/test/CodeGen/Hexagon/swp-carried-1.ll b/llvm/test/CodeGen/Hexagon/swp-carried-1.ll
index f2beadfbfa64b..7ae737a78f086 100644
--- a/llvm/test/CodeGen/Hexagon/swp-carried-1.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-carried-1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -rdf-opt=0 -disable-hexagon-misched -hexagon-initial-cfg-cleanup=0 -lsr-setupcost-depth-limit=1 -disable-cgp-delete-phis < %s -pipeliner-experimental-cg=true -terminal-rule=0 | FileCheck %s
+; RUN: llc -mtriple=hexagon -rdf-opt=0 -disable-hexagon-misched -hexagon-initial-cfg-cleanup=0 -lsr-setupcost-depth-limit=1 -cgp-delete-phis=0 < %s -pipeliner-experimental-cg=true -terminal-rule=0 | FileCheck %s
; Test that we generate the correct code when a loop carried value
; is scheduled one stage earlier than it's use. The code in
diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll
index c6631bd9dc16d..9ca398d6604a9 100644
--- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true -disable-cgp-delete-phis -terminal-rule=0 < %s | FileCheck %s
+; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true -cgp-delete-phis=0 -terminal-rule=0 < %s | FileCheck %s
; Test epilogue generation when reading loop-carried dependency from a previous
; stage. The first epilogue should read value from iteration N-1 of the kernel.
diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll
index 3b9ee75b9ffaf..b7cafe49275da 100644
--- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -O2 -debug-only=pipeliner -hexagon-initial-cfg-cleanup=0 -disable-cgp-delete-phis < %s -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc -mtriple=hexagon -O2 -debug-only=pipeliner -hexagon-initial-cfg-cleanup=0 -cgp-delete-phis=0 < %s -o - 2>&1 > /dev/null | FileCheck %s
; REQUIRES: asserts
; Test that the phi in the first epilog block is getter the correct
diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll
index 549428643ccaa..1d774d42f1add 100644
--- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll
@@ -1,5 +1,5 @@
; XFAIL: Hexagon
-; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -disable-cgp-delete-phis < %s | FileCheck %s
+; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -cgp-delete-phis=0 < %s | FileCheck %s
; Test that we generate the correct Phi name in the last couple of epilog
; blocks, when there are 3 epilog blocks. The Phi was scheduled in stage
diff --git a/llvm/test/CodeGen/Hexagon/swp-lots-deps.ll b/llvm/test/CodeGen/Hexagon/swp-lots-deps.ll
index f5f480d161a9d..813c764b00269 100644
--- a/llvm/test/CodeGen/Hexagon/swp-lots-deps.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-lots-deps.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -enable-pipeliner -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true -disable-cgp-delete-phis | FileCheck %s --check-prefix=STATS
+; RUN: llc -mtriple=hexagon -enable-pipeliner -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true -cgp-delete-phis=0 | FileCheck %s --check-prefix=STATS
; REQUIRES: asserts
; STATS: 1 pipeliner - Number of loops software pipelined
diff --git a/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll b/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll
index ecb3c869d3637..d12016b68e11f 100644
--- a/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true -disable-cgp-delete-phis | FileCheck %s
+; RUN: llc -mtriple=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true -cgp-delete-phis=0 | FileCheck %s
; Test that we generate the correct name for a value in a prolog block. The
; pipeliner was using an incorrect value for an instruction in the 2nd prolog
diff --git a/llvm/test/CodeGen/Hexagon/swp-tfri.ll b/llvm/test/CodeGen/Hexagon/swp-tfri.ll
index 26009793f63c4..96e8fe168ba59 100644
--- a/llvm/test/CodeGen/Hexagon/swp-tfri.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-tfri.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true -disable-cgp-delete-phis | FileCheck %s --check-prefix=STATS
+; RUN: llc -mtriple=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true -cgp-delete-phis=0 | FileCheck %s --check-prefix=STATS
; REQUIRES: asserts
; Check that we handle the case when a value is first defined in the loop.
diff --git a/llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll b/llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll
index b6494f918b031..21ca1a391d60b 100644
--- a/llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll
+++ b/llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -disable-cgp-delete-phis < %s | FileCheck %s
+; RUN: llc -mtriple=hexagon -cgp-delete-phis=0 < %s | FileCheck %s
; Test that we no longer generate an unaligned vector store for a spill when
; a function has an alloca.
diff --git a/llvm/test/CodeGen/Mips/brdelayslot.ll b/llvm/test/CodeGen/Mips/brdelayslot.ll
index da14564b77e64..36779eee4e435 100644
--- a/llvm/test/CodeGen/Mips/brdelayslot.ll
+++ b/llvm/test/CodeGen/Mips/brdelayslot.ll
@@ -7,7 +7,7 @@
; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=FORWARD
; RUN: llc -mtriple=mipsel -disable-mips-df-backward-search -relocation-model=pic \
; RUN: -enable-shrink-wrap=false \
-; RUN: -disable-mips-df-succbb-search=false -disable-preheader-prot=true < %s | \
+; RUN: -disable-mips-df-succbb-search=false -cgp-preheader-prot=0 < %s | \
; RUN: FileCheck %s -check-prefix=SUCCBB
define void @foo1() nounwind {
diff --git a/llvm/test/CodeGen/PowerPC/sink-side-effect.ll b/llvm/test/CodeGen/PowerPC/sink-side-effect.ll
index 94d2a090bce10..125a59d8a55b4 100644
--- a/llvm/test/CodeGen/PowerPC/sink-side-effect.ll
+++ b/llvm/test/CodeGen/PowerPC/sink-side-effect.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=powerpc64le -mcpu=pwr9 -verify-machineinstrs -disable-cgp-delete-phis < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le -mcpu=pwr9 -verify-machineinstrs -cgp-delete-phis=0 < %s | FileCheck %s
define double @zot(ptr %arg, ptr %arg1, ptr %arg2) {
; CHECK-LABEL: zot:
diff --git a/llvm/test/CodeGen/PowerPC/sms-iterator.ll b/llvm/test/CodeGen/PowerPC/sms-iterator.ll
index 35e448ff35f5b..7e70d5e8d3dad 100644
--- a/llvm/test/CodeGen/PowerPC/sms-iterator.ll
+++ b/llvm/test/CodeGen/PowerPC/sms-iterator.ll
@@ -1,6 +1,6 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
-; RUN: -mcpu=pwr9 --ppc-enable-pipeliner -debug-only=pipeliner -disable-cgp-delete-phis 2>&1 \
+; RUN: -mcpu=pwr9 --ppc-enable-pipeliner -debug-only=pipeliner -cgp-delete-phis=0 2>&1 \
; RUN: >/dev/null | FileCheck %s
%0 = type { i32, [16 x double] }
diff --git a/llvm/test/CodeGen/PowerPC/splitstore-check-volatile.ll b/llvm/test/CodeGen/PowerPC/splitstore-check-volatile.ll
index 271e1e39c8dfd..4dce3f65eb223 100644
--- a/llvm/test/CodeGen/PowerPC/splitstore-check-volatile.ll
+++ b/llvm/test/CodeGen/PowerPC/splitstore-check-volatile.ll
@@ -1,6 +1,6 @@
; Test that CodeGenPrepare respect the volatile flag when splitting a store.
;
-; RUN: opt -S -mtriple=powerpc64le -codegenprepare -force-split-store < %s | FileCheck %s
+; RUN: opt -S -mtriple=powerpc64le -codegenprepare -cgp-force-split-store < %s | FileCheck %s
define void @fun(ptr %Src, ptr %Dst) {
; CHECK: store volatile i16 %8, ptr %Dst
diff --git a/llvm/test/CodeGen/SystemZ/codegenprepare-splitstore.ll b/llvm/test/CodeGen/SystemZ/codegenprepare-splitstore.ll
index 0b7cf9888f562..5ed55fa17a589 100644
--- a/llvm/test/CodeGen/SystemZ/codegenprepare-splitstore.ll
+++ b/llvm/test/CodeGen/SystemZ/codegenprepare-splitstore.ll
@@ -1,6 +1,6 @@
; Test that CodeGenPrepare respects endianness when splitting a store.
;
-; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -stop-after codegenprepare -force-split-store < %s | FileCheck %s
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -stop-after codegenprepare -cgp-force-split-store < %s | FileCheck %s
define void @fun(ptr %Src, ptr %Dst) {
; CHECK-LABEL: @fun(
diff --git a/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll b/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
index 813242f7d4ccb..55c17b676129c 100644
--- a/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
+++ b/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=RA_GREEDY
-; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -regalloc=basic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=RA_BASIC
+; RUN: llc < %s -mtriple=thumb-apple-darwin -cgp-branch-opts=0 -disable-post-ra -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=RA_GREEDY
+; RUN: llc < %s -mtriple=thumb-apple-darwin -cgp-branch-opts=0 -disable-post-ra -regalloc=basic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=RA_BASIC
%struct.state = type { i32, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, ptr }
%struct.info = type { i32, i32, i32, i32, i32, i32, i32, ptr }
diff --git a/llvm/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll b/llvm/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
index 24f87dc1292a1..c717be266612c 100644
--- a/llvm/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
+++ b/llvm/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=thumbv7-apple-darwin10 -arm-atomic-cfg-tidy=0 -disable-cgp-delete-phis < %s | FileCheck %s
+; RUN: llc -mtriple=thumbv7-apple-darwin10 -arm-atomic-cfg-tidy=0 -cgp-delete-phis=0 < %s | FileCheck %s
%struct.op = type { ptr, ptr, ptr, i32, i16, i16, i8, i8 }
diff --git a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
index 2ebdb2124afa2..6f1419c538eb7 100644
--- a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
+++ b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386-apple-darwin -disable-cgp-branch-opts | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin -cgp-branch-opts=0 | FileCheck %s
%struct.DBC_t = type { i32, ptr, i16, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, i32, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, ptr, i8, i16, ptr, i16 }
%struct.DRVOPT = type { i16, i32, i8, ptr }
diff --git a/llvm/test/CodeGen/X86/2012-10-18-crash-dagco.ll b/llvm/test/CodeGen/X86/2012-10-18-crash-dagco.ll
index 1c418a75c9b14..2b37c25acabda 100644
--- a/llvm/test/CodeGen/X86/2012-10-18-crash-dagco.ll
+++ b/llvm/test/CodeGen/X86/2012-10-18-crash-dagco.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=corei7 -disable-cgp-select2branch < %s
+; RUN: llc -mcpu=corei7 -cgp-select2branch=0 < %s
; We should not crash on this test.
diff --git a/llvm/test/CodeGen/X86/MachineSink-PHIUse.ll b/llvm/test/CodeGen/X86/MachineSink-PHIUse.ll
index 1329200c3e6e5..ef862f31409c4 100644
--- a/llvm/test/CodeGen/X86/MachineSink-PHIUse.ll
+++ b/llvm/test/CodeGen/X86/MachineSink-PHIUse.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc < %s -mtriple=x86_64-appel-darwin -disable-cgp-branch-opts -stats 2>&1 | grep "machine-sink"
+; RUN: llc < %s -mtriple=x86_64-appel-darwin -cgp-branch-opts=0 -stats 2>&1 | grep "machine-sink"
define fastcc void @t() nounwind ssp {
entry:
diff --git a/llvm/test/CodeGen/X86/and-sink.ll b/llvm/test/CodeGen/X86/and-sink.ll
index d9a34d743ac65..5f8df58792008 100644
--- a/llvm/test/CodeGen/X86/and-sink.ll
+++ b/llvm/test/CodeGen/X86/and-sink.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=i686-unknown -verify-machineinstrs < %s | FileCheck %s
; RUN: opt < %s -codegenprepare -S -mtriple=x86_64-unknown-unknown | FileCheck --check-prefix=CHECK-CGP %s
-; RUN: opt < %s -codegenprepare -cgpp-huge-func=0 -S -mtriple=x86_64-unknown-unknown | FileCheck --check-prefix=CHECK-CGP %s
+; RUN: opt < %s -codegenprepare -cgp-huge-func=0 -S -mtriple=x86_64-unknown-unknown | FileCheck --check-prefix=CHECK-CGP %s
@A = global i32 zeroinitializer
@B = global i32 zeroinitializer
diff --git a/llvm/test/CodeGen/X86/avx512-i1test.ll b/llvm/test/CodeGen/X86/avx512-i1test.ll
index c5d4c87d66da2..5cede2b979c16 100644
--- a/llvm/test/CodeGen/X86/avx512-i1test.ll
+++ b/llvm/test/CodeGen/X86/avx512-i1test.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mattr=+avx512f -disable-cgp-delete-phis | FileCheck %s
-; RUN: llc < %s -mattr=+avx512f -mattr=+avx512vl -mattr=+avx512bw -mattr=+avx512dq -disable-cgp-delete-phis | FileCheck %s
+; RUN: llc < %s -mattr=+avx512f -cgp-delete-phis=0 | FileCheck %s
+; RUN: llc < %s -mattr=+avx512f -mattr=+avx512vl -mattr=+avx512bw -mattr=+avx512dq -cgp-delete-phis=0 | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/CodeGen/X86/cmov.ll b/llvm/test/CodeGen/X86/cmov.ll
index 374e75967d52f..6bd0a24ccb553 100644
--- a/llvm/test/CodeGen/X86/cmov.ll
+++ b/llvm/test/CodeGen/X86/cmov.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -disable-cgp-select2branch -x86-cmov-converter=false | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -cgp-select2branch=0 -x86-cmov-converter=false | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
define i32 @test1(i32 %x, i32 %n, i32 %w, ptr %vp) nounwind readnone {
diff --git a/llvm/test/CodeGen/X86/codegen-prepare-extload.ll b/llvm/test/CodeGen/X86/codegen-prepare-extload.ll
index 7846f82ad54cd..de024da409ffa 100644
--- a/llvm/test/CodeGen/X86/codegen-prepare-extload.ll
+++ b/llvm/test/CodeGen/X86/codegen-prepare-extload.ll
@@ -2,8 +2,8 @@
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win64 | FileCheck %s
; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -mtriple=x86_64-apple-macosx -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
-; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -mtriple=x86_64-apple-macosx -S -stress-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
-; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -mtriple=x86_64-apple-macosx -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
+; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -mtriple=x86_64-apple-macosx -S -cgp-stress-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
+; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -mtriple=x86_64-apple-macosx -S -cgp-ext-ld-promotion=0 | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
; rdar://7304838
; CodeGenPrepare should move the zext into the block with the load
diff --git a/llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll b/llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll
index eccb32346a403..19da39c532305 100644
--- a/llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll
+++ b/llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-- -disable-cgp-delete-phis | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -cgp-delete-phis=0 | FileCheck %s
%struct.COMPOSITE = type { i8, i16, i16 }
%struct.FILE = type { ptr, i32, i32, i16, i16, %struct.__sbuf, i32, ptr, ptr, ptr, ptr, ptr, %struct.__sbuf, ptr, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
diff --git a/llvm/test/CodeGen/X86/phi-immediate-factoring.ll b/llvm/test/CodeGen/X86/phi-immediate-factoring.ll
index e90f66df871c5..189781f331556 100644
--- a/llvm/test/CodeGen/X86/phi-immediate-factoring.ll
+++ b/llvm/test/CodeGen/X86/phi-immediate-factoring.ll
@@ -1,7 +1,7 @@
; REQUIRES: asserts
-; RUN: llc < %s -disable-preheader-prot=true -stats 2>&1 | grep "Number of blocks eliminated" | grep 3
-; RUN: llc < %s -disable-preheader-prot=true -stats -cgp-freq-ratio-to-skip-merge=10 2>&1 | grep "Number of blocks eliminated" | grep 6
-; RUN: llc < %s -disable-preheader-prot=false -stats 2>&1 | grep "Number of blocks eliminated" | grep 3
+; RUN: llc < %s -cgp-preheader-prot=0 -stats 2>&1 | grep "Number of blocks eliminated" | grep 3
+; RUN: llc < %s -cgp-preheader-prot=0 -stats -cgp-freq-ratio-to-skip-merge=10 2>&1 | grep "Number of blocks eliminated" | grep 6
+; RUN: llc < %s -cgp-preheader-prot=1 -stats 2>&1 | grep "Number of blocks eliminated" | grep 3
; PR1296
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
diff --git a/llvm/test/CodeGen/X86/pr3366.ll b/llvm/test/CodeGen/X86/pr3366.ll
index 22129839eb2a4..4aeb4e65af52f 100644
--- a/llvm/test/CodeGen/X86/pr3366.ll
+++ b/llvm/test/CodeGen/X86/pr3366.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-- -disable-cgp-branch-opts | FileCheck %s
+; RUN: llc < %s -mtriple=i686-- -cgp-branch-opts=0 | FileCheck %s
; PR3366
define void @_ada_c34002a() nounwind {
diff --git a/llvm/test/CodeGen/X86/sext-i1.ll b/llvm/test/CodeGen/X86/sext-i1.ll
index 7a906aed1a42e..2f776167de7bf 100644
--- a/llvm/test/CodeGen/X86/sext-i1.ll
+++ b/llvm/test/CodeGen/X86/sext-i1.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -cgp-branch-opts=0 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -cgp-branch-opts=0 | FileCheck %s --check-prefix=X64
; rdar://7573216
; PR6146
diff --git a/llvm/test/CodeGen/X86/sink-blockfreq.ll b/llvm/test/CodeGen/X86/sink-blockfreq.ll
index c2653a86f53af..85d767896dcc7 100644
--- a/llvm/test/CodeGen/X86/sink-blockfreq.ll
+++ b/llvm/test/CodeGen/X86/sink-blockfreq.ll
@@ -1,6 +1,6 @@
-; RUN: llc -disable-preheader-prot=true -disable-machine-licm -machine-sink-bfi=true -mtriple=x86_64-apple-darwin < %s | FileCheck %s -check-prefix=MSINK_BFI
-; RUN: llc -disable-preheader-prot=true -disable-machine-licm -machine-sink-bfi=false -mtriple=x86_64-apple-darwin < %s | FileCheck %s -check-prefix=MSINK_NOBFI
-; RUN: llc -disable-preheader-prot=true -disable-machine-licm -machine-sink-bfi=true -force-pgso -mtriple=x86_64-apple-darwin < %s | FileCheck %s -check-prefix=MSINK_NOBFI
+; RUN: llc -cgp-preheader-prot=0 -disable-machine-licm -machine-sink-bfi=true -mtriple=x86_64-apple-darwin < %s | FileCheck %s -check-prefix=MSINK_BFI
+; RUN: llc -cgp-preheader-prot=0 -disable-machine-licm -machine-sink-bfi=false -mtriple=x86_64-apple-darwin < %s | FileCheck %s -check-prefix=MSINK_NOBFI
+; RUN: llc -cgp-preheader-prot=0 -disable-machine-licm -machine-sink-bfi=true -force-pgso -mtriple=x86_64-apple-darwin < %s | FileCheck %s -check-prefix=MSINK_NOBFI
; Test that by changing BlockFrequencyInfo we change the order in which
; machine-sink looks for successor blocks. By not using BFI, both G and B
diff --git a/llvm/test/CodeGen/X86/split-store.ll b/llvm/test/CodeGen/X86/split-store.ll
index 416c0cbeeddbd..56d07cf5df9ec 100644
--- a/llvm/test/CodeGen/X86/split-store.ll
+++ b/llvm/test/CodeGen/X86/split-store.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-unknown-unknown -force-split-store < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -cgp-force-split-store < %s | FileCheck %s
define void @int32_float_pair(i32 %tmp1, float %tmp2, ptr %ref.tmp) {
; CHECK-LABEL: int32_float_pair:
diff --git a/llvm/test/CodeGen/X86/tail-opts.ll b/llvm/test/CodeGen/X86/tail-opts.ll
index 6ee16149e0939..baee9a43c77cf 100644
--- a/llvm/test/CodeGen/X86/tail-opts.ll
+++ b/llvm/test/CodeGen/X86/tail-opts.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true -disable-cgp-delete-phis | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true -cgp-delete-phis=0 | FileCheck %s
declare dso_local void @bar(i32)
declare dso_local void @car(i32)
diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
index bd760f62817a0..023f989a24489 100644
--- a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
+++ b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp
-; RUN: llc %s -o - -enable-shrink-wrap=true -pass-remarks-output=%t -disable-cgp-delete-phis | FileCheck %s --check-prefix=ENABLE
+; RUN: llc %s -o - -enable-shrink-wrap=true -pass-remarks-output=%t -cgp-delete-phis=0 | FileCheck %s --check-prefix=ENABLE
; RUN: cat %t | FileCheck %s --check-prefix=REMARKS
-; RUN: llc %s -o - -enable-shrink-wrap=false -disable-cgp-delete-phis | FileCheck %s --check-prefix=DISABLE
+; RUN: llc %s -o - -enable-shrink-wrap=false -cgp-delete-phis=0 | FileCheck %s --check-prefix=DISABLE
;
; Note: Lots of tests use inline asm instead of regular calls.
; This allows to have a better control on what the allocation will do.
diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/sink-addrmode.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/sink-addrmode.ll
index 49cffe286a545..0fcb900a94c78 100644
--- a/llvm/test/Transforms/CodeGenPrepare/ARM/sink-addrmode.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/ARM/sink-addrmode.ll
@@ -1,4 +1,4 @@
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -mtriple=thumbv7m -disable-complex-addr-modes=false -addr-sink-new-select=true -addr-sink-new-phis=true < %s | FileCheck %s
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -mtriple=thumbv7m -cgp-complex-addr-modes=1 -cgp-addr-sink-new-select=true -cgp-addr-sink-new-phis=true < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll
index aac8161dd03f8..a0792820b1127 100644
--- a/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s
-; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -cgpp-huge-func=0 -S | FileCheck -check-prefix=CHECK %s
+; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -cgp-huge-func=0 -S | FileCheck -check-prefix=CHECK %s
; Sink the shufflevector/insertelement pair, followed by the trunc. The sunk instruction end up dead.
define signext i8 @dead(ptr noalias nocapture readonly %s1, i16 zeroext %x, ptr noalias nocapture %d, i32 %n) {
diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll
index 7dcee1c88c480..08bb267fe3728 100644
--- a/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s
-; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -cgpp-huge-func=0 -S | FileCheck -check-prefix=CHECK %s
+; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -cgp-huge-func=0 -S | FileCheck -check-prefix=CHECK %s
; Sink the shufflevector/insertelement pair, followed by the trunc. The sunk instruction end up dead.
define signext i8 @dead(ptr noalias nocapture readonly %s1, i16 zeroext %x, ptr noalias nocapture %d, i32 %n) {
diff --git a/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll b/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll
index 65177d5ae3d7d..57038e7fd4ad8 100644
--- a/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -mtriple=powerpc64-unknown-linux-gnu -data-layout="E-m:e-i64:64-n32:64" -force-split-store < %s | FileCheck --check-prefix=BE %s
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -mtriple=powerpc64le-unknown-linux-gnu -data-layout="e-m:e-i64:64-n32:64" -force-split-store < %s | FileCheck --check-prefix=LE %s
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -mtriple=powerpc64-unknown-linux-gnu -data-layout="E-m:e-i64:64-n32:64" -cgp-force-split-store < %s | FileCheck --check-prefix=BE %s
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -mtriple=powerpc64le-unknown-linux-gnu -data-layout="e-m:e-i64:64-n32:64" -cgp-force-split-store < %s | FileCheck --check-prefix=LE %s
define void @split_store_align1(float %x, ptr %p) {
; BE-LABEL: @split_store_align1(
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/baseoffs-sext-bug.ll b/llvm/test/Transforms/CodeGenPrepare/X86/baseoffs-sext-bug.ll
index 51a461e61d886..d295b250ea05d 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/baseoffs-sext-bug.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/baseoffs-sext-bug.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' < %s | FileCheck --check-prefix=GEP %s
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -addr-sink-using-gep=false < %s | FileCheck --check-prefix=NO-GEP %s
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgp-addr-sink-using-gep=false < %s | FileCheck --check-prefix=NO-GEP %s
target triple = "x86_64--linux-gnu"
target datalayout = "e-m:e-p0:128:128-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll b/llvm/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll
index 5ddd0b9f4107c..617d21c2951cb 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll
@@ -1,4 +1,4 @@
-; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -disable-cgp-branch-opts -S < %s | FileCheck %s
+; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -cgp-branch-opts=0 -S < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll
index ab6eca39d1efd..61393e2022821 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' < %s | FileCheck %s
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgpp-huge-func=0 < %s | FileCheck %s
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgp-huge-func=0 < %s | FileCheck %s
target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/nonintegral.ll b/llvm/test/Transforms/CodeGenPrepare/X86/nonintegral.ll
index 9d53855ada794..8f16feec7a7bf 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/nonintegral.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/nonintegral.ll
@@ -1,5 +1,5 @@
; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' < %s | FileCheck %s
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -addr-sink-using-gep=false < %s | FileCheck %s
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgp-addr-sink-using-gep=false < %s | FileCheck %s
; This target data layout is modified to have a non-integral addrspace(1),
; in order to verify that codegenprepare does not try to introduce illegal
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/pr35658.ll b/llvm/test/Transforms/CodeGenPrepare/X86/pr35658.ll
index e9d0806235c9f..60f9262ece7cc 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/pr35658.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/pr35658.ll
@@ -1,4 +1,4 @@
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -disable-complex-addr-modes=false -addr-sink-new-phis=true -addr-sink-new-select=true %s | FileCheck %s
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgp-complex-addr-modes=1 -cgp-addr-sink-new-phis=true -cgp-addr-sink-new-select=true %s | FileCheck %s
target triple = "x86_64-unknown-linux-gnu"
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addr-recreate.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addr-recreate.ll
index d0d87b38e0589..1ab161110f8ed 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addr-recreate.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addr-recreate.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -S -p 'require<profile-summary>,codegenprepare' -cgpp-huge-func=0 < %s | FileCheck %s
+; RUN: opt -S -p 'require<profile-summary>,codegenprepare' -cgp-huge-func=0 < %s | FileCheck %s
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-grtev4-linux-gnu"
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addr-reuse.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addr-reuse.ll
index 019f311406550..db7dc3ad40501 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addr-reuse.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addr-reuse.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -S -p 'require<profile-summary>,codegenprepare' -cgpp-huge-func=0 < %s | FileCheck %s
+; RUN: opt -S -p 'require<profile-summary>,codegenprepare' -cgp-huge-func=0 < %s | FileCheck %s
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-grtev4-linux-gnu"
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
index 899ff4f8621c3..7248d5c42e43b 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -disable-complex-addr-modes=false -addr-sink-new-phis=true -addr-sink-new-select=true -disable-cgp-delete-phis %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-YES
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -disable-complex-addr-modes=false -addr-sink-new-phis=false -addr-sink-new-select=true -disable-cgp-delete-phis %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NO
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgp-complex-addr-modes=1 -cgp-addr-sink-new-phis=true -cgp-addr-sink-new-select=true -cgp-delete-phis=0 %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-YES
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgp-complex-addr-modes=1 -cgp-addr-sink-new-phis=false -cgp-addr-sink-new-select=true -cgp-delete-phis=0 %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NO
target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-select.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-select.ll
index 076915028aef6..7dc7301eb9ced 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-select.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-select.ll
@@ -1,4 +1,4 @@
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -disable-complex-addr-modes=false -addr-sink-new-select=true %s | FileCheck %s --check-prefix=CHECK
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgp-complex-addr-modes=1 -cgp-addr-sink-new-select=true %s | FileCheck %s --check-prefix=CHECK
target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-two-phi.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-two-phi.ll
index 2945a007bf578..5e1c7656e8d42 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-two-phi.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-two-phi.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -disable-complex-addr-modes=false -disable-cgp-delete-phis %s | FileCheck %s --check-prefix=CHECK
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgp-complex-addr-modes=1 -cgp-delete-phis=0 %s | FileCheck %s --check-prefix=CHECK
target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll b/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll
index 51710edd6e762..a668c65668626 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -mtriple=x86_64-unknown-unknown -force-split-store -S < %s | FileCheck %s
+; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -mtriple=x86_64-unknown-unknown -cgp-force-split-store -S < %s | FileCheck %s
target datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n8:16:32-a:0:32-S32"
target triple = "i686-w64-windows-gnu"
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/store-extract-division-ub.ll b/llvm/test/Transforms/CodeGenPrepare/X86/store-extract-division-ub.ll
index 872a527d5de6d..fb01defad6d29 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/store-extract-division-ub.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/store-extract-division-ub.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; test for issue (https://github.com/llvm/llvm-project/issues/218570)
-; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -stress-cgp-store-extract < %s | FileCheck %s
+; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgp-stress-store-extract < %s | FileCheck %s
target triple = "x86_64-unknown-linux-gnu"
More information about the llvm-commits
mailing list