[llvm] [Mips] Add microMIPS CP0 move encodings (PR #228884)

[Jiaxun Yang via llvm-commits]

https://github.com/FlyGoat updated https://github.com/llvm/llvm-project/pull/228884

>From aef3c65ccddeaee225baef2abc0edbd406ce1175 Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: Sun, 4 Oct 2026 12:23:43 +0100
Subject: [PATCH] [Mips] Add microMIPS CP0 move encodings

Define the microMIPS MFC0 and MTC0 formats and instruction records for
pre-R6 targets, including the select field. Accept the two-operand forms
with an implicit select value of zero and add generic scheduling entries.

Extend the control-instruction tests with explicit and implicit select
operands, checking both byte orders.

Assisted-by: OpenAI Codex # Testcases
---
 llvm/lib/Target/Mips/MicroMipsInstrFormats.td     | 15 +++++++++++++++
 llvm/lib/Target/Mips/MicroMipsInstrInfo.td        | 11 +++++++++++
 llvm/lib/Target/Mips/MipsScheduleGeneric.td       |  4 ++--
 .../test/MC/Mips/micromips-control-instructions.s | 13 ++++++++++++-
 4 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
index ff2b0ff491a3c..faaa9bc15efdf 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
@@ -868,6 +868,21 @@ class CMov_I_F_FM_MM<bits<8> funct, bits<2> fmt> : MMArch {
   let Inst{7-0}   = funct;
 }
 
+class MFC0_FM_MM<bits<11> funct> : MMArch {
+  bits<5> rt;
+  bits<5> rd;
+  bits<3> sel;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rd;
+  let Inst{15-14} = 0;
+  let Inst{13-11} = sel;
+  let Inst{10-0} = funct;
+}
+
 class MFC1_FM_MM<bits<8> funct> : MMArch {
   bits<5> rt;
   bits<5> fs;
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index dff57a5d59dc1..a4fa5e73b24df 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -1051,6 +1051,11 @@ let DecoderNamespace = "MicroMips" in {
   def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>,
                  ISA_MICROMIPS;
 
+  def MFC0_MM : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>,
+                MFC0_FM_MM<0x0fc>, ISA_MICROMIPS32_NOT_MIPS32R6;
+  def MTC0_MM : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>,
+                MFC0_FM_MM<0x2fc>, ISA_MICROMIPS32_NOT_MIPS32R6;
+
   def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>,
                 ISA_MICROMIPS;
   def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>,
@@ -1287,6 +1292,12 @@ class UncondBranchMMPseudo<string opstr> :
 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
 
 let EncodingPredicates = [InMicroMips] in {
+  def : MipsInstAlias<"mfc0 $rt, $rd",
+                      (MFC0_MM GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>,
+        ISA_MICROMIPS32_NOT_MIPS32R6;
+  def : MipsInstAlias<"mtc0 $rt, $rd",
+                      (MTC0_MM COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>,
+        ISA_MICROMIPS32_NOT_MIPS32R6;
   def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
                                      0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
   def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
index d2526ee238f72..5ebe336b3443d 100644
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@ -446,8 +446,8 @@ def GenericWriteCOP0Short : SchedWriteRes<[GenericIssueCOP0]>;
 def : InstRW<[GenericWriteCOP0TLB], (instrs TLBP, TLBR, TLBWI, TLBWR)>;
 def : InstRW<[GenericWriteCOP0TLB], (instrs TLBINV, TLBINVF)>;
 
-def : InstRW<[GenericReadCOP0], (instrs MFC0)>;
-def : InstRW<[GenericWriteCOP0], (instrs MTC0)>;
+def : InstRW<[GenericReadCOP0], (instrs MFC0, MFC0_MM)>;
+def : InstRW<[GenericWriteCOP0], (instrs MTC0, MTC0_MM)>;
 
 def : InstRW<[GenericWriteCOP0], (instrs EVP, DVP)>;
 
diff --git a/llvm/test/MC/Mips/micromips-control-instructions.s b/llvm/test/MC/Mips/micromips-control-instructions.s
index e4946be5c34db..afa33395d4abe 100644
--- a/llvm/test/MC/Mips/micromips-control-instructions.s
+++ b/llvm/test/MC/Mips/micromips-control-instructions.s
@@ -51,6 +51,10 @@
 # CHECK-EL:    tlbwi                      # encoding: [0x00,0x00,0x7c,0x23]
 # CHECK-EL:    tlbwr                      # encoding: [0x00,0x00,0x7c,0x33]
 # CHECK-EL:    prefx 1, $3($5)            # encoding: [0x65,0x54,0xa0,0x09]
+# CHECK-EL:    mfc0 $2, $12, 0            # encoding: [0x4c,0x00,0xfc,0x00]
+# CHECK-EL:    mfc0 $3, $16, 7            # encoding: [0x70,0x00,0xfc,0x38]
+# CHECK-EL:    mtc0 $4, $12, 0            # encoding: [0x8c,0x00,0xfc,0x02]
+# CHECK-EL:    mtc0 $5, $16, 7            # encoding: [0xb0,0x00,0xfc,0x3a]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
@@ -85,6 +89,10 @@
 # CHECK-EB:   tlbwi                       # encoding: [0x00,0x00,0x23,0x7c]
 # CHECK-EB:   tlbwr                       # encoding: [0x00,0x00,0x33,0x7c]
 # CHECK-EB:   prefx 1, $3($5)             # encoding: [0x54,0x65,0x09,0xa0]
+# CHECK-EB:   mfc0 $2, $12, 0             # encoding: [0x00,0x4c,0x00,0xfc]
+# CHECK-EB:   mfc0 $3, $16, 7             # encoding: [0x00,0x70,0x38,0xfc]
+# CHECK-EB:   mtc0 $4, $12, 0             # encoding: [0x00,0x8c,0x02,0xfc]
+# CHECK-EB:   mtc0 $5, $16, 7             # encoding: [0x00,0xb0,0x3a,0xfc]
 
     sdbbp
     sdbbp 34
@@ -114,4 +122,7 @@
     tlbwi
     tlbwr
     prefx 1, $3($5)
-
+    mfc0 $2, $12
+    mfc0 $3, $16, 7
+    mtc0 $4, $12
+    mtc0 $5, $16, 7