[llvm] [Mips] Restrict microMIPS GP load folding to word loads (PR #228881)

[Jiaxun Yang via llvm-commits]

https://github.com/FlyGoat updated https://github.com/llvm/llvm-project/pull/228881

>From 00ae38553013938621c04f158eb0834326c80393 Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: Sun, 4 Oct 2026 12:23:42 +0100
Subject: [PATCH] [Mips] Restrict microMIPS GP load folding to word loads

Only LW has a GP-relative variant, so restrict the folding to LW_MM and
LW_MMR6.

Assisted-by: OpenAI Codex # Testcases
---
 llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 48163a54f4837..d2ef7003721e1 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -2135,7 +2135,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
   }
 
   if (inMicroMipsMode()) {
-    if (MCID.mayLoad() && Opcode != Mips::LWP_MM) {
+    if (Opcode == Mips::LW_MM || Opcode == Mips::LW_MMR6) {
       // Try to create 16-bit GP relative load instruction.
       for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
         const MCOperandInfo &OpInfo = MCID.operands()[i];
@@ -2159,7 +2159,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
           }
         }
       } // for
-    }   // if load
+    } // if load
 
     // TODO: Handle this with the AsmOperandClass.PredicateMethod.