[llvm] [Mips] Add microMIPS hazard-barrier jump encodings (PR #228885)
Jiaxun Yang via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 4 05:41:42 PDT 2026
https://github.com/FlyGoat created https://github.com/llvm/llvm-project/pull/228885
Add microMIPS encodings for jr.hb and jalr.hb. Use BaseOpcode and MMRel
to map the standard opcodes to their microMIPS encodings.
Assisted-by: OpenAI Codex # Testcases
Validation: `git diff --check` passes. Tests were not rerun for this cherry-pick.
>From 4a6ba8a05971a31b609572d1e9df12a65f71445b Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: Sun, 4 Oct 2026 12:23:43 +0100
Subject: [PATCH] [Mips] Add microMIPS hazard-barrier jump encodings
Add microMIPS encodings for jr.hb and jalr.hb. Use BaseOpcode and MMRel
to map the standard opcodes to their microMIPS encodings.
Assisted-by: OpenAI Codex # Testcases
---
llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 8 ++++++++
llvm/lib/Target/Mips/MipsInstrInfo.td | 12 +++++++-----
llvm/lib/Target/Mips/MipsScheduleGeneric.td | 4 ++--
.../MC/Mips/micromips-jump-instructions.s | 19 +++++++++++++++++++
4 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index dff57a5d59dc1..100d213af1b9b 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -938,6 +938,11 @@ let DecoderNamespace = "MicroMips" in {
def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>,
ISA_MICROMIPS32_NOT_MIPS32R6;
+ def JR_HB_MM : MMRel, JR_HB_DESC<GPR32Opnd>, JR_FM_MM<0x7c>,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
+ def JALR_HB_MM : MMRel, JALR_HB_DESC<GPR32Opnd>, JALR_FM_MM<0x07c>, MMArch,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
+
/// Jump Instructions - Short Delay Slot
def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>,
ISA_MICROMIPS32_NOT_MIPS32R6;
@@ -1393,6 +1398,9 @@ let EncodingPredicates = [InMicroMips] in {
def : MipsInstAlias<"bal $offset", (BGEZAL_MM ZERO, brtarget_mm:$offset), 1>,
ISA_MICROMIPS32_NOT_MIPS32R6;
+ def : MipsInstAlias<"jalr.hb $rs", (JALR_HB_MM RA, GPR32Opnd:$rs), 0>,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
+
def : MipsInstAlias<"j $rs", (JR_MM GPR32Opnd:$rs), 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
}
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 3b523af856d1c..73824b28340e4 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -2516,7 +2516,8 @@ class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
}
class JR_HB_DESC<RegisterOperand RO> :
- InstSE<(outs), (ins), "", [], FrmJ>, JR_HB_DESC_BASE<"jr.hb", RO> {
+ InstSE<(outs), (ins), "", [], FrmJ, "jr.hb">,
+ JR_HB_DESC_BASE<"jr.hb", RO> {
let isBranch=1;
let isIndirectBranch=1;
let hasDelaySlot=1;
@@ -2526,8 +2527,8 @@ class JR_HB_DESC<RegisterOperand RO> :
}
class JALR_HB_DESC<RegisterOperand RO> :
- InstSE<(outs), (ins), "", [], FrmJ>, JALR_HB_DESC_BASE<"jalr.hb",
- RO> {
+ InstSE<(outs), (ins), "", [], FrmJ, "jalr.hb">,
+ JALR_HB_DESC_BASE<"jalr.hb", RO> {
let isIndirectBranch=1;
let hasDelaySlot=1;
bit isCTI = 1;
@@ -2536,8 +2537,9 @@ class JALR_HB_DESC<RegisterOperand RO> :
class JR_HB_ENC : JR_HB_FM<8>;
class JALR_HB_ENC : JALR_HB_FM<9>;
-def JR_HB : JR_HB_DESC<GPR32Opnd>, JR_HB_ENC, ISA_MIPS32R2_NOT_32R6_64R6;
-def JALR_HB : JALR_HB_DESC<GPR32Opnd>, JALR_HB_ENC, ISA_MIPS32;
+def JR_HB : MMRel, JR_HB_DESC<GPR32Opnd>, JR_HB_ENC,
+ ISA_MIPS32R2_NOT_32R6_64R6;
+def JALR_HB : MMRel, JALR_HB_DESC<GPR32Opnd>, JALR_HB_ENC, ISA_MIPS32;
let AdditionalPredicates = [NotInMicroMips, UseIndirectJumpsHazard] in
def JALRHBPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR_HB, RA>;
diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
index d2526ee238f72..81d7d4a7646c3 100644
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@ -285,7 +285,7 @@ def GenericWriteJumpAndLink : SchedWriteRes<[GenericIssueCTISTD]> {
// jalr, jr.hb, jr, jalr.hb, jarlc, jialc
def : InstRW<[GenericWriteJump], (instrs B, BAL, BAL_BR, BEQ, BNE, BGTZ, BGEZ,
BLEZ, BLTZ, BLTZAL, J, JALX, JR, JR_HB, ERET,
- ERet, ERETNC, DERET, NAL)>;
+ ERet, ERETNC, DERET, NAL, JR_HB_MM)>;
def : InstRW<[GenericWriteJump], (instrs BEQL, BNEL, BGEZL, BGTZL, BLEZL,
BLTZL)>;
@@ -296,7 +296,7 @@ def : InstRW<[GenericWriteJump], (instrs TAILCALL, TAILCALLREG,
RetRA)>;
def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZAL, JAL, JALR, JALR_HB,
- JALRHBPseudo, JALRPseudo)>;
+ JALRHBPseudo, JALRPseudo, JALR_HB_MM)>;
def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZALL, BLTZALL)>;
diff --git a/llvm/test/MC/Mips/micromips-jump-instructions.s b/llvm/test/MC/Mips/micromips-jump-instructions.s
index f8d4974de6cd3..ac0c9ee6ab816 100644
--- a/llvm/test/MC/Mips/micromips-jump-instructions.s
+++ b/llvm/test/MC/Mips/micromips-jump-instructions.s
@@ -1,3 +1,5 @@
+# RUN: llvm-mc -triple=mipsel -mcpu=mips32r2 -mattr=+micromips -filetype=obj %s | llvm-objdump -d --mattr=+micromips - | FileCheck %s --check-prefix=DIS
+# RUN: llvm-mc -triple=mips -mcpu=mips32r2 -mattr=+micromips -filetype=obj %s | llvm-objdump -d --mattr=+micromips - | FileCheck %s --check-prefix=DIS
# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
# RUN: | FileCheck %s -check-prefix=CHECK-EL
# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
@@ -63,3 +65,20 @@
jalrs $ra, $6
jal $25
jal $4, $25
+
+.set noreorder
+jr.hb $3
+# CHECK-EL: jr.hb $3 # encoding: [0x03,0x00,0x3c,0x1f]
+# CHECK-EB: jr.hb $3 # encoding: [0x00,0x03,0x1f,0x3c]
+# DIS: jr.hb $3
+nop
+jalr.hb $6, $7
+# CHECK-EL: jalr.hb $6, $7 # encoding: [0xc7,0x00,0x3c,0x1f]
+# CHECK-EB: jalr.hb $6, $7 # encoding: [0x00,0xc7,0x1f,0x3c]
+# DIS: jalr.hb $6, $7
+nop
+jalr.hb $8
+# CHECK-EL: jalr.hb $ra, $8 # encoding: [0xe8,0x03,0x3c,0x1f]
+# CHECK-EB: jalr.hb $ra, $8 # encoding: [0x03,0xe8,0x1f,0x3c]
+# DIS: jalr.hb $ra, $8
+nop
More information about the llvm-commits
mailing list