[llvm] CodeGen: Run LiveIntervals before PHIElimination and drop LiveVariables from it (PR #228618)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 4 00:39:29 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/228618
>From e9d4ced47bf538ce0e237b55108e1874f15c31d5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 8 Sep 2026 23:37:53 +0200
Subject: [PATCH] CodeGen: Run LiveIntervals before PHIElimination and drop
LiveVariables from it
Move LiveIntervals to run before PHIElimination in the optimized register
allocation pipeline, and make PHIElimination maintain LiveIntervals only.
This removes the last explicit use of LiveVariables. The actual analysis is no
longer used. There are implicit dependencies on the side effects of running the
analysis due to adjustments of dead flags, so further work is still needed to
complete the removal.
This perturbs register allocation in a number of tests. The same codegen result
can be achieved by not preserving the analysis and recomputing fresh. Greedy is
just sensitive to the exact slot index and value numbering with identical MIR.
Measured across every affected test the emitted instruction count goes from
145124 to 145196, +0.050%, with changes in both directions. The largest
regression is AArch64/phi.ll, where the GlobalISel output gains about 30
instructions and no longer matches the SelectionDAG output; the largest
improvements are ARM/fpclamptosat.ll and PowerPC/common-chain.ll.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
---
llvm/lib/CodeGen/PHIElimination.cpp | 249 +-
llvm/lib/CodeGen/TargetPassConfig.cpp | 9 +-
llvm/lib/Passes/CodeGenPassBuilder.cpp | 11 +-
llvm/test/CodeGen/AArch64/O3-pipeline.ll | 2 +-
.../AArch64/PHIElimination-debugloc.mir | 2 +-
.../AArch64/atomic-ops-not-barriers.ll | 3 +-
llvm/test/CodeGen/AArch64/call-rv-marker.ll | 9 +-
llvm/test/CodeGen/AArch64/div-i256.ll | 484 +--
llvm/test/CodeGen/AArch64/phi.ll | 662 ++--
llvm/test/CodeGen/AArch64/pr164181.ll | 132 +-
.../AArch64/ragreedy-local-interval-cost.ll | 170 +-
llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 4 +-
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll | 159 +-
.../CodeGen/AMDGPU/phi-elim-mli-available.mir | 29 +-
.../AMDGPU/phi-elimination-assertion.mir | 10 +-
.../CodeGen/AMDGPU/phi-elimination-end-cf.mir | 6 +-
.../waterfall-loop-exec-update-terminator.mir | 12 +-
llvm/test/CodeGen/ARM/O3-pipeline.ll | 4 +-
.../ARM/ParallelDSP/multi-use-loads.ll | 75 +-
llvm/test/CodeGen/ARM/aes-erratum-fix.ll | 170 +-
llvm/test/CodeGen/ARM/code-placement.ll | 7 +-
llvm/test/CodeGen/ARM/fp16-promote.ll | 43 +-
llvm/test/CodeGen/ARM/fpclamptosat.ll | 138 +-
llvm/test/CodeGen/ARM/fptoi-sat-store.ll | 12 +-
llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll | 36 +-
llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll | 212 +-
llvm/test/CodeGen/ARM/sat-to-bitop.ll | 24 +-
llvm/test/CodeGen/BPF/jump_table_blockaddr.ll | 8 +-
llvm/test/CodeGen/BPF/sockex2.ll | 2 +-
llvm/test/CodeGen/Hexagon/rdf-copy.ll | 2 +-
.../test/CodeGen/Hexagon/swp-matmul-bitext.ll | 2 +-
llvm/test/CodeGen/LoongArch/opt-pipeline.ll | 2 +-
.../test/CodeGen/NVPTX/switch-loop-header.mir | 2 +-
.../CodeGen/PowerPC/2013-07-01-PHIElimBug.mir | 16 +-
llvm/test/CodeGen/PowerPC/O3-pipeline.ll | 4 +-
llvm/test/CodeGen/PowerPC/all-atomics.ll | 70 +-
.../PowerPC/atomicrmw-cond-sub-clamp.ll | 24 +-
.../PowerPC/atomicrmw-uinc-udec-wrap.ll | 24 +-
llvm/test/CodeGen/PowerPC/common-chain.ll | 165 +-
llvm/test/CodeGen/PowerPC/csr-split.ll | 40 +-
llvm/test/CodeGen/PowerPC/livevars-crash1.mir | 99 +-
llvm/test/CodeGen/PowerPC/livevars-crash2.mir | 153 +-
llvm/test/CodeGen/PowerPC/phi-eliminate.mir | 167 +-
llvm/test/CodeGen/PowerPC/prefer-dqform.ll | 138 +-
llvm/test/CodeGen/PowerPC/shrink-wrap.ll | 6 +-
.../umulo-128-legalisation-lowering.ll | 62 +-
.../RISCV/GlobalISel/double-intrinsics.ll | 76 +-
.../CodeGen/RISCV/GlobalISel/rotl-rotr.ll | 162 +-
.../CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll | 18 +-
llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll | 14 +-
llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll | 118 +-
...lar-shift-by-byte-multiple-legalization.ll | 3098 +++++++++--------
llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll | 2 +-
llvm/test/CodeGen/RISCV/O3-pipeline.ll | 2 +-
llvm/test/CodeGen/RISCV/abdu-neg.ll | 300 +-
llvm/test/CodeGen/RISCV/abdu.ll | 580 +--
llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll | 375 +-
llvm/test/CodeGen/RISCV/fpclamptosat.ll | 332 +-
llvm/test/CodeGen/RISCV/idiv_large.ll | 782 ++---
llvm/test/CodeGen/RISCV/machine-pipeliner.ll | 26 +-
.../RISCV/rv64m-w-insts-legalization.ll | 20 +-
llvm/test/CodeGen/RISCV/rv64xtheadbb.ll | 14 +-
llvm/test/CodeGen/RISCV/rv64zbb.ll | 14 +-
.../RISCV/rvv/dont-sink-splat-operands.ll | 44 +-
.../fixed-vector-convert-from-arbitrary-fp.ll | 50 +-
.../RISCV/rvv/fixed-vectors-masked-gather.ll | 424 +--
.../CodeGen/RISCV/rvv/fpclamptosat_vec.ll | 280 +-
.../CodeGen/RISCV/rvv/sink-splat-operands.ll | 180 +-
.../RISCV/rvv/vector-extract-last-active.ll | 20 +-
llvm/test/CodeGen/RISCV/rvv/vpload.ll | 30 +-
llvm/test/CodeGen/RISCV/smulh.ll | 156 +-
.../CodeGen/RISCV/zicond-fp-select-zfinx.ll | 10 +-
.../SPARC/umulo-128-legalisation-lowering.ll | 42 +-
.../SystemZ/fp-half-vector-fcmp-select.ll | 14 +-
llvm/test/CodeGen/Thumb/scmp.ll | 60 +-
llvm/test/CodeGen/Thumb/ucmp.ll | 60 +-
llvm/test/CodeGen/Thumb/umul_fix_sat.ll | 55 +-
.../cond-vector-reduce-mve-codegen.ll | 46 +-
.../Thumb2/LowOverheadLoops/reductions.ll | 96 +-
.../varying-outer-2d-reduction.ll | 28 +-
.../LowOverheadLoops/vector-arith-codegen.ll | 12 +-
.../Thumb2/LowOverheadLoops/while-loops.ll | 67 +-
.../CodeGen/Thumb2/aligned-nonfallthrough.ll | 12 +-
.../CodeGen/Thumb2/mve-float16regloops.ll | 76 +-
.../CodeGen/Thumb2/mve-float32regloops.ll | 191 +-
.../CodeGen/Thumb2/mve-gather-increment.ll | 143 +-
llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll | 88 +-
llvm/test/CodeGen/Thumb2/mve-phireg.ll | 24 +-
llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll | 35 +-
llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll | 106 +-
llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 113 +-
.../CodeGen/Thumb2/mve-vecreduce-loops.ll | 85 +-
llvm/test/CodeGen/VE/Scalar/atomic.ll | 66 +-
.../CodeGen/X86/2007-11-30-LoadFolding-Bug.ll | 10 +-
llvm/test/CodeGen/X86/apx/push2-pop2.ll | 193 +-
llvm/test/CodeGen/X86/atom-fixup-lea2.ll | 2 +-
llvm/test/CodeGen/X86/block-placement.ll | 2 +-
.../CodeGen/X86/branchfolding-debugloc.ll | 2 +-
llvm/test/CodeGen/X86/bsf.ll | 86 +-
llvm/test/CodeGen/X86/bsr.ll | 36 +-
llvm/test/CodeGen/X86/call-rv-marker.ll | 9 +-
.../CodeGen/X86/callbr-asm-branch-folding.ll | 5 +-
.../callbr-asm-different-indirect-target.mir | 4 +-
llvm/test/CodeGen/X86/callbr-asm-kill.mir | 6 +-
...alescer-copy-from-erasable-implicit-def.ll | 8 +-
.../X86/codegen-prepare-addrmode-tls.ll | 12 +-
.../X86/div-rem-pair-recomposition-signed.ll | 356 +-
.../div-rem-pair-recomposition-unsigned.ll | 124 +-
llvm/test/CodeGen/X86/extract-bits.ll | 28 +-
llvm/test/CodeGen/X86/extract-lowbits.ll | 136 +-
llvm/test/CodeGen/X86/fp-intrinsics.ll | 10 +-
.../X86/fp-strict-scalar-fptoint-fp16.ll | 10 +-
.../CodeGen/X86/fp-strict-scalar-fptoint.ll | 20 +-
llvm/test/CodeGen/X86/fptoui-sat-scalar.ll | 72 +-
llvm/test/CodeGen/X86/fshl.ll | 53 +-
llvm/test/CodeGen/X86/fshr.ll | 71 +-
llvm/test/CodeGen/X86/gpr-to-mask.ll | 12 +-
llvm/test/CodeGen/X86/i128-udiv.ll | 2043 +++++------
llvm/test/CodeGen/X86/lea-opt-cse4.ll | 16 +-
llvm/test/CodeGen/X86/legalize-shift-64.ll | 16 +-
llvm/test/CodeGen/X86/llc-pipeline-npm.ll | 4 +-
.../test/CodeGen/X86/masked_gather_scatter.ll | 30 +-
llvm/test/CodeGen/X86/opt-pipeline.ll | 2 +-
.../CodeGen/X86/phi-elim-undef-livevars.mir | 4 +-
llvm/test/CodeGen/X86/phielim-undef.mir | 10 +-
llvm/test/CodeGen/X86/pr38539.ll | 20 +-
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 22 +-
.../CodeGen/X86/vec-strict-fptoint-128.ll | 70 +-
.../CodeGen/X86/vec-strict-fptoint-256.ll | 44 +-
.../X86/vector-constrained-fp-intrinsics.ll | 128 +-
llvm/test/CodeGen/X86/x86-cmov-converter.ll | 18 +-
.../AArch64/postidx-load.ll | 13 +-
132 files changed, 7997 insertions(+), 7916 deletions(-)
diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp
index 2a3d7dfc6e341..1612a810692db 100644
--- a/llvm/lib/CodeGen/PHIElimination.cpp
+++ b/llvm/lib/CodeGen/PHIElimination.cpp
@@ -21,7 +21,6 @@
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervals.h"
-#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
@@ -74,7 +73,6 @@ namespace {
class PHIEliminationImpl {
MachineRegisterInfo *MRI = nullptr; // Machine register information
- LiveVariables *LV = nullptr;
SlotIndexes *SI = nullptr;
LiveIntervals *LIS = nullptr;
MachineLoopInfo *MLI = nullptr;
@@ -100,12 +98,8 @@ class PHIEliminationImpl {
/// Split critical edges where necessary for good coalescer performance.
bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
- MachineLoopInfo *MLI,
- std::vector<SparseBitVector<>> *LiveInSets,
- MachineDomTreeUpdater &MDTU);
+ MachineLoopInfo *MLI, MachineDomTreeUpdater &MDTU);
- // These functions are temporary abstractions around LiveVariables and
- // LiveIntervals, so they can go away when LiveVariables does.
bool isLiveIn(Register Reg, const MachineBasicBlock *MBB);
bool isLiveOutPastPHIs(Register Reg, const MachineBasicBlock *MBB);
@@ -132,7 +126,6 @@ class PHIEliminationImpl {
public:
PHIEliminationImpl(MachineFunctionPass *P) : P(P) {
- auto *LVWrapper = P->getAnalysisIfAvailable<LiveVariablesWrapperPass>();
auto *SIWrapper = P->getAnalysisIfAvailable<SlotIndexesWrapperPass>();
auto *LISWrapper = P->getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
auto *MLIWrapper = P->getAnalysisIfAvailable<MachineLoopInfoWrapperPass>();
@@ -145,7 +138,6 @@ class PHIEliminationImpl {
auto *MBFIWrapper =
P->getAnalysisIfAvailable<MachineBlockFrequencyInfoWrapperPass>();
- LV = LVWrapper ? &LVWrapper->getLV() : nullptr;
SI = SIWrapper ? &SIWrapper->getSI() : nullptr;
LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr;
@@ -156,8 +148,7 @@ class PHIEliminationImpl {
}
PHIEliminationImpl(MachineFunction &MF, MachineFunctionAnalysisManager &AM)
- : LV(AM.getCachedResult<LiveVariablesAnalysis>(MF)),
- SI(AM.getCachedResult<SlotIndexesAnalysis>(MF)),
+ : SI(AM.getCachedResult<SlotIndexesAnalysis>(MF)),
LIS(AM.getCachedResult<LiveIntervalsAnalysis>(MF)),
MLI(AM.getCachedResult<MachineLoopAnalysis>(MF)),
MDT(AM.getCachedResult<MachineDominatorTreeAnalysis>(MF)),
@@ -198,7 +189,6 @@ PHIEliminationPass::run(MachineFunction &MF,
return PreservedAnalyses::all();
auto PA = getMachineFunctionPassPreservedAnalyses();
PA.preserve<LiveIntervalsAnalysis>();
- PA.preserve<LiveVariablesAnalysis>();
PA.preserve<SlotIndexesAnalysis>();
PA.preserve<MachineDominatorTreeAnalysis>();
PA.preserve<MachinePostDominatorTreeAnalysis>();
@@ -218,16 +208,17 @@ char &llvm::PHIEliminationID = PHIElimination::ID;
INITIALIZE_PASS_BEGIN(PHIElimination, DEBUG_TYPE,
"Eliminate PHI nodes for register allocation", false,
false)
-INITIALIZE_PASS_DEPENDENCY(LiveVariablesWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfoWrapperPass)
INITIALIZE_PASS_END(PHIElimination, DEBUG_TYPE,
"Eliminate PHI nodes for register allocation", false, false)
void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
- AU.addUsedIfAvailable<LiveVariablesWrapperPass>();
+ AU.addUsedIfAvailable<SlotIndexesWrapperPass>();
+ AU.addUsedIfAvailable<LiveIntervalsWrapperPass>();
AU.addUsedIfAvailable<MachineLoopInfoWrapperPass>();
- AU.addPreserved<LiveVariablesWrapperPass>();
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addPreserved<MachineDominatorTreeWrapperPass>();
@@ -247,46 +238,16 @@ bool PHIEliminationImpl::run(MachineFunction &MF) {
bool Changed = false;
// Split critical edges to help the coalescer.
- if (!DisableEdgeSplitting && (LV || LIS)) {
- // A set of live-in regs for each MBB which is used to update LV
- // efficiently also with large functions.
- std::vector<SparseBitVector<>> LiveInSets;
- if (LV) {
- LiveInSets.resize(MF.size());
- for (unsigned Index = 0, e = MRI->getNumVirtRegs(); Index != e; ++Index) {
- // Set the bit for this register for each MBB where it is
- // live-through or live-in (killed).
- Register VirtReg = Register::index2VirtReg(Index);
- MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
- if (!DefMI)
- continue;
- LiveVariables::VarInfo &VI = LV->getVarInfo(VirtReg);
- SparseBitVector<>::iterator AliveBlockItr = VI.AliveBlocks.begin();
- SparseBitVector<>::iterator EndItr = VI.AliveBlocks.end();
- while (AliveBlockItr != EndItr) {
- unsigned BlockNum = *(AliveBlockItr++);
- LiveInSets[BlockNum].set(Index);
- }
- // The register is live into an MBB in which it is killed but not
- // defined. See comment for VarInfo in LiveVariables.h.
- MachineBasicBlock *DefMBB = DefMI->getParent();
- if (VI.Kills.size() > 1 ||
- (!VI.Kills.empty() && VI.Kills.front()->getParent() != DefMBB))
- for (auto *MI : VI.Kills)
- LiveInSets[MI->getParent()->getNumber()].set(Index);
- }
- }
-
+ if (!DisableEdgeSplitting && LIS) {
for (auto &MBB : MF)
- Changed |=
- SplitPHIEdges(MF, MBB, MLI, (LV ? &LiveInSets : nullptr), MDTU);
+ Changed |= SplitPHIEdges(MF, MBB, MLI, MDTU);
}
// This pass takes the function out of SSA form.
MRI->leaveSSA();
// Populate VRegPHIUseCount
- if (LV || LIS)
+ if (LIS)
analyzePHINodes(MF);
// Eliminate PHI instructions by inserting copies into predecessor blocks.
@@ -394,7 +355,6 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
Register DestReg = MPhi->getOperand(0).getReg();
assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
- bool isDead = MPhi->getOperand(0).isDead();
// Create a new register for the incoming PHI arguments.
MachineFunction &MF = *MBB.getParent();
@@ -451,62 +411,6 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
(void)Res;
}
- // Update live variable information if there is any.
- if (LV) {
- if (IncomingReg) {
- LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
-
- MachineInstr *OldKill = nullptr;
- bool IsPHICopyAfterOldKill = false;
-
- if (reusedIncoming && (OldKill = VI.findKill(&MBB))) {
- // Calculate whether the PHICopy is after the OldKill.
- // In general, the PHICopy is inserted as the first non-phi instruction
- // by default, so it's before the OldKill. But some Target hooks for
- // createPHIDestinationCopy() may modify the default insert position of
- // PHICopy.
- for (auto I = MBB.SkipPHIsAndLabels(MBB.begin()), E = MBB.end(); I != E;
- ++I) {
- if (I == PHICopy)
- break;
-
- if (I == OldKill) {
- IsPHICopyAfterOldKill = true;
- break;
- }
- }
- }
-
- // When we are reusing the incoming register and it has been marked killed
- // by OldKill, if the PHICopy is after the OldKill, we should remove the
- // killed flag from OldKill.
- if (IsPHICopyAfterOldKill) {
- LLVM_DEBUG(dbgs() << "Remove old kill from " << *OldKill);
- LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
- LLVM_DEBUG(MBB.dump());
- }
-
- // Add information to LiveVariables to know that the first used incoming
- // value or the resued incoming value whose PHICopy is after the OldKIll
- // is killed. Note that because the value is defined in several places
- // (once each for each incoming block), the "def" block and instruction
- // fields for the VarInfo is not filled in.
- if (!OldKill || IsPHICopyAfterOldKill)
- LV->addVirtualRegisterKilled(IncomingReg, *PHICopy);
- }
-
- // Since we are going to be deleting the PHI node, if it is the last use of
- // any registers, or if the value itself is dead, we need to move this
- // information over to the new copy we just inserted.
- LV->removeVirtualRegistersKilled(*MPhi);
-
- // If the result is dead, update LV.
- if (isDead) {
- LV->addVirtualRegisterDead(DestReg, *PHICopy);
- LV->removeVirtualRegisterDead(DestReg, *MPhi);
- }
- }
-
// Update LiveIntervals for the new copy or implicit def.
SlotIndex DestCopyIndex;
if (SI)
@@ -579,7 +483,7 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
}
// Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
- if (LV || LIS) {
+ if (LIS) {
for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
if (!MPhi->getOperand(i).isUndef()) {
--VRegPHIUseCount[BBVRegPair(
@@ -621,12 +525,15 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
"Expected a single use from UnspillableTerminator");
SrcRegDef->getOperand(0).setReg(IncomingReg);
- // Update LiveVariables.
- if (LV) {
- LiveVariables::VarInfo &SrcVI = LV->getVarInfo(SrcReg);
- LiveVariables::VarInfo &IncomingVI = LV->getVarInfo(IncomingReg);
- IncomingVI.AliveBlocks = std::move(SrcVI.AliveBlocks);
- SrcVI.AliveBlocks.clear();
+ if (LIS) {
+ LiveInterval &SrcLI = LIS->getInterval(SrcReg);
+ SlotIndex DefIdx = LIS->getInstructionIndex(*SrcRegDef).getRegSlot();
+ LiveInterval &IncomingLI = LIS->getOrCreateEmptyInterval(IncomingReg);
+ VNInfo *VNI =
+ IncomingLI.getNextValue(DefIdx, LIS->getVNInfoAllocator());
+ for (const LiveInterval::Segment &S : SrcLI)
+ IncomingLI.addSegment(LiveInterval::Segment(S.start, S.end, VNI));
+ LIS->removeInterval(SrcReg);
}
continue;
@@ -660,72 +567,6 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
}
}
- // We only need to update the LiveVariables kill of SrcReg if this was the
- // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
- // out of the predecessor. We can also ignore undef sources.
- if (LV && !SrcUndef &&
- !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
- !LV->isLiveOut(SrcReg, opBlock)) {
- // We want to be able to insert a kill of the register if this PHI (aka,
- // the copy we just inserted) is the last use of the source value. Live
- // variable analysis conservatively handles this by saying that the value
- // is live until the end of the block the PHI entry lives in. If the value
- // really is dead at the PHI copy, there will be no successor blocks which
- // have the value live-in.
-
- // Okay, if we now know that the value is not live out of the block, we
- // can add a kill marker in this block saying that it kills the incoming
- // value!
-
- // In our final twist, we have to decide which instruction kills the
- // register. In most cases this is the copy, however, terminator
- // instructions at the end of the block may also use the value. In this
- // case, we should mark the last such terminator as being the killing
- // block, not the copy.
- MachineBasicBlock::iterator KillInst = opBlock.end();
- for (MachineBasicBlock::iterator Term = InsertPos; Term != opBlock.end();
- ++Term) {
- if (Term->readsRegister(SrcReg, /*TRI=*/nullptr))
- KillInst = Term;
- }
-
- if (KillInst == opBlock.end()) {
- // No terminator uses the register.
-
- if (reusedIncoming || !IncomingReg) {
- // We may have to rewind a bit if we didn't insert a copy this time.
- KillInst = InsertPos;
- while (KillInst != opBlock.begin()) {
- --KillInst;
- if (KillInst->isDebugInstr())
- continue;
- if (KillInst->readsRegister(SrcReg, /*TRI=*/nullptr))
- break;
- }
- } else {
- // We just inserted this copy.
- KillInst = NewSrcInstr;
- }
- }
- assert(KillInst->readsRegister(SrcReg, /*TRI=*/nullptr) &&
- "Cannot find kill instruction");
-
- // Finally, mark it killed.
- LV->addVirtualRegisterKilled(SrcReg, *KillInst);
-
- // This vreg no longer lives all of the way through opBlock.
- unsigned opBlockNum = opBlock.getNumber();
- LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
- } else if (LV && SrcUndef &&
- !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
- !LV->isLiveOut(SrcReg, opBlock)) {
- // For undef sources we don't need a kill marker, but the register may
- // no longer be live through intermediate blocks after the PHI use is
- // removed. Recompute its LiveVariables info to clear stale AliveBlocks.
- if (MRI->getVRegDef(SrcReg))
- LV->recomputeForSingleDefVirtReg(SrcReg);
- }
-
if (SI && NewSrcInstr)
SI->insertMachineInstrInMaps(*NewSrcInstr);
@@ -820,9 +661,10 @@ void PHIEliminationImpl::analyzePHINodes(const MachineFunction &MF) {
}
}
-bool PHIEliminationImpl::SplitPHIEdges(
- MachineFunction &MF, MachineBasicBlock &MBB, MachineLoopInfo *MLI,
- std::vector<SparseBitVector<>> *LiveInSets, MachineDomTreeUpdater &MDTU) {
+bool PHIEliminationImpl::SplitPHIEdges(MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineLoopInfo *MLI,
+ MachineDomTreeUpdater &MDTU) {
if (MBB.empty() || !MBB.front().isPHI() || MBB.isEHPad())
return false; // Quick exit for basic blocks without PHIs.
@@ -847,10 +689,10 @@ bool PHIEliminationImpl::SplitPHIEdges(
if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
continue;
- // LV doesn't consider a phi use live-out, so isLiveOut only returns true
- // when the source register is live-out for some other reason than a phi
- // use. That means the copy we will insert in PreMBB won't be a kill, and
- // there is a risk it may not be coalesced away.
+ // isLiveOutPastPHIs only returns true when the source register is
+ // live-out for some other reason than a phi use. That means the copy we
+ // will insert in PreMBB won't be a kill, and there is a risk it may not
+ // be coalesced away.
//
// If the copy would be a kill, there is no need to split the edge.
bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
@@ -891,9 +733,9 @@ bool PHIEliminationImpl::SplitPHIEdges(
continue;
MachineBasicBlock *NewBB;
if (P)
- NewBB = PreMBB->SplitCriticalEdge(&MBB, *P, LiveInSets, &MDTU);
+ NewBB = PreMBB->SplitCriticalEdge(&MBB, *P, nullptr, &MDTU);
else
- NewBB = PreMBB->SplitCriticalEdge(&MBB, *MFAM, LiveInSets, &MDTU);
+ NewBB = PreMBB->SplitCriticalEdge(&MBB, *MFAM, nullptr, &MDTU);
if (!NewBB) {
LLVM_DEBUG(dbgs() << "Failed to split critical edge.\n");
continue;
@@ -913,30 +755,19 @@ bool PHIEliminationImpl::SplitPHIEdges(
}
bool PHIEliminationImpl::isLiveIn(Register Reg, const MachineBasicBlock *MBB) {
- assert((LV || LIS) &&
- "isLiveIn() requires either LiveVariables or LiveIntervals");
- if (LIS)
- return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
- else
- return LV->isLiveIn(Reg, *MBB);
+ assert(LIS && "isLiveIn() requires LiveIntervals");
+ return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
}
bool PHIEliminationImpl::isLiveOutPastPHIs(Register Reg,
const MachineBasicBlock *MBB) {
- assert((LV || LIS) &&
- "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
- // LiveVariables considers uses in PHIs to be in the predecessor basic block,
- // so that a register used only in a PHI is not live out of the block. In
- // contrast, LiveIntervals considers uses in PHIs to be on the edge rather
- // than in the predecessor basic block, so that a register used only in a PHI
- // is live out of the block.
- if (LIS) {
- const LiveInterval &LI = LIS->getInterval(Reg);
- for (const MachineBasicBlock *SI : MBB->successors())
- if (LI.liveAt(LIS->getMBBStartIdx(SI)))
- return true;
- return false;
- } else {
- return LV->isLiveOut(Reg, *MBB);
- }
+ assert(LIS && "isLiveOutPastPHIs() requires LiveIntervals");
+ // LiveIntervals considers uses in PHIs to be on the edge rather than in the
+ // predecessor basic block, so that a register used only in a PHI is live out
+ // of the block.
+ const LiveInterval &LI = LIS->getInterval(Reg);
+ for (const MachineBasicBlock *SI : MBB->successors())
+ if (LI.liveAt(LIS->getMBBStartIdx(SI)))
+ return true;
+ return false;
}
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 9683d988e8084..a09ef03fc4918 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -1504,16 +1504,15 @@ void TargetPassConfig::addOptimizedRegAlloc() {
addPass(&UnreachableMachineBlockElimID);
addPass(&LiveVariablesID);
- // Edge splitting is smarter with machine loop info.
- addPass(&MachineLoopInfoID);
- addPass(&PHIEliminationID);
-
// LiveIntervals is computed unconditionally before TwoAddressInstruction so
// that pass can rely on it instead of LiveVariables. This is a step toward
// removing LiveVariables entirely.
- // FIXME: Eventually, we want to run LiveIntervals before PHI elimination.
addPass(&LiveIntervalsID);
+ // Edge splitting is smarter with machine loop info.
+ addPass(&MachineLoopInfoID);
+ addPass(&PHIEliminationID);
+
addPass(&TwoAddressInstructionPassID);
addPass(&RegisterCoalescerID);
diff --git a/llvm/lib/Passes/CodeGenPassBuilder.cpp b/llvm/lib/Passes/CodeGenPassBuilder.cpp
index d5418c54b6ac4..0eba4e74ade30 100644
--- a/llvm/lib/Passes/CodeGenPassBuilder.cpp
+++ b/llvm/lib/Passes/CodeGenPassBuilder.cpp
@@ -870,18 +870,17 @@ Error CodeGenPassBuilder::addOptimizedRegAlloc(PassManagerWrapper &PMW) {
addMachineFunctionPass(
RequireAnalysisPass<LiveVariablesAnalysis, MachineFunction>(), PMW);
- // Edge splitting is smarter with machine loop info.
- addMachineFunctionPass(
- RequireAnalysisPass<MachineLoopAnalysis, MachineFunction>(), PMW);
- addMachineFunctionPass(PHIEliminationPass(), PMW);
-
// LiveIntervals is computed unconditionally before TwoAddressInstruction so
// that pass can rely on it instead of LiveVariables. This is a step toward
// removing LiveVariables entirely.
- // FIXME: Eventually, we want to run LiveIntervals before PHI elimination.
addMachineFunctionPass(
RequireAnalysisPass<LiveIntervalsAnalysis, MachineFunction>(), PMW);
+ // Edge splitting is smarter with machine loop info.
+ addMachineFunctionPass(
+ RequireAnalysisPass<MachineLoopAnalysis, MachineFunction>(), PMW);
+ addMachineFunctionPass(PHIEliminationPass(), PMW);
+
addMachineFunctionPass(TwoAddressInstructionPass(), PMW);
addMachineFunctionPass(RegisterCoalescerPass(), PMW);
diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
index bdf5d4177baea..9a2f7b18e23f1 100644
--- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -181,9 +181,9 @@
; CHECK-NEXT: Process Implicit Definitions
; CHECK-NEXT: Remove unreachable machine basic blocks
; CHECK-NEXT: Live Variable Analysis
-; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
+; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
diff --git a/llvm/test/CodeGen/AArch64/PHIElimination-debugloc.mir b/llvm/test/CodeGen/AArch64/PHIElimination-debugloc.mir
index 01c44e3f253bb..a5130eac1dfd0 100644
--- a/llvm/test/CodeGen/AArch64/PHIElimination-debugloc.mir
+++ b/llvm/test/CodeGen/AArch64/PHIElimination-debugloc.mir
@@ -37,7 +37,7 @@ body: |
bb.1:
%x:gpr32 = COPY $wzr
; Test that the debug location is not copied into bb1!
- ; CHECK: %3:gpr32 = COPY killed %x{{$}}
+ ; CHECK: %3:gpr32 = COPY %x{{$}}
; CHECK-LABEL: bb.2:
bb.2:
%y:gpr32 = PHI %x:gpr32, %bb.1, undef %undef:gpr32, %bb.0, debug-location !14
diff --git a/llvm/test/CodeGen/AArch64/atomic-ops-not-barriers.ll b/llvm/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
index b45d5246ddbf0..6cfc513c513fe 100644
--- a/llvm/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
+++ b/llvm/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
@@ -21,7 +21,8 @@ atomic_ver:
; The key point here is that the second dmb isn't immediately followed by the
; simple_ver basic block, which LLVM attempted to do when DMB had been marked
; with isBarrier. For now, look for something that looks like "somewhere".
-; CHECK-NEXT: ret
+; CHECK-NOT: %simple_ver
+; CHECK: ret
somewhere:
%combined = phi i32 [ %val, %atomic_ver ], [ %newval, %simple_ver]
ret i32 %combined
diff --git a/llvm/test/CodeGen/AArch64/call-rv-marker.ll b/llvm/test/CodeGen/AArch64/call-rv-marker.ll
index fa291e6c7cd74..a2a9138f57f9a 100644
--- a/llvm/test/CodeGen/AArch64/call-rv-marker.ll
+++ b/llvm/test/CodeGen/AArch64/call-rv-marker.ll
@@ -260,17 +260,18 @@ define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
; CHECK-SD-NEXT: ret
; CHECK-SD-NEXT: LBB4_3: ; %lpad1
; CHECK-SD-NEXT: Ltmp8: ; EH_LABEL
-; CHECK-SD-NEXT: mov x20, x0
-; CHECK-SD-NEXT: mov x0, x19
+; CHECK-SD-NEXT: mov x1, x19
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x0, x1
; CHECK-SD-NEXT: bl _objc_release
; CHECK-SD-NEXT: b LBB4_5
; CHECK-SD-NEXT: LBB4_4: ; %lpad
; CHECK-SD-NEXT: Ltmp5: ; EH_LABEL
-; CHECK-SD-NEXT: mov x20, x0
+; CHECK-SD-NEXT: mov x19, x0
; CHECK-SD-NEXT: LBB4_5: ; %ehcleanup
; CHECK-SD-NEXT: add x0, sp, #15
; CHECK-SD-NEXT: bl __ZN1SD1Ev
-; CHECK-SD-NEXT: mov x0, x20
+; CHECK-SD-NEXT: mov x0, x19
; CHECK-SD-NEXT: bl __Unwind_Resume
; CHECK-SD-NEXT: Lfunc_end1:
; CHECK-SD-NEXT: .cfi_endproc
diff --git a/llvm/test/CodeGen/AArch64/div-i256.ll b/llvm/test/CodeGen/AArch64/div-i256.ll
index 5f8d362c85bb2..746815b857ead 100644
--- a/llvm/test/CodeGen/AArch64/div-i256.ll
+++ b/llvm/test/CodeGen/AArch64/div-i256.ll
@@ -202,219 +202,219 @@ define i256 @udiv256(i256 %a, i256 %b) nounwind {
define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: sdiv256:
; CHECK: // %bb.0: // %_udiv-special-cases
-; CHECK-NEXT: asr x12, x3, #63
+; CHECK-NEXT: asr x11, x3, #63
; CHECK-NEXT: asr x13, x7, #63
-; CHECK-NEXT: eor x8, x0, x12
-; CHECK-NEXT: eor x9, x1, x12
+; CHECK-NEXT: eor x8, x0, x11
+; CHECK-NEXT: eor x9, x1, x11
; CHECK-NEXT: eor x10, x4, x13
-; CHECK-NEXT: subs x14, x8, x12
-; CHECK-NEXT: eor x8, x2, x12
-; CHECK-NEXT: eor x11, x5, x13
-; CHECK-NEXT: sbcs x15, x9, x12
-; CHECK-NEXT: eor x9, x3, x12
-; CHECK-NEXT: clz x16, x14
-; CHECK-NEXT: sbcs x18, x8, x12
-; CHECK-NEXT: clz x17, x15
-; CHECK-NEXT: add x16, x16, #64
-; CHECK-NEXT: sbc x0, x9, x12
+; CHECK-NEXT: subs x0, x8, x11
+; CHECK-NEXT: eor x8, x2, x11
+; CHECK-NEXT: eor x12, x5, x13
+; CHECK-NEXT: sbcs x1, x9, x11
+; CHECK-NEXT: eor x9, x3, x11
+; CHECK-NEXT: clz x14, x0
+; CHECK-NEXT: sbcs x4, x8, x11
+; CHECK-NEXT: clz x15, x1
+; CHECK-NEXT: add x14, x14, #64
+; CHECK-NEXT: sbc x5, x9, x11
; CHECK-NEXT: subs x8, x10, x13
; CHECK-NEXT: eor x10, x6, x13
-; CHECK-NEXT: sbcs x9, x11, x13
-; CHECK-NEXT: eor x11, x7, x13
-; CHECK-NEXT: orr x1, x14, x18
+; CHECK-NEXT: sbcs x9, x12, x13
+; CHECK-NEXT: eor x12, x7, x13
+; CHECK-NEXT: orr x16, x0, x4
; CHECK-NEXT: sbcs x10, x10, x13
-; CHECK-NEXT: orr x4, x15, x0
-; CHECK-NEXT: clz x5, x8
-; CHECK-NEXT: sbc x11, x11, x13
-; CHECK-NEXT: orr x2, x8, x10
-; CHECK-NEXT: orr x1, x1, x4
-; CHECK-NEXT: orr x3, x9, x11
-; CHECK-NEXT: add x5, x5, #64
-; CHECK-NEXT: orr x6, x10, x11
-; CHECK-NEXT: orr x2, x2, x3
-; CHECK-NEXT: clz x3, x10
-; CHECK-NEXT: eor x12, x13, x12
-; CHECK-NEXT: cmp x2, #0
+; CHECK-NEXT: orr x2, x1, x5
+; CHECK-NEXT: clz x3, x8
+; CHECK-NEXT: sbc x12, x12, x13
+; CHECK-NEXT: orr x17, x8, x10
+; CHECK-NEXT: orr x16, x16, x2
+; CHECK-NEXT: orr x18, x9, x12
; CHECK-NEXT: add x3, x3, #64
-; CHECK-NEXT: clz x2, x9
-; CHECK-NEXT: ccmp x1, #0, #4, ne
-; CHECK-NEXT: clz x1, x11
-; CHECK-NEXT: cset w4, eq
-; CHECK-NEXT: cmp x11, #0
-; CHECK-NEXT: csel x1, x1, x3, ne
+; CHECK-NEXT: orr x6, x10, x12
+; CHECK-NEXT: orr x17, x17, x18
+; CHECK-NEXT: clz x18, x10
+; CHECK-NEXT: eor x11, x13, x11
+; CHECK-NEXT: cmp x17, #0
+; CHECK-NEXT: add x18, x18, #64
+; CHECK-NEXT: clz x17, x9
+; CHECK-NEXT: ccmp x16, #0, #4, ne
+; CHECK-NEXT: clz x16, x12
+; CHECK-NEXT: cset w2, eq
+; CHECK-NEXT: cmp x12, #0
+; CHECK-NEXT: csel x16, x16, x18, ne
; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: clz x3, x18
-; CHECK-NEXT: csel x2, x2, x5, ne
+; CHECK-NEXT: clz x18, x4
+; CHECK-NEXT: csel x17, x17, x3, ne
; CHECK-NEXT: cmp x6, #0
-; CHECK-NEXT: add x3, x3, #64
-; CHECK-NEXT: add x2, x2, #128
-; CHECK-NEXT: clz x5, x0
-; CHECK-NEXT: csel x1, x1, x2, ne
-; CHECK-NEXT: cmp x0, #0
-; CHECK-NEXT: csel x2, x5, x3, ne
-; CHECK-NEXT: cmp x15, #0
-; CHECK-NEXT: orr x3, x18, x0
-; CHECK-NEXT: csel x16, x17, x16, ne
-; CHECK-NEXT: cmp x3, #0
-; CHECK-NEXT: mov w3, #255 // =0xff
-; CHECK-NEXT: add x16, x16, #128
-; CHECK-NEXT: csel x16, x2, x16, ne
-; CHECK-NEXT: subs x2, x1, x16
+; CHECK-NEXT: add x18, x18, #64
+; CHECK-NEXT: add x17, x17, #128
+; CHECK-NEXT: clz x3, x5
+; CHECK-NEXT: csel x16, x16, x17, ne
+; CHECK-NEXT: cmp x5, #0
+; CHECK-NEXT: csel x17, x3, x18, ne
+; CHECK-NEXT: cmp x1, #0
+; CHECK-NEXT: orr x18, x4, x5
+; CHECK-NEXT: csel x14, x15, x14, ne
+; CHECK-NEXT: cmp x18, #0
+; CHECK-NEXT: mov w18, #255 // =0xff
+; CHECK-NEXT: add x14, x14, #128
+; CHECK-NEXT: csel x14, x17, x14, ne
+; CHECK-NEXT: subs x17, x16, x14
+; CHECK-NEXT: ngcs x14, xzr
; CHECK-NEXT: ngcs x16, xzr
-; CHECK-NEXT: ngcs x17, xzr
-; CHECK-NEXT: ngc x1, xzr
-; CHECK-NEXT: cmp x3, x2
+; CHECK-NEXT: ngc x15, xzr
+; CHECK-NEXT: cmp x18, x17
+; CHECK-NEXT: ngcs xzr, x14
; CHECK-NEXT: ngcs xzr, x16
-; CHECK-NEXT: ngcs xzr, x17
-; CHECK-NEXT: ngcs xzr, x1
-; CHECK-NEXT: csinc w5, w4, wzr, hs
-; CHECK-NEXT: cmp w5, #0
-; CHECK-NEXT: csel x13, xzr, x0, ne
-; CHECK-NEXT: csel x4, xzr, x18, ne
-; CHECK-NEXT: csel x7, xzr, x15, ne
-; CHECK-NEXT: csel x3, xzr, x14, ne
-; CHECK-NEXT: tbnz w5, #0, .LBB1_6
+; CHECK-NEXT: ngcs xzr, x15
+; CHECK-NEXT: csinc w3, w2, wzr, hs
+; CHECK-NEXT: cmp w3, #0
+; CHECK-NEXT: csel x13, xzr, x5, ne
+; CHECK-NEXT: csel x2, xzr, x4, ne
+; CHECK-NEXT: csel x7, xzr, x1, ne
+; CHECK-NEXT: csel x18, xzr, x0, ne
+; CHECK-NEXT: tbnz w3, #0, .LBB1_6
; CHECK-NEXT: // %bb.1: // %_udiv-special-cases
-; CHECK-NEXT: eor x5, x2, #0xff
-; CHECK-NEXT: orr x6, x16, x1
-; CHECK-NEXT: orr x5, x5, x17
-; CHECK-NEXT: orr x5, x5, x6
-; CHECK-NEXT: cbz x5, .LBB1_6
+; CHECK-NEXT: eor x3, x17, #0xff
+; CHECK-NEXT: orr x6, x14, x15
+; CHECK-NEXT: orr x3, x3, x16
+; CHECK-NEXT: orr x3, x3, x6
+; CHECK-NEXT: cbz x3, .LBB1_6
; CHECK-NEXT: // %bb.2: // %udiv-bb1
; CHECK-NEXT: sub sp, sp, #208
; CHECK-NEXT: mov w13, #255 // =0xff
; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: add x4, sp, #64
-; CHECK-NEXT: sub x3, x13, x2
-; CHECK-NEXT: add x4, x4, #32
+; CHECK-NEXT: add x2, sp, #64
+; CHECK-NEXT: sub x18, x13, x17
+; CHECK-NEXT: add x2, x2, #32
; CHECK-NEXT: stp x28, x27, [sp, #128] // 16-byte Folded Spill
-; CHECK-NEXT: lsr x13, x3, #3
+; CHECK-NEXT: lsr x13, x18, #3
; CHECK-NEXT: stp x26, x25, [sp, #144] // 16-byte Folded Spill
; CHECK-NEXT: stp x24, x23, [sp, #160] // 16-byte Folded Spill
; CHECK-NEXT: and x13, x13, #0x18
; CHECK-NEXT: stp x22, x21, [sp, #176] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #192] // 16-byte Folded Spill
-; CHECK-NEXT: sub x4, x4, x13
-; CHECK-NEXT: adds x13, x2, #1
-; CHECK-NEXT: stp x14, x15, [sp, #96]
-; CHECK-NEXT: and x19, x3, #0x3f
-; CHECK-NEXT: adcs x16, x16, xzr
-; CHECK-NEXT: stp x18, x0, [sp, #112]
-; CHECK-NEXT: mvn w20, w3
+; CHECK-NEXT: sub x2, x2, x13
+; CHECK-NEXT: adds x13, x17, #1
+; CHECK-NEXT: stp x0, x1, [sp, #96]
+; CHECK-NEXT: and x19, x18, #0x3f
+; CHECK-NEXT: adcs x14, x14, xzr
+; CHECK-NEXT: stp x4, x5, [sp, #112]
+; CHECK-NEXT: mvn w20, w18
; CHECK-NEXT: eor x19, x19, #0x3f
; CHECK-NEXT: stp q0, q0, [sp, #64]
-; CHECK-NEXT: adcs x17, x17, xzr
-; CHECK-NEXT: ldp x2, x6, [x4, #8]
-; CHECK-NEXT: ldr x7, [x4]
-; CHECK-NEXT: ldr x5, [x4, #24]
+; CHECK-NEXT: adcs x16, x16, xzr
+; CHECK-NEXT: ldp x17, x6, [x2, #8]
+; CHECK-NEXT: ldr x7, [x2]
+; CHECK-NEXT: ldr x3, [x2, #24]
; CHECK-NEXT: lsr x22, x7, #1
-; CHECK-NEXT: lsr x4, x2, #1
+; CHECK-NEXT: lsr x2, x17, #1
; CHECK-NEXT: lsr x21, x6, #1
-; CHECK-NEXT: lsl x5, x5, x3
-; CHECK-NEXT: lsl x6, x6, x3
-; CHECK-NEXT: lsl x2, x2, x3
-; CHECK-NEXT: lsr x20, x4, x20
+; CHECK-NEXT: lsl x3, x3, x18
+; CHECK-NEXT: lsl x6, x6, x18
+; CHECK-NEXT: lsl x17, x17, x18
+; CHECK-NEXT: lsr x20, x2, x20
; CHECK-NEXT: lsr x21, x21, x19
; CHECK-NEXT: lsr x19, x22, x19
-; CHECK-NEXT: adcs x4, x1, xzr
-; CHECK-NEXT: lsl x1, x7, x3
+; CHECK-NEXT: adcs x2, x15, xzr
+; CHECK-NEXT: lsl x15, x7, x18
; CHECK-NEXT: cset w22, hs
-; CHECK-NEXT: orr x5, x5, x21
-; CHECK-NEXT: orr x3, x6, x20
-; CHECK-NEXT: orr x2, x2, x19
+; CHECK-NEXT: orr x3, x3, x21
+; CHECK-NEXT: orr x18, x6, x20
+; CHECK-NEXT: orr x17, x17, x19
; CHECK-NEXT: mov x6, xzr
; CHECK-NEXT: tbnz w22, #0, .LBB1_5
; CHECK-NEXT: // %bb.3: // %udiv-preheader
; CHECK-NEXT: lsr x21, x13, #3
-; CHECK-NEXT: stp x14, x15, [sp]
-; CHECK-NEXT: mov x15, sp
+; CHECK-NEXT: stp x0, x1, [sp]
+; CHECK-NEXT: mov x1, sp
; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: mov x19, xzr
; CHECK-NEXT: mov x20, xzr
-; CHECK-NEXT: and x14, x21, #0x18
-; CHECK-NEXT: stp x18, x0, [sp, #16]
-; CHECK-NEXT: and x0, x13, #0x3f
-; CHECK-NEXT: add x14, x15, x14
+; CHECK-NEXT: and x0, x21, #0x18
+; CHECK-NEXT: stp x4, x5, [sp, #16]
+; CHECK-NEXT: and x5, x13, #0x3f
+; CHECK-NEXT: add x0, x1, x0
; CHECK-NEXT: mvn w21, w13
-; CHECK-NEXT: eor x0, x0, #0x3f
-; CHECK-NEXT: ldp x15, x18, [x14, #16]
+; CHECK-NEXT: eor x5, x5, #0x3f
+; CHECK-NEXT: ldp x1, x4, [x0, #16]
; CHECK-NEXT: mov x7, xzr
-; CHECK-NEXT: ldp x24, x22, [x14]
-; CHECK-NEXT: lsl x14, x15, #1
-; CHECK-NEXT: lsl x23, x18, #1
-; CHECK-NEXT: lsr x25, x15, x13
-; CHECK-NEXT: lsl x15, x22, #1
+; CHECK-NEXT: ldp x24, x22, [x0]
+; CHECK-NEXT: lsl x0, x1, #1
+; CHECK-NEXT: lsl x23, x4, #1
+; CHECK-NEXT: lsr x25, x1, x13
+; CHECK-NEXT: lsl x1, x22, #1
; CHECK-NEXT: lsr x27, x22, x13
; CHECK-NEXT: lsr x28, x24, x13
-; CHECK-NEXT: lsl x26, x14, x21
-; CHECK-NEXT: subs x14, x8, #1
-; CHECK-NEXT: lsl x23, x23, x0
-; CHECK-NEXT: lsl x0, x15, x0
-; CHECK-NEXT: sbcs x15, x9, xzr
-; CHECK-NEXT: lsr x22, x18, x13
-; CHECK-NEXT: sbcs x18, x10, xzr
+; CHECK-NEXT: lsl x26, x0, x21
+; CHECK-NEXT: subs x0, x8, #1
+; CHECK-NEXT: lsl x23, x23, x5
+; CHECK-NEXT: lsl x5, x1, x5
+; CHECK-NEXT: sbcs x1, x9, xzr
+; CHECK-NEXT: lsr x22, x4, x13
+; CHECK-NEXT: sbcs x4, x10, xzr
; CHECK-NEXT: orr x21, x23, x25
; CHECK-NEXT: orr x24, x27, x26
-; CHECK-NEXT: orr x23, x0, x28
-; CHECK-NEXT: sbc x0, x11, xzr
+; CHECK-NEXT: orr x23, x5, x28
+; CHECK-NEXT: sbc x5, x12, xzr
; CHECK-NEXT: .LBB1_4: // %udiv-do-while
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: extr x25, x23, x5, #63
+; CHECK-NEXT: extr x25, x23, x3, #63
; CHECK-NEXT: extr x26, x24, x23, #63
; CHECK-NEXT: extr x27, x21, x24, #63
; CHECK-NEXT: extr x22, x22, x21, #63
-; CHECK-NEXT: extr x5, x5, x3, #63
-; CHECK-NEXT: extr x3, x3, x2, #63
-; CHECK-NEXT: cmp x14, x25
-; CHECK-NEXT: sbcs xzr, x15, x26
-; CHECK-NEXT: orr x3, x20, x3
-; CHECK-NEXT: orr x5, x7, x5
-; CHECK-NEXT: sbcs xzr, x18, x27
+; CHECK-NEXT: extr x3, x3, x18, #63
+; CHECK-NEXT: extr x18, x18, x17, #63
+; CHECK-NEXT: cmp x0, x25
+; CHECK-NEXT: sbcs xzr, x1, x26
+; CHECK-NEXT: orr x18, x20, x18
+; CHECK-NEXT: orr x3, x7, x3
+; CHECK-NEXT: sbcs xzr, x4, x27
; CHECK-NEXT: mov x7, xzr
-; CHECK-NEXT: sbc x21, x0, x22
+; CHECK-NEXT: sbc x21, x5, x22
; CHECK-NEXT: asr x28, x21, #63
; CHECK-NEXT: and x21, x28, x8
; CHECK-NEXT: subs x23, x25, x21
; CHECK-NEXT: and x21, x28, x9
-; CHECK-NEXT: and x25, x28, x11
+; CHECK-NEXT: and x25, x28, x12
; CHECK-NEXT: sbcs x24, x26, x21
; CHECK-NEXT: and x21, x28, x10
; CHECK-NEXT: sbcs x21, x27, x21
; CHECK-NEXT: sbc x22, x22, x25
; CHECK-NEXT: subs x13, x13, #1
-; CHECK-NEXT: extr x25, x2, x1, #63
-; CHECK-NEXT: sbcs x16, x16, xzr
-; CHECK-NEXT: orr x1, x6, x1, lsl #1
+; CHECK-NEXT: extr x25, x17, x15, #63
+; CHECK-NEXT: sbcs x14, x14, xzr
+; CHECK-NEXT: orr x15, x6, x15, lsl #1
; CHECK-NEXT: and x6, x28, #0x1
-; CHECK-NEXT: sbcs x17, x17, xzr
-; CHECK-NEXT: orr x2, x19, x25
-; CHECK-NEXT: sbc x4, x4, xzr
-; CHECK-NEXT: orr x20, x13, x17
-; CHECK-NEXT: orr x19, x16, x4
+; CHECK-NEXT: sbcs x16, x16, xzr
+; CHECK-NEXT: orr x17, x19, x25
+; CHECK-NEXT: sbc x2, x2, xzr
+; CHECK-NEXT: orr x20, x13, x16
+; CHECK-NEXT: orr x19, x14, x2
; CHECK-NEXT: orr x25, x20, x19
; CHECK-NEXT: mov x19, xzr
; CHECK-NEXT: mov x20, xzr
; CHECK-NEXT: cbnz x25, .LBB1_4
; CHECK-NEXT: .LBB1_5: // %udiv-loop-exit
; CHECK-NEXT: ldp x20, x19, [sp, #192] // 16-byte Folded Reload
-; CHECK-NEXT: extr x7, x2, x1, #63
+; CHECK-NEXT: extr x7, x17, x15, #63
; CHECK-NEXT: ldp x22, x21, [sp, #176] // 16-byte Folded Reload
-; CHECK-NEXT: extr x4, x3, x2, #63
+; CHECK-NEXT: extr x2, x18, x17, #63
; CHECK-NEXT: ldp x24, x23, [sp, #160] // 16-byte Folded Reload
-; CHECK-NEXT: extr x13, x5, x3, #63
+; CHECK-NEXT: extr x13, x3, x18, #63
; CHECK-NEXT: ldp x26, x25, [sp, #144] // 16-byte Folded Reload
-; CHECK-NEXT: orr x3, x6, x1, lsl #1
+; CHECK-NEXT: orr x18, x6, x15, lsl #1
; CHECK-NEXT: ldp x28, x27, [sp, #128] // 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #208
; CHECK-NEXT: .LBB1_6: // %udiv-end
-; CHECK-NEXT: eor x8, x3, x12
-; CHECK-NEXT: eor x9, x7, x12
-; CHECK-NEXT: subs x0, x8, x12
-; CHECK-NEXT: eor x8, x4, x12
-; CHECK-NEXT: sbcs x1, x9, x12
-; CHECK-NEXT: eor x9, x13, x12
-; CHECK-NEXT: sbcs x2, x8, x12
-; CHECK-NEXT: sbc x3, x9, x12
+; CHECK-NEXT: eor x8, x18, x11
+; CHECK-NEXT: eor x9, x7, x11
+; CHECK-NEXT: subs x0, x8, x11
+; CHECK-NEXT: eor x8, x2, x11
+; CHECK-NEXT: sbcs x1, x9, x11
+; CHECK-NEXT: eor x9, x13, x11
+; CHECK-NEXT: sbcs x2, x8, x11
+; CHECK-NEXT: sbc x3, x9, x11
; CHECK-NEXT: ret
%r = sdiv i256 %a, %b
ret i256 %r
@@ -463,12 +463,12 @@ define i256 @urem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: subs x12, x8, x9
; CHECK-NEXT: mov w8, #255 // =0xff
; CHECK-NEXT: ngcs x9, xzr
-; CHECK-NEXT: ngcs x10, xzr
-; CHECK-NEXT: ngc x11, xzr
+; CHECK-NEXT: ngcs x11, xzr
+; CHECK-NEXT: ngc x10, xzr
; CHECK-NEXT: cmp x8, x12
; CHECK-NEXT: ngcs xzr, x9
-; CHECK-NEXT: ngcs xzr, x10
; CHECK-NEXT: ngcs xzr, x11
+; CHECK-NEXT: ngcs xzr, x10
; CHECK-NEXT: csinc w15, w13, wzr, hs
; CHECK-NEXT: cmp w15, #0
; CHECK-NEXT: csel x13, xzr, x3, ne
@@ -478,8 +478,8 @@ define i256 @urem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: tbnz w15, #0, .LBB2_6
; CHECK-NEXT: // %bb.1: // %_udiv-special-cases
; CHECK-NEXT: eor x15, x12, #0xff
-; CHECK-NEXT: orr x16, x9, x11
-; CHECK-NEXT: orr x15, x15, x10
+; CHECK-NEXT: orr x16, x9, x10
+; CHECK-NEXT: orr x15, x15, x11
; CHECK-NEXT: orr x15, x15, x16
; CHECK-NEXT: cbz x15, .LBB2_6
; CHECK-NEXT: // %bb.2: // %udiv-bb1
@@ -504,7 +504,7 @@ define i256 @urem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: mvn w20, w13
; CHECK-NEXT: adcs x9, x9, xzr
; CHECK-NEXT: stp x0, x1, [sp, #112]
-; CHECK-NEXT: adcs x10, x10, xzr
+; CHECK-NEXT: adcs x11, x11, xzr
; CHECK-NEXT: stp x2, x3, [sp, #128]
; CHECK-NEXT: stp q0, q0, [sp, #80]
; CHECK-NEXT: ldp x12, x16, [x14, #8]
@@ -519,8 +519,8 @@ define i256 @urem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: lsr x21, x14, x20
; CHECK-NEXT: lsr x20, x17, #1
; CHECK-NEXT: lsr x19, x19, x18
-; CHECK-NEXT: adcs x14, x11, xzr
-; CHECK-NEXT: lsl x11, x17, x13
+; CHECK-NEXT: adcs x14, x10, xzr
+; CHECK-NEXT: lsl x10, x17, x13
; CHECK-NEXT: lsr x18, x20, x18
; CHECK-NEXT: cset w20, hs
; CHECK-NEXT: orr x15, x15, x19
@@ -586,14 +586,14 @@ define i256 @urem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: sbcs x24, x30, x24
; CHECK-NEXT: sbc x25, x25, x28
; CHECK-NEXT: subs x8, x8, #1
-; CHECK-NEXT: extr x28, x12, x11, #63
+; CHECK-NEXT: extr x28, x12, x10, #63
; CHECK-NEXT: sbcs x9, x9, xzr
-; CHECK-NEXT: orr x11, x16, x11, lsl #1
+; CHECK-NEXT: orr x10, x16, x10, lsl #1
; CHECK-NEXT: and x16, x20, #0x1
-; CHECK-NEXT: sbcs x10, x10, xzr
+; CHECK-NEXT: sbcs x11, x11, xzr
; CHECK-NEXT: orr x12, x18, x28
; CHECK-NEXT: sbc x14, x14, xzr
-; CHECK-NEXT: orr x19, x8, x10
+; CHECK-NEXT: orr x19, x8, x11
; CHECK-NEXT: orr x18, x9, x14
; CHECK-NEXT: orr x20, x19, x18
; CHECK-NEXT: mov x18, xzr
@@ -601,13 +601,13 @@ define i256 @urem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: cbnz x20, .LBB2_4
; CHECK-NEXT: .LBB2_5: // %udiv-loop-exit
; CHECK-NEXT: ldp x20, x19, [sp, #224] // 16-byte Folded Reload
-; CHECK-NEXT: extr x14, x12, x11, #63
+; CHECK-NEXT: extr x14, x12, x10, #63
; CHECK-NEXT: ldp x22, x21, [sp, #208] // 16-byte Folded Reload
; CHECK-NEXT: extr x17, x13, x12, #63
; CHECK-NEXT: ldp x24, x23, [sp, #192] // 16-byte Folded Reload
; CHECK-NEXT: extr x13, x15, x13, #63
; CHECK-NEXT: ldp x26, x25, [sp, #176] // 16-byte Folded Reload
-; CHECK-NEXT: orr x8, x16, x11, lsl #1
+; CHECK-NEXT: orr x8, x16, x10, lsl #1
; CHECK-NEXT: ldp x28, x27, [sp, #160] // 16-byte Folded Reload
; CHECK-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-NEXT: ldp x29, x30, [sp, #144] // 16-byte Folded Reload
@@ -718,12 +718,12 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: subs x2, x18, x17
; CHECK-NEXT: mov w17, #255 // =0xff
; CHECK-NEXT: ngcs x18, xzr
-; CHECK-NEXT: ngcs x0, xzr
-; CHECK-NEXT: ngc x1, xzr
+; CHECK-NEXT: ngcs x1, xzr
+; CHECK-NEXT: ngc x0, xzr
; CHECK-NEXT: cmp x17, x2
; CHECK-NEXT: ngcs xzr, x18
-; CHECK-NEXT: ngcs xzr, x0
; CHECK-NEXT: ngcs xzr, x1
+; CHECK-NEXT: ngcs xzr, x0
; CHECK-NEXT: csinc w5, w3, wzr, hs
; CHECK-NEXT: cmp w5, #0
; CHECK-NEXT: csel x3, xzr, x11, ne
@@ -733,8 +733,8 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: tbnz w5, #0, .LBB3_6
; CHECK-NEXT: // %bb.1: // %_udiv-special-cases
; CHECK-NEXT: eor x5, x2, #0xff
-; CHECK-NEXT: orr x6, x18, x1
-; CHECK-NEXT: orr x5, x5, x0
+; CHECK-NEXT: orr x6, x18, x0
+; CHECK-NEXT: orr x5, x5, x1
; CHECK-NEXT: orr x5, x5, x6
; CHECK-NEXT: cbz x5, .LBB3_6
; CHECK-NEXT: // %bb.2: // %udiv-bb1
@@ -758,7 +758,7 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: ldr x10, [x10]
; CHECK-NEXT: adcs x18, x18, xzr
; CHECK-NEXT: stp x23, x22, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: adcs x0, x0, xzr
+; CHECK-NEXT: adcs x1, x1, xzr
; CHECK-NEXT: lsl x3, x3, x9
; CHECK-NEXT: lsr x4, x2, #1
; CHECK-NEXT: lsr x19, x5, #1
@@ -768,8 +768,8 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: lsr x7, x4, x7
; CHECK-NEXT: lsr x19, x19, x6
; CHECK-NEXT: lsr x6, x20, x6
-; CHECK-NEXT: adcs x4, x1, xzr
-; CHECK-NEXT: lsl x1, x10, x9
+; CHECK-NEXT: adcs x4, x0, xzr
+; CHECK-NEXT: lsl x0, x10, x9
; CHECK-NEXT: cset w20, hs
; CHECK-NEXT: orr x5, x3, x19
; CHECK-NEXT: orr x3, x21, x7
@@ -835,24 +835,24 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: and x9, x10, x16
; CHECK-NEXT: sbc x26, x26, x9
; CHECK-NEXT: subs x17, x17, #1
-; CHECK-NEXT: extr x9, x2, x1, #63
+; CHECK-NEXT: extr x9, x2, x0, #63
; CHECK-NEXT: sbcs x18, x18, xzr
-; CHECK-NEXT: orr x1, x6, x1, lsl #1
+; CHECK-NEXT: orr x0, x6, x0, lsl #1
; CHECK-NEXT: and x6, x10, #0x1
-; CHECK-NEXT: sbcs x0, x0, xzr
+; CHECK-NEXT: sbcs x1, x1, xzr
; CHECK-NEXT: orr x2, x19, x9
; CHECK-NEXT: sbc x4, x4, xzr
-; CHECK-NEXT: orr x19, x17, x0
+; CHECK-NEXT: orr x19, x17, x1
; CHECK-NEXT: orr x9, x18, x4
; CHECK-NEXT: orr x9, x19, x9
; CHECK-NEXT: mov x19, xzr
; CHECK-NEXT: cbnz x9, .LBB3_4
; CHECK-NEXT: .LBB3_5: // %udiv-loop-exit
; CHECK-NEXT: ldp x23, x22, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: extr x4, x2, x1, #63
+; CHECK-NEXT: extr x4, x2, x0, #63
; CHECK-NEXT: extr x7, x3, x2, #63
; CHECK-NEXT: extr x3, x5, x3, #63
-; CHECK-NEXT: orr x17, x6, x1, lsl #1
+; CHECK-NEXT: orr x17, x6, x0, lsl #1
; CHECK-NEXT: .LBB3_6: // %udiv-end
; CHECK-NEXT: umulh x10, x17, x15
; CHECK-NEXT: ldp x20, x19, [sp, #224] // 16-byte Folded Reload
@@ -927,22 +927,22 @@ define i256 @sdiv256_const(i256 %a) nounwind {
; CHECK-NEXT: mov w13, #255 // =0xff
; CHECK-NEXT: eor x9, x0, x8
; CHECK-NEXT: eor x10, x1, x8
-; CHECK-NEXT: subs x18, x9, x8
+; CHECK-NEXT: subs x4, x9, x8
; CHECK-NEXT: eor x9, x2, x8
-; CHECK-NEXT: sbcs x0, x10, x8
+; CHECK-NEXT: sbcs x2, x10, x8
; CHECK-NEXT: eor x10, x3, x8
-; CHECK-NEXT: sbcs x1, x9, x8
-; CHECK-NEXT: clz x9, x18
-; CHECK-NEXT: clz x11, x0
+; CHECK-NEXT: sbcs x3, x9, x8
+; CHECK-NEXT: clz x9, x4
+; CHECK-NEXT: clz x11, x2
; CHECK-NEXT: sbcs x5, x10, x8
-; CHECK-NEXT: clz x10, x1
+; CHECK-NEXT: clz x10, x3
; CHECK-NEXT: add x9, x9, #64
; CHECK-NEXT: add x10, x10, #64
; CHECK-NEXT: clz x12, x5
-; CHECK-NEXT: orr x14, x0, x5
+; CHECK-NEXT: orr x14, x2, x5
; CHECK-NEXT: csel x10, x12, x10, ne
-; CHECK-NEXT: cmp x0, #0
-; CHECK-NEXT: orr x12, x1, x5
+; CHECK-NEXT: cmp x2, #0
+; CHECK-NEXT: orr x12, x3, x5
; CHECK-NEXT: csel x9, x11, x9, ne
; CHECK-NEXT: cmp x12, #0
; CHECK-NEXT: mov w11, #253 // =0xfd
@@ -950,24 +950,24 @@ define i256 @sdiv256_const(i256 %a) nounwind {
; CHECK-NEXT: csel x9, x10, x9, ne
; CHECK-NEXT: subs x9, x11, x9
; CHECK-NEXT: ngcs x10, xzr
-; CHECK-NEXT: ngcs x11, xzr
-; CHECK-NEXT: ngc x12, xzr
+; CHECK-NEXT: ngcs x12, xzr
+; CHECK-NEXT: ngc x11, xzr
; CHECK-NEXT: cmp x13, x9
-; CHECK-NEXT: orr x13, x18, x1
+; CHECK-NEXT: orr x13, x4, x3
; CHECK-NEXT: ngcs xzr, x10
; CHECK-NEXT: orr x13, x13, x14
-; CHECK-NEXT: ngcs xzr, x11
; CHECK-NEXT: ngcs xzr, x12
+; CHECK-NEXT: ngcs xzr, x11
; CHECK-NEXT: ccmp x13, #0, #4, hs
; CHECK-NEXT: csel x13, xzr, x5, eq
-; CHECK-NEXT: csel x15, xzr, x1, eq
-; CHECK-NEXT: csel x2, xzr, x0, eq
-; CHECK-NEXT: csel x14, xzr, x18, eq
+; CHECK-NEXT: csel x15, xzr, x3, eq
+; CHECK-NEXT: csel x18, xzr, x2, eq
+; CHECK-NEXT: csel x14, xzr, x4, eq
; CHECK-NEXT: b.eq .LBB5_6
; CHECK-NEXT: // %bb.1: // %_udiv-special-cases
; CHECK-NEXT: eor x16, x9, #0xff
-; CHECK-NEXT: orr x17, x10, x12
-; CHECK-NEXT: orr x16, x16, x11
+; CHECK-NEXT: orr x17, x10, x11
+; CHECK-NEXT: orr x16, x16, x12
; CHECK-NEXT: orr x16, x16, x17
; CHECK-NEXT: cbz x16, .LBB5_6
; CHECK-NEXT: // %bb.2: // %udiv-bb1
@@ -982,65 +982,65 @@ define i256 @sdiv256_const(i256 %a) nounwind {
; CHECK-NEXT: stp x24, x23, [sp, #144] // 16-byte Folded Spill
; CHECK-NEXT: adds x9, x9, #1
; CHECK-NEXT: stp x22, x21, [sp, #160] // 16-byte Folded Spill
-; CHECK-NEXT: and x3, x13, #0x3f
+; CHECK-NEXT: and x0, x13, #0x3f
; CHECK-NEXT: adcs x10, x10, xzr
; CHECK-NEXT: and x14, x14, #0x18
; CHECK-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill
-; CHECK-NEXT: mvn w4, w13
-; CHECK-NEXT: stp x18, x0, [sp, #96]
+; CHECK-NEXT: mvn w1, w13
+; CHECK-NEXT: stp x4, x2, [sp, #96]
; CHECK-NEXT: sub x14, x15, x14
-; CHECK-NEXT: eor x3, x3, #0x3f
-; CHECK-NEXT: str x1, [sp, #112]
-; CHECK-NEXT: adcs x11, x11, xzr
+; CHECK-NEXT: eor x0, x0, #0x3f
+; CHECK-NEXT: str x3, [sp, #112]
+; CHECK-NEXT: adcs x12, x12, xzr
; CHECK-NEXT: stp q0, q0, [sp, #64]
-; CHECK-NEXT: ldp x16, x2, [x14, #8]
+; CHECK-NEXT: ldp x16, x18, [x14, #8]
; CHECK-NEXT: ldr x17, [x14, #24]
; CHECK-NEXT: ldr x14, [x14]
; CHECK-NEXT: lsl x17, x17, x13
; CHECK-NEXT: lsr x15, x16, #1
-; CHECK-NEXT: lsr x6, x2, #1
+; CHECK-NEXT: lsr x6, x18, #1
; CHECK-NEXT: lsr x7, x14, #1
-; CHECK-NEXT: lsl x2, x2, x13
+; CHECK-NEXT: lsl x18, x18, x13
; CHECK-NEXT: lsl x19, x16, x13
-; CHECK-NEXT: lsr x4, x15, x4
-; CHECK-NEXT: lsr x6, x6, x3
-; CHECK-NEXT: lsr x3, x7, x3
-; CHECK-NEXT: adcs x15, x12, xzr
-; CHECK-NEXT: lsl x12, x14, x13
+; CHECK-NEXT: lsr x1, x15, x1
+; CHECK-NEXT: lsr x6, x6, x0
+; CHECK-NEXT: lsr x0, x7, x0
+; CHECK-NEXT: adcs x15, x11, xzr
+; CHECK-NEXT: lsl x11, x14, x13
; CHECK-NEXT: cset w7, hs
; CHECK-NEXT: orr x16, x17, x6
-; CHECK-NEXT: orr x14, x2, x4
-; CHECK-NEXT: orr x13, x19, x3
+; CHECK-NEXT: orr x14, x18, x1
+; CHECK-NEXT: orr x13, x19, x0
; CHECK-NEXT: mov x17, xzr
; CHECK-NEXT: tbnz w7, #0, .LBB5_5
; CHECK-NEXT: // %bb.3: // %udiv-preheader
; CHECK-NEXT: lsr x6, x9, #3
-; CHECK-NEXT: stp x18, x0, [sp]
-; CHECK-NEXT: mov x0, sp
+; CHECK-NEXT: stp x4, x2, [sp]
+; CHECK-NEXT: mov x4, sp
; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: mvn w7, w9
-; CHECK-NEXT: mov x3, xzr
-; CHECK-NEXT: and x18, x6, #0x18
-; CHECK-NEXT: stp x1, x5, [sp, #16]
+; CHECK-NEXT: mov x0, xzr
+; CHECK-NEXT: and x2, x6, #0x18
+; CHECK-NEXT: stp x3, x5, [sp, #16]
; CHECK-NEXT: and x6, x9, #0x3f
-; CHECK-NEXT: add x0, x0, x18
-; CHECK-NEXT: mov w18, #7 // =0x7
+; CHECK-NEXT: add x3, x4, x2
+; CHECK-NEXT: mov w2, #7 // =0x7
; CHECK-NEXT: eor x6, x6, #0x3f
-; CHECK-NEXT: ldp x1, x5, [x0, #16]
-; CHECK-NEXT: mov x4, xzr
-; CHECK-NEXT: ldp x21, x19, [x0]
-; CHECK-NEXT: mov x2, xzr
-; CHECK-NEXT: lsl x0, x1, #1
+; CHECK-NEXT: ldp x4, x5, [x3, #16]
+; CHECK-NEXT: mov x1, xzr
+; CHECK-NEXT: ldp x21, x19, [x3]
+; CHECK-NEXT: mov x18, xzr
+; CHECK-NEXT: lsl x3, x4, #1
; CHECK-NEXT: lsl x20, x5, #1
-; CHECK-NEXT: lsr x22, x1, x9
-; CHECK-NEXT: lsl x1, x19, #1
+; CHECK-NEXT: lsr x22, x4, x9
+; CHECK-NEXT: lsl x4, x19, #1
; CHECK-NEXT: lsr x24, x19, x9
; CHECK-NEXT: lsr x21, x21, x9
-; CHECK-NEXT: lsl x23, x0, x7
-; CHECK-NEXT: subs x0, x18, #1
+; CHECK-NEXT: lsl x23, x3, x7
+; CHECK-NEXT: subs x3, x2, #1
; CHECK-NEXT: lsl x20, x20, x6
-; CHECK-NEXT: lsl x6, x1, x6
-; CHECK-NEXT: ngcs x1, xzr
+; CHECK-NEXT: lsl x6, x4, x6
+; CHECK-NEXT: ngcs x4, xzr
; CHECK-NEXT: lsr x19, x5, x9
; CHECK-NEXT: ngcs x5, xzr
; CHECK-NEXT: orr x7, x20, x22
@@ -1055,46 +1055,46 @@ define i256 @sdiv256_const(i256 %a) nounwind {
; CHECK-NEXT: extr x19, x19, x7, #63
; CHECK-NEXT: extr x16, x16, x14, #63
; CHECK-NEXT: extr x14, x14, x13, #63
-; CHECK-NEXT: cmp x0, x22
-; CHECK-NEXT: sbcs xzr, x1, x23
-; CHECK-NEXT: orr x14, x4, x14
-; CHECK-NEXT: orr x16, x2, x16
+; CHECK-NEXT: cmp x3, x22
+; CHECK-NEXT: sbcs xzr, x4, x23
+; CHECK-NEXT: orr x14, x1, x14
+; CHECK-NEXT: orr x16, x18, x16
; CHECK-NEXT: sbcs xzr, x5, x24
-; CHECK-NEXT: mov x2, xzr
+; CHECK-NEXT: mov x18, xzr
; CHECK-NEXT: sbc x7, x6, x19
; CHECK-NEXT: asr x25, x7, #63
-; CHECK-NEXT: and x7, x25, x18
+; CHECK-NEXT: and x7, x25, x2
; CHECK-NEXT: subs x21, x22, x7
-; CHECK-NEXT: extr x22, x13, x12, #63
-; CHECK-NEXT: orr x12, x17, x12, lsl #1
+; CHECK-NEXT: extr x22, x13, x11, #63
+; CHECK-NEXT: orr x11, x17, x11, lsl #1
; CHECK-NEXT: sbcs x20, x23, xzr
; CHECK-NEXT: and x17, x25, #0x1
; CHECK-NEXT: sbcs x7, x24, xzr
-; CHECK-NEXT: orr x13, x3, x22
+; CHECK-NEXT: orr x13, x0, x22
; CHECK-NEXT: sbc x19, x19, xzr
; CHECK-NEXT: subs x9, x9, #1
; CHECK-NEXT: sbcs x10, x10, xzr
-; CHECK-NEXT: sbcs x11, x11, xzr
+; CHECK-NEXT: sbcs x12, x12, xzr
; CHECK-NEXT: sbc x15, x15, xzr
-; CHECK-NEXT: orr x4, x9, x11
-; CHECK-NEXT: orr x3, x10, x15
-; CHECK-NEXT: orr x22, x4, x3
-; CHECK-NEXT: mov x3, xzr
-; CHECK-NEXT: mov x4, xzr
+; CHECK-NEXT: orr x1, x9, x12
+; CHECK-NEXT: orr x0, x10, x15
+; CHECK-NEXT: orr x22, x1, x0
+; CHECK-NEXT: mov x0, xzr
+; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: cbnz x22, .LBB5_4
; CHECK-NEXT: .LBB5_5: // %udiv-loop-exit
; CHECK-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
-; CHECK-NEXT: extr x2, x13, x12, #63
+; CHECK-NEXT: extr x18, x13, x11, #63
; CHECK-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload
; CHECK-NEXT: extr x15, x14, x13, #63
; CHECK-NEXT: ldp x24, x23, [sp, #144] // 16-byte Folded Reload
; CHECK-NEXT: extr x13, x16, x14, #63
-; CHECK-NEXT: orr x14, x17, x12, lsl #1
+; CHECK-NEXT: orr x14, x17, x11, lsl #1
; CHECK-NEXT: ldr x25, [sp, #128] // 8-byte Reload
; CHECK-NEXT: add sp, sp, #192
; CHECK-NEXT: .LBB5_6: // %udiv-end
; CHECK-NEXT: eor x9, x14, x8
-; CHECK-NEXT: eor x10, x2, x8
+; CHECK-NEXT: eor x10, x18, x8
; CHECK-NEXT: subs x0, x9, x8
; CHECK-NEXT: eor x9, x15, x8
; CHECK-NEXT: sbcs x1, x10, x8
diff --git a/llvm/test/CodeGen/AArch64/phi.ll b/llvm/test/CodeGen/AArch64/phi.ll
index 399c19dbd7b2c..5e21f99ef1b9b 100644
--- a/llvm/test/CodeGen/AArch64/phi.ll
+++ b/llvm/test/CodeGen/AArch64/phi.ll
@@ -141,15 +141,16 @@ define i128 @ti128(i1 %c, ptr %p, i128 %a, i128 %b) {
;
; CHECK-GI-LABEL: ti128:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov w8, w0
+; CHECK-GI-NEXT: mov w9, w0
+; CHECK-GI-NEXT: mov x8, x1
; CHECK-GI-NEXT: mov x0, x4
-; CHECK-GI-NEXT: tbz w8, #0, .LBB4_2
+; CHECK-GI-NEXT: mov x1, x5
+; CHECK-GI-NEXT: tbz w9, #0, .LBB4_2
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: mov x0, x2
-; CHECK-GI-NEXT: mov x5, x3
-; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: mov x1, x3
+; CHECK-GI-NEXT: str wzr, [x8]
; CHECK-GI-NEXT: .LBB4_2: // %e
-; CHECK-GI-NEXT: mov x1, x5
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -193,15 +194,26 @@ e:
}
define half @tf16(i1 %c, ptr %p, half %a, half %b) {
-; CHECK-LABEL: tf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB6_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov s1, s0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB6_2: // %e
-; CHECK-NEXT: fmov s0, s1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB6_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov s1, s0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB6_2: // %e
+; CHECK-SD-NEXT: fmov s0, s1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov s2, s0
+; CHECK-GI-NEXT: fmov s0, s1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB6_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov s0, s2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB6_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -213,15 +225,26 @@ e:
}
define float @tf32(i1 %c, ptr %p, float %a, float %b) {
-; CHECK-LABEL: tf32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB7_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov s1, s0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB7_2: // %e
-; CHECK-NEXT: fmov s0, s1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tf32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB7_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov s1, s0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB7_2: // %e
+; CHECK-SD-NEXT: fmov s0, s1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tf32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov s2, s0
+; CHECK-GI-NEXT: fmov s0, s1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB7_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov s0, s2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB7_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -233,15 +256,26 @@ e:
}
define double @tf64(i1 %c, ptr %p, double %a, double %b) {
-; CHECK-LABEL: tf64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB8_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov d1, d0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB8_2: // %e
-; CHECK-NEXT: fmov d0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tf64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB8_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov d1, d0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB8_2: // %e
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tf64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov d2, d0
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB8_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov d0, d2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB8_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -413,15 +447,26 @@ e:
}
define <8 x i8> @tv8i8(i1 %c, ptr %p, <8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: tv8i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB13_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov d1, d0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB13_2: // %e
-; CHECK-NEXT: fmov d0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv8i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB13_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov d1, d0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB13_2: // %e
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv8i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov d2, d0
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB13_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov d0, d2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB13_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -433,15 +478,26 @@ e:
}
define <16 x i8> @tv16i8(i1 %c, ptr %p, <16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: tv16i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB14_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB14_2: // %e
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv16i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB14_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB14_2: // %e
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv16i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov v2.16b, v0.16b
+; CHECK-GI-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NEXT: tbz w0, #0, .LBB14_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB14_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -468,14 +524,15 @@ define <32 x i8> @tv32i8(i1 %c, ptr %p, <32 x i8> %a, <32 x i8> %b) {
; CHECK-GI-LABEL: tv32i8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v4.16b, v0.16b
+; CHECK-GI-NEXT: mov v5.16b, v1.16b
; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: tbz w0, #0, .LBB15_2
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: mov v0.16b, v4.16b
-; CHECK-GI-NEXT: mov v3.16b, v1.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
; CHECK-GI-NEXT: str wzr, [x1]
; CHECK-GI-NEXT: .LBB15_2: // %e
-; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -521,15 +578,26 @@ e:
}
define <3 x i16> @tv3i16(i1 %c, ptr %p, <3 x i16> %a, <3 x i16> %b) {
-; CHECK-LABEL: tv3i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB17_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov d1, d0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB17_2: // %e
-; CHECK-NEXT: fmov d0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv3i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB17_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov d1, d0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB17_2: // %e
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv3i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov d2, d0
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB17_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov d0, d2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB17_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -541,15 +609,26 @@ e:
}
define <4 x i16> @tv4i16(i1 %c, ptr %p, <4 x i16> %a, <4 x i16> %b) {
-; CHECK-LABEL: tv4i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB18_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov d1, d0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB18_2: // %e
-; CHECK-NEXT: fmov d0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv4i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB18_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov d1, d0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB18_2: // %e
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv4i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov d2, d0
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB18_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov d0, d2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB18_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -561,15 +640,26 @@ e:
}
define <8 x i16> @tv8i16(i1 %c, ptr %p, <8 x i16> %a, <8 x i16> %b) {
-; CHECK-LABEL: tv8i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB19_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB19_2: // %e
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv8i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB19_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB19_2: // %e
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv8i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov v2.16b, v0.16b
+; CHECK-GI-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NEXT: tbz w0, #0, .LBB19_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB19_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -596,14 +686,15 @@ define <16 x i16> @tv16i16(i1 %c, ptr %p, <16 x i16> %a, <16 x i16> %b) {
; CHECK-GI-LABEL: tv16i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v4.16b, v0.16b
+; CHECK-GI-NEXT: mov v5.16b, v1.16b
; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: tbz w0, #0, .LBB20_2
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: mov v0.16b, v4.16b
-; CHECK-GI-NEXT: mov v3.16b, v1.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
; CHECK-GI-NEXT: str wzr, [x1]
; CHECK-GI-NEXT: .LBB20_2: // %e
-; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -616,15 +707,26 @@ e:
}
define <2 x i32> @tv2i32(i1 %c, ptr %p, <2 x i32> %a, <2 x i32> %b) {
-; CHECK-LABEL: tv2i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB21_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov d1, d0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB21_2: // %e
-; CHECK-NEXT: fmov d0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv2i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB21_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov d1, d0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB21_2: // %e
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv2i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov d2, d0
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB21_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov d0, d2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB21_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -636,15 +738,26 @@ e:
}
define <3 x i32> @tv3i32(i1 %c, ptr %p, <3 x i32> %a, <3 x i32> %b) {
-; CHECK-LABEL: tv3i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB22_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB22_2: // %e
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv3i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB22_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB22_2: // %e
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv3i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov v2.16b, v0.16b
+; CHECK-GI-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NEXT: tbz w0, #0, .LBB22_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB22_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -656,15 +769,26 @@ e:
}
define <4 x i32> @tv4i32(i1 %c, ptr %p, <4 x i32> %a, <4 x i32> %b) {
-; CHECK-LABEL: tv4i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB23_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB23_2: // %e
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv4i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB23_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB23_2: // %e
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv4i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov v2.16b, v0.16b
+; CHECK-GI-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NEXT: tbz w0, #0, .LBB23_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB23_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -691,14 +815,15 @@ define <8 x i32> @tv8i32(i1 %c, ptr %p, <8 x i32> %a, <8 x i32> %b) {
; CHECK-GI-LABEL: tv8i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v4.16b, v0.16b
+; CHECK-GI-NEXT: mov v5.16b, v1.16b
; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: tbz w0, #0, .LBB24_2
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: mov v0.16b, v4.16b
-; CHECK-GI-NEXT: mov v3.16b, v1.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
; CHECK-GI-NEXT: str wzr, [x1]
; CHECK-GI-NEXT: .LBB24_2: // %e
-; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -711,15 +836,26 @@ e:
}
define <2 x i64> @tv2i64(i1 %c, ptr %p, <2 x i64> %a, <2 x i64> %b) {
-; CHECK-LABEL: tv2i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB25_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB25_2: // %e
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv2i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB25_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB25_2: // %e
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv2i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov v2.16b, v0.16b
+; CHECK-GI-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NEXT: tbz w0, #0, .LBB25_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB25_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -804,14 +940,15 @@ define <4 x i64> @tv4i64(i1 %c, ptr %p, <4 x i64> %a, <4 x i64> %b) {
; CHECK-GI-LABEL: tv4i64:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v4.16b, v0.16b
+; CHECK-GI-NEXT: mov v5.16b, v1.16b
; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: tbz w0, #0, .LBB27_2
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: mov v0.16b, v4.16b
-; CHECK-GI-NEXT: mov v3.16b, v1.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
; CHECK-GI-NEXT: str wzr, [x1]
; CHECK-GI-NEXT: .LBB27_2: // %e
-; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -869,15 +1006,26 @@ e:
}
define <2 x ptr> @tv2p0(i1 %c, ptr %p, <2 x ptr> %a, <2 x ptr> %b) {
-; CHECK-LABEL: tv2p0:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB29_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB29_2: // %e
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv2p0:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB29_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB29_2: // %e
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv2p0:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov v2.16b, v0.16b
+; CHECK-GI-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NEXT: tbz w0, #0, .LBB29_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB29_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -962,14 +1110,15 @@ define <4 x ptr> @tv4p0(i1 %c, ptr %p, <4 x ptr> %a, <4 x ptr> %b) {
; CHECK-GI-LABEL: tv4p0:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v4.16b, v0.16b
+; CHECK-GI-NEXT: mov v5.16b, v1.16b
; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: tbz w0, #0, .LBB31_2
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: mov v0.16b, v4.16b
-; CHECK-GI-NEXT: mov v3.16b, v1.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
; CHECK-GI-NEXT: str wzr, [x1]
; CHECK-GI-NEXT: .LBB31_2: // %e
-; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -982,15 +1131,26 @@ e:
}
define <2 x half> @tv2f16(i1 %c, ptr %p, <2 x half> %a, <2 x half> %b) {
-; CHECK-LABEL: tv2f16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB32_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov d1, d0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB32_2: // %e
-; CHECK-NEXT: fmov d0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv2f16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB32_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov d1, d0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB32_2: // %e
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv2f16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov d2, d0
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB32_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov d0, d2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB32_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -1002,15 +1162,26 @@ e:
}
define <3 x half> @tv3f16(i1 %c, ptr %p, <3 x half> %a, <3 x half> %b) {
-; CHECK-LABEL: tv3f16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB33_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov d1, d0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB33_2: // %e
-; CHECK-NEXT: fmov d0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv3f16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB33_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov d1, d0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB33_2: // %e
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv3f16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov d2, d0
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB33_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov d0, d2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB33_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -1022,15 +1193,26 @@ e:
}
define <4 x half> @tv4f16(i1 %c, ptr %p, <4 x half> %a, <4 x half> %b) {
-; CHECK-LABEL: tv4f16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB34_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov d1, d0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB34_2: // %e
-; CHECK-NEXT: fmov d0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv4f16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB34_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov d1, d0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB34_2: // %e
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv4f16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov d2, d0
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB34_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov d0, d2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB34_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -1042,15 +1224,26 @@ e:
}
define <8 x half> @tv8f16(i1 %c, ptr %p, <8 x half> %a, <8 x half> %b) {
-; CHECK-LABEL: tv8f16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB35_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB35_2: // %e
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv8f16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB35_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB35_2: // %e
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv8f16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov v2.16b, v0.16b
+; CHECK-GI-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NEXT: tbz w0, #0, .LBB35_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB35_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -1077,14 +1270,15 @@ define <16 x half> @tv16f16(i1 %c, ptr %p, <16 x half> %a, <16 x half> %b) {
; CHECK-GI-LABEL: tv16f16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v4.16b, v0.16b
+; CHECK-GI-NEXT: mov v5.16b, v1.16b
; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: tbz w0, #0, .LBB36_2
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: mov v0.16b, v4.16b
-; CHECK-GI-NEXT: mov v3.16b, v1.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
; CHECK-GI-NEXT: str wzr, [x1]
; CHECK-GI-NEXT: .LBB36_2: // %e
-; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -1097,15 +1291,26 @@ e:
}
define <2 x float> @tv2f32(i1 %c, ptr %p, <2 x float> %a, <2 x float> %b) {
-; CHECK-LABEL: tv2f32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB37_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: fmov d1, d0
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB37_2: // %e
-; CHECK-NEXT: fmov d0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv2f32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB37_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: fmov d1, d0
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB37_2: // %e
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv2f32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov d2, d0
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: tbz w0, #0, .LBB37_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: fmov d0, d2
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB37_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -1117,15 +1322,26 @@ e:
}
define <3 x float> @tv3f32(i1 %c, ptr %p, <3 x float> %a, <3 x float> %b) {
-; CHECK-LABEL: tv3f32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB38_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB38_2: // %e
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv3f32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB38_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB38_2: // %e
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv3f32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov v2.16b, v0.16b
+; CHECK-GI-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NEXT: tbz w0, #0, .LBB38_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB38_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -1137,15 +1353,26 @@ e:
}
define <4 x float> @tv4f32(i1 %c, ptr %p, <4 x float> %a, <4 x float> %b) {
-; CHECK-LABEL: tv4f32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB39_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB39_2: // %e
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv4f32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB39_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB39_2: // %e
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv4f32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov v2.16b, v0.16b
+; CHECK-GI-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NEXT: tbz w0, #0, .LBB39_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB39_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -1172,14 +1399,15 @@ define <8 x float> @tv8f32(i1 %c, ptr %p, <8 x float> %a, <8 x float> %b) {
; CHECK-GI-LABEL: tv8f32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v4.16b, v0.16b
+; CHECK-GI-NEXT: mov v5.16b, v1.16b
; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: tbz w0, #0, .LBB40_2
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: mov v0.16b, v4.16b
-; CHECK-GI-NEXT: mov v3.16b, v1.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
; CHECK-GI-NEXT: str wzr, [x1]
; CHECK-GI-NEXT: .LBB40_2: // %e
-; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -1192,15 +1420,26 @@ e:
}
define <2 x double> @tv2f64(i1 %c, ptr %p, <2 x double> %a, <2 x double> %b) {
-; CHECK-LABEL: tv2f64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: tbz w0, #0, .LBB41_2
-; CHECK-NEXT: // %bb.1: // %t
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: str wzr, [x1]
-; CHECK-NEXT: .LBB41_2: // %e
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: tv2f64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tbz w0, #0, .LBB41_2
+; CHECK-SD-NEXT: // %bb.1: // %t
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: str wzr, [x1]
+; CHECK-SD-NEXT: .LBB41_2: // %e
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: tv2f64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov v2.16b, v0.16b
+; CHECK-GI-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NEXT: tbz w0, #0, .LBB41_2
+; CHECK-GI-NEXT: // %bb.1: // %t
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: str wzr, [x1]
+; CHECK-GI-NEXT: .LBB41_2: // %e
+; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
t:
@@ -1285,14 +1524,15 @@ define <4 x double> @tv4f64(i1 %c, ptr %p, <4 x double> %a, <4 x double> %b) {
; CHECK-GI-LABEL: tv4f64:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v4.16b, v0.16b
+; CHECK-GI-NEXT: mov v5.16b, v1.16b
; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: tbz w0, #0, .LBB43_2
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: mov v0.16b, v4.16b
-; CHECK-GI-NEXT: mov v3.16b, v1.16b
+; CHECK-GI-NEXT: mov v1.16b, v5.16b
; CHECK-GI-NEXT: str wzr, [x1]
; CHECK-GI-NEXT: .LBB43_2: // %e
-; CHECK-GI-NEXT: mov v1.16b, v3.16b
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -1349,3 +1589,5 @@ e:
%h = phi <2 x fp128> [%a, %t], [%b, %entry]
ret <2 x fp128> %h
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/pr164181.ll b/llvm/test/CodeGen/AArch64/pr164181.ll
index 7695e3fd61a84..972ce203611b3 100644
--- a/llvm/test/CodeGen/AArch64/pr164181.ll
+++ b/llvm/test/CodeGen/AArch64/pr164181.ll
@@ -37,26 +37,26 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: // %bb.2: // %for.body41.us.preheader
; CHECK-NEXT: ldrb w8, [sp, #368]
; CHECK-NEXT: ldrb w12, [sp, #256]
-; CHECK-NEXT: ldr w26, [sp, #264]
-; CHECK-NEXT: adrp x20, :got:var_50
-; CHECK-NEXT: mov x28, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov w21, #36006 // =0x8ca6
+; CHECK-NEXT: ldr w3, [sp, #264]
+; CHECK-NEXT: adrp x23, :got:var_50
+; CHECK-NEXT: add x26, x14, #120
+; CHECK-NEXT: mov x30, #-1 // =0xffffffffffffffff
; CHECK-NEXT: ldr x11, [sp, #376]
; CHECK-NEXT: ldrb w13, [sp, #360]
; CHECK-NEXT: ldp x17, x16, [sp, #296]
-; CHECK-NEXT: mov w22, #1 // =0x1
-; CHECK-NEXT: add x27, x14, #120
+; CHECK-NEXT: mov w20, #36006 // =0x8ca6
+; CHECK-NEXT: mov w21, #1 // =0x1
; CHECK-NEXT: ldr x18, [sp, #288]
; CHECK-NEXT: ldr x7, [sp, #272]
; CHECK-NEXT: ldr x5, [sp, #248]
+; CHECK-NEXT: add x22, x14, #120
; CHECK-NEXT: mov x10, xzr
-; CHECK-NEXT: mov w23, wzr
-; CHECK-NEXT: mov w30, wzr
+; CHECK-NEXT: mov w27, wzr
; CHECK-NEXT: ldrb w19, [sp, #240]
+; CHECK-NEXT: mov w28, wzr
; CHECK-NEXT: mov w25, wzr
; CHECK-NEXT: mov x24, xzr
; CHECK-NEXT: str w8, [sp, #108] // 4-byte Spill
-; CHECK-NEXT: mov x3, x26
; CHECK-NEXT: ldp x9, x8, [sp, #344]
; CHECK-NEXT: str w12, [sp, #92] // 4-byte Spill
; CHECK-NEXT: mov w12, #1 // =0x1
@@ -67,23 +67,22 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: ldp x9, x15, [sp, #328]
; CHECK-NEXT: madd x8, x8, x12, x9
; CHECK-NEXT: str x8, [sp, #64] // 8-byte Spill
-; CHECK-NEXT: add x8, x26, w26, uxtw #1
-; CHECK-NEXT: ldr x20, [x20, :got_lo12:var_50]
-; CHECK-NEXT: str x26, [sp, #96] // 8-byte Spill
-; CHECK-NEXT: str x14, [sp, #152] // 8-byte Spill
+; CHECK-NEXT: add x8, x3, w3, uxtw #1
+; CHECK-NEXT: ldr x23, [x23, :got_lo12:var_50]
+; CHECK-NEXT: str x3, [sp, #96] // 8-byte Spill
+; CHECK-NEXT: str x26, [sp, #80] // 8-byte Spill
; CHECK-NEXT: lsl x6, x8, #3
-; CHECK-NEXT: add x8, x14, #120
+; CHECK-NEXT: str x14, [sp, #152] // 8-byte Spill
; CHECK-NEXT: str x4, [sp, #24] // 8-byte Spill
; CHECK-NEXT: str w19, [sp, #16] // 4-byte Spill
-; CHECK-NEXT: str x8, [sp, #80] // 8-byte Spill
; CHECK-NEXT: b .LBB0_4
; CHECK-NEXT: .p2align 5, , 16
; CHECK-NEXT: .LBB0_3: // in Loop: Header=BB0_4 Depth=1
; CHECK-NEXT: ldr w19, [sp, #16] // 4-byte Reload
; CHECK-NEXT: ldr x24, [sp, #40] // 8-byte Reload
; CHECK-NEXT: ldr x14, [sp, #152] // 8-byte Reload
-; CHECK-NEXT: mov w23, #1 // =0x1
-; CHECK-NEXT: mov w30, #1 // =0x1
+; CHECK-NEXT: mov w27, #1 // =0x1
+; CHECK-NEXT: mov w28, #1 // =0x1
; CHECK-NEXT: mov w25, w19
; CHECK-NEXT: .LBB0_4: // %for.body41.us
; CHECK-NEXT: // =>This Loop Header: Depth=1
@@ -106,7 +105,7 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: ldr w9, [sp, #36] // 4-byte Reload
; CHECK-NEXT: ldr x4, [sp, #24] // 8-byte Reload
; CHECK-NEXT: ldp x24, x12, [sp, #48] // 16-byte Folded Reload
-; CHECK-NEXT: mov x22, xzr
+; CHECK-NEXT: mov x21, xzr
; CHECK-NEXT: mov w25, wzr
; CHECK-NEXT: mov w8, wzr
; CHECK-NEXT: tbz w9, #0, .LBB0_3
@@ -124,16 +123,16 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: add x19, x4, w8, sxtw #2
; CHECK-NEXT: mov x9, xzr
; CHECK-NEXT: csel x12, x24, x12, lo
-; CHECK-NEXT: mov w4, w30
+; CHECK-NEXT: mov w4, w28
; CHECK-NEXT: str x12, [sp, #56] // 8-byte Spill
; CHECK-NEXT: b .LBB0_8
; CHECK-NEXT: .p2align 5, , 16
; CHECK-NEXT: .LBB0_7: // %for.cond.cleanup98.us
; CHECK-NEXT: // in Loop: Header=BB0_8 Depth=3
; CHECK-NEXT: ldr w4, [sp, #72] // 4-byte Reload
-; CHECK-NEXT: ldr w23, [sp, #128] // 4-byte Reload
+; CHECK-NEXT: ldr w27, [sp, #128] // 4-byte Reload
; CHECK-NEXT: mov w9, #1 // =0x1
-; CHECK-NEXT: mov x22, xzr
+; CHECK-NEXT: mov x21, xzr
; CHECK-NEXT: tbnz w0, #0, .LBB0_5
; CHECK-NEXT: .LBB0_8: // %for.cond95.preheader.us
; CHECK-NEXT: // Parent Loop BB0_4 Depth=1
@@ -148,24 +147,24 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: mov w24, #1 // =0x1
; CHECK-NEXT: mov w12, wzr
; CHECK-NEXT: str wzr, [sp, #132] // 4-byte Spill
-; CHECK-NEXT: mov w30, w4
+; CHECK-NEXT: mov w28, w4
; CHECK-NEXT: madd x8, x9, x14, x8
; CHECK-NEXT: mov w14, #1 // =0x1
; CHECK-NEXT: str x8, [sp, #120] // 8-byte Spill
; CHECK-NEXT: add x8, x9, x9, lsl #1
; CHECK-NEXT: lsl x26, x8, #4
-; CHECK-NEXT: sxtb w8, w23
-; CHECK-NEXT: mov w23, w25
+; CHECK-NEXT: sxtb w8, w27
+; CHECK-NEXT: mov w27, w25
; CHECK-NEXT: str w8, [sp, #116] // 4-byte Spill
; CHECK-NEXT: b .LBB0_10
; CHECK-NEXT: .p2align 5, , 16
; CHECK-NEXT: .LBB0_9: // %for.cond510.preheader.us
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
-; CHECK-NEXT: ldr w23, [sp, #92] // 4-byte Reload
-; CHECK-NEXT: mov x22, x8
+; CHECK-NEXT: ldr w27, [sp, #92] // 4-byte Reload
+; CHECK-NEXT: mov x21, x8
; CHECK-NEXT: ldr x3, [sp, #96] // 8-byte Reload
-; CHECK-NEXT: ldr x27, [sp, #80] // 8-byte Reload
-; CHECK-NEXT: mov x28, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ldr x22, [sp, #80] // 8-byte Reload
+; CHECK-NEXT: mov x30, #-1 // =0xffffffffffffffff
; CHECK-NEXT: mov x14, xzr
; CHECK-NEXT: ldr w8, [sp, #76] // 4-byte Reload
; CHECK-NEXT: tbz w8, #31, .LBB0_7
@@ -198,15 +197,16 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: cbnz w4, .LBB0_14
; CHECK-NEXT: // %bb.13: // %cond.true146.us
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
-; CHECK-NEXT: ldrsb w4, [x27, x3]
+; CHECK-NEXT: ldrsb w4, [x22, x3]
; CHECK-NEXT: b .LBB0_15
; CHECK-NEXT: .p2align 5, , 16
; CHECK-NEXT: .LBB0_14: // in Loop: Header=BB0_10 Depth=4
; CHECK-NEXT: mov w4, wzr
; CHECK-NEXT: .LBB0_15: // %cond.end154.us
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
-; CHECK-NEXT: mov w25, #18984 // =0x4a28
-; CHECK-NEXT: mul w8, w8, w25
+; CHECK-NEXT: mov w25, w27
+; CHECK-NEXT: mov w27, #18984 // =0x4a28
+; CHECK-NEXT: mul w8, w8, w27
; CHECK-NEXT: and w8, w8, #0xfff8
; CHECK-NEXT: lsl w8, w8, w4
; CHECK-NEXT: cbz w8, .LBB0_17
@@ -217,13 +217,13 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: .LBB0_17: // %if.end.us
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
; CHECK-NEXT: ldr w8, [sp, #108] // 4-byte Reload
-; CHECK-NEXT: mov w4, #18984 // =0x4a28
-; CHECK-NEXT: mov w25, w23
-; CHECK-NEXT: strb w8, [x18]
-; CHECK-NEXT: ldrsb w8, [x27, x3]
-; CHECK-NEXT: lsl w8, w4, w8
+; CHECK-NEXT: mov x27, x3
; CHECK-NEXT: mov x4, #-18403 // =0xffffffffffffb81d
; CHECK-NEXT: movk x4, #58909, lsl #16
+; CHECK-NEXT: strb w8, [x18]
+; CHECK-NEXT: ldrsb w8, [x22, x3]
+; CHECK-NEXT: mov w3, #18984 // =0x4a28
+; CHECK-NEXT: lsl w8, w3, w8
; CHECK-NEXT: cbz w8, .LBB0_19
; CHECK-NEXT: // %bb.18: // %if.then.us.2
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
@@ -231,12 +231,12 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: strb wzr, [x18]
; CHECK-NEXT: .LBB0_19: // %if.then.us.5
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
-; CHECK-NEXT: ldr w23, [sp, #132] // 4-byte Reload
+; CHECK-NEXT: ldr w3, [sp, #132] // 4-byte Reload
; CHECK-NEXT: mov w8, #29625 // =0x73b9
; CHECK-NEXT: movk w8, #21515, lsl #16
-; CHECK-NEXT: cmp w23, w8
-; CHECK-NEXT: csel w23, w23, w8, lt
-; CHECK-NEXT: str w23, [sp, #132] // 4-byte Spill
+; CHECK-NEXT: cmp w3, w8
+; CHECK-NEXT: csel w3, w3, w8, lt
+; CHECK-NEXT: str w3, [sp, #132] // 4-byte Spill
; CHECK-NEXT: tbz w0, #0, .LBB0_21
; CHECK-NEXT: // %bb.20: // in Loop: Header=BB0_10 Depth=4
; CHECK-NEXT: mov w8, wzr
@@ -244,12 +244,12 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: .p2align 5, , 16
; CHECK-NEXT: .LBB0_21: // %cond.true146.us.7
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
-; CHECK-NEXT: ldrsb w8, [x27, x3]
+; CHECK-NEXT: ldrsb w8, [x22, x27]
; CHECK-NEXT: .LBB0_22: // %cond.end154.us.7
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
-; CHECK-NEXT: mov w23, #18984 // =0x4a28
+; CHECK-NEXT: mov w22, #18984 // =0x4a28
; CHECK-NEXT: mov w3, #149 // =0x95
-; CHECK-NEXT: lsl w8, w23, w8
+; CHECK-NEXT: lsl w8, w22, w8
; CHECK-NEXT: cbz w8, .LBB0_24
; CHECK-NEXT: // %bb.23: // %if.then.us.7
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
@@ -258,7 +258,7 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: str wzr, [x8]
; CHECK-NEXT: .LBB0_24: // %if.end.us.7
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
-; CHECK-NEXT: mov x23, xzr
+; CHECK-NEXT: mov x22, xzr
; CHECK-NEXT: b .LBB0_28
; CHECK-NEXT: .p2align 5, , 16
; CHECK-NEXT: .LBB0_25: // %cond.true331.us
@@ -267,20 +267,20 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: .LBB0_26: // %cond.end345.us
; CHECK-NEXT: // in Loop: Header=BB0_28 Depth=5
; CHECK-NEXT: strh w4, [x18]
-; CHECK-NEXT: mul x4, x22, x28
-; CHECK-NEXT: adrp x22, :got:var_46
+; CHECK-NEXT: mul x4, x21, x30
+; CHECK-NEXT: adrp x21, :got:var_46
; CHECK-NEXT: mov x8, xzr
-; CHECK-NEXT: ldr x22, [x22, :got_lo12:var_46]
-; CHECK-NEXT: str x4, [x22]
+; CHECK-NEXT: ldr x21, [x21, :got_lo12:var_46]
+; CHECK-NEXT: str x4, [x21]
; CHECK-NEXT: mov x4, #-18403 // =0xffffffffffffb81d
; CHECK-NEXT: movk x4, #58909, lsl #16
; CHECK-NEXT: .LBB0_27: // %for.inc371.us
; CHECK-NEXT: // in Loop: Header=BB0_28 Depth=5
-; CHECK-NEXT: mov w22, #-18978 // =0xffffb5de
-; CHECK-NEXT: orr x23, x23, #0x1
+; CHECK-NEXT: mov w21, #-18978 // =0xffffb5de
+; CHECK-NEXT: orr x22, x22, #0x1
; CHECK-NEXT: mov x24, xzr
-; CHECK-NEXT: mul w12, w12, w22
-; CHECK-NEXT: mov x22, x5
+; CHECK-NEXT: mul w12, w12, w21
+; CHECK-NEXT: mov x21, x5
; CHECK-NEXT: tbz w0, #0, .LBB0_33
; CHECK-NEXT: .LBB0_28: // %if.then222.us
; CHECK-NEXT: // Parent Loop BB0_4 Depth=1
@@ -327,29 +327,29 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: .LBB0_33: // %for.cond376.preheader.us
; CHECK-NEXT: // in Loop: Header=BB0_10 Depth=4
; CHECK-NEXT: mov w3, #1152 // =0x480
-; CHECK-NEXT: mov x22, xzr
+; CHECK-NEXT: mov x21, xzr
; CHECK-NEXT: mov w4, wzr
; CHECK-NEXT: mov x24, x27
-; CHECK-NEXT: lsl x23, x14, #1
+; CHECK-NEXT: lsl x22, x14, #1
; CHECK-NEXT: mov x27, #-1 // =0xffffffffffffffff
; CHECK-NEXT: madd x14, x14, x3, x11
-; CHECK-NEXT: mov w28, w30
+; CHECK-NEXT: mov w30, w28
; CHECK-NEXT: mov w3, #-7680 // =0xffffe200
; CHECK-NEXT: b .LBB0_36
; CHECK-NEXT: .p2align 5, , 16
; CHECK-NEXT: .LBB0_34: // %if.then466.us
; CHECK-NEXT: // in Loop: Header=BB0_36 Depth=5
-; CHECK-NEXT: ldr x28, [sp, #152] // 8-byte Reload
+; CHECK-NEXT: ldr x30, [sp, #152] // 8-byte Reload
; CHECK-NEXT: ldr x3, [sp, #136] // 8-byte Reload
; CHECK-NEXT: sxtb w4, w4
; CHECK-NEXT: bic w4, w4, w4, asr #31
-; CHECK-NEXT: str x3, [x28]
+; CHECK-NEXT: str x3, [x30]
; CHECK-NEXT: mov w3, #-7680 // =0xffffe200
; CHECK-NEXT: .LBB0_35: // %for.inc505.us
; CHECK-NEXT: // in Loop: Header=BB0_36 Depth=5
-; CHECK-NEXT: add x22, x22, #1
+; CHECK-NEXT: add x21, x21, #1
; CHECK-NEXT: adds x27, x27, #1
-; CHECK-NEXT: mov w28, wzr
+; CHECK-NEXT: mov w30, wzr
; CHECK-NEXT: b.ne .LBB0_9
; CHECK-NEXT: .LBB0_36: // %for.body380.us
; CHECK-NEXT: // Parent Loop BB0_4 Depth=1
@@ -357,17 +357,17 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: // Parent Loop BB0_8 Depth=3
; CHECK-NEXT: // Parent Loop BB0_10 Depth=4
; CHECK-NEXT: // => This Inner Loop Header: Depth=5
-; CHECK-NEXT: mov w30, w28
-; CHECK-NEXT: ldrh w28, [x23]
+; CHECK-NEXT: mov w28, w30
+; CHECK-NEXT: ldrh w30, [x22]
; CHECK-NEXT: tst w0, #0x1
-; CHECK-NEXT: strh w28, [x11]
-; CHECK-NEXT: csel w28, w21, w3, ne
-; CHECK-NEXT: str w28, [x20]
+; CHECK-NEXT: strh w30, [x11]
+; CHECK-NEXT: csel w30, w20, w3, ne
+; CHECK-NEXT: str w30, [x23]
; CHECK-NEXT: cbz x15, .LBB0_35
; CHECK-NEXT: // %bb.37: // %if.then436.us
; CHECK-NEXT: // in Loop: Header=BB0_36 Depth=5
-; CHECK-NEXT: ldrh w28, [x14]
-; CHECK-NEXT: cbnz w28, .LBB0_34
+; CHECK-NEXT: ldrh w30, [x14]
+; CHECK-NEXT: cbnz w30, .LBB0_34
; CHECK-NEXT: // %bb.38: // in Loop: Header=BB0_36 Depth=5
; CHECK-NEXT: mov w4, wzr
; CHECK-NEXT: b .LBB0_35
diff --git a/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll b/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
index 9f513a940015e..bda6cd5258e68 100644
--- a/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
+++ b/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
@@ -25,148 +25,152 @@ define dso_local void @run_test() local_unnamed_addr uwtable {
; CHECK-NEXT: .cfi_offset b13, -64
; CHECK-NEXT: .cfi_offset b14, -72
; CHECK-NEXT: .cfi_offset b15, -80
-; CHECK-NEXT: movi v7.2d, #0000000000000000
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: adrp x14, B+48
; CHECK-NEXT: add x14, x14, :lo12:B+48
-; CHECK-NEXT: // implicit-def: $q18
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: mov w9, #8 // =0x8
; CHECK-NEXT: adrp x10, A
; CHECK-NEXT: add x10, x10, :lo12:A
; CHECK-NEXT: mov x11, xzr
-; CHECK-NEXT: // kill: killed $q18
-; CHECK-NEXT: // implicit-def: $q18
+; CHECK-NEXT: // implicit-def: $q7
; CHECK-NEXT: mov x12, xzr
; CHECK-NEXT: mov x13, x14
-; CHECK-NEXT: // implicit-def: $q0
+; CHECK-NEXT: // implicit-def: $q18
; CHECK-NEXT: // implicit-def: $q2
; CHECK-NEXT: // implicit-def: $q3
; CHECK-NEXT: // implicit-def: $q4
; CHECK-NEXT: // implicit-def: $q5
-; CHECK-NEXT: // implicit-def: $q1
+; CHECK-NEXT: // implicit-def: $q6
; CHECK-NEXT: // implicit-def: $q16
; CHECK-NEXT: // implicit-def: $q17
-; CHECK-NEXT: // implicit-def: $q6
+; CHECK-NEXT: // implicit-def: $q10
; CHECK-NEXT: // implicit-def: $q19
; CHECK-NEXT: // implicit-def: $q20
; CHECK-NEXT: // implicit-def: $q21
; CHECK-NEXT: // implicit-def: $q22
; CHECK-NEXT: // implicit-def: $q12
-; CHECK-NEXT: // implicit-def: $q23
+; CHECK-NEXT: // implicit-def: $q11
; CHECK-NEXT: // implicit-def: $q25
; CHECK-NEXT: // implicit-def: $q26
; CHECK-NEXT: // implicit-def: $q27
; CHECK-NEXT: // implicit-def: $q30
; CHECK-NEXT: // implicit-def: $q8
-; CHECK-NEXT: // implicit-def: $q11
+; CHECK-NEXT: // implicit-def: $q9
; CHECK-NEXT: // implicit-def: $q28
+; CHECK-NEXT: // implicit-def: $q23
+; CHECK-NEXT: // implicit-def: $q31
; CHECK-NEXT: // implicit-def: $q29
-; CHECK-NEXT: // implicit-def: $q13
-; CHECK-NEXT: // implicit-def: $q10
; CHECK-NEXT: // implicit-def: $q15
-; CHECK-NEXT: // kill: killed $q18
-; CHECK-NEXT: // implicit-def: $q18
-; CHECK-NEXT: // kill: killed $q18
+; CHECK-NEXT: // kill: killed $q7
+; CHECK-NEXT: // implicit-def: $q7
+; CHECK-NEXT: // kill: killed $q7
+; CHECK-NEXT: // implicit-def: $q13
; CHECK-NEXT: .LBB0_1: // %for.cond1.preheader
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr x18, [x8]
; CHECK-NEXT: ldr x15, [x8]
-; CHECK-NEXT: mov v18.16b, v0.16b
-; CHECK-NEXT: ldr x16, [x9]
-; CHECK-NEXT: stp q15, q4, [sp] // 32-byte Folded Spill
; CHECK-NEXT: add x5, x10, x11
+; CHECK-NEXT: ldr x16, [x9]
+; CHECK-NEXT: ldr x14, [x14, #8]
+; CHECK-NEXT: mov v7.16b, v1.16b
; CHECK-NEXT: mul x1, x18, x15
; CHECK-NEXT: ldr x2, [x13], #64
-; CHECK-NEXT: stp q6, q23, [sp, #32] // 32-byte Folded Spill
-; CHECK-NEXT: ldr q23, [sp, #80] // 16-byte Reload
-; CHECK-NEXT: ldr x14, [x14, #8]
-; CHECK-NEXT: mul x0, x18, x18
; CHECK-NEXT: ldr x5, [x5, #128]
+; CHECK-NEXT: stp q29, q23, [sp] // 32-byte Folded Spill
+; CHECK-NEXT: mov v29.16b, v15.16b
+; CHECK-NEXT: mul x0, x18, x18
+; CHECK-NEXT: str q11, [sp, #64] // 16-byte Spill
+; CHECK-NEXT: mov v11.16b, v9.16b
; CHECK-NEXT: mov v9.16b, v30.16b
; CHECK-NEXT: mov v30.16b, v25.16b
; CHECK-NEXT: mov v25.16b, v20.16b
-; CHECK-NEXT: mov v20.16b, v1.16b
; CHECK-NEXT: mul x17, x16, x18
+; CHECK-NEXT: mov v20.16b, v6.16b
+; CHECK-NEXT: mov v6.16b, v13.16b
+; CHECK-NEXT: fmov d14, x1
+; CHECK-NEXT: ldr q13, [sp, #80] // 16-byte Reload
+; CHECK-NEXT: mov v23.16b, v31.16b
+; CHECK-NEXT: mul x3, x14, x18
; CHECK-NEXT: mov v31.16b, v26.16b
; CHECK-NEXT: mov v26.16b, v21.16b
-; CHECK-NEXT: fmov d14, x1
+; CHECK-NEXT: fmov d15, x0
; CHECK-NEXT: mov v21.16b, v16.16b
; CHECK-NEXT: mov v16.16b, v2.16b
+; CHECK-NEXT: mov v0.16b, v14.16b
; CHECK-NEXT: mul x4, x2, x18
-; CHECK-NEXT: mov v6.16b, v10.16b
+; CHECK-NEXT: stp q4, q10, [sp, #32] // 32-byte Folded Spill
; CHECK-NEXT: mov v10.16b, v17.16b
-; CHECK-NEXT: fmov d15, x0
; CHECK-NEXT: mov v17.16b, v3.16b
; CHECK-NEXT: mov v24.16b, v19.16b
-; CHECK-NEXT: mov v0.16b, v14.16b
-; CHECK-NEXT: mul x3, x14, x18
+; CHECK-NEXT: mul x18, x18, x5
+; CHECK-NEXT: mov v15.d[1], x17
; CHECK-NEXT: mov v19.16b, v5.16b
+; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: add x11, x11, #8
; CHECK-NEXT: add x12, x12, #1
-; CHECK-NEXT: mov v15.d[1], x17
; CHECK-NEXT: mul x6, x15, x15
; CHECK-NEXT: cmp x11, #64
-; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov d1, x4
; CHECK-NEXT: mul x7, x15, x5
-; CHECK-NEXT: mul x18, x18, x5
+; CHECK-NEXT: fmov d2, x18
+; CHECK-NEXT: add v13.2d, v13.2d, v0.2d
+; CHECK-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-NEXT: mul x19, x16, x5
; CHECK-NEXT: mov v1.d[1], x3
-; CHECK-NEXT: add v23.2d, v23.2d, v0.2d
-; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-NEXT: fmov d4, x6
-; CHECK-NEXT: mul x20, x2, x5
; CHECK-NEXT: add v0.2d, v0.2d, v15.2d
+; CHECK-NEXT: mul x20, x2, x5
+; CHECK-NEXT: str q13, [sp, #80] // 16-byte Spill
+; CHECK-NEXT: add v13.2d, v6.2d, v15.2d
; CHECK-NEXT: fmov d3, x7
-; CHECK-NEXT: mul x19, x16, x5
-; CHECK-NEXT: mov v4.d[1], x6
-; CHECK-NEXT: fmov d2, x18
+; CHECK-NEXT: mov v6.16b, v20.16b
+; CHECK-NEXT: mov v20.16b, v25.16b
; CHECK-NEXT: mul x0, x14, x5
-; CHECK-NEXT: stp q0, q23, [sp, #64] // 32-byte Folded Spill
-; CHECK-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-NEXT: fmov d5, x20
-; CHECK-NEXT: mov v3.d[1], x7
-; CHECK-NEXT: ldr q23, [sp, #48] // 16-byte Reload
-; CHECK-NEXT: mul x17, x2, x15
-; CHECK-NEXT: add v0.2d, v0.2d, v15.2d
-; CHECK-NEXT: ldr q15, [sp] // 16-byte Reload
+; CHECK-NEXT: mov v4.d[1], x6
+; CHECK-NEXT: str q0, [sp, #96] // 16-byte Spill
; CHECK-NEXT: mov v2.d[1], x19
-; CHECK-NEXT: add v13.2d, v13.2d, v4.2d
-; CHECK-NEXT: add v12.2d, v12.2d, v4.2d
+; CHECK-NEXT: mov v25.16b, v30.16b
+; CHECK-NEXT: mov v30.16b, v9.16b
+; CHECK-NEXT: mul x17, x2, x15
+; CHECK-NEXT: mov v3.d[1], x7
+; CHECK-NEXT: add v15.2d, v29.2d, v1.2d
+; CHECK-NEXT: fmov d5, x20
; CHECK-NEXT: mul x16, x16, x15
-; CHECK-NEXT: add v15.2d, v15.2d, v1.2d
-; CHECK-NEXT: mov v1.16b, v20.16b
-; CHECK-NEXT: mov v5.d[1], x0
-; CHECK-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-NEXT: mov v20.16b, v25.16b
+; CHECK-NEXT: add v12.2d, v12.2d, v4.2d
+; CHECK-NEXT: add v6.2d, v6.2d, v4.2d
+; CHECK-NEXT: add v8.2d, v8.2d, v2.2d
+; CHECK-NEXT: mov v2.16b, v16.16b
+; CHECK-NEXT: mov v16.16b, v21.16b
; CHECK-NEXT: mul x14, x14, x15
-; CHECK-NEXT: mov v25.16b, v30.16b
-; CHECK-NEXT: add v11.2d, v11.2d, v3.2d
+; CHECK-NEXT: mov v5.d[1], x0
+; CHECK-NEXT: mov v21.16b, v26.16b
; CHECK-NEXT: fmov d0, x17
+; CHECK-NEXT: mov v26.16b, v31.16b
+; CHECK-NEXT: add v9.2d, v11.2d, v3.2d
; CHECK-NEXT: mov v3.16b, v17.16b
; CHECK-NEXT: mov v17.16b, v10.16b
-; CHECK-NEXT: mov v10.16b, v6.16b
-; CHECK-NEXT: add v8.2d, v8.2d, v2.2d
-; CHECK-NEXT: mov v2.16b, v16.16b
+; CHECK-NEXT: add v31.2d, v23.2d, v4.2d
; CHECK-NEXT: mov v14.d[1], x16
-; CHECK-NEXT: mov v16.16b, v21.16b
-; CHECK-NEXT: mov v21.16b, v26.16b
-; CHECK-NEXT: add v30.2d, v9.2d, v5.2d
+; CHECK-NEXT: add v1.2d, v7.2d, v4.2d
+; CHECK-NEXT: ldr q11, [sp, #64] // 16-byte Reload
+; CHECK-NEXT: add v30.2d, v30.2d, v5.2d
; CHECK-NEXT: mov v5.16b, v19.16b
-; CHECK-NEXT: add v26.2d, v31.2d, v4.2d
+; CHECK-NEXT: add v26.2d, v26.2d, v4.2d
; CHECK-NEXT: mov v0.d[1], x14
; CHECK-NEXT: add v19.2d, v24.2d, v4.2d
-; CHECK-NEXT: add v1.2d, v1.2d, v4.2d
-; CHECK-NEXT: add v7.2d, v7.2d, v4.2d
-; CHECK-NEXT: ldp q4, q6, [sp, #16] // 32-byte Folded Reload
-; CHECK-NEXT: add v10.2d, v10.2d, v14.2d
-; CHECK-NEXT: add v29.2d, v29.2d, v14.2d
+; CHECK-NEXT: mov x14, x13
+; CHECK-NEXT: ldp q4, q10, [sp, #32] // 32-byte Folded Reload
+; CHECK-NEXT: ldp q29, q23, [sp] // 32-byte Folded Reload
; CHECK-NEXT: add v27.2d, v27.2d, v14.2d
-; CHECK-NEXT: add v23.2d, v23.2d, v14.2d
+; CHECK-NEXT: add v11.2d, v11.2d, v14.2d
; CHECK-NEXT: add v22.2d, v22.2d, v14.2d
; CHECK-NEXT: add v20.2d, v20.2d, v14.2d
-; CHECK-NEXT: add v6.2d, v6.2d, v14.2d
+; CHECK-NEXT: add v10.2d, v10.2d, v14.2d
; CHECK-NEXT: add v16.2d, v16.2d, v14.2d
; CHECK-NEXT: add v5.2d, v5.2d, v14.2d
+; CHECK-NEXT: add v29.2d, v29.2d, v14.2d
+; CHECK-NEXT: add v23.2d, v23.2d, v14.2d
; CHECK-NEXT: add v3.2d, v3.2d, v14.2d
; CHECK-NEXT: add v2.2d, v2.2d, v14.2d
; CHECK-NEXT: add v28.2d, v28.2d, v0.2d
@@ -174,35 +178,33 @@ define dso_local void @run_test() local_unnamed_addr uwtable {
; CHECK-NEXT: add v21.2d, v21.2d, v0.2d
; CHECK-NEXT: add v17.2d, v17.2d, v0.2d
; CHECK-NEXT: add v4.2d, v4.2d, v0.2d
-; CHECK-NEXT: add v0.2d, v18.2d, v0.2d
-; CHECK-NEXT: mov x14, x13
+; CHECK-NEXT: add v18.2d, v18.2d, v0.2d
; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %for.cond.cleanup
-; CHECK-NEXT: ldp q24, q18, [sp, #64] // 32-byte Folded Reload
+; CHECK-NEXT: ldp q0, q7, [sp, #80] // 32-byte Folded Reload
; CHECK-NEXT: adrp x8, C
; CHECK-NEXT: add x8, x8, :lo12:C
; CHECK-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
-; CHECK-NEXT: stp q10, q13, [x8, #64]
-; CHECK-NEXT: stp q24, q18, [x8]
-; CHECK-NEXT: ldr q18, [sp, #96] // 16-byte Reload
-; CHECK-NEXT: stp q29, q28, [x8, #96]
-; CHECK-NEXT: stp q18, q15, [x8, #32]
+; CHECK-NEXT: stp q29, q31, [x8, #64]
+; CHECK-NEXT: stp q13, q0, [x8]
+; CHECK-NEXT: stp q7, q15, [x8, #32]
; CHECK-NEXT: ldp d15, d14, [sp, #112] // 16-byte Folded Reload
-; CHECK-NEXT: stp q11, q8, [x8, #144]
+; CHECK-NEXT: stp q23, q28, [x8, #96]
+; CHECK-NEXT: stp q9, q8, [x8, #144]
; CHECK-NEXT: ldp d9, d8, [sp, #160] // 16-byte Folded Reload
+; CHECK-NEXT: stp q30, q27, [x8, #176]
+; CHECK-NEXT: stp q25, q11, [x8, #240]
; CHECK-NEXT: stp q12, q22, [x8, #272]
-; CHECK-NEXT: ldp d11, d10, [sp, #144] // 16-byte Folded Reload
; CHECK-NEXT: ldp d13, d12, [sp, #128] // 16-byte Folded Reload
-; CHECK-NEXT: stp q30, q27, [x8, #176]
-; CHECK-NEXT: str q26, [x8, #208]
-; CHECK-NEXT: stp q25, q23, [x8, #240]
; CHECK-NEXT: stp q21, q20, [x8, #304]
-; CHECK-NEXT: stp q19, q6, [x8, #336]
+; CHECK-NEXT: stp q19, q10, [x8, #336]
+; CHECK-NEXT: ldp d11, d10, [sp, #144] // 16-byte Folded Reload
+; CHECK-NEXT: str q26, [x8, #208]
; CHECK-NEXT: stp q17, q16, [x8, #368]
-; CHECK-NEXT: stp q1, q5, [x8, #400]
+; CHECK-NEXT: stp q6, q5, [x8, #400]
; CHECK-NEXT: stp q4, q3, [x8, #432]
-; CHECK-NEXT: stp q7, q2, [x8, #464]
-; CHECK-NEXT: str q0, [x8, #496]
+; CHECK-NEXT: stp q1, q2, [x8, #464]
+; CHECK-NEXT: str q18, [x8, #496]
; CHECK-NEXT: add sp, sp, #192
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w19
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
index 267efaad60c79..a06d8303ffe78 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
@@ -222,11 +222,11 @@
; GCN-O2-NEXT: process-imp-defs
; GCN-O2-NEXT: unreachable-mbb-elimination
; GCN-O2-NEXT: require<live-vars>
+; GCN-O2-NEXT: require<live-intervals>
; GCN-O2-NEXT: require<machine-loops>
; GCN-O2-NEXT: si-opt-vgpr-liverange
; GCN-O2-NEXT: phi-node-elimination
; GCN-O2-NEXT: si-lower-control-flow
-; GCN-O2-NEXT: require<live-intervals>
; GCN-O2-NEXT: two-address-instruction
; GCN-O2-NEXT: register-coalescer
; GCN-O2-NEXT: rename-independent-subregs
@@ -411,11 +411,11 @@
; GCN-O3-NEXT: process-imp-defs
; GCN-O3-NEXT: unreachable-mbb-elimination
; GCN-O3-NEXT: require<live-vars>
+; GCN-O3-NEXT: require<live-intervals>
; GCN-O3-NEXT: require<machine-loops>
; GCN-O3-NEXT: si-opt-vgpr-liverange
; GCN-O3-NEXT: phi-node-elimination
; GCN-O3-NEXT: si-lower-control-flow
-; GCN-O3-NEXT: require<live-intervals>
; GCN-O3-NEXT: two-address-instruction
; GCN-O3-NEXT: register-coalescer
; GCN-O3-NEXT: rename-independent-subregs
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index df1d419bea1d7..a97c1955c94f5 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -13,18 +13,7 @@
; REQUIRES: asserts
-; GCN-O0:Target Library Information
-; GCN-O0-NEXT:Runtime Library Function Analysis
-; GCN-O0-NEXT:Target Pass Configuration
-; GCN-O0-NEXT:Machine Module Information
-; GCN-O0-NEXT:Target Transform Information
-; GCN-O0-NEXT:Library Function Lowering Analysis
-; GCN-O0-NEXT:Assumption Cache Tracker
-; GCN-O0-NEXT:Profile summary info
-; GCN-O0-NEXT:Create Garbage Collector Module Metadata
-; GCN-O0-NEXT:Register Usage Information Storage
-; GCN-O0-NEXT:Machine Branch Probability Analysis
-; GCN-O0-NEXT: ModulePass Manager
+; GCN-O0: ModulePass Manager
; GCN-O0-NEXT: Pre-ISel Intrinsic Lowering
; GCN-O0-NEXT: FunctionPass Manager
; GCN-O0-NEXT: Expand IR instructions
@@ -168,25 +157,22 @@
; GCN-O0-NEXT: Function register usage analysis
; GCN-O0-NEXT: AMDGPU Assembly Printer
; GCN-O0-NEXT: Free MachineFunction
+; GCN-O0-NEXT:Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -basic-aa -aa
+; GCN-O0-NEXT:Assumption Cache Tracker
+; GCN-O0-NEXT:Target Library Information
+; GCN-O0-NEXT: FunctionPass Manager
+; GCN-O0-NEXT: Dominator Tree Construction
+; GCN-O0-NEXT: Basic Alias Analysis (stateless AA impl)
+; GCN-O0-NEXT: Function Alias Analysis Results
+; GCN-O0-NEXT:Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -loops -scalar-evolution
+; GCN-O0-NEXT:Assumption Cache Tracker
+; GCN-O0-NEXT:Target Library Information
+; GCN-O0-NEXT: FunctionPass Manager
+; GCN-O0-NEXT: Dominator Tree Construction
+; GCN-O0-NEXT: Natural Loop Information
+; GCN-O0-NEXT: Scalar Evolution Analysis
-; GCN-O1:Target Library Information
-; GCN-O1-NEXT:Runtime Library Function Analysis
-; GCN-O1-NEXT:Target Pass Configuration
-; GCN-O1-NEXT:Machine Module Information
-; GCN-O1-NEXT:Target Transform Information
-; GCN-O1-NEXT:Assumption Cache Tracker
-; GCN-O1-NEXT:Library Function Lowering Analysis
-; GCN-O1-NEXT:Profile summary info
-; GCN-O1-NEXT:AMDGPU Address space based Alias Analysis
-; GCN-O1-NEXT:External Alias Analysis
-; GCN-O1-NEXT:Type-Based Alias Analysis
-; GCN-O1-NEXT:Scoped NoAlias Alias Analysis
-; GCN-O1-NEXT:Create Garbage Collector Module Metadata
-; GCN-O1-NEXT:Machine Branch Probability Analysis
-; GCN-O1-NEXT:Register Usage Information Storage
-; GCN-O1-NEXT:Default Regalloc Eviction Advisor
-; GCN-O1-NEXT:Default Regalloc Priority Advisor
-; GCN-O1-NEXT: ModulePass Manager
+; GCN-O1: ModulePass Manager
; GCN-O1-NEXT: FunctionPass Manager
; GCN-O1-NEXT: Dominator Tree Construction
; GCN-O1-NEXT: Basic Alias Analysis (stateless AA impl)
@@ -471,25 +457,22 @@
; GCN-O1-NEXT: Function register usage analysis
; GCN-O1-NEXT: AMDGPU Assembly Printer
; GCN-O1-NEXT: Free MachineFunction
+; GCN-O1-NEXT:Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -basic-aa -aa
+; GCN-O1-NEXT:Assumption Cache Tracker
+; GCN-O1-NEXT:Target Library Information
+; GCN-O1-NEXT: FunctionPass Manager
+; GCN-O1-NEXT: Dominator Tree Construction
+; GCN-O1-NEXT: Basic Alias Analysis (stateless AA impl)
+; GCN-O1-NEXT: Function Alias Analysis Results
+; GCN-O1-NEXT:Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -loops -scalar-evolution
+; GCN-O1-NEXT:Assumption Cache Tracker
+; GCN-O1-NEXT:Target Library Information
+; GCN-O1-NEXT: FunctionPass Manager
+; GCN-O1-NEXT: Dominator Tree Construction
+; GCN-O1-NEXT: Natural Loop Information
+; GCN-O1-NEXT: Scalar Evolution Analysis
-; GCN-O1-OPTS:Target Library Information
-; GCN-O1-OPTS-NEXT:Runtime Library Function Analysis
-; GCN-O1-OPTS-NEXT:Target Pass Configuration
-; GCN-O1-OPTS-NEXT:Machine Module Information
-; GCN-O1-OPTS-NEXT:Target Transform Information
-; GCN-O1-OPTS-NEXT:Assumption Cache Tracker
-; GCN-O1-OPTS-NEXT:Library Function Lowering Analysis
-; GCN-O1-OPTS-NEXT:Profile summary info
-; GCN-O1-OPTS-NEXT:AMDGPU Address space based Alias Analysis
-; GCN-O1-OPTS-NEXT:External Alias Analysis
-; GCN-O1-OPTS-NEXT:Type-Based Alias Analysis
-; GCN-O1-OPTS-NEXT:Scoped NoAlias Alias Analysis
-; GCN-O1-OPTS-NEXT:Create Garbage Collector Module Metadata
-; GCN-O1-OPTS-NEXT:Machine Branch Probability Analysis
-; GCN-O1-OPTS-NEXT:Register Usage Information Storage
-; GCN-O1-OPTS-NEXT:Default Regalloc Eviction Advisor
-; GCN-O1-OPTS-NEXT:Default Regalloc Priority Advisor
-; GCN-O1-OPTS-NEXT: ModulePass Manager
+; GCN-O1-OPTS: ModulePass Manager
; GCN-O1-OPTS-NEXT: FunctionPass Manager
; GCN-O1-OPTS-NEXT: Dominator Tree Construction
; GCN-O1-OPTS-NEXT: Basic Alias Analysis (stateless AA impl)
@@ -803,25 +786,22 @@
; GCN-O1-OPTS-NEXT: Function register usage analysis
; GCN-O1-OPTS-NEXT: AMDGPU Assembly Printer
; GCN-O1-OPTS-NEXT: Free MachineFunction
+; GCN-O1-OPTS-NEXT:Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -basic-aa -aa
+; GCN-O1-OPTS-NEXT:Assumption Cache Tracker
+; GCN-O1-OPTS-NEXT:Target Library Information
+; GCN-O1-OPTS-NEXT: FunctionPass Manager
+; GCN-O1-OPTS-NEXT: Dominator Tree Construction
+; GCN-O1-OPTS-NEXT: Basic Alias Analysis (stateless AA impl)
+; GCN-O1-OPTS-NEXT: Function Alias Analysis Results
+; GCN-O1-OPTS-NEXT:Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -loops -scalar-evolution
+; GCN-O1-OPTS-NEXT:Assumption Cache Tracker
+; GCN-O1-OPTS-NEXT:Target Library Information
+; GCN-O1-OPTS-NEXT: FunctionPass Manager
+; GCN-O1-OPTS-NEXT: Dominator Tree Construction
+; GCN-O1-OPTS-NEXT: Natural Loop Information
+; GCN-O1-OPTS-NEXT: Scalar Evolution Analysis
-; GCN-O2:Target Library Information
-; GCN-O2-NEXT:Runtime Library Function Analysis
-; GCN-O2-NEXT:Target Pass Configuration
-; GCN-O2-NEXT:Machine Module Information
-; GCN-O2-NEXT:Target Transform Information
-; GCN-O2-NEXT:Assumption Cache Tracker
-; GCN-O2-NEXT:Library Function Lowering Analysis
-; GCN-O2-NEXT:Profile summary info
-; GCN-O2-NEXT:AMDGPU Address space based Alias Analysis
-; GCN-O2-NEXT:External Alias Analysis
-; GCN-O2-NEXT:Type-Based Alias Analysis
-; GCN-O2-NEXT:Scoped NoAlias Alias Analysis
-; GCN-O2-NEXT:Create Garbage Collector Module Metadata
-; GCN-O2-NEXT:Machine Branch Probability Analysis
-; GCN-O2-NEXT:Register Usage Information Storage
-; GCN-O2-NEXT:Default Regalloc Eviction Advisor
-; GCN-O2-NEXT:Default Regalloc Priority Advisor
-; GCN-O2-NEXT: ModulePass Manager
+; GCN-O2: ModulePass Manager
; GCN-O2-NEXT: FunctionPass Manager
; GCN-O2-NEXT: Dominator Tree Construction
; GCN-O2-NEXT: Basic Alias Analysis (stateless AA impl)
@@ -1140,25 +1120,22 @@
; GCN-O2-NEXT: Function register usage analysis
; GCN-O2-NEXT: AMDGPU Assembly Printer
; GCN-O2-NEXT: Free MachineFunction
+; GCN-O2-NEXT:Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -basic-aa -aa
+; GCN-O2-NEXT:Assumption Cache Tracker
+; GCN-O2-NEXT:Target Library Information
+; GCN-O2-NEXT: FunctionPass Manager
+; GCN-O2-NEXT: Dominator Tree Construction
+; GCN-O2-NEXT: Basic Alias Analysis (stateless AA impl)
+; GCN-O2-NEXT: Function Alias Analysis Results
+; GCN-O2-NEXT:Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -loops -scalar-evolution
+; GCN-O2-NEXT:Assumption Cache Tracker
+; GCN-O2-NEXT:Target Library Information
+; GCN-O2-NEXT: FunctionPass Manager
+; GCN-O2-NEXT: Dominator Tree Construction
+; GCN-O2-NEXT: Natural Loop Information
+; GCN-O2-NEXT: Scalar Evolution Analysis
-; GCN-O3:Target Library Information
-; GCN-O3-NEXT:Runtime Library Function Analysis
-; GCN-O3-NEXT:Target Pass Configuration
-; GCN-O3-NEXT:Machine Module Information
-; GCN-O3-NEXT:Target Transform Information
-; GCN-O3-NEXT:Assumption Cache Tracker
-; GCN-O3-NEXT:Library Function Lowering Analysis
-; GCN-O3-NEXT:Profile summary info
-; GCN-O3-NEXT:AMDGPU Address space based Alias Analysis
-; GCN-O3-NEXT:External Alias Analysis
-; GCN-O3-NEXT:Type-Based Alias Analysis
-; GCN-O3-NEXT:Scoped NoAlias Alias Analysis
-; GCN-O3-NEXT:Create Garbage Collector Module Metadata
-; GCN-O3-NEXT:Machine Branch Probability Analysis
-; GCN-O3-NEXT:Register Usage Information Storage
-; GCN-O3-NEXT:Default Regalloc Eviction Advisor
-; GCN-O3-NEXT:Default Regalloc Priority Advisor
-; GCN-O3-NEXT: ModulePass Manager
+; GCN-O3: ModulePass Manager
; GCN-O3-NEXT: FunctionPass Manager
; GCN-O3-NEXT: Dominator Tree Construction
; GCN-O3-NEXT: Basic Alias Analysis (stateless AA impl)
@@ -1492,6 +1469,20 @@
; GCN-O3-NEXT: Function register usage analysis
; GCN-O3-NEXT: AMDGPU Assembly Printer
; GCN-O3-NEXT: Free MachineFunction
+; GCN-O3-NEXT:Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -basic-aa -aa
+; GCN-O3-NEXT:Assumption Cache Tracker
+; GCN-O3-NEXT:Target Library Information
+; GCN-O3-NEXT: FunctionPass Manager
+; GCN-O3-NEXT: Dominator Tree Construction
+; GCN-O3-NEXT: Basic Alias Analysis (stateless AA impl)
+; GCN-O3-NEXT: Function Alias Analysis Results
+; GCN-O3-NEXT:Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -loops -scalar-evolution
+; GCN-O3-NEXT:Assumption Cache Tracker
+; GCN-O3-NEXT:Target Library Information
+; GCN-O3-NEXT: FunctionPass Manager
+; GCN-O3-NEXT: Dominator Tree Construction
+; GCN-O3-NEXT: Natural Loop Information
+; GCN-O3-NEXT: Scalar Evolution Analysis
define void @empty() {
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir b/llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
index 657336340415b..072b03ac5de05 100644
--- a/llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
+++ b/llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
@@ -17,39 +17,32 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY killed $sgpr0
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]
; CHECK-NEXT: S_BRANCH %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[COPY2]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_I32_e64 [[COPY3]], [[COPY1]], implicit $exec
; CHECK-NEXT: $vcc = COPY killed [[V_CMP_LT_I32_e64_]]
- ; CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.4:
- ; CHECK-NEXT: successors: %bb.3(0x80000000)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed [[COPY3]]
- ; CHECK-NEXT: S_BRANCH %bb.3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
+ ; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[COPY3]], [[COPY]], 0, implicit $exec
; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_ADD_U32_e64_]], [[COPY1]], implicit $exec
; CHECK-NEXT: $vcc = COPY killed [[V_CMP_EQ_U32_e64_]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; CHECK-NEXT: S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.5:
- ; CHECK-NEXT: successors: %bb.3(0x80000000)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed [[V_ADD_U32_e64_]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
+ ; CHECK-NEXT: S_BRANCH %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY4]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
; CHECK-NEXT: $vgpr0 = COPY killed [[COPY5]]
; CHECK-NEXT: SI_RETURN implicit killed $vgpr0
bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir b/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
index 474eb3f80840d..d9ab3d15db8b6 100644
--- a/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
+++ b/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
@@ -27,8 +27,8 @@ body: |
# CHECK-LABEL: name: foo
# CHECK: bb.3:
-# CHECK-NEXT: dead %2:sreg_32_xm0 = IMPLICIT_DEF
-# CHECK-NEXT: %3:sreg_32_xm0 = COPY killed %4
+# CHECK-NEXT: %2:sreg_32_xm0 = IMPLICIT_DEF
+# CHECK-NEXT: %3:sreg_32_xm0 = COPY %4
# CHECK-NEXT: S_NOP 0, implicit killed %3
@@ -65,8 +65,8 @@ body: |
# CHECK-LABEL: name: bar
# CHECK: bb.3:
-# CHECK-NEXT: dead %3:sreg_32_xm0 = IMPLICIT_DEF
-# CHECK-NEXT: %2:sreg_32_xm0 = COPY killed %4
+# CHECK-NEXT: %3:sreg_32_xm0 = IMPLICIT_DEF
+# CHECK-NEXT: %2:sreg_32_xm0 = COPY %4
# CHECK-NEXT: S_NOP 0, implicit killed %2
@@ -93,4 +93,4 @@ body: |
# CHECK-LABEL: name: bax
# CHECK: bb.3:
-# CHECK-NEXT: %2:sreg_32_xm0 = COPY killed %3
+# CHECK-NEXT: %2:sreg_32_xm0 = COPY %3
diff --git a/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir b/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
index c2b9f34ea78b0..5c1715dd97452 100644
--- a/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
+++ b/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
@@ -5,15 +5,15 @@
# CHECK: bb.0:
# CHECK: [[COND:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64
# CHECK: [[IF_SOURCE0:%[0-9]+]]:sreg_64 = SI_IF [[COND]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
-# CHECK: [[IF_INPUT_REG:%[0-9]+]]:sreg_64 = S_MOV_B64_term killed [[IF_SOURCE0]], implicit $exec
+# CHECK: [[IF_INPUT_REG:%[0-9]+]]:sreg_64 = S_MOV_B64_term [[IF_SOURCE0]], implicit $exec
# CHECK: bb.1:
-# CHECK: [[END_CF_ARG:%[0-9]+]]:sreg_64 = COPY killed [[IF_INPUT_REG]]
+# CHECK: [[END_CF_ARG:%[0-9]+]]:sreg_64 = COPY [[IF_INPUT_REG]]
# CHECK: SI_END_CF killed [[END_CF_ARG]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
# CHECK: bb.2:
# CHECK: [[IF_SOURCE1:%[0-9]+]]:sreg_64 = SI_IF [[COND]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
-# CHECK: [[IF_INPUT_REG]]:sreg_64 = S_MOV_B64_term killed [[IF_SOURCE1]], implicit $exec
+# CHECK: [[IF_INPUT_REG]]:sreg_64 = S_MOV_B64_term [[IF_SOURCE1]], implicit $exec
...
diff --git a/llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir b/llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
index cba7d41ea815f..d583cdd017774 100644
--- a/llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
+++ b/llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
@@ -30,12 +30,12 @@ body: |
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY4]], %subreg.sub0, killed [[COPY3]], %subreg.sub1, killed [[COPY2]], %subreg.sub2, killed [[COPY1]], %subreg.sub3
; W32-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
; W32-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
- ; W32-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0_xexec = COPY killed [[S_MOV_B32_1]]
+ ; W32-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[S_MOV_B32_1]]
; W32-NEXT: {{ $}}
; W32-NEXT: .1:
; W32-NEXT: successors: %bb.2(0x80000000)
; W32-NEXT: {{ $}}
- ; W32-NEXT: [[COPY6:%[0-9]+]]:sreg_32_xm0_xexec = COPY killed [[COPY5]]
+ ; W32-NEXT: [[COPY6:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY5]]
; W32-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub0, implicit $exec
; W32-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub1, implicit $exec
; W32-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
@@ -52,7 +52,7 @@ body: |
; W32-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[COPY]], killed [[REG_SEQUENCE3]], 0, 0, 0, 0, implicit $exec
; W32-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_B32 killed [[COPY6]], $exec_lo, implicit-def dead $scc
; W32-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[S_ANDN2_B32_]]
- ; W32-NEXT: $exec_lo = S_MOV_B32_term killed [[S_ANDN2_B32_]]
+ ; W32-NEXT: $exec_lo = S_MOV_B32_term [[S_ANDN2_B32_]]
; W32-NEXT: SI_WATERFALL_LOOP %bb.1, implicit $exec
; W32-NEXT: {{ $}}
; W32-NEXT: .3:
@@ -72,12 +72,12 @@ body: |
; W64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY4]], %subreg.sub0, killed [[COPY3]], %subreg.sub1, killed [[COPY2]], %subreg.sub2, killed [[COPY1]], %subreg.sub3
; W64-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; W64-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
- ; W64-NEXT: [[COPY5:%[0-9]+]]:sreg_64_xexec = COPY killed [[S_MOV_B64_1]]
+ ; W64-NEXT: [[COPY5:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_1]]
; W64-NEXT: {{ $}}
; W64-NEXT: .1:
; W64-NEXT: successors: %bb.2(0x80000000)
; W64-NEXT: {{ $}}
- ; W64-NEXT: [[COPY6:%[0-9]+]]:sreg_64_xexec = COPY killed [[COPY5]]
+ ; W64-NEXT: [[COPY6:%[0-9]+]]:sreg_64_xexec = COPY [[COPY5]]
; W64-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub0, implicit $exec
; W64-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub1, implicit $exec
; W64-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
@@ -94,7 +94,7 @@ body: |
; W64-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[COPY]], killed [[REG_SEQUENCE3]], 0, 0, 0, 0, implicit $exec
; W64-NEXT: [[S_ANDN2_B64_:%[0-9]+]]:sreg_64_xexec = S_ANDN2_B64 killed [[COPY6]], $exec, implicit-def dead $scc
; W64-NEXT: [[COPY5:%[0-9]+]]:sreg_64_xexec = COPY [[S_ANDN2_B64_]]
- ; W64-NEXT: $exec = S_MOV_B64_term killed [[S_ANDN2_B64_]]
+ ; W64-NEXT: $exec = S_MOV_B64_term [[S_ANDN2_B64_]]
; W64-NEXT: SI_WATERFALL_LOOP %bb.1, implicit $exec
; W64-NEXT: {{ $}}
; W64-NEXT: .3:
diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll
index 6850e41d1f816..e3798ef253002 100644
--- a/llvm/test/CodeGen/ARM/O3-pipeline.ll
+++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll
@@ -123,10 +123,10 @@
; CHECK-NEXT: Remove unreachable machine basic blocks
; CHECK-NEXT: Live Variable Analysis
; CHECK-NEXT: MachineDominator Tree Construction
-; CHECK-NEXT: Machine Natural Loop Construction
-; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
+; CHECK-NEXT: Machine Natural Loop Construction
+; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll b/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
index e45985136cf34..af53e50b94a2c 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
@@ -34,35 +34,34 @@ define i32 @add_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture reado
;
; CHECK-BE-LABEL: add_user:
; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-BE-NEXT: push {r4, r5, r7, lr}
; CHECK-BE-NEXT: cmp r0, #1
; CHECK-BE-NEXT: blt .LBB0_4
; CHECK-BE-NEXT: @ %bb.1: @ %for.body.preheader
-; CHECK-BE-NEXT: .save {r4, r5, r7, lr}
-; CHECK-BE-NEXT: push {r4, r5, r7, lr}
; CHECK-BE-NEXT: subs r3, #2
; CHECK-BE-NEXT: subs r2, #2
; CHECK-BE-NEXT: mov.w r12, #0
-; CHECK-BE-NEXT: movs r1, #0
+; CHECK-BE-NEXT: mov.w lr, #0
; CHECK-BE-NEXT: .LBB0_2: @ %for.body
; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-BE-NEXT: ldrsh lr, [r3, #2]!
+; CHECK-BE-NEXT: ldrsh r1, [r3, #2]!
; CHECK-BE-NEXT: subs r0, #1
; CHECK-BE-NEXT: ldrsh r4, [r2, #2]!
-; CHECK-BE-NEXT: add r1, lr
+; CHECK-BE-NEXT: add lr, r1
; CHECK-BE-NEXT: ldrsh.w r5, [r2, #2]
-; CHECK-BE-NEXT: smlabb r12, r4, lr, r12
+; CHECK-BE-NEXT: smlabb r12, r4, r1, r12
; CHECK-BE-NEXT: ldrsh.w r4, [r3, #2]
; CHECK-BE-NEXT: smlabb r12, r5, r4, r12
; CHECK-BE-NEXT: bne .LBB0_2
-; CHECK-BE-NEXT: @ %bb.3:
-; CHECK-BE-NEXT: pop.w {r4, r5, r7, lr}
-; CHECK-BE-NEXT: add.w r0, r12, r1
-; CHECK-BE-NEXT: bx lr
+; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-BE-NEXT: add.w r0, r12, lr
+; CHECK-BE-NEXT: pop {r4, r5, r7, pc}
; CHECK-BE-NEXT: .LBB0_4:
; CHECK-BE-NEXT: mov.w r12, #0
-; CHECK-BE-NEXT: movs r1, #0
-; CHECK-BE-NEXT: add.w r0, r12, r1
-; CHECK-BE-NEXT: bx lr
+; CHECK-BE-NEXT: mov.w lr, #0
+; CHECK-BE-NEXT: add.w r0, r12, lr
+; CHECK-BE-NEXT: pop {r4, r5, r7, pc}
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
@@ -137,35 +136,34 @@ define i32 @mul_bottom_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocaptur
;
; CHECK-BE-LABEL: mul_bottom_user:
; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-BE-NEXT: push {r4, r5, r7, lr}
; CHECK-BE-NEXT: cmp r0, #1
; CHECK-BE-NEXT: blt .LBB1_4
; CHECK-BE-NEXT: @ %bb.1: @ %for.body.preheader
-; CHECK-BE-NEXT: .save {r4, r5, r7, lr}
-; CHECK-BE-NEXT: push {r4, r5, r7, lr}
; CHECK-BE-NEXT: subs r3, #2
; CHECK-BE-NEXT: subs r2, #2
; CHECK-BE-NEXT: mov.w r12, #0
-; CHECK-BE-NEXT: movs r1, #0
+; CHECK-BE-NEXT: mov.w lr, #0
; CHECK-BE-NEXT: .LBB1_2: @ %for.body
; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-BE-NEXT: ldrsh lr, [r3, #2]!
+; CHECK-BE-NEXT: ldrsh r1, [r3, #2]!
; CHECK-BE-NEXT: subs r0, #1
; CHECK-BE-NEXT: ldrsh r4, [r2, #2]!
; CHECK-BE-NEXT: ldrsh.w r5, [r2, #2]
-; CHECK-BE-NEXT: mul r1, lr, r1
-; CHECK-BE-NEXT: smlabb r12, r4, lr, r12
+; CHECK-BE-NEXT: mul lr, r1, lr
+; CHECK-BE-NEXT: smlabb r12, r4, r1, r12
; CHECK-BE-NEXT: ldrsh.w r4, [r3, #2]
; CHECK-BE-NEXT: smlabb r12, r5, r4, r12
; CHECK-BE-NEXT: bne .LBB1_2
-; CHECK-BE-NEXT: @ %bb.3:
-; CHECK-BE-NEXT: pop.w {r4, r5, r7, lr}
-; CHECK-BE-NEXT: add.w r0, r12, r1
-; CHECK-BE-NEXT: bx lr
+; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-BE-NEXT: add.w r0, r12, lr
+; CHECK-BE-NEXT: pop {r4, r5, r7, pc}
; CHECK-BE-NEXT: .LBB1_4:
; CHECK-BE-NEXT: mov.w r12, #0
-; CHECK-BE-NEXT: movs r1, #0
-; CHECK-BE-NEXT: add.w r0, r12, r1
-; CHECK-BE-NEXT: bx lr
+; CHECK-BE-NEXT: mov.w lr, #0
+; CHECK-BE-NEXT: add.w r0, r12, lr
+; CHECK-BE-NEXT: pop {r4, r5, r7, pc}
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
@@ -343,35 +341,34 @@ define i32 @and_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture reado
;
; CHECK-BE-LABEL: and_user:
; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-BE-NEXT: push {r4, r5, r7, lr}
; CHECK-BE-NEXT: cmp r0, #1
; CHECK-BE-NEXT: blt .LBB3_4
; CHECK-BE-NEXT: @ %bb.1: @ %for.body.preheader
-; CHECK-BE-NEXT: .save {r4, r5, r7, lr}
-; CHECK-BE-NEXT: push {r4, r5, r7, lr}
; CHECK-BE-NEXT: subs r3, #2
; CHECK-BE-NEXT: subs r2, #2
; CHECK-BE-NEXT: mov.w r12, #0
-; CHECK-BE-NEXT: movs r1, #0
+; CHECK-BE-NEXT: mov.w lr, #0
; CHECK-BE-NEXT: .LBB3_2: @ %for.body
; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-BE-NEXT: ldrh lr, [r3, #2]!
+; CHECK-BE-NEXT: ldrh r1, [r3, #2]!
; CHECK-BE-NEXT: subs r0, #1
; CHECK-BE-NEXT: ldrsh r4, [r2, #2]!
; CHECK-BE-NEXT: ldrsh.w r5, [r2, #2]
-; CHECK-BE-NEXT: mul r1, lr, r1
-; CHECK-BE-NEXT: smlabb r12, r4, lr, r12
+; CHECK-BE-NEXT: mul lr, r1, lr
+; CHECK-BE-NEXT: smlabb r12, r4, r1, r12
; CHECK-BE-NEXT: ldrsh.w r4, [r3, #2]
; CHECK-BE-NEXT: smlabb r12, r5, r4, r12
; CHECK-BE-NEXT: bne .LBB3_2
-; CHECK-BE-NEXT: @ %bb.3:
-; CHECK-BE-NEXT: pop.w {r4, r5, r7, lr}
-; CHECK-BE-NEXT: add.w r0, r12, r1
-; CHECK-BE-NEXT: bx lr
+; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-BE-NEXT: add.w r0, r12, lr
+; CHECK-BE-NEXT: pop {r4, r5, r7, pc}
; CHECK-BE-NEXT: .LBB3_4:
; CHECK-BE-NEXT: mov.w r12, #0
-; CHECK-BE-NEXT: movs r1, #0
-; CHECK-BE-NEXT: add.w r0, r12, r1
-; CHECK-BE-NEXT: bx lr
+; CHECK-BE-NEXT: mov.w lr, #0
+; CHECK-BE-NEXT: add.w r0, r12, lr
+; CHECK-BE-NEXT: pop {r4, r5, r7, pc}
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
diff --git a/llvm/test/CodeGen/ARM/aes-erratum-fix.ll b/llvm/test/CodeGen/ARM/aes-erratum-fix.ll
index 3fded99368800..7427d0ca8036e 100644
--- a/llvm/test/CodeGen/ARM/aes-erratum-fix.ll
+++ b/llvm/test/CodeGen/ARM/aes-erratum-fix.ll
@@ -1444,8 +1444,8 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX: @ %bb.0:
; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-CORTEX-FIX-NEXT: .pad #16
-; CHECK-CORTEX-FIX-NEXT: sub sp, sp, #16
+; CHECK-CORTEX-FIX-NEXT: .pad #20
+; CHECK-CORTEX-FIX-NEXT: sub sp, sp, #20
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
; CHECK-CORTEX-FIX-NEXT: beq .LBB36_2
; CHECK-CORTEX-FIX-NEXT: @ %bb.1:
@@ -1453,8 +1453,11 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX-NEXT: ldrh r11, [r1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d17[0]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d17[3]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d17[0]
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[2]
+; CHECK-CORTEX-FIX-NEXT: str r7, [sp, #8] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[3]
; CHECK-CORTEX-FIX-NEXT: b .LBB36_3
; CHECK-CORTEX-FIX-NEXT: .LBB36_2:
; CHECK-CORTEX-FIX-NEXT: vld1.32 {d16[0]}, [r2:32]
@@ -1467,17 +1470,18 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r11, d16[0]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d17[0]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d17[3]
-; CHECK-CORTEX-FIX-NEXT: .LBB36_3:
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d17[0]
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #4] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[2]
-; CHECK-CORTEX-FIX-NEXT: str r7, [sp, #4] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #12] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: str r7, [sp, #8] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[3]
+; CHECK-CORTEX-FIX-NEXT: .LBB36_3:
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #16] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[3]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #12] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d17[1]
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
+; CHECK-CORTEX-FIX-NEXT: str r7, [sp] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: beq .LBB36_5
; CHECK-CORTEX-FIX-NEXT: @ %bb.4:
; CHECK-CORTEX-FIX-NEXT: ldrh r4, [r1]
@@ -1486,28 +1490,29 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r4, d0[0]
; CHECK-CORTEX-FIX-NEXT: .LBB36_6:
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r5, d0[1]
+; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r6, d0[2]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r12, d0[3]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d1[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d1[0]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r1, d1[1]
-; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r9, r3, lsl #16
; CHECK-CORTEX-FIX-NEXT: vmov.u16 lr, d1[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d1[3]
-; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r8, r3, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d1[3]
; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r11, r0, lsl #16
; CHECK-CORTEX-FIX-NEXT: pkhbt r5, r4, r5, lsl #16
-; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r6, r12, lsl #16
-; CHECK-CORTEX-FIX-NEXT: pkhbt r1, r9, r1, lsl #16
; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[0], r0
-; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[0], r3
-; CHECK-CORTEX-FIX-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
-; CHECK-CORTEX-FIX-NEXT: pkhbt r7, lr, r7, lsl #16
+; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r6, r12, lsl #16
+; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: ldr r3, [sp] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: pkhbt r1, r10, r1, lsl #16
+; CHECK-CORTEX-FIX-NEXT: pkhbt r7, lr, r8, lsl #16
; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r5
-; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r0, r10, lsl #16
+; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r0, r3, lsl #16
+; CHECK-CORTEX-FIX-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[1], r6
; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[0], r1
-; CHECK-CORTEX-FIX-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r3, r6, lsl #16
; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[1], r3
; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[1], r0
@@ -1515,7 +1520,7 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX-NEXT: aese.8 q9, q8
; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q9
; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2]
-; CHECK-CORTEX-FIX-NEXT: add sp, sp, #16
+; CHECK-CORTEX-FIX-NEXT: add sp, sp, #20
; CHECK-CORTEX-FIX-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
br i1 %0, label %5, label %12
@@ -1571,15 +1576,15 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_val(i1 zeroext %0, half %1, <1
; CHECK-FIX-NOSCHED-NEXT: @ %bb.1:
; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-FIX-NOSCHED-NEXT: vmov.f32 s2, s0
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[1]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r7, d17[3]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 lr, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 lr, d17[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r10, d16[3]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r11, d16[2]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r8, d16[1]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[0]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[1]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d16[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[0]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp] @ 4-byte Spill
; CHECK-FIX-NOSCHED-NEXT: b .LBB37_3
; CHECK-FIX-NOSCHED-NEXT: .LBB37_2:
@@ -1590,22 +1595,22 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_val(i1 zeroext %0, half %1, <1
; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d16[1]}, [r2:32]
; CHECK-FIX-NOSCHED-NEXT: add r2, r1, #12
; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d17[1]}, [r2:32]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[1]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r7, d17[3]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 lr, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 lr, d17[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r10, d16[3]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r11, d16[2]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r8, d16[1]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[0]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[1]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d16[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[0]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp] @ 4-byte Spill
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d16[0]
; CHECK-FIX-NOSCHED-NEXT: vmov s2, r2
; CHECK-FIX-NOSCHED-NEXT: .LBB37_3:
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r9, d3[3]
; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r10, d3[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r7, d3[2]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d3[1]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d3[0]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r4, d2[3]
@@ -1629,18 +1634,18 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_val(i1 zeroext %0, half %1, <1
; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r5, r4, lsl #16
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[0], r6
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d18[1], r0
-; CHECK-FIX-NOSCHED-NEXT: ldr r0, [sp] @ 4-byte Reload
-; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r11, r0, lsl #16
+; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r11, r10, lsl #16
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[1], r0
; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r3, r2, lsl #16
-; CHECK-FIX-NOSCHED-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
+; CHECK-FIX-NOSCHED-NEXT: ldr r2, [sp] @ 4-byte Reload
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[0], r0
-; CHECK-FIX-NOSCHED-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-FIX-NOSCHED-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r0, lsl #16
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[0], r0
-; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r10, r9, lsl #16
+; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r7, r9, lsl #16
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[1], r0
-; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, lr, r7, lsl #16
+; CHECK-FIX-NOSCHED-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r0, lr, lsl #16
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[1], r0
; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q9
; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8
@@ -3585,8 +3590,8 @@ define arm_aapcs_vfpcc void @aesd_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX: @ %bb.0:
; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-CORTEX-FIX-NEXT: .pad #16
-; CHECK-CORTEX-FIX-NEXT: sub sp, sp, #16
+; CHECK-CORTEX-FIX-NEXT: .pad #20
+; CHECK-CORTEX-FIX-NEXT: sub sp, sp, #20
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
; CHECK-CORTEX-FIX-NEXT: beq .LBB82_2
; CHECK-CORTEX-FIX-NEXT: @ %bb.1:
@@ -3594,8 +3599,11 @@ define arm_aapcs_vfpcc void @aesd_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX-NEXT: ldrh r11, [r1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d17[0]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d17[3]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d17[0]
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[2]
+; CHECK-CORTEX-FIX-NEXT: str r7, [sp, #8] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[3]
; CHECK-CORTEX-FIX-NEXT: b .LBB82_3
; CHECK-CORTEX-FIX-NEXT: .LBB82_2:
; CHECK-CORTEX-FIX-NEXT: vld1.32 {d16[0]}, [r2:32]
@@ -3608,17 +3616,18 @@ define arm_aapcs_vfpcc void @aesd_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r11, d16[0]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d17[0]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d17[3]
-; CHECK-CORTEX-FIX-NEXT: .LBB82_3:
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d17[0]
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #4] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[2]
-; CHECK-CORTEX-FIX-NEXT: str r7, [sp, #4] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #12] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: str r7, [sp, #8] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[3]
+; CHECK-CORTEX-FIX-NEXT: .LBB82_3:
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #16] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[3]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #12] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d17[1]
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
+; CHECK-CORTEX-FIX-NEXT: str r7, [sp] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: beq .LBB82_5
; CHECK-CORTEX-FIX-NEXT: @ %bb.4:
; CHECK-CORTEX-FIX-NEXT: ldrh r4, [r1]
@@ -3627,28 +3636,29 @@ define arm_aapcs_vfpcc void @aesd_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r4, d0[0]
; CHECK-CORTEX-FIX-NEXT: .LBB82_6:
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r5, d0[1]
+; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r6, d0[2]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r12, d0[3]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d1[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d1[0]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r1, d1[1]
-; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r9, r3, lsl #16
; CHECK-CORTEX-FIX-NEXT: vmov.u16 lr, d1[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d1[3]
-; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r8, r3, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d1[3]
; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r11, r0, lsl #16
; CHECK-CORTEX-FIX-NEXT: pkhbt r5, r4, r5, lsl #16
-; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r6, r12, lsl #16
-; CHECK-CORTEX-FIX-NEXT: pkhbt r1, r9, r1, lsl #16
; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[0], r0
-; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[0], r3
-; CHECK-CORTEX-FIX-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
-; CHECK-CORTEX-FIX-NEXT: pkhbt r7, lr, r7, lsl #16
+; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r6, r12, lsl #16
+; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: ldr r3, [sp] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: pkhbt r1, r10, r1, lsl #16
+; CHECK-CORTEX-FIX-NEXT: pkhbt r7, lr, r8, lsl #16
; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r5
-; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r0, r10, lsl #16
+; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r0, r3, lsl #16
+; CHECK-CORTEX-FIX-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[1], r6
; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[0], r1
-; CHECK-CORTEX-FIX-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r3, r6, lsl #16
; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[1], r3
; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[1], r0
@@ -3656,7 +3666,7 @@ define arm_aapcs_vfpcc void @aesd_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX-NEXT: aesd.8 q9, q8
; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q9
; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2]
-; CHECK-CORTEX-FIX-NEXT: add sp, sp, #16
+; CHECK-CORTEX-FIX-NEXT: add sp, sp, #20
; CHECK-CORTEX-FIX-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
br i1 %0, label %5, label %12
@@ -3712,15 +3722,15 @@ define arm_aapcs_vfpcc void @aesd_setf16_cond_via_val(i1 zeroext %0, half %1, <1
; CHECK-FIX-NOSCHED-NEXT: @ %bb.1:
; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-FIX-NOSCHED-NEXT: vmov.f32 s2, s0
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[1]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r7, d17[3]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 lr, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 lr, d17[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r10, d16[3]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r11, d16[2]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r8, d16[1]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[0]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[1]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d16[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[0]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp] @ 4-byte Spill
; CHECK-FIX-NOSCHED-NEXT: b .LBB83_3
; CHECK-FIX-NOSCHED-NEXT: .LBB83_2:
@@ -3731,22 +3741,22 @@ define arm_aapcs_vfpcc void @aesd_setf16_cond_via_val(i1 zeroext %0, half %1, <1
; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d16[1]}, [r2:32]
; CHECK-FIX-NOSCHED-NEXT: add r2, r1, #12
; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d17[1]}, [r2:32]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[1]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r7, d17[3]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 lr, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 lr, d17[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r10, d16[3]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r11, d16[2]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r8, d16[1]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[0]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[1]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d16[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[0]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp] @ 4-byte Spill
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d16[0]
; CHECK-FIX-NOSCHED-NEXT: vmov s2, r2
; CHECK-FIX-NOSCHED-NEXT: .LBB83_3:
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r9, d3[3]
; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r10, d3[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r7, d3[2]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d3[1]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d3[0]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r4, d2[3]
@@ -3770,18 +3780,18 @@ define arm_aapcs_vfpcc void @aesd_setf16_cond_via_val(i1 zeroext %0, half %1, <1
; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r5, r4, lsl #16
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[0], r6
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d18[1], r0
-; CHECK-FIX-NOSCHED-NEXT: ldr r0, [sp] @ 4-byte Reload
-; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r11, r0, lsl #16
+; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r11, r10, lsl #16
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[1], r0
; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r3, r2, lsl #16
-; CHECK-FIX-NOSCHED-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
+; CHECK-FIX-NOSCHED-NEXT: ldr r2, [sp] @ 4-byte Reload
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[0], r0
-; CHECK-FIX-NOSCHED-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-FIX-NOSCHED-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r0, lsl #16
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[0], r0
-; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r10, r9, lsl #16
+; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r7, r9, lsl #16
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[1], r0
-; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, lr, r7, lsl #16
+; CHECK-FIX-NOSCHED-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r0, lr, lsl #16
; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[1], r0
; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q9
; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8
diff --git a/llvm/test/CodeGen/ARM/code-placement.ll b/llvm/test/CodeGen/ARM/code-placement.ll
index c8bb10cd104cf..2cac332aaced4 100644
--- a/llvm/test/CodeGen/ARM/code-placement.ll
+++ b/llvm/test/CodeGen/ARM/code-placement.ll
@@ -11,10 +11,9 @@ entry:
br i1 %0, label %bb2, label %bb
bb:
-; CHECK: LBB0_[[LABEL:[0-9]]]:
-; CHECK: bne LBB0_[[LABEL]]
-; CHECK-NOT: b LBB0_[[LABEL]]
-; CHECK: bx lr
+; CHECK: LBB0_[[LABEL:[0-9]]]: @ %bb
+; CHECK: bxeq lr
+; CHECK: b LBB0_[[LABEL]]
%list_addr.05 = phi ptr [ %2, %bb ], [ %list, %entry ]
%next.04 = phi ptr [ %list_addr.05, %bb ], [ null, %entry ]
%1 = getelementptr inbounds %struct.list_head, ptr %list_addr.05, i32 0, i32 0
diff --git a/llvm/test/CodeGen/ARM/fp16-promote.ll b/llvm/test/CodeGen/ARM/fp16-promote.ll
index d126b79e2558b..f0e1bf0cb67d0 100644
--- a/llvm/test/CodeGen/ARM/fp16-promote.ll
+++ b/llvm/test/CodeGen/ARM/fp16-promote.ll
@@ -548,35 +548,20 @@ else:
declare i1 @test_dummy(ptr %p) #0
define void @test_phi(ptr %p) #0 {
-; CHECK-VFP-LABEL: test_phi:
-; CHECK-VFP: .save {r4, r5, r6, lr}
-; CHECK-VFP-NEXT: push {r4, r5, r6, lr}
-; CHECK-VFP-NEXT: ldrh r6, [r0]
-; CHECK-VFP-NEXT: mov r4, r0
-; CHECK-VFP-NEXT: .LBB13_1:
-; CHECK-VFP-NEXT: mov r0, r4
-; CHECK-VFP-NEXT: mov r5, r6
-; CHECK-VFP-NEXT: ldrh r6, [r4]
-; CHECK-VFP-NEXT: bl test_dummy
-; CHECK-VFP-NEXT: tst r0, #1
-; CHECK-VFP-NEXT: bne .LBB13_1
-; CHECK-VFP-NEXT: strh r5, [r4]
-; CHECK-VFP-NEXT: pop {r4, r5, r6, pc}
-;
-; CHECK-NOVFP-LABEL: test_phi:
-; CHECK-NOVFP: .save {r4, r5, r6, lr}
-; CHECK-NOVFP-NEXT: push {r4, r5, r6, lr}
-; CHECK-NOVFP-NEXT: ldrh r5, [r0]
-; CHECK-NOVFP-NEXT: mov r4, r0
-; CHECK-NOVFP-NEXT: .LBB13_1:
-; CHECK-NOVFP-NEXT: mov r0, r4
-; CHECK-NOVFP-NEXT: mov r6, r5
-; CHECK-NOVFP-NEXT: ldrh r5, [r4]
-; CHECK-NOVFP-NEXT: bl test_dummy
-; CHECK-NOVFP-NEXT: tst r0, #1
-; CHECK-NOVFP-NEXT: bne .LBB13_1
-; CHECK-NOVFP-NEXT: strh r6, [r4]
-; CHECK-NOVFP-NEXT: pop {r4, r5, r6, pc}
+; CHECK-ALL-LABEL: test_phi:
+; CHECK-ALL: .save {r4, r5, r6, lr}
+; CHECK-ALL-NEXT: push {r4, r5, r6, lr}
+; CHECK-ALL-NEXT: ldrh r6, [r0]
+; CHECK-ALL-NEXT: mov r4, r0
+; CHECK-ALL-NEXT: .LBB13_1:
+; CHECK-ALL-NEXT: mov r0, r4
+; CHECK-ALL-NEXT: mov r5, r6
+; CHECK-ALL-NEXT: ldrh r6, [r4]
+; CHECK-ALL-NEXT: bl test_dummy
+; CHECK-ALL-NEXT: tst r0, #1
+; CHECK-ALL-NEXT: bne .LBB13_1
+; CHECK-ALL-NEXT: strh r5, [r4]
+; CHECK-ALL-NEXT: pop {r4, r5, r6, pc}
entry:
%a = load half, ptr %p
br label %loop
diff --git a/llvm/test/CodeGen/ARM/fpclamptosat.ll b/llvm/test/CodeGen/ARM/fpclamptosat.ll
index a6f0a03fc7e5b..51c5aed957e45 100644
--- a/llvm/test/CodeGen/ARM/fpclamptosat.ll
+++ b/llvm/test/CodeGen/ARM/fpclamptosat.ll
@@ -2592,21 +2592,22 @@ define i64 @stest_f64i64_mm(double %x) {
; SOFT: @ %bb.0: @ %entry
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr}
-; SOFT-NEXT: .pad #12
-; SOFT-NEXT: sub sp, #12
+; SOFT-NEXT: .pad #4
+; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: bl __fixdfti
-; SOFT-NEXT: mov r7, r0
-; SOFT-NEXT: movs r0, #1
+; SOFT-NEXT: movs r7, #1
; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: ldr r6, .LCPI45_0
-; SOFT-NEXT: adds r4, r7, #1
+; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
+; SOFT-NEXT: adds r4, r0, #1
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: sbcs r4, r6
; SOFT-NEXT: mov r4, r2
; SOFT-NEXT: sbcs r4, r5
; SOFT-NEXT: mov r4, r3
; SOFT-NEXT: sbcs r4, r5
-; SOFT-NEXT: mov r4, r0
+; SOFT-NEXT: mov r4, r7
; SOFT-NEXT: blt .LBB45_2
; SOFT-NEXT: @ %bb.1: @ %entry
; SOFT-NEXT: mov r4, r5
@@ -2617,53 +2618,48 @@ define i64 @stest_f64i64_mm(double %x) {
; SOFT-NEXT: @ %bb.3: @ %entry
; SOFT-NEXT: beq .LBB45_13
; SOFT-NEXT: .LBB45_4: @ %entry
-; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: beq .LBB45_14
; SOFT-NEXT: .LBB45_5: @ %entry
-; SOFT-NEXT: str r3, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: bne .LBB45_7
; SOFT-NEXT: .LBB45_6: @ %entry
-; SOFT-NEXT: mov r7, r6
+; SOFT-NEXT: str r6, [sp] @ 4-byte Spill
; SOFT-NEXT: .LBB45_7: @ %entry
-; SOFT-NEXT: lsls r3, r0, #31
-; SOFT-NEXT: rsbs r4, r7, #0
-; SOFT-NEXT: mov r4, r3
+; SOFT-NEXT: lsls r0, r7, #31
+; SOFT-NEXT: ldr r4, [sp] @ 4-byte Reload
+; SOFT-NEXT: rsbs r4, r4, #0
+; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: sbcs r4, r1
; SOFT-NEXT: mov r4, r6
-; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: sbcs r4, r2
-; SOFT-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
-; SOFT-NEXT: sbcs r6, r2
+; SOFT-NEXT: sbcs r6, r3
; SOFT-NEXT: bge .LBB45_15
; SOFT-NEXT: @ %bb.8: @ %entry
-; SOFT-NEXT: cmp r0, #0
+; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: beq .LBB45_16
; SOFT-NEXT: .LBB45_9: @ %entry
; SOFT-NEXT: bne .LBB45_11
; SOFT-NEXT: .LBB45_10: @ %entry
-; SOFT-NEXT: mov r1, r3
+; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: .LBB45_11: @ %entry
-; SOFT-NEXT: mov r0, r7
-; SOFT-NEXT: add sp, #12
+; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
+; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB45_12: @ %entry
; SOFT-NEXT: mov r3, r4
; SOFT-NEXT: bne .LBB45_4
; SOFT-NEXT: .LBB45_13: @ %entry
; SOFT-NEXT: mov r2, r4
-; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: bne .LBB45_5
; SOFT-NEXT: .LBB45_14: @ %entry
-; SOFT-NEXT: ldr r1, .LCPI45_0
-; SOFT-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: beq .LBB45_6
; SOFT-NEXT: b .LBB45_7
; SOFT-NEXT: .LBB45_15: @ %entry
-; SOFT-NEXT: mov r0, r5
-; SOFT-NEXT: cmp r0, #0
+; SOFT-NEXT: mov r7, r5
+; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB45_9
; SOFT-NEXT: .LBB45_16: @ %entry
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: str r7, [sp] @ 4-byte Spill
; SOFT-NEXT: beq .LBB45_10
; SOFT-NEXT: b .LBB45_11
; SOFT-NEXT: .p2align 2
@@ -2905,21 +2901,22 @@ define i64 @stest_f32i64_mm(float %x) {
; SOFT: @ %bb.0: @ %entry
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr}
-; SOFT-NEXT: .pad #12
-; SOFT-NEXT: sub sp, #12
+; SOFT-NEXT: .pad #4
+; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: bl __fixsfti
-; SOFT-NEXT: mov r7, r0
-; SOFT-NEXT: movs r0, #1
+; SOFT-NEXT: movs r7, #1
; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: ldr r6, .LCPI48_0
-; SOFT-NEXT: adds r4, r7, #1
+; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
+; SOFT-NEXT: adds r4, r0, #1
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: sbcs r4, r6
; SOFT-NEXT: mov r4, r2
; SOFT-NEXT: sbcs r4, r5
; SOFT-NEXT: mov r4, r3
; SOFT-NEXT: sbcs r4, r5
-; SOFT-NEXT: mov r4, r0
+; SOFT-NEXT: mov r4, r7
; SOFT-NEXT: blt .LBB48_2
; SOFT-NEXT: @ %bb.1: @ %entry
; SOFT-NEXT: mov r4, r5
@@ -2930,53 +2927,48 @@ define i64 @stest_f32i64_mm(float %x) {
; SOFT-NEXT: @ %bb.3: @ %entry
; SOFT-NEXT: beq .LBB48_13
; SOFT-NEXT: .LBB48_4: @ %entry
-; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: beq .LBB48_14
; SOFT-NEXT: .LBB48_5: @ %entry
-; SOFT-NEXT: str r3, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: bne .LBB48_7
; SOFT-NEXT: .LBB48_6: @ %entry
-; SOFT-NEXT: mov r7, r6
+; SOFT-NEXT: str r6, [sp] @ 4-byte Spill
; SOFT-NEXT: .LBB48_7: @ %entry
-; SOFT-NEXT: lsls r3, r0, #31
-; SOFT-NEXT: rsbs r4, r7, #0
-; SOFT-NEXT: mov r4, r3
+; SOFT-NEXT: lsls r0, r7, #31
+; SOFT-NEXT: ldr r4, [sp] @ 4-byte Reload
+; SOFT-NEXT: rsbs r4, r4, #0
+; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: sbcs r4, r1
; SOFT-NEXT: mov r4, r6
-; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: sbcs r4, r2
-; SOFT-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
-; SOFT-NEXT: sbcs r6, r2
+; SOFT-NEXT: sbcs r6, r3
; SOFT-NEXT: bge .LBB48_15
; SOFT-NEXT: @ %bb.8: @ %entry
-; SOFT-NEXT: cmp r0, #0
+; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: beq .LBB48_16
; SOFT-NEXT: .LBB48_9: @ %entry
; SOFT-NEXT: bne .LBB48_11
; SOFT-NEXT: .LBB48_10: @ %entry
-; SOFT-NEXT: mov r1, r3
+; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: .LBB48_11: @ %entry
-; SOFT-NEXT: mov r0, r7
-; SOFT-NEXT: add sp, #12
+; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
+; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB48_12: @ %entry
; SOFT-NEXT: mov r3, r4
; SOFT-NEXT: bne .LBB48_4
; SOFT-NEXT: .LBB48_13: @ %entry
; SOFT-NEXT: mov r2, r4
-; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: bne .LBB48_5
; SOFT-NEXT: .LBB48_14: @ %entry
-; SOFT-NEXT: ldr r1, .LCPI48_0
-; SOFT-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: beq .LBB48_6
; SOFT-NEXT: b .LBB48_7
; SOFT-NEXT: .LBB48_15: @ %entry
-; SOFT-NEXT: mov r0, r5
-; SOFT-NEXT: cmp r0, #0
+; SOFT-NEXT: mov r7, r5
+; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB48_9
; SOFT-NEXT: .LBB48_16: @ %entry
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: str r7, [sp] @ 4-byte Spill
; SOFT-NEXT: beq .LBB48_10
; SOFT-NEXT: b .LBB48_11
; SOFT-NEXT: .p2align 2
@@ -3218,23 +3210,24 @@ define i64 @stest_f16i64_mm(half %x) {
; SOFT: @ %bb.0: @ %entry
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr}
-; SOFT-NEXT: .pad #12
-; SOFT-NEXT: sub sp, #12
+; SOFT-NEXT: .pad #4
+; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: bl __fixsfti
-; SOFT-NEXT: mov r7, r0
-; SOFT-NEXT: movs r0, #1
+; SOFT-NEXT: movs r7, #1
; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: ldr r6, .LCPI51_0
-; SOFT-NEXT: adds r4, r7, #1
+; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
+; SOFT-NEXT: adds r4, r0, #1
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: sbcs r4, r6
; SOFT-NEXT: mov r4, r2
; SOFT-NEXT: sbcs r4, r5
; SOFT-NEXT: mov r4, r3
; SOFT-NEXT: sbcs r4, r5
-; SOFT-NEXT: mov r4, r0
+; SOFT-NEXT: mov r4, r7
; SOFT-NEXT: blt .LBB51_2
; SOFT-NEXT: @ %bb.1: @ %entry
; SOFT-NEXT: mov r4, r5
@@ -3245,53 +3238,48 @@ define i64 @stest_f16i64_mm(half %x) {
; SOFT-NEXT: @ %bb.3: @ %entry
; SOFT-NEXT: beq .LBB51_13
; SOFT-NEXT: .LBB51_4: @ %entry
-; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: beq .LBB51_14
; SOFT-NEXT: .LBB51_5: @ %entry
-; SOFT-NEXT: str r3, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: bne .LBB51_7
; SOFT-NEXT: .LBB51_6: @ %entry
-; SOFT-NEXT: mov r7, r6
+; SOFT-NEXT: str r6, [sp] @ 4-byte Spill
; SOFT-NEXT: .LBB51_7: @ %entry
-; SOFT-NEXT: lsls r3, r0, #31
-; SOFT-NEXT: rsbs r4, r7, #0
-; SOFT-NEXT: mov r4, r3
+; SOFT-NEXT: lsls r0, r7, #31
+; SOFT-NEXT: ldr r4, [sp] @ 4-byte Reload
+; SOFT-NEXT: rsbs r4, r4, #0
+; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: sbcs r4, r1
; SOFT-NEXT: mov r4, r6
-; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: sbcs r4, r2
-; SOFT-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
-; SOFT-NEXT: sbcs r6, r2
+; SOFT-NEXT: sbcs r6, r3
; SOFT-NEXT: bge .LBB51_15
; SOFT-NEXT: @ %bb.8: @ %entry
-; SOFT-NEXT: cmp r0, #0
+; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: beq .LBB51_16
; SOFT-NEXT: .LBB51_9: @ %entry
; SOFT-NEXT: bne .LBB51_11
; SOFT-NEXT: .LBB51_10: @ %entry
-; SOFT-NEXT: mov r1, r3
+; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: .LBB51_11: @ %entry
-; SOFT-NEXT: mov r0, r7
-; SOFT-NEXT: add sp, #12
+; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
+; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB51_12: @ %entry
; SOFT-NEXT: mov r3, r4
; SOFT-NEXT: bne .LBB51_4
; SOFT-NEXT: .LBB51_13: @ %entry
; SOFT-NEXT: mov r2, r4
-; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: bne .LBB51_5
; SOFT-NEXT: .LBB51_14: @ %entry
-; SOFT-NEXT: ldr r1, .LCPI51_0
-; SOFT-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: beq .LBB51_6
; SOFT-NEXT: b .LBB51_7
; SOFT-NEXT: .LBB51_15: @ %entry
-; SOFT-NEXT: mov r0, r5
-; SOFT-NEXT: cmp r0, #0
+; SOFT-NEXT: mov r7, r5
+; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB51_9
; SOFT-NEXT: .LBB51_16: @ %entry
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: str r7, [sp] @ 4-byte Spill
; SOFT-NEXT: beq .LBB51_10
; SOFT-NEXT: b .LBB51_11
; SOFT-NEXT: .p2align 2
diff --git a/llvm/test/CodeGen/ARM/fptoi-sat-store.ll b/llvm/test/CodeGen/ARM/fptoi-sat-store.ll
index d895fe89a2cdc..a87da2c8285e9 100644
--- a/llvm/test/CodeGen/ARM/fptoi-sat-store.ll
+++ b/llvm/test/CodeGen/ARM/fptoi-sat-store.ll
@@ -159,23 +159,23 @@ define void @test_unsigned_i32_f32(ptr %d, float %f) nounwind {
; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
-; SOFT-NEXT: mov r6, r1
+; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: mov r0, r1
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge
-; SOFT-NEXT: mov r7, r0
-; SOFT-NEXT: mov r0, r6
+; SOFT-NEXT: mov r6, r0
+; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_f2uiz
; SOFT-NEXT: mov r4, r0
-; SOFT-NEXT: cmp r7, #0
+; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB2_2
; SOFT-NEXT: @ %bb.1:
-; SOFT-NEXT: mov r4, r7
+; SOFT-NEXT: mov r4, r6
; SOFT-NEXT: .LBB2_2:
; SOFT-NEXT: ldr r1, .LCPI2_0
-; SOFT-NEXT: mov r0, r6
+; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB2_4
diff --git a/llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll b/llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
index bccb0ad150509..c78a050ad197e 100644
--- a/llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
@@ -657,18 +657,19 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bl __aeabi_f2lz
-; SOFT-NEXT: movs r2, #1
-; SOFT-NEXT: lsls r7, r2, #31
+; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: movs r0, #1
+; SOFT-NEXT: lsls r0, r0, #31
; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB7_2
; SOFT-NEXT: @ %bb.1:
-; SOFT-NEXT: mov r0, r6
+; SOFT-NEXT: mov r7, r6
; SOFT-NEXT: .LBB7_2:
-; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: beq .LBB7_4
; SOFT-NEXT: @ %bb.3:
-; SOFT-NEXT: mov r7, r1
+; SOFT-NEXT: mov r0, r1
; SOFT-NEXT: .LBB7_4:
+; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: ldr r1, .LCPI7_0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bl __aeabi_fcmpgt
@@ -677,11 +678,12 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB7_6
; SOFT-NEXT: @ %bb.5:
-; SOFT-NEXT: ldr r7, .LCPI7_1
+; SOFT-NEXT: ldr r0, .LCPI7_1
+; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: .LBB7_6:
; SOFT-NEXT: bne .LBB7_8
; SOFT-NEXT: @ %bb.7:
-; SOFT-NEXT: ldr r5, [sp] @ 4-byte Reload
+; SOFT-NEXT: mov r5, r7
; SOFT-NEXT: .LBB7_8:
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r4
@@ -694,7 +696,7 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; SOFT-NEXT: .LBB7_10:
; SOFT-NEXT: bne .LBB7_12
; SOFT-NEXT: @ %bb.11:
-; SOFT-NEXT: mov r6, r7
+; SOFT-NEXT: ldr r6, [sp] @ 4-byte Reload
; SOFT-NEXT: .LBB7_12:
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: add sp, #4
@@ -3134,18 +3136,19 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bl __aeabi_f2lz
-; SOFT-NEXT: movs r2, #1
-; SOFT-NEXT: lsls r7, r2, #31
+; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: movs r0, #1
+; SOFT-NEXT: lsls r0, r0, #31
; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB27_2
; SOFT-NEXT: @ %bb.1:
-; SOFT-NEXT: mov r0, r6
+; SOFT-NEXT: mov r7, r6
; SOFT-NEXT: .LBB27_2:
-; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: beq .LBB27_4
; SOFT-NEXT: @ %bb.3:
-; SOFT-NEXT: mov r7, r1
+; SOFT-NEXT: mov r0, r1
; SOFT-NEXT: .LBB27_4:
+; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: ldr r1, .LCPI27_0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bl __aeabi_fcmpgt
@@ -3154,11 +3157,12 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB27_6
; SOFT-NEXT: @ %bb.5:
-; SOFT-NEXT: ldr r7, .LCPI27_1
+; SOFT-NEXT: ldr r0, .LCPI27_1
+; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: .LBB27_6:
; SOFT-NEXT: bne .LBB27_8
; SOFT-NEXT: @ %bb.7:
-; SOFT-NEXT: ldr r5, [sp] @ 4-byte Reload
+; SOFT-NEXT: mov r5, r7
; SOFT-NEXT: .LBB27_8:
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r4
@@ -3171,7 +3175,7 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; SOFT-NEXT: .LBB27_10:
; SOFT-NEXT: bne .LBB27_12
; SOFT-NEXT: @ %bb.11:
-; SOFT-NEXT: mov r6, r7
+; SOFT-NEXT: ldr r6, [sp] @ 4-byte Reload
; SOFT-NEXT: .LBB27_12:
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: add sp, #4
diff --git a/llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll b/llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
index 5ea9a79483873..9de8dc2a8cadd 100644
--- a/llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
@@ -613,33 +613,33 @@ define i100 @test_signed_i100_f32(float %f) nounwind {
; SOFT-NEXT: .pad #12
; SOFT-NEXT: sub sp, #12
; SOFT-NEXT: mov r4, r0
-; SOFT-NEXT: movs r6, #0
-; SOFT-NEXT: mov r1, r6
+; SOFT-NEXT: movs r7, #0
+; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bl __fixunssfti
; SOFT-NEXT: mov r5, r0
-; SOFT-NEXT: cmp r7, #0
+; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: beq .LBB8_11
; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: beq .LBB8_12
; SOFT-NEXT: .LBB8_2:
; SOFT-NEXT: bne .LBB8_4
; SOFT-NEXT: .LBB8_3:
-; SOFT-NEXT: mov r1, r7
+; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: .LBB8_4:
; SOFT-NEXT: str r1, [sp] @ 4-byte Spill
; SOFT-NEXT: str r2, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: bne .LBB8_6
; SOFT-NEXT: @ %bb.5:
-; SOFT-NEXT: mov r5, r7
+; SOFT-NEXT: mov r5, r6
; SOFT-NEXT: .LBB8_6:
; SOFT-NEXT: ldr r1, .LCPI8_0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bl __aeabi_fcmpgt
-; SOFT-NEXT: mvns r2, r6
+; SOFT-NEXT: mvns r2, r7
; SOFT-NEXT: movs r3, #15
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r2
@@ -655,10 +655,10 @@ define i100 @test_signed_i100_f32(float %f) nounwind {
; SOFT-NEXT: add sp, #12
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB8_11:
-; SOFT-NEXT: mov r3, r7
+; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bne .LBB8_2
; SOFT-NEXT: .LBB8_12:
-; SOFT-NEXT: mov r2, r7
+; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: beq .LBB8_3
; SOFT-NEXT: b .LBB8_4
; SOFT-NEXT: .LBB8_13:
@@ -845,30 +845,30 @@ define i1 @test_signed_i1_f64(double %f) nounwind {
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r4, r1
-; SOFT-NEXT: mov r5, r0
-; SOFT-NEXT: movs r6, #0
-; SOFT-NEXT: mov r2, r6
-; SOFT-NEXT: mov r3, r6
+; SOFT-NEXT: mov r6, r0
+; SOFT-NEXT: movs r7, #0
+; SOFT-NEXT: mov r2, r7
+; SOFT-NEXT: mov r3, r7
; SOFT-NEXT: bl __aeabi_dcmpge
-; SOFT-NEXT: mov r7, r0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r5, r0
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_d2uiz
-; SOFT-NEXT: cmp r7, #0
+; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB10_2
; SOFT-NEXT: @ %bb.1:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB10_2:
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: ldr r3, .LCPI10_0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
-; SOFT-NEXT: mov r2, r6
+; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB10_4
; SOFT-NEXT: @ %bb.3:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB10_4:
@@ -927,30 +927,30 @@ define i8 @test_signed_i8_f64(double %f) nounwind {
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r4, r1
-; SOFT-NEXT: mov r5, r0
-; SOFT-NEXT: movs r6, #0
-; SOFT-NEXT: mov r2, r6
-; SOFT-NEXT: mov r3, r6
+; SOFT-NEXT: mov r6, r0
+; SOFT-NEXT: movs r7, #0
+; SOFT-NEXT: mov r2, r7
+; SOFT-NEXT: mov r3, r7
; SOFT-NEXT: bl __aeabi_dcmpge
-; SOFT-NEXT: mov r7, r0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r5, r0
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_d2uiz
-; SOFT-NEXT: cmp r7, #0
+; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB11_2
; SOFT-NEXT: @ %bb.1:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB11_2:
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: ldr r3, .LCPI11_0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
-; SOFT-NEXT: mov r2, r6
+; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB11_4
; SOFT-NEXT: @ %bb.3:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB11_4:
@@ -1017,30 +1017,30 @@ define i13 @test_signed_i13_f64(double %f) nounwind {
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r4, r1
-; SOFT-NEXT: mov r5, r0
-; SOFT-NEXT: movs r6, #0
-; SOFT-NEXT: mov r2, r6
-; SOFT-NEXT: mov r3, r6
+; SOFT-NEXT: mov r6, r0
+; SOFT-NEXT: movs r7, #0
+; SOFT-NEXT: mov r2, r7
+; SOFT-NEXT: mov r3, r7
; SOFT-NEXT: bl __aeabi_dcmpge
-; SOFT-NEXT: mov r7, r0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r5, r0
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_d2uiz
-; SOFT-NEXT: cmp r7, #0
+; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB12_2
; SOFT-NEXT: @ %bb.1:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB12_2:
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: ldr r3, .LCPI12_0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
-; SOFT-NEXT: mov r2, r6
+; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB12_4
; SOFT-NEXT: @ %bb.3:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB12_4:
@@ -1109,30 +1109,30 @@ define i16 @test_signed_i16_f64(double %f) nounwind {
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r4, r1
-; SOFT-NEXT: mov r5, r0
-; SOFT-NEXT: movs r6, #0
-; SOFT-NEXT: mov r2, r6
-; SOFT-NEXT: mov r3, r6
+; SOFT-NEXT: mov r6, r0
+; SOFT-NEXT: movs r7, #0
+; SOFT-NEXT: mov r2, r7
+; SOFT-NEXT: mov r3, r7
; SOFT-NEXT: bl __aeabi_dcmpge
-; SOFT-NEXT: mov r7, r0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r5, r0
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_d2uiz
-; SOFT-NEXT: cmp r7, #0
+; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB13_2
; SOFT-NEXT: @ %bb.1:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB13_2:
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: ldr r3, .LCPI13_0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
-; SOFT-NEXT: mov r2, r6
+; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB13_4
; SOFT-NEXT: @ %bb.3:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB13_4:
@@ -1201,30 +1201,30 @@ define i19 @test_signed_i19_f64(double %f) nounwind {
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r4, r1
-; SOFT-NEXT: mov r5, r0
-; SOFT-NEXT: movs r6, #0
-; SOFT-NEXT: mov r2, r6
-; SOFT-NEXT: mov r3, r6
+; SOFT-NEXT: mov r6, r0
+; SOFT-NEXT: movs r7, #0
+; SOFT-NEXT: mov r2, r7
+; SOFT-NEXT: mov r3, r7
; SOFT-NEXT: bl __aeabi_dcmpge
-; SOFT-NEXT: mov r7, r0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r5, r0
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_d2uiz
-; SOFT-NEXT: cmp r7, #0
+; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB14_2
; SOFT-NEXT: @ %bb.1:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB14_2:
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: ldr r3, .LCPI14_0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
-; SOFT-NEXT: mov r2, r6
+; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB14_4
; SOFT-NEXT: @ %bb.3:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB14_4:
@@ -1294,30 +1294,30 @@ define i32 @test_signed_i32_f64(double %f) nounwind {
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r5, r1
-; SOFT-NEXT: mov r6, r0
+; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: movs r4, #0
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: mov r3, r4
; SOFT-NEXT: bl __aeabi_dcmpge
-; SOFT-NEXT: mov r7, r0
-; SOFT-NEXT: mov r0, r6
+; SOFT-NEXT: mov r6, r0
+; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_d2uiz
-; SOFT-NEXT: cmp r7, #0
+; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB15_2
; SOFT-NEXT: @ %bb.1:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: .LBB15_2:
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: ldr r2, .LCPI15_0
; SOFT-NEXT: ldr r3, .LCPI15_1
-; SOFT-NEXT: mov r0, r6
+; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB15_4
; SOFT-NEXT: @ %bb.3:
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB15_4:
@@ -1475,29 +1475,29 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r4, r1
-; SOFT-NEXT: mov r5, r0
+; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: movs r7, #0
; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: mov r3, r7
; SOFT-NEXT: bl __aeabi_dcmpge
-; SOFT-NEXT: mov r6, r0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r5, r0
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_d2ulz
-; SOFT-NEXT: cmp r6, #0
+; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB17_2
; SOFT-NEXT: @ %bb.1:
-; SOFT-NEXT: mov r1, r6
+; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: .LBB17_2:
; SOFT-NEXT: str r1, [sp] @ 4-byte Spill
; SOFT-NEXT: bne .LBB17_4
; SOFT-NEXT: @ %bb.3:
-; SOFT-NEXT: mov r0, r6
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB17_4:
-; SOFT-NEXT: mov r6, r0
+; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mvns r7, r7
; SOFT-NEXT: ldr r3, .LCPI17_0
-; SOFT-NEXT: mov r0, r5
+; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: bl __aeabi_dcmpgt
@@ -1505,7 +1505,7 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bne .LBB17_6
; SOFT-NEXT: @ %bb.5:
-; SOFT-NEXT: mov r0, r6
+; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB17_6:
; SOFT-NEXT: bne .LBB17_8
; SOFT-NEXT: @ %bb.7:
@@ -1729,35 +1729,35 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; SOFT-NEXT: .pad #12
; SOFT-NEXT: sub sp, #12
; SOFT-NEXT: mov r6, r1
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpge
-; SOFT-NEXT: mov r4, r0
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __fixunsdfti
-; SOFT-NEXT: cmp r4, #0
+; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: beq .LBB19_12
; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: beq .LBB19_13
; SOFT-NEXT: .LBB19_2:
; SOFT-NEXT: bne .LBB19_4
; SOFT-NEXT: .LBB19_3:
-; SOFT-NEXT: mov r1, r4
+; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: .LBB19_4:
; SOFT-NEXT: str r1, [sp] @ 4-byte Spill
; SOFT-NEXT: str r2, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: bne .LBB19_6
; SOFT-NEXT: @ %bb.5:
-; SOFT-NEXT: mov r0, r4
+; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: .LBB19_6:
-; SOFT-NEXT: mov r4, r0
+; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mvns r5, r5
; SOFT-NEXT: ldr r3, .LCPI19_0
-; SOFT-NEXT: mov r0, r7
+; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: bl __aeabi_dcmpgt
@@ -1779,14 +1779,14 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; SOFT-NEXT: add sp, #12
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB19_12:
-; SOFT-NEXT: mov r3, r4
+; SOFT-NEXT: mov r3, r7
; SOFT-NEXT: bne .LBB19_2
; SOFT-NEXT: .LBB19_13:
-; SOFT-NEXT: mov r2, r4
+; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: beq .LBB19_3
; SOFT-NEXT: b .LBB19_4
; SOFT-NEXT: .LBB19_14:
-; SOFT-NEXT: mov r0, r4
+; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bne .LBB19_8
; SOFT-NEXT: .LBB19_15:
@@ -2580,33 +2580,33 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: mov r4, r0
-; SOFT-NEXT: movs r6, #0
-; SOFT-NEXT: mov r1, r6
+; SOFT-NEXT: movs r7, #0
+; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
-; SOFT-NEXT: mov r7, r0
+; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bl __fixunssfti
; SOFT-NEXT: mov r5, r0
-; SOFT-NEXT: cmp r7, #0
+; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: beq .LBB28_11
; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: beq .LBB28_12
; SOFT-NEXT: .LBB28_2:
; SOFT-NEXT: bne .LBB28_4
; SOFT-NEXT: .LBB28_3:
-; SOFT-NEXT: mov r1, r7
+; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: .LBB28_4:
; SOFT-NEXT: str r1, [sp] @ 4-byte Spill
; SOFT-NEXT: str r2, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: bne .LBB28_6
; SOFT-NEXT: @ %bb.5:
-; SOFT-NEXT: mov r5, r7
+; SOFT-NEXT: mov r5, r6
; SOFT-NEXT: .LBB28_6:
; SOFT-NEXT: ldr r1, .LCPI28_0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bl __aeabi_fcmpgt
-; SOFT-NEXT: mvns r2, r6
+; SOFT-NEXT: mvns r2, r7
; SOFT-NEXT: movs r3, #15
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r2
@@ -2622,10 +2622,10 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; SOFT-NEXT: add sp, #12
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB28_11:
-; SOFT-NEXT: mov r3, r7
+; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bne .LBB28_2
; SOFT-NEXT: .LBB28_12:
-; SOFT-NEXT: mov r2, r7
+; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: beq .LBB28_3
; SOFT-NEXT: b .LBB28_4
; SOFT-NEXT: .LBB28_13:
diff --git a/llvm/test/CodeGen/ARM/sat-to-bitop.ll b/llvm/test/CodeGen/ARM/sat-to-bitop.ll
index dcd396749ce57..dfcc555a36de2 100644
--- a/llvm/test/CodeGen/ARM/sat-to-bitop.ll
+++ b/llvm/test/CodeGen/ARM/sat-to-bitop.ll
@@ -165,16 +165,16 @@ define i16 @sat1_base_16bit(i16 %x) #0 {
;
; CHECK-T-LABEL: sat1_base_16bit:
; CHECK-T: @ %bb.0: @ %entry
-; CHECK-T-NEXT: movs r1, #0
-; CHECK-T-NEXT: mvns r1, r1
-; CHECK-T-NEXT: lsls r2, r0, #16
+; CHECK-T-NEXT: movs r1, r0
+; CHECK-T-NEXT: movs r0, #0
+; CHECK-T-NEXT: mvns r0, r0
+; CHECK-T-NEXT: lsls r2, r1, #16
; CHECK-T-NEXT: asrs r2, r2, #16
-; CHECK-T-NEXT: cmp r2, r1
+; CHECK-T-NEXT: cmp r2, r0
; CHECK-T-NEXT: blt .LBB5_2
; CHECK-T-NEXT: @ %bb.1: @ %entry
-; CHECK-T-NEXT: movs r1, r0
-; CHECK-T-NEXT: .LBB5_2: @ %entry
; CHECK-T-NEXT: movs r0, r1
+; CHECK-T-NEXT: .LBB5_2: @ %entry
; CHECK-T-NEXT: bx lr
;
; CHECK-T2-LABEL: sat1_base_16bit:
@@ -203,16 +203,16 @@ define i8 @sat1_base_8bit(i8 %x) #0 {
;
; CHECK-T-LABEL: sat1_base_8bit:
; CHECK-T: @ %bb.0: @ %entry
-; CHECK-T-NEXT: movs r1, #0
-; CHECK-T-NEXT: mvns r1, r1
-; CHECK-T-NEXT: lsls r2, r0, #24
+; CHECK-T-NEXT: movs r1, r0
+; CHECK-T-NEXT: movs r0, #0
+; CHECK-T-NEXT: mvns r0, r0
+; CHECK-T-NEXT: lsls r2, r1, #24
; CHECK-T-NEXT: asrs r2, r2, #24
-; CHECK-T-NEXT: cmp r2, r1
+; CHECK-T-NEXT: cmp r2, r0
; CHECK-T-NEXT: blt .LBB6_2
; CHECK-T-NEXT: @ %bb.1: @ %entry
-; CHECK-T-NEXT: movs r1, r0
-; CHECK-T-NEXT: .LBB6_2: @ %entry
; CHECK-T-NEXT: movs r0, r1
+; CHECK-T-NEXT: .LBB6_2: @ %entry
; CHECK-T-NEXT: bx lr
;
; CHECK-T2-LABEL: sat1_base_8bit:
diff --git a/llvm/test/CodeGen/BPF/jump_table_blockaddr.ll b/llvm/test/CodeGen/BPF/jump_table_blockaddr.ll
index fabbad13b28c3..880ba8fe495c3 100644
--- a/llvm/test/CodeGen/BPF/jump_table_blockaddr.ll
+++ b/llvm/test/CodeGen/BPF/jump_table_blockaddr.ll
@@ -59,14 +59,14 @@ llc -march=bpf -mcpu=v4 < test.ll \
; CHECK: .cfi_startproc
; CHECK: # %bb.0: # %entry
; CHECK: r2 = BPF.JT.0.0 ll
+; CHECK: r3 = *(u64 *)(r2 + 0)
+; CHECK: r2 = BPF.JT.0.1 ll
; CHECK: r2 = *(u64 *)(r2 + 0)
-; CHECK: r3 = BPF.JT.0.1 ll
-; CHECK: r3 = *(u64 *)(r3 + 0)
; CHECK: if w1 == 0 goto .LBB0_2
; CHECK: # %bb.1: # %entry
-; CHECK: r3 = r2
+; CHECK: r2 = r3
; CHECK: .LBB0_2: # %entry
-; CHECK: *(u64 *)(r10 - 8) = r3
+; CHECK: *(u64 *)(r10 - 8) = r2
; CHECK: r1 = *(u64 *)(r10 - 8)
; CHECK: gotox r1
; CHECK: .Ltmp0: # Block address taken
diff --git a/llvm/test/CodeGen/BPF/sockex2.ll b/llvm/test/CodeGen/BPF/sockex2.ll
index 6874751124b30..4ac573f62020e 100644
--- a/llvm/test/CodeGen/BPF/sockex2.ll
+++ b/llvm/test/CodeGen/BPF/sockex2.ll
@@ -311,7 +311,7 @@ flow_dissector.exit.thread: ; preds = %86, %12, %196, %199
; CHECK-LABEL: bpf_prog2:
; CHECK: r0 = *(u16 *)skb[12] # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00]
; CHECK: r0 = *(u16 *)skb[16] # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00]
-; CHECK: implicit-def: $r7
+; CHECK: implicit-def: $r1
; CHECK: r1 =
; CHECK: call 1 # encoding: [0x85,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
; CHECK: call 2 # encoding: [0x85,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
diff --git a/llvm/test/CodeGen/Hexagon/rdf-copy.ll b/llvm/test/CodeGen/Hexagon/rdf-copy.ll
index 084cc7e507922..ad8b5e2f0965e 100644
--- a/llvm/test/CodeGen/Hexagon/rdf-copy.ll
+++ b/llvm/test/CodeGen/Hexagon/rdf-copy.ll
@@ -15,7 +15,7 @@
; r0 = memw(r0 + #0)
; }
;
-; CHECK-LABEL: LBB0_1
+; CHECK-LABEL: %while.cond
; CHECK: [[DST:r[0-9]+]] = [[SRC:r[0-9]+]]
; CHECK-DAG: memw([[SRC]]
; CHECK-NOT: memw([[DST]]
diff --git a/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll b/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll
index cfb459c6d2055..45990c26d7877 100644
--- a/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll
@@ -9,8 +9,8 @@
; CHECK: += mpyi
; CHECK: [[REG1:(r[0-9]+)]] = memh
; CHECK: = extractu([[REG0:(r[0-9]+)]],
-; CHECK: = extractu([[REG0]],
; CHECK: [[REG2:(r[0-9]+)]] = memh
+; CHECK: = extractu([[REG0]],
; CHECK: endloop{{[01]}}
%union_h2_sem_t = type { i32 }
diff --git a/llvm/test/CodeGen/LoongArch/opt-pipeline.ll b/llvm/test/CodeGen/LoongArch/opt-pipeline.ll
index afc9db8af177e..334dfa39081c0 100644
--- a/llvm/test/CodeGen/LoongArch/opt-pipeline.ll
+++ b/llvm/test/CodeGen/LoongArch/opt-pipeline.ll
@@ -118,10 +118,10 @@
; LAXX-NEXT: Process Implicit Definitions
; LAXX-NEXT: Remove unreachable machine basic blocks
; LAXX-NEXT: Live Variable Analysis
-; LAXX-NEXT: Eliminate PHI nodes for register allocation
; LAXX-NEXT: MachineDominator Tree Construction
; LAXX-NEXT: Slot index numbering
; LAXX-NEXT: Live Interval Analysis
+; LAXX-NEXT: Eliminate PHI nodes for register allocation
; LAXX-NEXT: Two-Address instruction pass
; LAXX-NEXT: Register Coalescer
; LAXX-NEXT: Rename Disconnected Subregister Components
diff --git a/llvm/test/CodeGen/NVPTX/switch-loop-header.mir b/llvm/test/CodeGen/NVPTX/switch-loop-header.mir
index eecb3b9618871..0053053ba6db1 100644
--- a/llvm/test/CodeGen/NVPTX/switch-loop-header.mir
+++ b/llvm/test/CodeGen/NVPTX/switch-loop-header.mir
@@ -116,7 +116,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead [[DEF2:%[0-9]+]]:b32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:b32 = IMPLICIT_DEF
; CHECK-NEXT: GOTO %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir b/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
index 8bdf719f4bb5b..01707e1d326d8 100644
--- a/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
+++ b/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
@@ -70,24 +70,24 @@ body: |
# CHECK-NEXT: BCC 76, killed %3, %bb.2
# CHECK: bb.1:
# CHECK: %4:g8rc = ADDI8 killed %1, 24
-# CHECK-NEXT: %16:g8rc_and_g8rc_nox0 = COPY killed %4
+# CHECK-NEXT: %16:g8rc_and_g8rc_nox0 = COPY %4
# CHECK-NEXT: B %bb.4
# CHECK: bb.2:
# CHECK: %5:g8rc = ADDI8 killed %1, 24
# CHECK-NEXT: %6:g8rc = LI8 0
# CHECK-NEXT: %7:crrc = CMPLWI undef %8:gprc, 20
-# CHECK-NEXT: %14:g8rc = COPY killed %5
-# CHECK-NEXT: %15:g8rc = COPY killed %6
+# CHECK-NEXT: %14:g8rc = COPY %5
+# CHECK-NEXT: %15:g8rc = COPY %6
# CHECK: bb.3:
-# CHECK: %10:g8rc = COPY killed %15
-# CHECK-NEXT: %9:g8rc = COPY killed %14
-# CHECK-NEXT: %14:g8rc = COPY killed %10
+# CHECK: %10:g8rc = COPY %15
+# CHECK-NEXT: %9:g8rc = COPY %14
+# CHECK-NEXT: %14:g8rc = COPY %10
# CHECK-NEXT: %15:g8rc = IMPLICIT_DEF
-# CHECK-NEXT: %16:g8rc_and_g8rc_nox0 = COPY killed %9
+# CHECK-NEXT: %16:g8rc_and_g8rc_nox0 = COPY %9
# CHECK-NEXT: BCC 68, %7, %bb.3
# CHECK-NEXT: B %bb.4
# CHECK: bb.4:
-# CHECK: %12:g8rc_and_g8rc_nox0 = COPY killed %16
+# CHECK: %12:g8rc_and_g8rc_nox0 = COPY %16
# CHECK-NEXT: %13:g8rc = LI8 0
# CHECK-NEXT: STW8 killed %13, 0, killed %12 :: (store (s32))
# CHECK-NEXT: BLR8 implicit $lr8, implicit $rm
diff --git a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
index 077fb28fb3c7f..2ab7c950655ff 100644
--- a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
+++ b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
@@ -157,10 +157,10 @@
; CHECK-NEXT: Remove unreachable machine basic blocks
; CHECK-NEXT: Live Variable Analysis
; CHECK-NEXT: MachineDominator Tree Construction
-; CHECK-NEXT: Machine Natural Loop Construction
-; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
+; CHECK-NEXT: Machine Natural Loop Construction
+; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
diff --git a/llvm/test/CodeGen/PowerPC/all-atomics.ll b/llvm/test/CodeGen/PowerPC/all-atomics.ll
index 17b3b75a66800..4585809a01a07 100644
--- a/llvm/test/CodeGen/PowerPC/all-atomics.ll
+++ b/llvm/test/CodeGen/PowerPC/all-atomics.ll
@@ -4785,19 +4785,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: stw 0, 152(1)
; AIX32-NEXT: stw 29, 132(1) # 4-byte Folded Spill
; AIX32-NEXT: lwz 29, L..C0(2) # @sc
-; AIX32-NEXT: stw 26, 120(1) # 4-byte Folded Spill
+; AIX32-NEXT: stw 27, 124(1) # 4-byte Folded Spill
; AIX32-NEXT: not 3, 29
; AIX32-NEXT: stw 30, 136(1) # 4-byte Folded Spill
; AIX32-NEXT: lwz 30, L..C1(2) # @uc
; AIX32-NEXT: lbz 4, 0(30)
; AIX32-NEXT: lbz 5, 0(29)
-; AIX32-NEXT: stw 27, 124(1) # 4-byte Folded Spill
-; AIX32-NEXT: rlwinm 27, 29, 0, 0, 29
+; AIX32-NEXT: stw 28, 128(1) # 4-byte Folded Spill
+; AIX32-NEXT: rlwinm 28, 29, 0, 0, 29
; AIX32-NEXT: stw 14, 72(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 15, 76(1) # 4-byte Folded Spill
-; AIX32-NEXT: rlwinm 26, 3, 3, 27, 28
+; AIX32-NEXT: rlwinm 27, 3, 3, 27, 28
; AIX32-NEXT: li 3, 255
-; AIX32-NEXT: slw 3, 3, 26
+; AIX32-NEXT: slw 3, 3, 27
; AIX32-NEXT: stw 16, 80(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 17, 84(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 18, 88(1) # 4-byte Folded Spill
@@ -4808,33 +4808,33 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: stw 23, 108(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 24, 112(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 25, 116(1) # 4-byte Folded Spill
-; AIX32-NEXT: stw 28, 128(1) # 4-byte Folded Spill
+; AIX32-NEXT: stw 26, 120(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 31, 140(1) # 4-byte Folded Spill
; AIX32-NEXT: not 25, 3
-; AIX32-NEXT: lwarx 3, 0, 27
-; AIX32-NEXT: srw 6, 3, 26
+; AIX32-NEXT: lwarx 3, 0, 28
+; AIX32-NEXT: srw 6, 3, 27
; AIX32-NEXT: clrlwi 6, 6, 24
; AIX32-NEXT: cmplw 6, 4
; AIX32-NEXT: bne- 0, L..BB3_4
; AIX32-NEXT: # %bb.1: # %cmpxchg.fencedstore289
; AIX32-NEXT: sync
-; AIX32-NEXT: slw 5, 5, 26
+; AIX32-NEXT: slw 5, 5, 27
; AIX32-NEXT: L..BB3_2: # %cmpxchg.trystore288
; AIX32-NEXT: #
; AIX32-NEXT: and 6, 3, 25
; AIX32-NEXT: or 6, 6, 5
-; AIX32-NEXT: stwcx. 6, 0, 27
+; AIX32-NEXT: stwcx. 6, 0, 28
; AIX32-NEXT: beq+ 0, L..BB3_4
; AIX32-NEXT: # %bb.3: # %cmpxchg.releasedload287
; AIX32-NEXT: #
-; AIX32-NEXT: lwarx 3, 0, 27
-; AIX32-NEXT: srw 6, 3, 26
+; AIX32-NEXT: lwarx 3, 0, 28
+; AIX32-NEXT: srw 6, 3, 27
; AIX32-NEXT: clrlwi 6, 6, 24
; AIX32-NEXT: cmplw 6, 4
; AIX32-NEXT: beq+ 0, L..BB3_2
; AIX32-NEXT: L..BB3_4: # %cmpxchg.nostore285
; AIX32-NEXT: not 4, 30
-; AIX32-NEXT: srw 5, 3, 26
+; AIX32-NEXT: srw 5, 3, 27
; AIX32-NEXT: lwsync
; AIX32-NEXT: lbz 3, 0(30)
; AIX32-NEXT: rlwinm 24, 30, 0, 0, 29
@@ -4963,11 +4963,11 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: beq+ 0, L..BB3_18
; AIX32-NEXT: L..BB3_20: # %cmpxchg.nostore167
; AIX32-NEXT: lwsync
-; AIX32-NEXT: lwz 28, L..C5(2) # @ui
+; AIX32-NEXT: lwz 26, L..C5(2) # @ui
; AIX32-NEXT: stw 3, 0(15)
; AIX32-NEXT: lbz 4, 0(30)
; AIX32-NEXT: lbz 5, 0(29)
-; AIX32-NEXT: lwarx 3, 0, 28
+; AIX32-NEXT: lwarx 3, 0, 26
; AIX32-NEXT: cmplw 3, 4
; AIX32-NEXT: bne- 0, L..BB3_24
; AIX32-NEXT: # %bb.21: # %cmpxchg.fencedstore152
@@ -4975,16 +4975,16 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: sync
; AIX32-NEXT: L..BB3_22: # %cmpxchg.trystore151
; AIX32-NEXT: #
-; AIX32-NEXT: stwcx. 5, 0, 28
+; AIX32-NEXT: stwcx. 5, 0, 26
; AIX32-NEXT: beq+ 0, L..BB3_24
; AIX32-NEXT: # %bb.23: # %cmpxchg.releasedload150
; AIX32-NEXT: #
-; AIX32-NEXT: lwarx 3, 0, 28
+; AIX32-NEXT: lwarx 3, 0, 26
; AIX32-NEXT: cmplw 3, 4
; AIX32-NEXT: beq+ 0, L..BB3_22
; AIX32-NEXT: L..BB3_24: # %cmpxchg.nostore148
; AIX32-NEXT: lwsync
-; AIX32-NEXT: stw 3, 0(28)
+; AIX32-NEXT: stw 3, 0(26)
; AIX32-NEXT: lwz 31, L..C6(2) # @sll
; AIX32-NEXT: lbz 3, 0(29)
; AIX32-NEXT: li 14, 0
@@ -5022,24 +5022,24 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: stw 4, 4(31)
; AIX32-NEXT: stw 3, 0(31)
; AIX32-NEXT: lbz 3, 0(30)
-; AIX32-NEXT: lwarx 4, 0, 27
-; AIX32-NEXT: srw 6, 4, 26
+; AIX32-NEXT: lwarx 4, 0, 28
+; AIX32-NEXT: srw 6, 4, 27
; AIX32-NEXT: clrlwi 6, 6, 24
; AIX32-NEXT: cmplw 6, 3
; AIX32-NEXT: bne- 0, L..BB3_28
; AIX32-NEXT: # %bb.25: # %cmpxchg.fencedstore119
; AIX32-NEXT: sync
-; AIX32-NEXT: slw 5, 5, 26
+; AIX32-NEXT: slw 5, 5, 27
; AIX32-NEXT: L..BB3_26: # %cmpxchg.trystore118
; AIX32-NEXT: #
; AIX32-NEXT: and 4, 4, 25
; AIX32-NEXT: or 4, 4, 5
-; AIX32-NEXT: stwcx. 4, 0, 27
+; AIX32-NEXT: stwcx. 4, 0, 28
; AIX32-NEXT: beq+ 0, L..BB3_29
; AIX32-NEXT: # %bb.27: # %cmpxchg.releasedload117
; AIX32-NEXT: #
-; AIX32-NEXT: lwarx 4, 0, 27
-; AIX32-NEXT: srw 6, 4, 26
+; AIX32-NEXT: lwarx 4, 0, 28
+; AIX32-NEXT: srw 6, 4, 27
; AIX32-NEXT: clrlwi 6, 6, 24
; AIX32-NEXT: cmplw 6, 3
; AIX32-NEXT: beq+ 0, L..BB3_26
@@ -5055,7 +5055,7 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: li 4, 1
; AIX32-NEXT: lbz 5, 0(29)
; AIX32-NEXT: isel 3, 4, 3, 20
-; AIX32-NEXT: stw 3, 0(28)
+; AIX32-NEXT: stw 3, 0(26)
; AIX32-NEXT: lbz 3, 0(30)
; AIX32-NEXT: lwarx 4, 0, 24
; AIX32-NEXT: srw 6, 4, 23
@@ -5090,7 +5090,7 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: li 4, 1
; AIX32-NEXT: lbz 5, 0(29)
; AIX32-NEXT: isel 3, 4, 3, 20
-; AIX32-NEXT: stw 3, 0(28)
+; AIX32-NEXT: stw 3, 0(26)
; AIX32-NEXT: lbz 3, 0(30)
; AIX32-NEXT: lwarx 4, 0, 21
; AIX32-NEXT: srw 6, 4, 20
@@ -5127,7 +5127,7 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: li 4, 1
; AIX32-NEXT: lbz 5, 0(29)
; AIX32-NEXT: isel 3, 4, 3, 20
-; AIX32-NEXT: stw 3, 0(28)
+; AIX32-NEXT: stw 3, 0(26)
; AIX32-NEXT: lbz 3, 0(30)
; AIX32-NEXT: lwarx 4, 0, 18
; AIX32-NEXT: srw 6, 4, 17
@@ -5164,7 +5164,7 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: li 4, 1
; AIX32-NEXT: isel 3, 4, 3, 20
; AIX32-NEXT: lbz 4, 0(29)
-; AIX32-NEXT: stw 3, 0(28)
+; AIX32-NEXT: stw 3, 0(26)
; AIX32-NEXT: lbz 3, 0(30)
; AIX32-NEXT: lwarx 5, 0, 15
; AIX32-NEXT: cmplw 5, 3
@@ -5193,9 +5193,9 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: li 4, 1
; AIX32-NEXT: isel 3, 4, 3, 20
; AIX32-NEXT: lbz 4, 0(29)
-; AIX32-NEXT: stw 3, 0(28)
+; AIX32-NEXT: stw 3, 0(26)
; AIX32-NEXT: lbz 3, 0(30)
-; AIX32-NEXT: lwarx 5, 0, 28
+; AIX32-NEXT: lwarx 5, 0, 26
; AIX32-NEXT: cmplw 5, 3
; AIX32-NEXT: bne- 0, L..BB3_58
; AIX32-NEXT: # %bb.55: # %cmpxchg.fencedstore
@@ -5203,11 +5203,11 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: sync
; AIX32-NEXT: L..BB3_56: # %cmpxchg.trystore
; AIX32-NEXT: #
-; AIX32-NEXT: stwcx. 4, 0, 28
+; AIX32-NEXT: stwcx. 4, 0, 26
; AIX32-NEXT: beq+ 0, L..BB3_59
; AIX32-NEXT: # %bb.57: # %cmpxchg.releasedload
; AIX32-NEXT: #
-; AIX32-NEXT: lwarx 5, 0, 28
+; AIX32-NEXT: lwarx 5, 0, 26
; AIX32-NEXT: cmplw 5, 3
; AIX32-NEXT: beq+ 0, L..BB3_56
; AIX32-NEXT: L..BB3_58: # %cmpxchg.nostore
@@ -5225,7 +5225,7 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: li 7, 5
; AIX32-NEXT: li 8, 5
; AIX32-NEXT: extsb 6, 4
-; AIX32-NEXT: stw 3, 0(28)
+; AIX32-NEXT: stw 3, 0(26)
; AIX32-NEXT: lbz 3, 0(30)
; AIX32-NEXT: addi 4, 1, 64
; AIX32-NEXT: stw 31, 64(1)
@@ -5235,7 +5235,7 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: bl .__atomic_compare_exchange_8[PR]
; AIX32-NEXT: nop
; AIX32-NEXT: lbz 4, 0(29)
-; AIX32-NEXT: stw 3, 0(28)
+; AIX32-NEXT: stw 3, 0(26)
; AIX32-NEXT: lbz 3, 0(30)
; AIX32-NEXT: li 7, 5
; AIX32-NEXT: li 8, 5
@@ -5247,7 +5247,7 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 {
; AIX32-NEXT: srawi 5, 6, 31
; AIX32-NEXT: bl .__atomic_compare_exchange_8[PR]
; AIX32-NEXT: nop
-; AIX32-NEXT: stw 3, 0(28)
+; AIX32-NEXT: stw 3, 0(26)
; AIX32-NEXT: lwz 31, 140(1) # 4-byte Folded Reload
; AIX32-NEXT: lwz 30, 136(1) # 4-byte Folded Reload
; AIX32-NEXT: lwz 29, 132(1) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll b/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
index ff176c80ab342..afee0b2cc12eb 100644
--- a/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
+++ b/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
@@ -217,17 +217,17 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) {
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB4_4 Depth 2
; CHECK-NEXT: srw 8, 7, 3
-; CHECK-NEXT: clrlwi 9, 8, 24
-; CHECK-NEXT: sub 8, 9, 4
-; CHECK-NEXT: cmplw 8, 9
-; CHECK-NEXT: li 9, 0
+; CHECK-NEXT: clrlwi 8, 8, 24
+; CHECK-NEXT: sub 9, 8, 4
+; CHECK-NEXT: cmplw 9, 8
+; CHECK-NEXT: li 8, 0
; CHECK-NEXT: bgt 0, .LBB4_3
; CHECK-NEXT: # %bb.2: # %atomicrmw.start
; CHECK-NEXT: #
-; CHECK-NEXT: mr 9, 8
+; CHECK-NEXT: mr 8, 9
; CHECK-NEXT: .LBB4_3: # %atomicrmw.start
; CHECK-NEXT: #
-; CHECK-NEXT: slw 8, 9, 3
+; CHECK-NEXT: slw 8, 8, 3
; CHECK-NEXT: and 9, 7, 6
; CHECK-NEXT: or 9, 9, 8
; CHECK-NEXT: .LBB4_4: # %cmpxchg.start
@@ -276,17 +276,17 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) {
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB5_4 Depth 2
; CHECK-NEXT: srw 8, 7, 3
-; CHECK-NEXT: clrlwi 9, 8, 16
-; CHECK-NEXT: sub 8, 9, 4
-; CHECK-NEXT: cmplw 8, 9
-; CHECK-NEXT: li 9, 0
+; CHECK-NEXT: clrlwi 8, 8, 16
+; CHECK-NEXT: sub 9, 8, 4
+; CHECK-NEXT: cmplw 9, 8
+; CHECK-NEXT: li 8, 0
; CHECK-NEXT: bgt 0, .LBB5_3
; CHECK-NEXT: # %bb.2: # %atomicrmw.start
; CHECK-NEXT: #
-; CHECK-NEXT: mr 9, 8
+; CHECK-NEXT: mr 8, 9
; CHECK-NEXT: .LBB5_3: # %atomicrmw.start
; CHECK-NEXT: #
-; CHECK-NEXT: slw 8, 9, 3
+; CHECK-NEXT: slw 8, 8, 3
; CHECK-NEXT: and 9, 7, 6
; CHECK-NEXT: or 9, 9, 8
; CHECK-NEXT: .LBB5_4: # %cmpxchg.start
diff --git a/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
index 4dc6d0ad3d5c7..0ed3432f64351 100644
--- a/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
+++ b/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
@@ -16,17 +16,17 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
; CHECK-NEXT: .LBB0_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB0_4 Depth 2
-; CHECK-NEXT: srw 8, 7, 3
-; CHECK-NEXT: clrlwi 9, 8, 24
-; CHECK-NEXT: cmplw 9, 4
-; CHECK-NEXT: li 9, 0
+; CHECK-NEXT: srw 9, 7, 3
+; CHECK-NEXT: clrlwi 8, 9, 24
+; CHECK-NEXT: cmplw 8, 4
+; CHECK-NEXT: li 8, 0
; CHECK-NEXT: bge 0, .LBB0_3
; CHECK-NEXT: # %bb.2: # %atomicrmw.start
; CHECK-NEXT: #
-; CHECK-NEXT: addi 9, 8, 1
+; CHECK-NEXT: addi 8, 9, 1
; CHECK-NEXT: .LBB0_3: # %atomicrmw.start
; CHECK-NEXT: #
-; CHECK-NEXT: clrlwi 8, 9, 24
+; CHECK-NEXT: clrlwi 8, 8, 24
; CHECK-NEXT: slw 8, 8, 3
; CHECK-NEXT: and 9, 7, 6
; CHECK-NEXT: or 9, 9, 8
@@ -75,17 +75,17 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
; CHECK-NEXT: .LBB1_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB1_4 Depth 2
-; CHECK-NEXT: srw 8, 7, 3
-; CHECK-NEXT: clrlwi 9, 8, 16
-; CHECK-NEXT: cmplw 9, 4
-; CHECK-NEXT: li 9, 0
+; CHECK-NEXT: srw 9, 7, 3
+; CHECK-NEXT: clrlwi 8, 9, 16
+; CHECK-NEXT: cmplw 8, 4
+; CHECK-NEXT: li 8, 0
; CHECK-NEXT: bge 0, .LBB1_3
; CHECK-NEXT: # %bb.2: # %atomicrmw.start
; CHECK-NEXT: #
-; CHECK-NEXT: addi 9, 8, 1
+; CHECK-NEXT: addi 8, 9, 1
; CHECK-NEXT: .LBB1_3: # %atomicrmw.start
; CHECK-NEXT: #
-; CHECK-NEXT: clrlwi 8, 9, 16
+; CHECK-NEXT: clrlwi 8, 8, 16
; CHECK-NEXT: slw 8, 8, 3
; CHECK-NEXT: and 9, 7, 6
; CHECK-NEXT: or 9, 9, 8
diff --git a/llvm/test/CodeGen/PowerPC/common-chain.ll b/llvm/test/CodeGen/PowerPC/common-chain.ll
index 8283e7bac3457..748143ed5d8f8 100644
--- a/llvm/test/CodeGen/PowerPC/common-chain.ll
+++ b/llvm/test/CodeGen/PowerPC/common-chain.ll
@@ -721,13 +721,6 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
; CHECK-LABEL: spill_reduce_succ:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpdi r6, 0
-; CHECK-NEXT: ble cr0, .LBB7_9
-; CHECK-NEXT: # %bb.1: # %for.body.preheader
-; CHECK-NEXT: sldi r6, r6, 2
-; CHECK-NEXT: li r11, 1
-; CHECK-NEXT: std r26, -48(r1) # 8-byte Folded Spill
-; CHECK-NEXT: mr r26, r10
-; CHECK-NEXT: cmpdi r6, 1
; CHECK-NEXT: std r14, -144(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r15, -136(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r16, -128(r1) # 8-byte Folded Spill
@@ -740,85 +733,85 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
; CHECK-NEXT: std r23, -72(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r24, -64(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r25, -56(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r31, -8(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r2, -152(r1) # 8-byte Folded Spill
-; CHECK-NEXT: iselgt r11, r6, r11
-; CHECK-NEXT: addi r12, r11, -1
-; CHECK-NEXT: cmpldi r12, 3
-; CHECK-NEXT: clrldi r6, r11, 63
-; CHECK-NEXT: blt cr0, .LBB7_5
-; CHECK-NEXT: # %bb.2: # %for.body.preheader.new
-; CHECK-NEXT: rldicl r11, r11, 62, 2
-; CHECK-NEXT: sldi r20, r8, 3
-; CHECK-NEXT: mr r14, r7
-; CHECK-NEXT: sldi r7, r7, 3
-; CHECK-NEXT: sldi r21, r9, 3
+; CHECK-NEXT: std r9, -184(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r8, -176(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r7, -168(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r3, -160(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r9, -208(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r8, -184(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r5, -200(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r4, -168(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r11, -192(r1) # 8-byte Folded Spill
+; CHECK-NEXT: ble cr0, .LBB7_7
+; CHECK-NEXT: # %bb.1: # %for.body.preheader
+; CHECK-NEXT: sldi r6, r6, 2
+; CHECK-NEXT: li r7, 1
+; CHECK-NEXT: mr r9, r10
+; CHECK-NEXT: cmpdi r6, 1
+; CHECK-NEXT: iselgt r7, r6, r7
+; CHECK-NEXT: addi r8, r7, -1
+; CHECK-NEXT: clrldi r6, r7, 63
+; CHECK-NEXT: cmpldi r8, 3
+; CHECK-NEXT: blt cr0, .LBB7_4
+; CHECK-NEXT: # %bb.2: # %for.body.preheader.new
+; CHECK-NEXT: ld r16, -184(r1) # 8-byte Folded Reload
; CHECK-NEXT: sldi r11, r10, 5
-; CHECK-NEXT: add r0, r11, r20
-; CHECK-NEXT: add r12, r11, r21
+; CHECK-NEXT: ld r15, -176(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r14, -168(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r2, -160(r1) # 8-byte Folded Reload
+; CHECK-NEXT: rldicl r7, r7, 62, 2
+; CHECK-NEXT: sldi r8, r16, 3
+; CHECK-NEXT: sldi r3, r14, 3
+; CHECK-NEXT: add r9, r11, r8
+; CHECK-NEXT: add r12, r5, r9
+; CHECK-NEXT: sldi r9, r15, 3
+; CHECK-NEXT: add r0, r11, r9
; CHECK-NEXT: add r30, r5, r0
-; CHECK-NEXT: add r0, r11, r7
-; CHECK-NEXT: std r21, -216(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r20, -224(r1) # 8-byte Folded Spill
-; CHECK-NEXT: add r12, r5, r12
+; CHECK-NEXT: add r0, r11, r3
; CHECK-NEXT: add r29, r5, r0
; CHECK-NEXT: add r28, r4, r0
-; CHECK-NEXT: add r27, r3, r0
+; CHECK-NEXT: add r27, r2, r0
; CHECK-NEXT: mulli r0, r10, 24
-; CHECK-NEXT: std r14, -176(r1) # 8-byte Folded Spill
-; CHECK-NEXT: add r26, r0, r21
-; CHECK-NEXT: add r25, r0, r20
-; CHECK-NEXT: add r0, r0, r7
+; CHECK-NEXT: add r26, r0, r8
+; CHECK-NEXT: add r25, r0, r9
+; CHECK-NEXT: add r0, r0, r3
; CHECK-NEXT: add r24, r5, r0
; CHECK-NEXT: add r23, r4, r0
-; CHECK-NEXT: add r22, r3, r0
+; CHECK-NEXT: add r22, r2, r0
; CHECK-NEXT: sldi r0, r10, 4
; CHECK-NEXT: add r26, r5, r26
; CHECK-NEXT: add r25, r5, r25
-; CHECK-NEXT: add r21, r0, r21
-; CHECK-NEXT: add r20, r0, r20
-; CHECK-NEXT: add r0, r0, r7
+; CHECK-NEXT: add r21, r0, r8
+; CHECK-NEXT: add r20, r0, r9
+; CHECK-NEXT: add r0, r0, r3
; CHECK-NEXT: add r19, r5, r0
; CHECK-NEXT: add r18, r4, r0
-; CHECK-NEXT: add r17, r3, r0
-; CHECK-NEXT: add r0, r10, r9
+; CHECK-NEXT: add r17, r2, r0
+; CHECK-NEXT: add r0, r10, r16
; CHECK-NEXT: add r21, r5, r21
; CHECK-NEXT: add r20, r5, r20
; CHECK-NEXT: sldi r0, r0, 3
; CHECK-NEXT: add r16, r5, r0
-; CHECK-NEXT: add r0, r10, r8
+; CHECK-NEXT: add r0, r10, r15
; CHECK-NEXT: sldi r0, r0, 3
; CHECK-NEXT: add r15, r5, r0
; CHECK-NEXT: add r0, r10, r14
; CHECK-NEXT: sldi r0, r0, 3
-; CHECK-NEXT: add r2, r3, r0
-; CHECK-NEXT: ld r3, -224(r1) # 8-byte Folded Reload
; CHECK-NEXT: add r14, r5, r0
; CHECK-NEXT: add r31, r4, r0
-; CHECK-NEXT: sub r0, r3, r7
-; CHECK-NEXT: ld r3, -192(r1) # 8-byte Folded Reload
-; CHECK-NEXT: rldicl r9, r3, 2, 1
-; CHECK-NEXT: ld r3, -216(r1) # 8-byte Folded Reload
+; CHECK-NEXT: add r2, r2, r0
+; CHECK-NEXT: sub r0, r9, r3
+; CHECK-NEXT: rldicl r9, r7, 2, 1
+; CHECK-NEXT: sub r7, r8, r3
; CHECK-NEXT: addi r8, r9, -4
-; CHECK-NEXT: rldicl r8, r8, 62, 2
-; CHECK-NEXT: sub r7, r3, r7
; CHECK-NEXT: ori r3, r9, 1
+; CHECK-NEXT: rldicl r8, r8, 62, 2
+; CHECK-NEXT: mulld r9, r10, r3
; CHECK-NEXT: addi r8, r8, 1
-; CHECK-NEXT: mulld r3, r10, r3
; CHECK-NEXT: mtctr r8
; CHECK-NEXT: li r8, 0
-; CHECK-NEXT: std r10, -192(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r3, -216(r1) # 8-byte Folded Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB7_3: # %for.body
; CHECK-NEXT: #
@@ -905,38 +898,33 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
; CHECK-NEXT: stfdx f0, r12, r8
; CHECK-NEXT: add r8, r8, r11
; CHECK-NEXT: bdnz .LBB7_3
-; CHECK-NEXT: # %bb.4:
-; CHECK-NEXT: ld r3, -160(r1) # 8-byte Folded Reload
-; CHECK-NEXT: ld r4, -168(r1) # 8-byte Folded Reload
-; CHECK-NEXT: ld r7, -176(r1) # 8-byte Folded Reload
-; CHECK-NEXT: ld r8, -184(r1) # 8-byte Folded Reload
-; CHECK-NEXT: ld r10, -192(r1) # 8-byte Folded Reload
-; CHECK-NEXT: ld r5, -200(r1) # 8-byte Folded Reload
-; CHECK-NEXT: ld r9, -208(r1) # 8-byte Folded Reload
-; CHECK-NEXT: ld r26, -216(r1) # 8-byte Folded Reload
-; CHECK-NEXT: .LBB7_5: # %for.cond.cleanup.loopexit.unr-lcssa
+; CHECK-NEXT: .LBB7_4: # %for.cond.cleanup.loopexit.unr-lcssa
; CHECK-NEXT: cmpldi r6, 0
-; CHECK-NEXT: beq cr0, .LBB7_8
-; CHECK-NEXT: # %bb.6: # %for.body.epil.preheader
-; CHECK-NEXT: add r11, r26, r9
-; CHECK-NEXT: add r12, r26, r8
-; CHECK-NEXT: add r9, r26, r7
-; CHECK-NEXT: sldi r27, r10, 3
-; CHECK-NEXT: sldi r11, r11, 3
-; CHECK-NEXT: sldi r0, r12, 3
-; CHECK-NEXT: sldi r9, r9, 3
-; CHECK-NEXT: add r28, r5, r11
-; CHECK-NEXT: add r10, r4, r11
-; CHECK-NEXT: add r11, r3, r11
-; CHECK-NEXT: add r12, r5, r0
-; CHECK-NEXT: add r30, r4, r0
-; CHECK-NEXT: add r29, r3, r0
-; CHECK-NEXT: add r5, r5, r9
-; CHECK-NEXT: add r4, r4, r9
-; CHECK-NEXT: add r3, r3, r9
+; CHECK-NEXT: beq cr0, .LBB7_7
+; CHECK-NEXT: # %bb.5: # %for.body.epil.preheader
+; CHECK-NEXT: ld r3, -184(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r0, -160(r1) # 8-byte Folded Reload
+; CHECK-NEXT: sldi r8, r10, 3
+; CHECK-NEXT: add r3, r9, r3
+; CHECK-NEXT: sldi r3, r3, 3
+; CHECK-NEXT: add r7, r5, r3
+; CHECK-NEXT: add r10, r4, r3
+; CHECK-NEXT: add r11, r0, r3
+; CHECK-NEXT: ld r3, -176(r1) # 8-byte Folded Reload
+; CHECK-NEXT: add r3, r9, r3
+; CHECK-NEXT: sldi r3, r3, 3
+; CHECK-NEXT: add r12, r5, r3
+; CHECK-NEXT: add r30, r4, r3
+; CHECK-NEXT: add r29, r0, r3
+; CHECK-NEXT: ld r3, -168(r1) # 8-byte Folded Reload
+; CHECK-NEXT: add r3, r9, r3
; CHECK-NEXT: li r9, 0
+; CHECK-NEXT: sldi r3, r3, 3
+; CHECK-NEXT: add r5, r5, r3
+; CHECK-NEXT: add r4, r4, r3
+; CHECK-NEXT: add r3, r0, r3
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB7_7: # %for.body.epil
+; CHECK-NEXT: .LBB7_6: # %for.body.epil
; CHECK-NEXT: #
; CHECK-NEXT: lfdx f0, r3, r9
; CHECK-NEXT: lfdx f1, r4, r9
@@ -946,7 +934,7 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
; CHECK-NEXT: lfd f1, 0(r5)
; CHECK-NEXT: xsadddp f0, f1, f0
; CHECK-NEXT: stfd f0, 0(r5)
-; CHECK-NEXT: add r5, r5, r27
+; CHECK-NEXT: add r5, r5, r8
; CHECK-NEXT: lfdx f0, r29, r9
; CHECK-NEXT: lfdx f1, r30, r9
; CHECK-NEXT: xsmuldp f0, f0, f1
@@ -956,16 +944,17 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
; CHECK-NEXT: lfdx f0, r11, r9
; CHECK-NEXT: lfdx f1, r10, r9
; CHECK-NEXT: xsmuldp f0, f0, f1
-; CHECK-NEXT: lfdx f1, r28, r9
+; CHECK-NEXT: lfdx f1, r7, r9
; CHECK-NEXT: xsadddp f0, f1, f0
-; CHECK-NEXT: stfdx f0, r28, r9
-; CHECK-NEXT: add r9, r9, r27
-; CHECK-NEXT: bne cr0, .LBB7_7
-; CHECK-NEXT: .LBB7_8:
+; CHECK-NEXT: stfdx f0, r7, r9
+; CHECK-NEXT: add r9, r9, r8
+; CHECK-NEXT: bne cr0, .LBB7_6
+; CHECK-NEXT: .LBB7_7: # %for.cond.cleanup
; CHECK-NEXT: ld r2, -152(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r31, -8(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-NEXT: li r3, 0
; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
@@ -981,8 +970,6 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
; CHECK-NEXT: ld r16, -128(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r14, -144(r1) # 8-byte Folded Reload
-; CHECK-NEXT: .LBB7_9: # %for.cond.cleanup
-; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
%cmp49 = icmp sgt i64 %m, 0
diff --git a/llvm/test/CodeGen/PowerPC/csr-split.ll b/llvm/test/CodeGen/PowerPC/csr-split.ll
index e24c7e3eaab6b..dea07f3c57420 100644
--- a/llvm/test/CodeGen/PowerPC/csr-split.ll
+++ b/llvm/test/CodeGen/PowerPC/csr-split.ll
@@ -11,47 +11,35 @@
define dso_local signext i32 @test1(ptr %b) local_unnamed_addr {
; CHECK-PWR9-LABEL: test1:
; CHECK-PWR9: # %bb.0: # %entry
-; CHECK-PWR9-NEXT: addis r4, r2, a at toc@ha
-; CHECK-PWR9-NEXT: lwa r4, a at toc@l(r4)
-; CHECK-PWR9-NEXT: cmpld r4, r3
-; CHECK-PWR9-NEXT: # implicit-def: $r4
-; CHECK-PWR9-NEXT: beq cr0, .LBB0_2
-; CHECK-PWR9-NEXT: # %bb.1: # %if.end
-; CHECK-PWR9-NEXT: extsw r3, r4
-; CHECK-PWR9-NEXT: blr
-; CHECK-PWR9-NEXT: .LBB0_2: # %if.then
; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset r30, -16
; CHECK-PWR9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stdu r1, -48(r1)
-; CHECK-PWR9-NEXT: std r0, 64(r1)
; CHECK-PWR9-NEXT: mr r30, r3
+; CHECK-PWR9-NEXT: addis r3, r2, a at toc@ha
+; CHECK-PWR9-NEXT: std r0, 64(r1)
+; CHECK-PWR9-NEXT: lwa r3, a at toc@l(r3)
+; CHECK-PWR9-NEXT: cmpld r3, r30
+; CHECK-PWR9-NEXT: # implicit-def: $r3
+; CHECK-PWR9-NEXT: bne cr0, .LBB0_2
+; CHECK-PWR9-NEXT: # %bb.1: # %if.then
; CHECK-PWR9-NEXT: bl callVoid
; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: bl callNonVoid
; CHECK-PWR9-NEXT: nop
-; CHECK-PWR9-NEXT: mr r4, r3
+; CHECK-PWR9-NEXT: .LBB0_2: # %if.end
+; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: addi r1, r1, 48
; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0
-; CHECK-PWR9-NEXT: extsw r3, r4
; CHECK-PWR9-NEXT: blr
;
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, a at toc@ha
-; CHECK-NEXT: lwa r4, a at toc@l(r4)
-; CHECK-NEXT: cmpld r4, r3
-; CHECK-NEXT: # implicit-def: $r4
-; CHECK-NEXT: beq cr0, .LBB0_2
-; CHECK-NEXT: # %bb.1: # %if.end
-; CHECK-NEXT: extsw r3, r4
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB0_2: # %if.then
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -128(r1)
; CHECK-NEXT: std r0, 144(r1)
@@ -60,17 +48,23 @@ define dso_local signext i32 @test1(ptr %b) local_unnamed_addr {
; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; CHECK-NEXT: mr r30, r3
+; CHECK-NEXT: addis r3, r2, a at toc@ha
+; CHECK-NEXT: lwa r3, a at toc@l(r3)
+; CHECK-NEXT: cmpld r3, r30
+; CHECK-NEXT: # implicit-def: $r3
+; CHECK-NEXT: bne cr0, .LBB0_2
+; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: bl callVoid
; CHECK-NEXT: nop
; CHECK-NEXT: mr r3, r30
; CHECK-NEXT: bl callNonVoid
; CHECK-NEXT: nop
+; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: ld r30, 112(r1) # 8-byte Folded Reload
-; CHECK-NEXT: mr r4, r3
+; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: addi r1, r1, 128
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
-; CHECK-NEXT: extsw r3, r4
; CHECK-NEXT: blr
entry:
%0 = load i32, ptr @a, align 4, !tbaa !2
diff --git a/llvm/test/CodeGen/PowerPC/livevars-crash1.mir b/llvm/test/CodeGen/PowerPC/livevars-crash1.mir
index ec01a3c326cfa..c424bc11d4236 100644
--- a/llvm/test/CodeGen/PowerPC/livevars-crash1.mir
+++ b/llvm/test/CodeGen/PowerPC/livevars-crash1.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple powerpc64le-unknown-linux-gnu %s -o - 2>&1 \
# RUN: -run-pass=livevars,phi-node-elimination -verify-machineinstrs | \
# RUN: FileCheck %s
@@ -11,7 +12,7 @@
entry:
%.pre = load ptr, ptr %p, align 8
br label %loop
-
+
loop: ; preds = %loop, %if.then3, %entry
%0 = phi ptr [ %.pre, %entry ], [ %incdec.ptr4, %if.then3 ], [ %incdec.ptr, %loop ]
%1 = load i8, ptr %0, align 1
@@ -22,13 +23,13 @@
%tobool2 = icmp ne i8 %2, 0
%or.cond = and i1 %tobool, %tobool2
br i1 %or.cond, label %if.then3, label %loop
-
+
if.then3: ; preds = %loop
%incdec.ptr4 = getelementptr inbounds i8, ptr %0, i64 2
store ptr %incdec.ptr4, ptr %p, align 8
br label %loop
}
-
+
...
---
@@ -50,16 +51,55 @@ registers:
liveins:
- { reg: '$x3', virtual-reg: '%4' }
body: |
+ ; CHECK-LABEL: name: zext_free
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
+ ; CHECK-NEXT: [[LD:%[0-9]+]]:g8rc = LD 0, [[COPY]] :: (dereferenceable load (s64) from %ir.p)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[LD]]
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.loop:
+ ; CHECK-NEXT: successors: %bb.1(0x20000000), %bb.2(0x60000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LBZ:%[0-9]+]]:gprc = LBZ 0, [[COPY2]] :: (load (s8) from %ir.0)
+ ; CHECK-NEXT: [[CMPWI:%[0-9]+]]:crrc = CMPWI killed [[LBZ]], 0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:crbitrc = COPY killed [[CMPWI]].sub_eq
+ ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc = nuw ADDI8 [[COPY2]], 1
+ ; CHECK-NEXT: STD [[ADDI8_]], 0, [[COPY]] :: (store (s64) into %ir.p)
+ ; CHECK-NEXT: [[LBZ1:%[0-9]+]]:gprc = LBZ 1, [[COPY2]] :: (load (s8) from %ir.incdec.ptr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_]]
+ ; CHECK-NEXT: BCn killed [[COPY3]], %bb.1
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.loop:
+ ; CHECK-NEXT: successors: %bb.3(0x55555555), %bb.1(0x2aaaaaab)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[CMPWI1:%[0-9]+]]:crrc = CMPWI killed [[LBZ1]], 0
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:crbitrc = COPY killed [[CMPWI1]].sub_eq
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_]]
+ ; CHECK-NEXT: BC killed [[COPY4]], %bb.1
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.if.then3:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADDI8_1:%[0-9]+]]:g8rc = nuw ADDI8 killed [[COPY2]], 2
+ ; CHECK-NEXT: STD [[ADDI8_1]], 0, [[COPY]] :: (store (s64) into %ir.p)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_1]]
+ ; CHECK-NEXT: B %bb.1
bb.0.entry:
successors: %bb.1(0x80000000)
liveins: $x3
-
+
%4:g8rc_and_g8rc_nox0 = COPY killed $x3
%0:g8rc = LD 0, %4 :: (dereferenceable load (s64) from %ir.p)
-
+
bb.1.loop:
successors: %bb.1(0x20000000), %bb.2(0x60000000)
-
+
%1:g8rc_and_g8rc_nox0 = PHI %0, %bb.0, %2, %bb.1, %3, %bb.3, %2, %bb.2
%5:gprc = LBZ 0, %1 :: (load (s8) from %ir.0)
%6:crrc = CMPWI killed %5, 0
@@ -69,61 +109,30 @@ body: |
%8:gprc = LBZ 1, %1 :: (load (s8) from %ir.incdec.ptr)
BCn killed %7, %bb.1
B %bb.2
-
+
bb.2.loop:
successors: %bb.3(0x55555555), %bb.1(0x2aaaaaab)
-
+
%9:crrc = CMPWI killed %8, 0
%10:crbitrc = COPY killed %9.sub_eq
BC killed %10, %bb.1
B %bb.3
-
+
bb.3.if.then3:
successors: %bb.1(0x80000000)
-
+
%3:g8rc = nuw ADDI8 killed %1, 2
STD %3, 0, %4 :: (store (s64) into %ir.p)
B %bb.1
- ; CHECK-LABEL: name: zext_free
- ; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $x3
- ; CHECK: %4:g8rc_and_g8rc_nox0 = COPY killed $x3
- ; CHECK: %0:g8rc = LD 0, %4 :: (dereferenceable load (s64) from %ir.p)
- ; CHECK: %12:g8rc_and_g8rc_nox0 = COPY killed %0
- ; CHECK: bb.1.loop:
- ; CHECK: successors: %bb.1(0x20000000), %bb.2(0x60000000)
- ; CHECK: %1:g8rc_and_g8rc_nox0 = COPY killed %12
- ; CHECK: %5:gprc = LBZ 0, %1 :: (load (s8) from %ir.0)
- ; CHECK: %6:crrc = CMPWI killed %5, 0
; CHEXK: %7:crbitrc = COPY killed %6.sub_eq
- ; CHECK: %2:g8rc = nuw ADDI8 %1, 1
- ; CHECK: STD %2, 0, %4 :: (store (s64) into %ir.p)
- ; CHECK: %8:gprc = LBZ 1, %1 :: (load (s8) from %ir.incdec.ptr)
- ; CHECK: %12:g8rc_and_g8rc_nox0 = COPY %2
- ; CHECK: BCn killed %7, %bb.1
- ; CHECK: B %bb.2
-
- ; CHECK: bb.2.loop:
- ; CHECK: successors: %bb.3(0x55555555), %bb.1(0x2aaaaaab)
-
- ; CHECK: %9:crrc = CMPWI killed %8, 0
- ; CHECK: %10:crbitrc = COPY killed %9.sub_eq
- ; CHECK: %12:g8rc_and_g8rc_nox0 = COPY killed %2
- ; CHECK: BC killed %10, %bb.1
- ; CHECK: B %bb.3
-
- ; CHECK: bb.3.if.then3:
- ; CHECK: successors: %bb.1(0x80000000)
-
- ; CHECK: %3:g8rc = nuw ADDI8 killed %1, 2
- ; CHECK: STD %3, 0, %4 :: (store (s64) into %ir.p)
- ; CHECK: %12:g8rc_and_g8rc_nox0 = COPY killed %3
- ; CHECK: B %bb.1
+
+
+
+
...
diff --git a/llvm/test/CodeGen/PowerPC/livevars-crash2.mir b/llvm/test/CodeGen/PowerPC/livevars-crash2.mir
index c7a98f81b3e25..827fe8b77ce15 100644
--- a/llvm/test/CodeGen/PowerPC/livevars-crash2.mir
+++ b/llvm/test/CodeGen/PowerPC/livevars-crash2.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple powerpc64le-unknown-linux-gnu %s -o - 2>&1 \
# RUN: -run-pass=livevars,phi-node-elimination -verify-machineinstrs | \
# RUN: FileCheck %s
@@ -14,12 +15,12 @@
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
}
-
+
define signext i32 @select-i1-vs-i1(ptr nocapture dereferenceable(8) %p) #0 {
entry:
%.pre = load ptr, ptr %p, align 8
br label %loop
-
+
loop: ; preds = %loop, %if.then3, %entry
%0 = phi ptr [ %.pre, %entry ], [ %incdec.ptr4, %if.then3 ], [ %incdec.ptr, %loop ]
%1 = load i8, ptr %0, align 1
@@ -30,13 +31,13 @@
%tobool2 = icmp ne i8 %2, 0
%or.cond = and i1 %tobool, %tobool2
br i1 %or.cond, label %if.then3, label %loop
-
+
if.then3: ; preds = %loop
%incdec.ptr4 = getelementptr inbounds i8, ptr %0, i64 2
store ptr %incdec.ptr4, ptr %p, align 8
br label %loop
}
-
+
...
---
name: testfloatslt
@@ -62,10 +63,43 @@ liveins:
- { reg: '$f5', virtual-reg: '%4' }
- { reg: '$f6', virtual-reg: '%5' }
body: |
+ ; CHECK-LABEL: name: testfloatslt
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.2(0x20000000), %bb.1(0x60000000)
+ ; CHECK-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:f4rc = COPY killed $f6
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:f4rc = COPY killed $f5
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:f4rc = COPY killed $f4
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:f4rc = COPY killed $f3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:f4rc = COPY killed $f2
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:f4rc = COPY killed $f1
+ ; CHECK-NEXT: [[FCMPUS:%[0-9]+]]:crrc = FCMPUS killed [[COPY3]], killed [[COPY2]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:crbitrc = COPY killed [[FCMPUS]].sub_eq
+ ; CHECK-NEXT: BC killed [[COPY6]], %bb.2
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.entry:
+ ; CHECK-NEXT: successors: %bb.2(0x2aaaaaab), %bb.3(0x55555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[FCMPUS1:%[0-9]+]]:crrc = FCMPUS killed [[COPY5]], killed [[COPY4]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:crbitrc = COPY killed [[FCMPUS1]].sub_eq
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:f4rc = COPY [[COPY1]]
+ ; CHECK-NEXT: BC killed [[COPY7]], %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:f4rc = COPY [[COPY]]
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.entry:
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:f4rc = COPY [[COPY8]]
+ ; CHECK-NEXT: $f1 = COPY killed [[COPY9]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $f1
bb.0.entry:
successors: %bb.2(0x20000000), %bb.1(0x60000000)
liveins: $f1, $f2, $f3, $f4, $f5, $f6
-
+
%5:f4rc = COPY killed $f6
%4:f4rc = COPY killed $f5
%3:f4rc = COPY killed $f4
@@ -76,18 +110,18 @@ body: |
%7:crbitrc = COPY killed %6.sub_eq
BC killed %7, %bb.2
B %bb.1
-
+
bb.1.entry:
successors: %bb.2(0x2aaaaaab), %bb.3(0x55555555)
-
+
%8:crrc = FCMPUS killed %0, killed %1
%9:crbitrc = COPY killed %8.sub_eq
BC killed %9, %bb.3
-
+
bb.2.entry:
successors: %bb.3(0x80000000)
-
-
+
+
bb.3.entry:
%11:f4rc = PHI %5, %bb.2, %4, %bb.1
$f1 = COPY killed %11
@@ -144,16 +178,55 @@ callSites: []
constants: []
machineFunctionInfo: {}
body: |
+ ; CHECK-LABEL: name: select-i1-vs-i1
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
+ ; CHECK-NEXT: [[LD:%[0-9]+]]:g8rc = LD 0, [[COPY]] :: (dereferenceable load (s64) from %ir.p)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[LD]]
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.loop:
+ ; CHECK-NEXT: successors: %bb.1(0x20000000), %bb.2(0x60000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LBZ:%[0-9]+]]:gprc = LBZ 0, [[COPY2]] :: (load (s8) from %ir.0)
+ ; CHECK-NEXT: [[CMPWI:%[0-9]+]]:crrc = CMPWI killed [[LBZ]], 0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:crbitrc = COPY killed [[CMPWI]].sub_eq
+ ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc = nuw ADDI8 [[COPY2]], 1
+ ; CHECK-NEXT: STD [[ADDI8_]], 0, [[COPY]] :: (store (s64) into %ir.p)
+ ; CHECK-NEXT: [[LBZ1:%[0-9]+]]:gprc = LBZ 1, [[COPY2]] :: (load (s8) from %ir.incdec.ptr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_]]
+ ; CHECK-NEXT: BCn killed [[COPY3]], %bb.1
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.loop:
+ ; CHECK-NEXT: successors: %bb.3(0x55555555), %bb.1(0x2aaaaaab)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[CMPWI1:%[0-9]+]]:crrc = CMPWI killed [[LBZ1]], 0
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:crbitrc = COPY killed [[CMPWI1]].sub_eq
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_]]
+ ; CHECK-NEXT: BC killed [[COPY4]], %bb.1
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.if.then3:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADDI8_1:%[0-9]+]]:g8rc = nuw ADDI8 killed [[COPY2]], 2
+ ; CHECK-NEXT: STD [[ADDI8_1]], 0, [[COPY]] :: (store (s64) into %ir.p)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_1]]
+ ; CHECK-NEXT: B %bb.1
bb.0.entry:
successors: %bb.1(0x80000000)
liveins: $x3
-
+
%4:g8rc_and_g8rc_nox0 = COPY killed $x3
%0:g8rc = LD 0, %4 :: (dereferenceable load (s64) from %ir.p)
-
+
bb.1.loop:
successors: %bb.1(0x20000000), %bb.2(0x60000000)
-
+
%1:g8rc_and_g8rc_nox0 = PHI %0, %bb.0, %2, %bb.1, %3, %bb.3, %2, %bb.2
%5:gprc = LBZ 0, %1 :: (load (s8) from %ir.0)
%6:crrc = CMPWI killed %5, 0
@@ -163,60 +236,28 @@ body: |
%8:gprc = LBZ 1, %1 :: (load (s8) from %ir.incdec.ptr)
BCn killed %7, %bb.1
B %bb.2
-
+
bb.2.loop:
successors: %bb.3(0x55555555), %bb.1(0x2aaaaaab)
-
+
%9:crrc = CMPWI killed %8, 0
%10:crbitrc = COPY killed %9.sub_eq
BC killed %10, %bb.1
B %bb.3
-
+
bb.3.if.then3:
successors: %bb.1(0x80000000)
-
+
%3:g8rc = nuw ADDI8 killed %1, 2
STD %3, 0, %4 :: (store (s64) into %ir.p)
B %bb.1
- ; CHECK-LABEL: name: testfloatslt
- ; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $x3
-
- ; CHECK: %4:g8rc_and_g8rc_nox0 = COPY killed $x3
- ; CHECK: %0:g8rc = LD 0, %4 :: (dereferenceable load (s64) from %ir.p)
- ; CHECK: %12:g8rc_and_g8rc_nox0 = COPY killed %0
-
- ; CHECK: bb.1.loop:
- ; CHECK: successors: %bb.1(0x20000000), %bb.2(0x60000000)
-
- ; CHECK: %1:g8rc_and_g8rc_nox0 = COPY killed %12
- ; CHECK: %5:gprc = LBZ 0, %1 :: (load (s8) from %ir.0)
- ; CHECK: %6:crrc = CMPWI killed %5, 0
- ; CHECK: %7:crbitrc = COPY killed %6.sub_eq
- ; CHECK: %2:g8rc = nuw ADDI8 %1, 1
- ; CHECK: STD %2, 0, %4 :: (store (s64) into %ir.p)
- ; CHECK: %8:gprc = LBZ 1, %1 :: (load (s8) from %ir.incdec.ptr)
- ; CHECK: %12:g8rc_and_g8rc_nox0 = COPY %2
- ; CHECK: BCn killed %7, %bb.1
- ; CHECK: B %bb.2
-
- ; CHECK: bb.2.loop:
- ; CHECK: successors: %bb.3(0x55555555), %bb.1(0x2aaaaaab)
-
- ; CHECK: %9:crrc = CMPWI killed %8, 0
- ; CHECK: %10:crbitrc = COPY killed %9.sub_eq
- ; CHECK: %12:g8rc_and_g8rc_nox0 = COPY killed %2
- ; CHECK: BC killed %10, %bb.1
- ; CHECK: B %bb.3
-
- ; CHECK: bb.3.if.then3:
- ; CHECK: successors: %bb.1(0x80000000)
-
- ; CHECK: %3:g8rc = nuw ADDI8 killed %1, 2
- ; CHECK: STD %3, 0, %4 :: (store (s64) into %ir.p)
- ; CHECK: %12:g8rc_and_g8rc_nox0 = COPY killed %3
- ; CHECK: B %bb.1
+
+
+
+
+
+
+
...
diff --git a/llvm/test/CodeGen/PowerPC/phi-eliminate.mir b/llvm/test/CodeGen/PowerPC/phi-eliminate.mir
index 17060a88fb527..e74e5dd387db9 100644
--- a/llvm/test/CodeGen/PowerPC/phi-eliminate.mir
+++ b/llvm/test/CodeGen/PowerPC/phi-eliminate.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 %s -o - \
# RUN: -run-pass=livevars,phi-node-elimination | FileCheck %s
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 %s -o - \
@@ -132,91 +133,101 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: phi_eliminate
; CHECK: bb.0 (%ir-block.3):
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $x3, $x4
- ; CHECK: %6:g8rc = COPY killed $x4
- ; CHECK: %5:g8rc = COPY killed $x3
- ; CHECK: %9:gprc = COPY killed %6.sub_32
- ; CHECK: %8:gprc = COPY killed %5.sub_32
- ; CHECK: MTCTR8loop undef %10:g8rc, implicit-def dead $ctr8
- ; CHECK: %14:gprc_and_gprc_nor0 = LI 55
- ; CHECK: %15:gprc_and_gprc_nor0 = LI 48
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x3, $x4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x4
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc = COPY killed $x3
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY killed [[COPY1]].sub_32
+ ; CHECK-NEXT: MTCTR8loop undef %10:g8rc, implicit-def dead $ctr8
+ ; CHECK-NEXT: [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 55
+ ; CHECK-NEXT: [[LI1:%[0-9]+]]:gprc_and_gprc_nor0 = LI 48
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1 (%ir-block.4):
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DIVW:%[0-9]+]]:gprc = DIVW [[COPY3]], [[COPY2]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY3]]
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:g8rc_and_g8rc_nox0 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprc = COPY [[DIVW]]
+ ; CHECK-NEXT: BDZ8 %bb.5, implicit-def $ctr8, implicit $ctr8
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2 (%ir-block.4):
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[MULLW:%[0-9]+]]:gprc = nsw MULLW [[DIVW]], [[COPY2]]
+ ; CHECK-NEXT: [[SUBF:%[0-9]+]]:gprc = SUBF killed [[MULLW]], killed [[COPY3]]
+ ; CHECK-NEXT: [[CMPLWI:%[0-9]+]]:crrc = CMPLWI [[SUBF]], 10
+ ; CHECK-NEXT: [[ISEL:%[0-9]+]]:gprc = ISEL [[LI1]], [[LI]], killed [[CMPLWI]].sub_lt
+ ; CHECK-NEXT: [[ADD4_:%[0-9]+]]:gprc = ADD4 killed [[ISEL]], killed [[SUBF]]
+ ; CHECK-NEXT: [[STBU:%[0-9]+]]:g8rc_and_g8rc_nox0 = STBU killed [[ADD4_]], -1, undef %0:g8rc_and_g8rc_nox0 :: (store (s8) into %ir.7)
+ ; CHECK-NEXT: [[DIVW1:%[0-9]+]]:gprc = DIVW [[DIVW]], [[COPY2]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gprc = COPY [[DIVW1]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gprc = COPY [[DIVW]]
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[STBU]]
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gprc = COPY [[DIVW]]
+ ; CHECK-NEXT: BDZ8 %bb.4, implicit-def $ctr8, implicit $ctr8
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3 (%ir-block.4):
+ ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[COPY8]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gprc = COPY [[COPY6]]
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gprc = COPY [[COPY7]]
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:gprc = COPY [[COPY6]]
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed [[COPY10]]
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:gprc = COPY [[COPY13]]
+ ; CHECK-NEXT: [[DIVW2:%[0-9]+]]:gprc = DIVW [[COPY15]], [[COPY2]]
+ ; CHECK-NEXT: [[MULLW1:%[0-9]+]]:gprc = nsw MULLW killed [[COPY11]], [[COPY2]]
+ ; CHECK-NEXT: [[SUBF1:%[0-9]+]]:gprc = SUBF killed [[MULLW1]], killed [[COPY12]]
+ ; CHECK-NEXT: [[CMPLWI1:%[0-9]+]]:crrc = CMPLWI [[SUBF1]], 10
+ ; CHECK-NEXT: [[ISEL1:%[0-9]+]]:gprc = ISEL [[LI1]], [[LI]], killed [[CMPLWI1]].sub_lt
+ ; CHECK-NEXT: [[ADD4_1:%[0-9]+]]:gprc = ADD4 killed [[ISEL1]], killed [[SUBF1]]
+ ; CHECK-NEXT: [[STBU1:%[0-9]+]]:g8rc_and_g8rc_nox0 = STBU killed [[ADD4_1]], -1, killed [[COPY14]] :: (store unknown-size into %ir.7, align 1)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gprc = COPY [[DIVW2]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gprc = COPY [[COPY13]]
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[STBU1]]
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gprc = COPY [[COPY15]]
+ ; CHECK-NEXT: BDNZ8 %bb.3, implicit-def $ctr8, implicit $ctr8
+ ; CHECK-NEXT: B %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY16:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[COPY8]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:gprc = COPY [[COPY6]]
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:gprc = COPY [[COPY9]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:g8rc = COPY killed [[COPY16]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY18]]
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[COPY19]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY17]]
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5:
+ ; CHECK-NEXT: successors: %bb.6(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY20:%[0-9]+]]:gprc = COPY [[COPY5]]
+ ; CHECK-NEXT: [[COPY21:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[DEF]]
+ ; CHECK-NEXT: [[COPY22:%[0-9]+]]:gprc = COPY [[COPY4]]
+ ; CHECK-NEXT: [[MULLW2:%[0-9]+]]:gprc = nsw MULLW killed [[COPY20]], killed [[COPY2]]
+ ; CHECK-NEXT: [[SUBF2:%[0-9]+]]:gprc = SUBF killed [[MULLW2]], killed [[COPY22]]
+ ; CHECK-NEXT: [[CMPLWI2:%[0-9]+]]:crrc = CMPLWI [[SUBF2]], 10
+ ; CHECK-NEXT: [[ISEL2:%[0-9]+]]:gprc = ISEL killed [[LI1]], killed [[LI]], killed [[CMPLWI2]].sub_lt
+ ; CHECK-NEXT: [[ADD4_2:%[0-9]+]]:gprc = ADD4 killed [[ISEL2]], killed [[SUBF2]]
+ ; CHECK-NEXT: dead [[STBU2:%[0-9]+]]:g8rc_and_g8rc_nox0 = STBU killed [[ADD4_2]], -1, killed [[COPY21]] :: (store unknown-size into %ir.7, align 1)
+ ; CHECK-NEXT: B %bb.6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6 (%ir-block.16):
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm
- ; CHECK: bb.1 (%ir-block.4):
- ; CHECK: successors: %bb.2(0x40000000), %bb.7(0x40000000)
- ; CHECK: %19:gprc = DIVW %8, %9
- ; CHECK: BDNZ8 %bb.2, implicit-def $ctr8, implicit $ctr8
- ; CHECK: bb.7:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: %61:gprc = COPY killed %8
- ; CHECK: %62:g8rc_and_g8rc_nox0 = IMPLICIT_DEF
- ; CHECK: %63:gprc = COPY killed %19
- ; CHECK: B %bb.5
- ; CHECK: bb.2 (%ir-block.4):
- ; CHECK: successors: %bb.3(0x40000000), %bb.4(0x40000000)
- ; CHECK: %20:gprc = nsw MULLW %19, %9
- ; CHECK: %21:gprc = SUBF killed %20, killed %8
- ; CHECK: %22:crrc = CMPLWI %21, 10
- ; CHECK: %23:gprc = ISEL %15, %14, killed %22.sub_lt
- ; CHECK: %24:gprc = ADD4 killed %23, killed %21
- ; CHECK: %25:g8rc_and_g8rc_nox0 = STBU killed %24, -1, undef %0:g8rc_and_g8rc_nox0 :: (store (s8) into %ir.7)
- ; CHECK: %26:gprc = DIVW %19, %9
- ; CHECK: %57:gprc = COPY killed %26
- ; CHECK: %58:gprc = COPY %19
- ; CHECK: %59:g8rc_and_g8rc_nox0 = COPY killed %25
- ; CHECK: %60:gprc = COPY killed %19
- ; CHECK: BDZ8 %bb.4, implicit-def $ctr8, implicit $ctr8
- ; CHECK: B %bb.3
- ; CHECK: bb.3 (%ir-block.4):
- ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
- ; CHECK: %38:g8rc_and_g8rc_nox0 = COPY killed %59
- ; CHECK: %37:gprc = COPY %57
- ; CHECK: %36:gprc = COPY killed %58
- ; CHECK: %35:gprc = COPY killed %57
- ; CHECK: %27:g8rc_and_g8rc_nox0 = COPY killed %38
- ; CHECK: %56:gprc = COPY %35
- ; CHECK: %28:gprc = DIVW %56, %9
- ; CHECK: %29:gprc = nsw MULLW killed %37, %9
- ; CHECK: %30:gprc = SUBF killed %29, killed %36
- ; CHECK: %31:crrc = CMPLWI %30, 10
- ; CHECK: %32:gprc = ISEL %15, %14, killed %31.sub_lt
- ; CHECK: %33:gprc = ADD4 killed %32, killed %30
- ; CHECK: %34:g8rc_and_g8rc_nox0 = STBU killed %33, -1, killed %27 :: (store unknown-size into %ir.7, align 1)
- ; CHECK: %57:gprc = COPY killed %28
- ; CHECK: %58:gprc = COPY killed %35
- ; CHECK: %59:g8rc_and_g8rc_nox0 = COPY killed %34
- ; CHECK: %60:gprc = COPY killed %56
- ; CHECK: BDNZ8 %bb.3, implicit-def $ctr8, implicit $ctr8
- ; CHECK: B %bb.4
- ; CHECK: bb.4:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: %44:g8rc_and_g8rc_nox0 = COPY killed %59
- ; CHECK: %43:gprc = COPY killed %57
- ; CHECK: %41:gprc = COPY killed %60
- ; CHECK: %39:g8rc = COPY killed %44
- ; CHECK: %61:gprc = COPY killed %41
- ; CHECK: %62:g8rc_and_g8rc_nox0 = COPY killed %39
- ; CHECK: %63:gprc = COPY killed %43
- ; CHECK: bb.5:
- ; CHECK: successors: %bb.6(0x80000000)
- ; CHECK: %55:gprc = COPY killed %63
- ; CHECK: %54:g8rc_and_g8rc_nox0 = COPY killed %62
- ; CHECK: %53:gprc = COPY killed %61
- ; CHECK: %45:gprc = nsw MULLW killed %55, killed %9
- ; CHECK: %46:gprc = SUBF killed %45, killed %53
- ; CHECK: %47:crrc = CMPLWI %46, 10
- ; CHECK: %48:gprc = ISEL killed %15, killed %14, killed %47.sub_lt
- ; CHECK: %49:gprc = ADD4 killed %48, killed %46
- ; CHECK: dead %50:g8rc_and_g8rc_nox0 = STBU killed %49, -1, killed %54 :: (store unknown-size into %ir.7, align 1)
- ; CHECK: B %bb.6
- ; CHECK: bb.6 (%ir-block.16):
- ; CHECK: BLR8 implicit $lr8, implicit $rm
bb.0 (%ir-block.3):
successors: %bb.1(0x80000000)
diff --git a/llvm/test/CodeGen/PowerPC/prefer-dqform.ll b/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
index 912a74ba8df8f..0c6a36285a933 100644
--- a/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
+++ b/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
@@ -16,49 +16,49 @@ define void @test(ptr dereferenceable(4) %.ial, ptr noalias dereferenceable(4) %
; CHECK-P9-NEXT: andi. r3, r6, 15
; CHECK-P9-NEXT: li r3, 2
; CHECK-P9-NEXT: li r10, 1
-; CHECK-P9-NEXT: lwz r4, 0(r4)
-; CHECK-P9-NEXT: lwz r5, 0(r5)
-; CHECK-P9-NEXT: iseleq r3, r10, r3
-; CHECK-P9-NEXT: subfic r10, r3, 1
-; CHECK-P9-NEXT: add r4, r10, r4
-; CHECK-P9-NEXT: srawi r4, r4, 4
+; CHECK-P9-NEXT: iseleq r10, r10, r3
+; CHECK-P9-NEXT: lwz r3, 0(r4)
+; CHECK-P9-NEXT: subfic r4, r10, 1
+; CHECK-P9-NEXT: add r3, r4, r3
+; CHECK-P9-NEXT: srawi r3, r3, 4
+; CHECK-P9-NEXT: addze r3, r3
+; CHECK-P9-NEXT: slwi r3, r3, 4
+; CHECK-P9-NEXT: sub r3, r3, r4
+; CHECK-P9-NEXT: lwz r4, 0(r5)
+; CHECK-P9-NEXT: cmpw r10, r3
+; CHECK-P9-NEXT: srawi r4, r4, 1
; CHECK-P9-NEXT: addze r4, r4
-; CHECK-P9-NEXT: srawi r5, r5, 1
-; CHECK-P9-NEXT: slwi r4, r4, 4
-; CHECK-P9-NEXT: addze r5, r5
-; CHECK-P9-NEXT: sub r4, r4, r10
-; CHECK-P9-NEXT: cmpw r3, r4
; CHECK-P9-NEXT: bgtlr cr0
; CHECK-P9-NEXT: # %bb.1: # %_loop_2_do_.lr.ph
-; CHECK-P9-NEXT: extswsli r5, r5, 3
-; CHECK-P9-NEXT: add r5, r8, r5
-; CHECK-P9-NEXT: addi r8, r5, -8
-; CHECK-P9-NEXT: lwz r5, 0(r7)
-; CHECK-P9-NEXT: extsw r7, r4
-; CHECK-P9-NEXT: rldic r4, r3, 3, 29
-; CHECK-P9-NEXT: sub r3, r7, r3
-; CHECK-P9-NEXT: addi r10, r4, 8
-; CHECK-P9-NEXT: lxvdsx vs0, 0, r8
-; CHECK-P9-NEXT: rldicl r3, r3, 60, 4
-; CHECK-P9-NEXT: extswsli r5, r5, 3
-; CHECK-P9-NEXT: addi r3, r3, 1
-; CHECK-P9-NEXT: sub r4, r10, r5
-; CHECK-P9-NEXT: add r5, r9, r10
-; CHECK-P9-NEXT: mtctr r3
-; CHECK-P9-NEXT: add r4, r6, r4
+; CHECK-P9-NEXT: extswsli r4, r4, 3
+; CHECK-P9-NEXT: add r4, r8, r4
+; CHECK-P9-NEXT: addi r5, r4, -8
+; CHECK-P9-NEXT: lwz r4, 0(r7)
+; CHECK-P9-NEXT: extsw r7, r3
+; CHECK-P9-NEXT: rldic r3, r10, 3, 29
+; CHECK-P9-NEXT: addi r8, r3, 8
+; CHECK-P9-NEXT: extswsli r4, r4, 3
+; CHECK-P9-NEXT: lxvdsx vs0, 0, r5
+; CHECK-P9-NEXT: sub r3, r8, r4
+; CHECK-P9-NEXT: add r4, r9, r8
+; CHECK-P9-NEXT: add r3, r6, r3
+; CHECK-P9-NEXT: sub r6, r7, r10
+; CHECK-P9-NEXT: rldicl r6, r6, 60, 4
+; CHECK-P9-NEXT: addi r6, r6, 1
+; CHECK-P9-NEXT: mtctr r6
; CHECK-P9-NEXT: .p2align 4
; CHECK-P9-NEXT: .LBB0_2: # %_loop_2_do_
; CHECK-P9-NEXT: #
-; CHECK-P9-NEXT: lxv vs1, -16(r5)
-; CHECK-P9-NEXT: lxv vs2, 0(r5)
-; CHECK-P9-NEXT: lxv vs3, -16(r4)
-; CHECK-P9-NEXT: lxv vs4, 0(r4)
-; CHECK-P9-NEXT: addi r4, r4, 128
+; CHECK-P9-NEXT: lxv vs1, -16(r4)
+; CHECK-P9-NEXT: lxv vs2, 0(r4)
+; CHECK-P9-NEXT: lxv vs3, -16(r3)
+; CHECK-P9-NEXT: lxv vs4, 0(r3)
+; CHECK-P9-NEXT: addi r3, r3, 128
; CHECK-P9-NEXT: xvmaddadp vs1, vs3, vs1
-; CHECK-P9-NEXT: stxv vs1, -16(r5)
+; CHECK-P9-NEXT: stxv vs1, -16(r4)
; CHECK-P9-NEXT: xvmaddadp vs2, vs4, vs0
-; CHECK-P9-NEXT: stxv vs2, 0(r5)
-; CHECK-P9-NEXT: addi r5, r5, 128
+; CHECK-P9-NEXT: stxv vs2, 0(r4)
+; CHECK-P9-NEXT: addi r4, r4, 128
; CHECK-P9-NEXT: bdnz .LBB0_2
; CHECK-P9-NEXT: # %bb.3: # %_return_bb
; CHECK-P9-NEXT: blr
@@ -68,49 +68,49 @@ define void @test(ptr dereferenceable(4) %.ial, ptr noalias dereferenceable(4) %
; CHECK-P10-NEXT: andi. r3, r6, 15
; CHECK-P10-NEXT: li r3, 2
; CHECK-P10-NEXT: li r10, 1
-; CHECK-P10-NEXT: lwz r4, 0(r4)
-; CHECK-P10-NEXT: lwz r5, 0(r5)
-; CHECK-P10-NEXT: iseleq r3, r10, r3
-; CHECK-P10-NEXT: subfic r10, r3, 1
-; CHECK-P10-NEXT: add r4, r10, r4
-; CHECK-P10-NEXT: srawi r4, r4, 4
+; CHECK-P10-NEXT: iseleq r10, r10, r3
+; CHECK-P10-NEXT: lwz r3, 0(r4)
+; CHECK-P10-NEXT: subfic r4, r10, 1
+; CHECK-P10-NEXT: add r3, r4, r3
+; CHECK-P10-NEXT: srawi r3, r3, 4
+; CHECK-P10-NEXT: addze r3, r3
+; CHECK-P10-NEXT: slwi r3, r3, 4
+; CHECK-P10-NEXT: sub r3, r3, r4
+; CHECK-P10-NEXT: lwz r4, 0(r5)
+; CHECK-P10-NEXT: cmpw r10, r3
+; CHECK-P10-NEXT: srawi r4, r4, 1
; CHECK-P10-NEXT: addze r4, r4
-; CHECK-P10-NEXT: srawi r5, r5, 1
-; CHECK-P10-NEXT: slwi r4, r4, 4
-; CHECK-P10-NEXT: addze r5, r5
-; CHECK-P10-NEXT: sub r4, r4, r10
-; CHECK-P10-NEXT: cmpw r3, r4
; CHECK-P10-NEXT: bgtlr cr0
; CHECK-P10-NEXT: # %bb.1: # %_loop_2_do_.lr.ph
-; CHECK-P10-NEXT: extswsli r5, r5, 3
-; CHECK-P10-NEXT: add r5, r8, r5
-; CHECK-P10-NEXT: addi r8, r5, -8
-; CHECK-P10-NEXT: lwz r5, 0(r7)
-; CHECK-P10-NEXT: extsw r7, r4
-; CHECK-P10-NEXT: rldic r4, r3, 3, 29
-; CHECK-P10-NEXT: addi r10, r4, 8
-; CHECK-P10-NEXT: sub r3, r7, r3
-; CHECK-P10-NEXT: lxvdsx vs0, 0, r8
-; CHECK-P10-NEXT: rldicl r3, r3, 60, 4
-; CHECK-P10-NEXT: extswsli r5, r5, 3
-; CHECK-P10-NEXT: addi r3, r3, 1
-; CHECK-P10-NEXT: sub r4, r10, r5
-; CHECK-P10-NEXT: add r5, r9, r10
-; CHECK-P10-NEXT: mtctr r3
-; CHECK-P10-NEXT: add r4, r6, r4
+; CHECK-P10-NEXT: extswsli r4, r4, 3
+; CHECK-P10-NEXT: add r4, r8, r4
+; CHECK-P10-NEXT: addi r5, r4, -8
+; CHECK-P10-NEXT: lwz r4, 0(r7)
+; CHECK-P10-NEXT: extsw r7, r3
+; CHECK-P10-NEXT: rldic r3, r10, 3, 29
+; CHECK-P10-NEXT: addi r8, r3, 8
+; CHECK-P10-NEXT: lxvdsx vs0, 0, r5
+; CHECK-P10-NEXT: extswsli r4, r4, 3
+; CHECK-P10-NEXT: sub r3, r8, r4
+; CHECK-P10-NEXT: add r4, r9, r8
+; CHECK-P10-NEXT: add r3, r6, r3
+; CHECK-P10-NEXT: sub r6, r7, r10
+; CHECK-P10-NEXT: rldicl r6, r6, 60, 4
+; CHECK-P10-NEXT: addi r6, r6, 1
+; CHECK-P10-NEXT: mtctr r6
; CHECK-P10-NEXT: .p2align 4
; CHECK-P10-NEXT: .LBB0_2: # %_loop_2_do_
; CHECK-P10-NEXT: #
-; CHECK-P10-NEXT: lxv vs1, -16(r5)
-; CHECK-P10-NEXT: lxv vs2, 0(r5)
-; CHECK-P10-NEXT: lxv vs3, -16(r4)
+; CHECK-P10-NEXT: lxv vs1, -16(r4)
+; CHECK-P10-NEXT: lxv vs2, 0(r4)
+; CHECK-P10-NEXT: lxv vs3, -16(r3)
; CHECK-P10-NEXT: xvmaddadp vs1, vs3, vs1
-; CHECK-P10-NEXT: lxv vs4, 0(r4)
+; CHECK-P10-NEXT: lxv vs4, 0(r3)
; CHECK-P10-NEXT: xvmaddadp vs2, vs4, vs0
+; CHECK-P10-NEXT: addi r3, r3, 128
+; CHECK-P10-NEXT: stxv vs1, -16(r4)
+; CHECK-P10-NEXT: stxv vs2, 0(r4)
; CHECK-P10-NEXT: addi r4, r4, 128
-; CHECK-P10-NEXT: stxv vs1, -16(r5)
-; CHECK-P10-NEXT: stxv vs2, 0(r5)
-; CHECK-P10-NEXT: addi r5, r5, 128
; CHECK-P10-NEXT: bdnz .LBB0_2
; CHECK-P10-NEXT: # %bb.3: # %_return_bb
; CHECK-P10-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/shrink-wrap.ll b/llvm/test/CodeGen/PowerPC/shrink-wrap.ll
index 12d0b056ca886..48fad4464eb7f 100644
--- a/llvm/test/CodeGen/PowerPC/shrink-wrap.ll
+++ b/llvm/test/CodeGen/PowerPC/shrink-wrap.ll
@@ -72,6 +72,8 @@ define signext i32 @shrinkwrapme(i32 signext %a, i32 signext %lim) {
; POWERPC32-AIX-NEXT: # %bb.1: # %for.body.preheader
; POWERPC32-AIX-NEXT: stw 14, -72(1) # 4-byte Folded Spill
; POWERPC32-AIX-NEXT: stw 15, -68(1) # 4-byte Folded Spill
+; POWERPC32-AIX-NEXT: mr 5, 3
+; POWERPC32-AIX-NEXT: li 3, 0
; POWERPC32-AIX-NEXT: stw 16, -64(1) # 4-byte Folded Spill
; POWERPC32-AIX-NEXT: stw 17, -60(1) # 4-byte Folded Spill
; POWERPC32-AIX-NEXT: stw 18, -56(1) # 4-byte Folded Spill
@@ -89,12 +91,11 @@ define signext i32 @shrinkwrapme(i32 signext %a, i32 signext %lim) {
; POWERPC32-AIX-NEXT: stw 30, -8(1) # 4-byte Folded Spill
; POWERPC32-AIX-NEXT: stw 31, -4(1) # 4-byte Folded Spill
; POWERPC32-AIX-NEXT: mtctr 4
-; POWERPC32-AIX-NEXT: li 4, 0
; POWERPC32-AIX-NEXT: .align 4
; POWERPC32-AIX-NEXT: L..BB0_2: # %for.body
; POWERPC32-AIX-NEXT: #
; POWERPC32-AIX-NEXT: #APP
-; POWERPC32-AIX-NEXT: add 4, 3, 4
+; POWERPC32-AIX-NEXT: add 3, 5, 3
; POWERPC32-AIX-NEXT: #NO_APP
; POWERPC32-AIX-NEXT: bdnz L..BB0_2
; POWERPC32-AIX-NEXT: # %bb.3:
@@ -102,7 +103,6 @@ define signext i32 @shrinkwrapme(i32 signext %a, i32 signext %lim) {
; POWERPC32-AIX-NEXT: lwz 30, -8(1) # 4-byte Folded Reload
; POWERPC32-AIX-NEXT: lwz 29, -12(1) # 4-byte Folded Reload
; POWERPC32-AIX-NEXT: lwz 28, -16(1) # 4-byte Folded Reload
-; POWERPC32-AIX-NEXT: mr 3, 4
; POWERPC32-AIX-NEXT: lwz 27, -20(1) # 4-byte Folded Reload
; POWERPC32-AIX-NEXT: lwz 26, -24(1) # 4-byte Folded Reload
; POWERPC32-AIX-NEXT: lwz 25, -28(1) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
index f573fdab1b153..17dd1b882f0ad 100644
--- a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
+++ b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
@@ -35,67 +35,67 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; PPC32: # %bb.0: # %start
; PPC32-NEXT: stwu 1, -64(1)
; PPC32-NEXT: stw 26, 40(1) # 4-byte Folded Spill
-; PPC32-NEXT: mfcr 12
+; PPC32-NEXT: mullw 26, 3, 10
; PPC32-NEXT: stw 27, 44(1) # 4-byte Folded Spill
-; PPC32-NEXT: mullw 27, 9, 4
-; PPC32-NEXT: stw 21, 20(1) # 4-byte Folded Spill
; PPC32-NEXT: mr 11, 7
-; PPC32-NEXT: stw 22, 24(1) # 4-byte Folded Spill
-; PPC32-NEXT: li 7, 0
-; PPC32-NEXT: mullw 26, 3, 10
-; PPC32-NEXT: stw 23, 28(1) # 4-byte Folded Spill
-; PPC32-NEXT: add 27, 26, 27
+; PPC32-NEXT: mr 0, 5
; PPC32-NEXT: stw 24, 32(1) # 4-byte Folded Spill
-; PPC32-NEXT: cmpwi 7, 11, 0
+; PPC32-NEXT: mullw 27, 9, 4
+; PPC32-NEXT: add 27, 26, 27
; PPC32-NEXT: stw 25, 36(1) # 4-byte Folded Spill
-; PPC32-NEXT: mullw 24, 11, 6
-; PPC32-NEXT: stw 28, 48(1) # 4-byte Folded Spill
-; PPC32-NEXT: stw 29, 52(1) # 4-byte Folded Spill
-; PPC32-NEXT: stw 30, 56(1) # 4-byte Folded Spill
-; PPC32-NEXT: mulhwu 0, 8, 6
-; PPC32-NEXT: stw 12, 16(1)
-; PPC32-NEXT: mr 12, 5
+; PPC32-NEXT: mfcr 12
+; PPC32-NEXT: li 7, 0
; PPC32-NEXT: mulhwu 5, 4, 10
; PPC32-NEXT: addc 5, 5, 27
+; PPC32-NEXT: stw 21, 20(1) # 4-byte Folded Spill
; PPC32-NEXT: addze 27, 7
+; PPC32-NEXT: stw 22, 24(1) # 4-byte Folded Spill
+; PPC32-NEXT: cmpwi 7, 11, 0
+; PPC32-NEXT: mullw 25, 0, 8
+; PPC32-NEXT: stw 23, 28(1) # 4-byte Folded Spill
; PPC32-NEXT: cmpwi 2, 27, 0
-; PPC32-NEXT: mullw 25, 12, 8
+; PPC32-NEXT: stw 28, 48(1) # 4-byte Folded Spill
+; PPC32-NEXT: mullw 24, 11, 6
+; PPC32-NEXT: stw 29, 52(1) # 4-byte Folded Spill
; PPC32-NEXT: add 26, 24, 25
-; PPC32-NEXT: addc 0, 0, 26
+; PPC32-NEXT: stw 30, 56(1) # 4-byte Folded Spill
+; PPC32-NEXT: stw 12, 16(1)
+; PPC32-NEXT: mulhwu 12, 8, 6
+; PPC32-NEXT: addc 12, 12, 26
; PPC32-NEXT: addze 26, 7
; PPC32-NEXT: mullw 23, 8, 6
; PPC32-NEXT: mullw 22, 4, 10
; PPC32-NEXT: addc 24, 22, 23
-; PPC32-NEXT: adde 22, 5, 0
+; PPC32-NEXT: adde 22, 5, 12
; PPC32-NEXT: mulhwu 29, 6, 10
-; PPC32-NEXT: mullw 21, 12, 10
+; PPC32-NEXT: mullw 21, 0, 10
; PPC32-NEXT: addc 5, 21, 29
-; PPC32-NEXT: mulhwu 30, 12, 10
-; PPC32-NEXT: addze 0, 30
+; PPC32-NEXT: mulhwu 30, 0, 10
+; PPC32-NEXT: addze 12, 30
; PPC32-NEXT: mullw 23, 6, 9
; PPC32-NEXT: addc 5, 23, 5
; PPC32-NEXT: mulhwu 28, 6, 9
; PPC32-NEXT: addze 29, 28
-; PPC32-NEXT: addc 0, 0, 29
+; PPC32-NEXT: addc 12, 12, 29
; PPC32-NEXT: addze 29, 7
-; PPC32-NEXT: mullw 30, 12, 9
-; PPC32-NEXT: addc 0, 30, 0
-; PPC32-NEXT: mulhwu 25, 12, 9
+; PPC32-NEXT: mullw 30, 0, 9
+; PPC32-NEXT: addc 12, 30, 12
+; PPC32-NEXT: mulhwu 25, 0, 9
; PPC32-NEXT: adde 30, 25, 29
-; PPC32-NEXT: addc 0, 0, 24
+; PPC32-NEXT: addc 12, 12, 24
; PPC32-NEXT: adde 30, 30, 22
; PPC32-NEXT: addze. 29, 7
; PPC32-NEXT: mcrf 1, 0
; PPC32-NEXT: mulhwu. 29, 11, 6
; PPC32-NEXT: mcrf 6, 0
-; PPC32-NEXT: mulhwu. 29, 12, 8
+; PPC32-NEXT: mulhwu. 29, 0, 8
; PPC32-NEXT: mcrf 5, 0
-; PPC32-NEXT: cmpwi 12, 0
+; PPC32-NEXT: cmpwi 0, 0
; PPC32-NEXT: crnor 20, 2, 30
; PPC32-NEXT: cmpwi 3, 0
; PPC32-NEXT: cmpwi 7, 9, 0
; PPC32-NEXT: crnor 24, 30, 2
-; PPC32-NEXT: mulhwu. 12, 3, 10
+; PPC32-NEXT: mulhwu. 0, 3, 10
; PPC32-NEXT: crorc 20, 20, 26
; PPC32-NEXT: mcrf 7, 0
; PPC32-NEXT: crorc 20, 20, 22
@@ -118,9 +118,9 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; PPC32-NEXT: # %bb.1: # %start
; PPC32-NEXT: li 7, 1
; PPC32-NEXT: .LBB0_2: # %start
+; PPC32-NEXT: mr 4, 12
; PPC32-NEXT: lwz 12, 16(1)
; PPC32-NEXT: mr 3, 30
-; PPC32-NEXT: mr 4, 0
; PPC32-NEXT: lwz 30, 56(1) # 4-byte Folded Reload
; PPC32-NEXT: mtcrf 32, 12 # cr2
; PPC32-NEXT: lwz 29, 52(1) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
index 2d59e2bc00453..4dba335dee011 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
@@ -1145,38 +1145,38 @@ define i1 @iszero_q_fpclass(fp128 %x) {
define i1 @isinf_q_fpclass(fp128 %x) {
; RV32IFD-LABEL: isinf_q_fpclass:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: lui a6, 1048560
+; RV32IFD-NEXT: lui a5, 1048560
; RV32IFD-NEXT: lw a1, 12(a0)
; RV32IFD-NEXT: lw a2, 0(a0)
-; RV32IFD-NEXT: lw a3, 4(a0)
-; RV32IFD-NEXT: lw a4, 8(a0)
-; RV32IFD-NEXT: slli a5, a1, 1
+; RV32IFD-NEXT: lw a4, 4(a0)
+; RV32IFD-NEXT: lw a3, 8(a0)
+; RV32IFD-NEXT: slli a6, a1, 1
; RV32IFD-NEXT: sltiu a0, a2, 0
-; RV32IFD-NEXT: seqz a2, a3
-; RV32IFD-NEXT: sltu a7, a3, a3
+; RV32IFD-NEXT: seqz a2, a4
+; RV32IFD-NEXT: sltu a7, a4, a4
; RV32IFD-NEXT: and a2, a2, a0
; RV32IFD-NEXT: or a7, a7, a2
-; RV32IFD-NEXT: seqz t0, a4
-; RV32IFD-NEXT: srli a5, a5, 1
-; RV32IFD-NEXT: sub a3, a3, a0
-; RV32IFD-NEXT: xor a2, a1, a5
+; RV32IFD-NEXT: seqz t0, a3
+; RV32IFD-NEXT: srli a6, a6, 1
+; RV32IFD-NEXT: sub a4, a4, a0
+; RV32IFD-NEXT: xor a2, a1, a6
; RV32IFD-NEXT: and t0, t0, a7
-; RV32IFD-NEXT: sub a1, a4, a7
-; RV32IFD-NEXT: sltu a4, a4, a4
-; RV32IFD-NEXT: or a4, a4, t0
-; RV32IFD-NEXT: add a6, a5, a6
-; RV32IFD-NEXT: beqz a3, .LBB28_2
+; RV32IFD-NEXT: sub a1, a3, a7
+; RV32IFD-NEXT: sltu a3, a3, a3
+; RV32IFD-NEXT: or a3, a3, t0
+; RV32IFD-NEXT: add a5, a6, a5
+; RV32IFD-NEXT: beqz a4, .LBB28_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: sltiu a0, a3, 0
+; RV32IFD-NEXT: sltiu a0, a4, 0
; RV32IFD-NEXT: .LBB28_2:
-; RV32IFD-NEXT: mv a5, a2
-; RV32IFD-NEXT: sub a2, a6, a4
+; RV32IFD-NEXT: mv a4, a2
+; RV32IFD-NEXT: sub a2, a5, a3
; RV32IFD-NEXT: lui a3, 524256
; RV32IFD-NEXT: beqz a1, .LBB28_4
; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: sltiu a0, a1, 0
; RV32IFD-NEXT: .LBB28_4:
-; RV32IFD-NEXT: snez a1, a5
+; RV32IFD-NEXT: snez a1, a4
; RV32IFD-NEXT: beq a2, a3, .LBB28_6
; RV32IFD-NEXT: # %bb.5:
; RV32IFD-NEXT: sltu a0, a2, a3
@@ -1209,38 +1209,38 @@ define i1 @isinf_q_fpclass(fp128 %x) {
;
; RV32I-LABEL: isinf_q_fpclass:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a6, 1048560
+; RV32I-NEXT: lui a5, 1048560
; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: lw a2, 0(a0)
-; RV32I-NEXT: lw a3, 4(a0)
-; RV32I-NEXT: lw a4, 8(a0)
-; RV32I-NEXT: slli a5, a1, 1
+; RV32I-NEXT: lw a4, 4(a0)
+; RV32I-NEXT: lw a3, 8(a0)
+; RV32I-NEXT: slli a6, a1, 1
; RV32I-NEXT: sltiu a0, a2, 0
-; RV32I-NEXT: seqz a2, a3
-; RV32I-NEXT: sltu a7, a3, a3
+; RV32I-NEXT: seqz a2, a4
+; RV32I-NEXT: sltu a7, a4, a4
; RV32I-NEXT: and a2, a2, a0
; RV32I-NEXT: or a7, a7, a2
-; RV32I-NEXT: seqz t0, a4
-; RV32I-NEXT: srli a5, a5, 1
-; RV32I-NEXT: sub a3, a3, a0
-; RV32I-NEXT: xor a2, a1, a5
+; RV32I-NEXT: seqz t0, a3
+; RV32I-NEXT: srli a6, a6, 1
+; RV32I-NEXT: sub a4, a4, a0
+; RV32I-NEXT: xor a2, a1, a6
; RV32I-NEXT: and t0, t0, a7
-; RV32I-NEXT: sub a1, a4, a7
-; RV32I-NEXT: sltu a4, a4, a4
-; RV32I-NEXT: or a4, a4, t0
-; RV32I-NEXT: add a6, a5, a6
-; RV32I-NEXT: beqz a3, .LBB28_2
+; RV32I-NEXT: sub a1, a3, a7
+; RV32I-NEXT: sltu a3, a3, a3
+; RV32I-NEXT: or a3, a3, t0
+; RV32I-NEXT: add a5, a6, a5
+; RV32I-NEXT: beqz a4, .LBB28_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: sltiu a0, a3, 0
+; RV32I-NEXT: sltiu a0, a4, 0
; RV32I-NEXT: .LBB28_2:
-; RV32I-NEXT: mv a5, a2
-; RV32I-NEXT: sub a2, a6, a4
+; RV32I-NEXT: mv a4, a2
+; RV32I-NEXT: sub a2, a5, a3
; RV32I-NEXT: lui a3, 524256
; RV32I-NEXT: beqz a1, .LBB28_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sltiu a0, a1, 0
; RV32I-NEXT: .LBB28_4:
-; RV32I-NEXT: snez a1, a5
+; RV32I-NEXT: snez a1, a4
; RV32I-NEXT: beq a2, a3, .LBB28_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: sltu a0, a2, a3
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
index 91cbf477efc03..b9ba15074e150 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
@@ -120,17 +120,17 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotl_64:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a6, a2, 63
-; RV32I-NEXT: li a3, 32
-; RV32I-NEXT: bltu a6, a3, .LBB2_2
+; RV32I-NEXT: li a4, 32
+; RV32I-NEXT: bltu a6, a4, .LBB2_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: li a4, 0
+; RV32I-NEXT: li a3, 0
; RV32I-NEXT: sll a7, a0, a6
; RV32I-NEXT: j .LBB2_3
; RV32I-NEXT: .LBB2_2:
-; RV32I-NEXT: neg a4, a6
-; RV32I-NEXT: srl a5, a0, a4
+; RV32I-NEXT: neg a3, a6
+; RV32I-NEXT: srl a5, a0, a3
; RV32I-NEXT: sll a7, a1, a2
-; RV32I-NEXT: sll a4, a0, a2
+; RV32I-NEXT: sll a3, a0, a2
; RV32I-NEXT: or a7, a5, a7
; RV32I-NEXT: .LBB2_3:
; RV32I-NEXT: neg a5, a2
@@ -140,7 +140,7 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32I-NEXT: mv a2, a7
; RV32I-NEXT: .LBB2_5:
; RV32I-NEXT: andi a6, a5, 63
-; RV32I-NEXT: bltu a6, a3, .LBB2_7
+; RV32I-NEXT: bltu a6, a4, .LBB2_7
; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: srl a7, a1, a6
; RV32I-NEXT: bnez a6, .LBB2_8
@@ -154,14 +154,14 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32I-NEXT: .LBB2_8:
; RV32I-NEXT: mv a0, a7
; RV32I-NEXT: .LBB2_9:
-; RV32I-NEXT: bltu a6, a3, .LBB2_11
+; RV32I-NEXT: bltu a6, a4, .LBB2_11
; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: j .LBB2_12
; RV32I-NEXT: .LBB2_11:
; RV32I-NEXT: srl a1, a1, a5
; RV32I-NEXT: .LBB2_12:
-; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: ret
;
@@ -176,17 +176,17 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32ZBB-LABEL: rotl_64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andi a6, a2, 63
-; RV32ZBB-NEXT: li a3, 32
-; RV32ZBB-NEXT: bltu a6, a3, .LBB2_2
+; RV32ZBB-NEXT: li a4, 32
+; RV32ZBB-NEXT: bltu a6, a4, .LBB2_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: li a4, 0
+; RV32ZBB-NEXT: li a3, 0
; RV32ZBB-NEXT: sll a7, a0, a6
; RV32ZBB-NEXT: j .LBB2_3
; RV32ZBB-NEXT: .LBB2_2:
-; RV32ZBB-NEXT: neg a4, a6
-; RV32ZBB-NEXT: srl a5, a0, a4
+; RV32ZBB-NEXT: neg a3, a6
+; RV32ZBB-NEXT: srl a5, a0, a3
; RV32ZBB-NEXT: sll a7, a1, a2
-; RV32ZBB-NEXT: sll a4, a0, a2
+; RV32ZBB-NEXT: sll a3, a0, a2
; RV32ZBB-NEXT: or a7, a5, a7
; RV32ZBB-NEXT: .LBB2_3:
; RV32ZBB-NEXT: neg a5, a2
@@ -196,7 +196,7 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32ZBB-NEXT: mv a2, a7
; RV32ZBB-NEXT: .LBB2_5:
; RV32ZBB-NEXT: andi a6, a5, 63
-; RV32ZBB-NEXT: bltu a6, a3, .LBB2_7
+; RV32ZBB-NEXT: bltu a6, a4, .LBB2_7
; RV32ZBB-NEXT: # %bb.6:
; RV32ZBB-NEXT: srl a7, a1, a6
; RV32ZBB-NEXT: bnez a6, .LBB2_8
@@ -210,14 +210,14 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32ZBB-NEXT: .LBB2_8:
; RV32ZBB-NEXT: mv a0, a7
; RV32ZBB-NEXT: .LBB2_9:
-; RV32ZBB-NEXT: bltu a6, a3, .LBB2_11
+; RV32ZBB-NEXT: bltu a6, a4, .LBB2_11
; RV32ZBB-NEXT: # %bb.10:
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: j .LBB2_12
; RV32ZBB-NEXT: .LBB2_11:
; RV32ZBB-NEXT: srl a1, a1, a5
; RV32ZBB-NEXT: .LBB2_12:
-; RV32ZBB-NEXT: or a0, a4, a0
+; RV32ZBB-NEXT: or a0, a3, a0
; RV32ZBB-NEXT: or a1, a2, a1
; RV32ZBB-NEXT: ret
;
@@ -229,17 +229,17 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32XTHEADBB-LABEL: rotl_64:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: andi a6, a2, 63
-; RV32XTHEADBB-NEXT: li a3, 32
-; RV32XTHEADBB-NEXT: bltu a6, a3, .LBB2_2
+; RV32XTHEADBB-NEXT: li a4, 32
+; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB2_2
; RV32XTHEADBB-NEXT: # %bb.1:
-; RV32XTHEADBB-NEXT: li a4, 0
+; RV32XTHEADBB-NEXT: li a3, 0
; RV32XTHEADBB-NEXT: sll a7, a0, a6
; RV32XTHEADBB-NEXT: j .LBB2_3
; RV32XTHEADBB-NEXT: .LBB2_2:
-; RV32XTHEADBB-NEXT: neg a4, a6
-; RV32XTHEADBB-NEXT: srl a5, a0, a4
+; RV32XTHEADBB-NEXT: neg a3, a6
+; RV32XTHEADBB-NEXT: srl a5, a0, a3
; RV32XTHEADBB-NEXT: sll a7, a1, a2
-; RV32XTHEADBB-NEXT: sll a4, a0, a2
+; RV32XTHEADBB-NEXT: sll a3, a0, a2
; RV32XTHEADBB-NEXT: or a7, a5, a7
; RV32XTHEADBB-NEXT: .LBB2_3:
; RV32XTHEADBB-NEXT: neg a5, a2
@@ -249,7 +249,7 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32XTHEADBB-NEXT: mv a2, a7
; RV32XTHEADBB-NEXT: .LBB2_5:
; RV32XTHEADBB-NEXT: andi a6, a5, 63
-; RV32XTHEADBB-NEXT: bltu a6, a3, .LBB2_7
+; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB2_7
; RV32XTHEADBB-NEXT: # %bb.6:
; RV32XTHEADBB-NEXT: srl a7, a1, a6
; RV32XTHEADBB-NEXT: bnez a6, .LBB2_8
@@ -263,14 +263,14 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32XTHEADBB-NEXT: .LBB2_8:
; RV32XTHEADBB-NEXT: mv a0, a7
; RV32XTHEADBB-NEXT: .LBB2_9:
-; RV32XTHEADBB-NEXT: bltu a6, a3, .LBB2_11
+; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB2_11
; RV32XTHEADBB-NEXT: # %bb.10:
; RV32XTHEADBB-NEXT: li a1, 0
; RV32XTHEADBB-NEXT: j .LBB2_12
; RV32XTHEADBB-NEXT: .LBB2_11:
; RV32XTHEADBB-NEXT: srl a1, a1, a5
; RV32XTHEADBB-NEXT: .LBB2_12:
-; RV32XTHEADBB-NEXT: or a0, a4, a0
+; RV32XTHEADBB-NEXT: or a0, a3, a0
; RV32XTHEADBB-NEXT: or a1, a2, a1
; RV32XTHEADBB-NEXT: ret
;
@@ -782,18 +782,18 @@ define i32 @rotr_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {
define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotl_64_mask:
; RV32I: # %bb.0:
-; RV32I-NEXT: li a4, 32
+; RV32I-NEXT: li a5, 32
; RV32I-NEXT: neg a3, a2
-; RV32I-NEXT: bltu a2, a4, .LBB10_2
+; RV32I-NEXT: bltu a2, a5, .LBB10_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: li a5, 0
+; RV32I-NEXT: li a4, 0
; RV32I-NEXT: sll t0, a0, a2
; RV32I-NEXT: j .LBB10_3
; RV32I-NEXT: .LBB10_2:
-; RV32I-NEXT: neg a5, a2
-; RV32I-NEXT: srl a6, a0, a5
+; RV32I-NEXT: neg a4, a2
+; RV32I-NEXT: srl a6, a0, a4
; RV32I-NEXT: sll a7, a1, a2
-; RV32I-NEXT: sll a5, a0, a2
+; RV32I-NEXT: sll a4, a0, a2
; RV32I-NEXT: or t0, a6, a7
; RV32I-NEXT: .LBB10_3:
; RV32I-NEXT: andi a7, a3, 63
@@ -802,7 +802,7 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: mv a6, t0
; RV32I-NEXT: .LBB10_5:
-; RV32I-NEXT: bltu a7, a4, .LBB10_7
+; RV32I-NEXT: bltu a7, a5, .LBB10_7
; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: srl a2, a1, a7
; RV32I-NEXT: bnez a7, .LBB10_8
@@ -816,14 +816,14 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
; RV32I-NEXT: .LBB10_8:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB10_9:
-; RV32I-NEXT: bltu a7, a4, .LBB10_11
+; RV32I-NEXT: bltu a7, a5, .LBB10_11
; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: j .LBB10_12
; RV32I-NEXT: .LBB10_11:
; RV32I-NEXT: srl a1, a1, a3
; RV32I-NEXT: .LBB10_12:
-; RV32I-NEXT: or a0, a5, a0
+; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a6, a1
; RV32I-NEXT: ret
;
@@ -837,18 +837,18 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
;
; RV32ZBB-LABEL: rotl_64_mask:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: li a4, 32
+; RV32ZBB-NEXT: li a5, 32
; RV32ZBB-NEXT: neg a3, a2
-; RV32ZBB-NEXT: bltu a2, a4, .LBB10_2
+; RV32ZBB-NEXT: bltu a2, a5, .LBB10_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: li a5, 0
+; RV32ZBB-NEXT: li a4, 0
; RV32ZBB-NEXT: sll t0, a0, a2
; RV32ZBB-NEXT: j .LBB10_3
; RV32ZBB-NEXT: .LBB10_2:
-; RV32ZBB-NEXT: neg a5, a2
-; RV32ZBB-NEXT: srl a6, a0, a5
+; RV32ZBB-NEXT: neg a4, a2
+; RV32ZBB-NEXT: srl a6, a0, a4
; RV32ZBB-NEXT: sll a7, a1, a2
-; RV32ZBB-NEXT: sll a5, a0, a2
+; RV32ZBB-NEXT: sll a4, a0, a2
; RV32ZBB-NEXT: or t0, a6, a7
; RV32ZBB-NEXT: .LBB10_3:
; RV32ZBB-NEXT: andi a7, a3, 63
@@ -857,7 +857,7 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
; RV32ZBB-NEXT: # %bb.4:
; RV32ZBB-NEXT: mv a6, t0
; RV32ZBB-NEXT: .LBB10_5:
-; RV32ZBB-NEXT: bltu a7, a4, .LBB10_7
+; RV32ZBB-NEXT: bltu a7, a5, .LBB10_7
; RV32ZBB-NEXT: # %bb.6:
; RV32ZBB-NEXT: srl a2, a1, a7
; RV32ZBB-NEXT: bnez a7, .LBB10_8
@@ -871,14 +871,14 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
; RV32ZBB-NEXT: .LBB10_8:
; RV32ZBB-NEXT: mv a0, a2
; RV32ZBB-NEXT: .LBB10_9:
-; RV32ZBB-NEXT: bltu a7, a4, .LBB10_11
+; RV32ZBB-NEXT: bltu a7, a5, .LBB10_11
; RV32ZBB-NEXT: # %bb.10:
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: j .LBB10_12
; RV32ZBB-NEXT: .LBB10_11:
; RV32ZBB-NEXT: srl a1, a1, a3
; RV32ZBB-NEXT: .LBB10_12:
-; RV32ZBB-NEXT: or a0, a5, a0
+; RV32ZBB-NEXT: or a0, a4, a0
; RV32ZBB-NEXT: or a1, a6, a1
; RV32ZBB-NEXT: ret
;
@@ -892,18 +892,18 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
;
; RV32XTHEADBB-LABEL: rotl_64_mask:
; RV32XTHEADBB: # %bb.0:
-; RV32XTHEADBB-NEXT: li a4, 32
+; RV32XTHEADBB-NEXT: li a5, 32
; RV32XTHEADBB-NEXT: neg a3, a2
-; RV32XTHEADBB-NEXT: bltu a2, a4, .LBB10_2
+; RV32XTHEADBB-NEXT: bltu a2, a5, .LBB10_2
; RV32XTHEADBB-NEXT: # %bb.1:
-; RV32XTHEADBB-NEXT: li a5, 0
+; RV32XTHEADBB-NEXT: li a4, 0
; RV32XTHEADBB-NEXT: sll t0, a0, a2
; RV32XTHEADBB-NEXT: j .LBB10_3
; RV32XTHEADBB-NEXT: .LBB10_2:
-; RV32XTHEADBB-NEXT: neg a5, a2
-; RV32XTHEADBB-NEXT: srl a6, a0, a5
+; RV32XTHEADBB-NEXT: neg a4, a2
+; RV32XTHEADBB-NEXT: srl a6, a0, a4
; RV32XTHEADBB-NEXT: sll a7, a1, a2
-; RV32XTHEADBB-NEXT: sll a5, a0, a2
+; RV32XTHEADBB-NEXT: sll a4, a0, a2
; RV32XTHEADBB-NEXT: or t0, a6, a7
; RV32XTHEADBB-NEXT: .LBB10_3:
; RV32XTHEADBB-NEXT: andi a7, a3, 63
@@ -912,7 +912,7 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
; RV32XTHEADBB-NEXT: # %bb.4:
; RV32XTHEADBB-NEXT: mv a6, t0
; RV32XTHEADBB-NEXT: .LBB10_5:
-; RV32XTHEADBB-NEXT: bltu a7, a4, .LBB10_7
+; RV32XTHEADBB-NEXT: bltu a7, a5, .LBB10_7
; RV32XTHEADBB-NEXT: # %bb.6:
; RV32XTHEADBB-NEXT: srl a2, a1, a7
; RV32XTHEADBB-NEXT: bnez a7, .LBB10_8
@@ -926,14 +926,14 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
; RV32XTHEADBB-NEXT: .LBB10_8:
; RV32XTHEADBB-NEXT: mv a0, a2
; RV32XTHEADBB-NEXT: .LBB10_9:
-; RV32XTHEADBB-NEXT: bltu a7, a4, .LBB10_11
+; RV32XTHEADBB-NEXT: bltu a7, a5, .LBB10_11
; RV32XTHEADBB-NEXT: # %bb.10:
; RV32XTHEADBB-NEXT: li a1, 0
; RV32XTHEADBB-NEXT: j .LBB10_12
; RV32XTHEADBB-NEXT: .LBB10_11:
; RV32XTHEADBB-NEXT: srl a1, a1, a3
; RV32XTHEADBB-NEXT: .LBB10_12:
-; RV32XTHEADBB-NEXT: or a0, a5, a0
+; RV32XTHEADBB-NEXT: or a0, a4, a0
; RV32XTHEADBB-NEXT: or a1, a6, a1
; RV32XTHEADBB-NEXT: ret
;
@@ -956,19 +956,19 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotl_64_mask_and_127_and_63:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a6, a2, 127
-; RV32I-NEXT: li a3, 32
-; RV32I-NEXT: bltu a6, a3, .LBB11_2
+; RV32I-NEXT: li a4, 32
+; RV32I-NEXT: bltu a6, a4, .LBB11_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: li a4, 0
+; RV32I-NEXT: li a3, 0
; RV32I-NEXT: sll a7, a0, a6
; RV32I-NEXT: mv a5, a1
; RV32I-NEXT: bnez a6, .LBB11_3
; RV32I-NEXT: j .LBB11_4
; RV32I-NEXT: .LBB11_2:
-; RV32I-NEXT: neg a4, a6
-; RV32I-NEXT: srl a5, a0, a4
+; RV32I-NEXT: neg a3, a6
+; RV32I-NEXT: srl a5, a0, a3
; RV32I-NEXT: sll a7, a1, a2
-; RV32I-NEXT: sll a4, a0, a2
+; RV32I-NEXT: sll a3, a0, a2
; RV32I-NEXT: or a7, a5, a7
; RV32I-NEXT: mv a5, a1
; RV32I-NEXT: beqz a6, .LBB11_4
@@ -977,7 +977,7 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV32I-NEXT: .LBB11_4:
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: andi a6, a2, 63
-; RV32I-NEXT: bltu a6, a3, .LBB11_6
+; RV32I-NEXT: bltu a6, a4, .LBB11_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: srl a7, a1, a6
; RV32I-NEXT: bnez a6, .LBB11_7
@@ -991,14 +991,14 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV32I-NEXT: .LBB11_7:
; RV32I-NEXT: mv a0, a7
; RV32I-NEXT: .LBB11_8:
-; RV32I-NEXT: bltu a6, a3, .LBB11_10
+; RV32I-NEXT: bltu a6, a4, .LBB11_10
; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: j .LBB11_11
; RV32I-NEXT: .LBB11_10:
; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: .LBB11_11:
-; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: ret
;
@@ -1013,19 +1013,19 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV32ZBB-LABEL: rotl_64_mask_and_127_and_63:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andi a6, a2, 127
-; RV32ZBB-NEXT: li a3, 32
-; RV32ZBB-NEXT: bltu a6, a3, .LBB11_2
+; RV32ZBB-NEXT: li a4, 32
+; RV32ZBB-NEXT: bltu a6, a4, .LBB11_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: li a4, 0
+; RV32ZBB-NEXT: li a3, 0
; RV32ZBB-NEXT: sll a7, a0, a6
; RV32ZBB-NEXT: mv a5, a1
; RV32ZBB-NEXT: bnez a6, .LBB11_3
; RV32ZBB-NEXT: j .LBB11_4
; RV32ZBB-NEXT: .LBB11_2:
-; RV32ZBB-NEXT: neg a4, a6
-; RV32ZBB-NEXT: srl a5, a0, a4
+; RV32ZBB-NEXT: neg a3, a6
+; RV32ZBB-NEXT: srl a5, a0, a3
; RV32ZBB-NEXT: sll a7, a1, a2
-; RV32ZBB-NEXT: sll a4, a0, a2
+; RV32ZBB-NEXT: sll a3, a0, a2
; RV32ZBB-NEXT: or a7, a5, a7
; RV32ZBB-NEXT: mv a5, a1
; RV32ZBB-NEXT: beqz a6, .LBB11_4
@@ -1034,7 +1034,7 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV32ZBB-NEXT: .LBB11_4:
; RV32ZBB-NEXT: neg a2, a2
; RV32ZBB-NEXT: andi a6, a2, 63
-; RV32ZBB-NEXT: bltu a6, a3, .LBB11_6
+; RV32ZBB-NEXT: bltu a6, a4, .LBB11_6
; RV32ZBB-NEXT: # %bb.5:
; RV32ZBB-NEXT: srl a7, a1, a6
; RV32ZBB-NEXT: bnez a6, .LBB11_7
@@ -1048,14 +1048,14 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV32ZBB-NEXT: .LBB11_7:
; RV32ZBB-NEXT: mv a0, a7
; RV32ZBB-NEXT: .LBB11_8:
-; RV32ZBB-NEXT: bltu a6, a3, .LBB11_10
+; RV32ZBB-NEXT: bltu a6, a4, .LBB11_10
; RV32ZBB-NEXT: # %bb.9:
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: j .LBB11_11
; RV32ZBB-NEXT: .LBB11_10:
; RV32ZBB-NEXT: srl a1, a1, a2
; RV32ZBB-NEXT: .LBB11_11:
-; RV32ZBB-NEXT: or a0, a4, a0
+; RV32ZBB-NEXT: or a0, a3, a0
; RV32ZBB-NEXT: or a1, a5, a1
; RV32ZBB-NEXT: ret
;
@@ -1070,19 +1070,19 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV32XTHEADBB-LABEL: rotl_64_mask_and_127_and_63:
; RV32XTHEADBB: # %bb.0:
; RV32XTHEADBB-NEXT: andi a6, a2, 127
-; RV32XTHEADBB-NEXT: li a3, 32
-; RV32XTHEADBB-NEXT: bltu a6, a3, .LBB11_2
+; RV32XTHEADBB-NEXT: li a4, 32
+; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB11_2
; RV32XTHEADBB-NEXT: # %bb.1:
-; RV32XTHEADBB-NEXT: li a4, 0
+; RV32XTHEADBB-NEXT: li a3, 0
; RV32XTHEADBB-NEXT: sll a7, a0, a6
; RV32XTHEADBB-NEXT: mv a5, a1
; RV32XTHEADBB-NEXT: bnez a6, .LBB11_3
; RV32XTHEADBB-NEXT: j .LBB11_4
; RV32XTHEADBB-NEXT: .LBB11_2:
-; RV32XTHEADBB-NEXT: neg a4, a6
-; RV32XTHEADBB-NEXT: srl a5, a0, a4
+; RV32XTHEADBB-NEXT: neg a3, a6
+; RV32XTHEADBB-NEXT: srl a5, a0, a3
; RV32XTHEADBB-NEXT: sll a7, a1, a2
-; RV32XTHEADBB-NEXT: sll a4, a0, a2
+; RV32XTHEADBB-NEXT: sll a3, a0, a2
; RV32XTHEADBB-NEXT: or a7, a5, a7
; RV32XTHEADBB-NEXT: mv a5, a1
; RV32XTHEADBB-NEXT: beqz a6, .LBB11_4
@@ -1091,7 +1091,7 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV32XTHEADBB-NEXT: .LBB11_4:
; RV32XTHEADBB-NEXT: neg a2, a2
; RV32XTHEADBB-NEXT: andi a6, a2, 63
-; RV32XTHEADBB-NEXT: bltu a6, a3, .LBB11_6
+; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB11_6
; RV32XTHEADBB-NEXT: # %bb.5:
; RV32XTHEADBB-NEXT: srl a7, a1, a6
; RV32XTHEADBB-NEXT: bnez a6, .LBB11_7
@@ -1105,14 +1105,14 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV32XTHEADBB-NEXT: .LBB11_7:
; RV32XTHEADBB-NEXT: mv a0, a7
; RV32XTHEADBB-NEXT: .LBB11_8:
-; RV32XTHEADBB-NEXT: bltu a6, a3, .LBB11_10
+; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB11_10
; RV32XTHEADBB-NEXT: # %bb.9:
; RV32XTHEADBB-NEXT: li a1, 0
; RV32XTHEADBB-NEXT: j .LBB11_11
; RV32XTHEADBB-NEXT: .LBB11_10:
; RV32XTHEADBB-NEXT: srl a1, a1, a2
; RV32XTHEADBB-NEXT: .LBB11_11:
-; RV32XTHEADBB-NEXT: or a0, a4, a0
+; RV32XTHEADBB-NEXT: or a0, a3, a0
; RV32XTHEADBB-NEXT: or a1, a5, a1
; RV32XTHEADBB-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
index d922d5aa02943..3abbd85356886 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
@@ -135,17 +135,17 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: rol_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a6, a2, 63
-; CHECK-NEXT: li a3, 32
-; CHECK-NEXT: bltu a6, a3, .LBB7_2
+; CHECK-NEXT: li a4, 32
+; CHECK-NEXT: bltu a6, a4, .LBB7_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a4, 0
+; CHECK-NEXT: li a3, 0
; CHECK-NEXT: sll a7, a0, a6
; CHECK-NEXT: j .LBB7_3
; CHECK-NEXT: .LBB7_2:
-; CHECK-NEXT: neg a4, a6
-; CHECK-NEXT: srl a5, a0, a4
+; CHECK-NEXT: neg a3, a6
+; CHECK-NEXT: srl a5, a0, a3
; CHECK-NEXT: sll a7, a1, a2
-; CHECK-NEXT: sll a4, a0, a2
+; CHECK-NEXT: sll a3, a0, a2
; CHECK-NEXT: or a7, a5, a7
; CHECK-NEXT: .LBB7_3:
; CHECK-NEXT: neg a5, a2
@@ -155,7 +155,7 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind {
; CHECK-NEXT: mv a2, a7
; CHECK-NEXT: .LBB7_5:
; CHECK-NEXT: andi a6, a5, 63
-; CHECK-NEXT: bltu a6, a3, .LBB7_7
+; CHECK-NEXT: bltu a6, a4, .LBB7_7
; CHECK-NEXT: # %bb.6:
; CHECK-NEXT: srl a7, a1, a6
; CHECK-NEXT: bnez a6, .LBB7_8
@@ -169,14 +169,14 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind {
; CHECK-NEXT: .LBB7_8:
; CHECK-NEXT: mv a0, a7
; CHECK-NEXT: .LBB7_9:
-; CHECK-NEXT: bltu a6, a3, .LBB7_11
+; CHECK-NEXT: bltu a6, a4, .LBB7_11
; CHECK-NEXT: # %bb.10:
; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB7_12
; CHECK-NEXT: .LBB7_11:
; CHECK-NEXT: srl a1, a1, a5
; CHECK-NEXT: .LBB7_12:
-; CHECK-NEXT: or a0, a4, a0
+; CHECK-NEXT: or a0, a3, a0
; CHECK-NEXT: or a1, a2, a1
; CHECK-NEXT: ret
%or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
index db388016de5c3..852b6369fc06d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
@@ -126,13 +126,13 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addiw a0, a0, -1
+; RV64I-NEXT: addiw a1, a0, -1
; RV64I-NEXT: li s0, 32
-; RV64I-NEXT: li a1, 32
-; RV64I-NEXT: beqz a0, .LBB2_2
+; RV64I-NEXT: li a0, 32
+; RV64I-NEXT: beqz a1, .LBB2_2
; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: srliw a1, a0, 1
-; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: srliw a0, a1, 1
+; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
@@ -162,9 +162,9 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: li a1, 32
; RV64I-NEXT: srliw a0, a0, 24
-; RV64I-NEXT: sub a1, a1, a0
+; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: .LBB2_2: # %cond.end
-; RV64I-NEXT: subw a0, s0, a1
+; RV64I-NEXT: subw a0, s0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll b/llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
index 0211f803f157d..35f386cd3cdc8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
@@ -209,43 +209,43 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: lshr128:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a2)
-; RV32I-NEXT: lw a3, 8(a1)
+; RV32I-NEXT: lw a4, 8(a1)
; RV32I-NEXT: lw a7, 12(a1)
; RV32I-NEXT: li t0, 32
-; RV32I-NEXT: neg t4, a2
-; RV32I-NEXT: srl t2, a3, a2
-; RV32I-NEXT: sll t6, a7, t4
+; RV32I-NEXT: neg t5, a2
+; RV32I-NEXT: srl t2, a4, a2
+; RV32I-NEXT: sll t6, a7, t5
; RV32I-NEXT: bltu a2, t0, .LBB6_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl a5, a7, a2
-; RV32I-NEXT: mv a4, a3
+; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: bnez a2, .LBB6_3
; RV32I-NEXT: j .LBB6_4
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: or a5, t2, t6
-; RV32I-NEXT: mv a4, a3
+; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: beqz a2, .LBB6_4
; RV32I-NEXT: .LBB6_3:
-; RV32I-NEXT: mv a4, a5
+; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: .LBB6_4:
; RV32I-NEXT: lw a5, 0(a1)
; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: bltu a2, t0, .LBB6_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: srl t5, a1, a2
+; RV32I-NEXT: srl t4, a1, a2
; RV32I-NEXT: j .LBB6_7
; RV32I-NEXT: .LBB6_6:
; RV32I-NEXT: srl t1, a5, a2
-; RV32I-NEXT: sll t3, a1, t4
+; RV32I-NEXT: sll t3, a1, t5
; RV32I-NEXT: srl a6, a7, a2
-; RV32I-NEXT: or t5, t1, t3
+; RV32I-NEXT: or t4, t1, t3
; RV32I-NEXT: .LBB6_7:
; RV32I-NEXT: li t1, 64
; RV32I-NEXT: mv t3, a5
; RV32I-NEXT: beqz a2, .LBB6_9
; RV32I-NEXT: # %bb.8:
-; RV32I-NEXT: mv t3, t5
+; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: .LBB6_9:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
@@ -254,20 +254,20 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sub s0, t1, a2
; RV32I-NEXT: bltu a2, t0, .LBB6_12
; RV32I-NEXT: # %bb.10:
-; RV32I-NEXT: li t5, 0
+; RV32I-NEXT: li t4, 0
; RV32I-NEXT: bgeu s0, t0, .LBB6_13
; RV32I-NEXT: .LBB6_11:
; RV32I-NEXT: neg s1, s0
-; RV32I-NEXT: srl s1, a3, s1
-; RV32I-NEXT: sll t4, a3, t4
+; RV32I-NEXT: srl s1, a4, s1
+; RV32I-NEXT: sll t5, a4, t5
; RV32I-NEXT: or s2, s1, t6
; RV32I-NEXT: j .LBB6_14
; RV32I-NEXT: .LBB6_12:
-; RV32I-NEXT: srl t5, a1, a2
+; RV32I-NEXT: srl t4, a1, a2
; RV32I-NEXT: bltu s0, t0, .LBB6_11
; RV32I-NEXT: .LBB6_13:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: sll s2, a3, s0
+; RV32I-NEXT: li t5, 0
+; RV32I-NEXT: sll s2, a4, s0
; RV32I-NEXT: .LBB6_14:
; RV32I-NEXT: addi s1, a2, -64
; RV32I-NEXT: mv t6, a7
@@ -286,7 +286,7 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: or t2, t2, s0
; RV32I-NEXT: beqz s1, .LBB6_20
; RV32I-NEXT: .LBB6_19:
-; RV32I-NEXT: mv a3, t2
+; RV32I-NEXT: mv a4, t2
; RV32I-NEXT: .LBB6_20:
; RV32I-NEXT: bltu s1, t0, .LBB6_22
; RV32I-NEXT: # %bb.21:
@@ -297,19 +297,19 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: srl a7, a7, a2
; RV32I-NEXT: bgeu a2, t1, .LBB6_24
; RV32I-NEXT: .LBB6_23:
-; RV32I-NEXT: or a3, t3, t4
-; RV32I-NEXT: or a7, t5, t6
+; RV32I-NEXT: or a4, t3, t5
+; RV32I-NEXT: or a7, t4, t6
; RV32I-NEXT: .LBB6_24:
; RV32I-NEXT: bnez a2, .LBB6_28
; RV32I-NEXT: # %bb.25:
; RV32I-NEXT: bltu a2, t1, .LBB6_27
; RV32I-NEXT: .LBB6_26:
-; RV32I-NEXT: li a4, 0
+; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a6, 0
; RV32I-NEXT: .LBB6_27:
; RV32I-NEXT: sw a5, 0(a0)
; RV32I-NEXT: sw a1, 4(a0)
-; RV32I-NEXT: sw a4, 8(a0)
+; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: sw a6, 12(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
@@ -317,7 +317,7 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB6_28:
-; RV32I-NEXT: mv a5, a3
+; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: bgeu a2, t1, .LBB6_26
; RV32I-NEXT: j .LBB6_27
@@ -355,24 +355,24 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: ashr128:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a2)
-; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a3, 12(a1)
; RV32I-NEXT: li t0, 32
; RV32I-NEXT: neg t5, a2
-; RV32I-NEXT: srl t2, a4, a2
+; RV32I-NEXT: srl t2, a5, a2
; RV32I-NEXT: sll t6, a3, t5
; RV32I-NEXT: bltu a2, t0, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sra a6, a3, a2
-; RV32I-NEXT: mv a5, a4
+; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: bnez a2, .LBB7_3
; RV32I-NEXT: j .LBB7_4
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: or a6, t2, t6
-; RV32I-NEXT: mv a5, a4
+; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: beqz a2, .LBB7_4
; RV32I-NEXT: .LBB7_3:
-; RV32I-NEXT: mv a5, a6
+; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: .LBB7_4:
; RV32I-NEXT: lw a6, 0(a1)
; RV32I-NEXT: lw a1, 4(a1)
@@ -404,8 +404,8 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: bgeu s0, t0, .LBB7_13
; RV32I-NEXT: .LBB7_11:
; RV32I-NEXT: neg s1, s0
-; RV32I-NEXT: srl s1, a4, s1
-; RV32I-NEXT: sll t5, a4, t5
+; RV32I-NEXT: srl s1, a5, s1
+; RV32I-NEXT: sll t5, a5, t5
; RV32I-NEXT: or s2, s1, t6
; RV32I-NEXT: j .LBB7_14
; RV32I-NEXT: .LBB7_12:
@@ -413,7 +413,7 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: bltu s0, t0, .LBB7_11
; RV32I-NEXT: .LBB7_13:
; RV32I-NEXT: li t5, 0
-; RV32I-NEXT: sll s2, a4, s0
+; RV32I-NEXT: sll s2, a5, s0
; RV32I-NEXT: .LBB7_14:
; RV32I-NEXT: addi s1, a2, -64
; RV32I-NEXT: mv t6, a3
@@ -432,7 +432,7 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: or t2, t2, s0
; RV32I-NEXT: beqz s1, .LBB7_20
; RV32I-NEXT: .LBB7_19:
-; RV32I-NEXT: mv a4, t2
+; RV32I-NEXT: mv a5, t2
; RV32I-NEXT: .LBB7_20:
; RV32I-NEXT: bltu s1, t0, .LBB7_22
; RV32I-NEXT: # %bb.21:
@@ -443,19 +443,19 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sra t0, a3, a2
; RV32I-NEXT: bgeu a2, t1, .LBB7_24
; RV32I-NEXT: .LBB7_23:
-; RV32I-NEXT: or a4, t3, t5
+; RV32I-NEXT: or a5, t3, t5
; RV32I-NEXT: or t0, t4, t6
; RV32I-NEXT: .LBB7_24:
; RV32I-NEXT: bnez a2, .LBB7_28
; RV32I-NEXT: # %bb.25:
; RV32I-NEXT: bltu a2, t1, .LBB7_27
; RV32I-NEXT: .LBB7_26:
-; RV32I-NEXT: srai a5, a3, 31
-; RV32I-NEXT: mv a7, a5
+; RV32I-NEXT: srai a4, a3, 31
+; RV32I-NEXT: mv a7, a4
; RV32I-NEXT: .LBB7_27:
; RV32I-NEXT: sw a6, 0(a0)
; RV32I-NEXT: sw a1, 4(a0)
-; RV32I-NEXT: sw a5, 8(a0)
+; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a7, 12(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
@@ -463,7 +463,7 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB7_28:
-; RV32I-NEXT: mv a6, a4
+; RV32I-NEXT: mv a6, a5
; RV32I-NEXT: mv a1, t0
; RV32I-NEXT: bgeu a2, t1, .LBB7_26
; RV32I-NEXT: j .LBB7_27
@@ -504,18 +504,18 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: lw a7, 0(a1)
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: li a6, 64
-; RV32I-NEXT: li t1, 32
+; RV32I-NEXT: li t2, 32
; RV32I-NEXT: neg t5, a2
-; RV32I-NEXT: srl t2, a7, t5
+; RV32I-NEXT: srl t1, a7, t5
; RV32I-NEXT: sll t0, a3, a2
-; RV32I-NEXT: bltu a2, t1, .LBB8_2
+; RV32I-NEXT: bltu a2, t2, .LBB8_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: sll t3, a7, a2
; RV32I-NEXT: j .LBB8_3
; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: sll a4, a7, a2
-; RV32I-NEXT: or t3, t2, t0
+; RV32I-NEXT: or t3, t1, t0
; RV32I-NEXT: .LBB8_3:
; RV32I-NEXT: sub t4, a6, a2
; RV32I-NEXT: mv a5, a3
@@ -523,22 +523,22 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: mv a5, t3
; RV32I-NEXT: .LBB8_5:
-; RV32I-NEXT: bltu t4, t1, .LBB8_7
+; RV32I-NEXT: bltu t4, t2, .LBB8_7
; RV32I-NEXT: # %bb.6:
-; RV32I-NEXT: srl t2, a3, t4
+; RV32I-NEXT: srl t1, a3, t4
; RV32I-NEXT: mv t3, a7
; RV32I-NEXT: bnez t4, .LBB8_8
; RV32I-NEXT: j .LBB8_9
; RV32I-NEXT: .LBB8_7:
; RV32I-NEXT: neg t3, t4
; RV32I-NEXT: sll t3, a3, t3
-; RV32I-NEXT: or t2, t2, t3
+; RV32I-NEXT: or t1, t1, t3
; RV32I-NEXT: mv t3, a7
; RV32I-NEXT: beqz t4, .LBB8_9
; RV32I-NEXT: .LBB8_8:
-; RV32I-NEXT: mv t3, t2
+; RV32I-NEXT: mv t3, t1
; RV32I-NEXT: .LBB8_9:
-; RV32I-NEXT: bltu t4, t1, .LBB8_11
+; RV32I-NEXT: bltu t4, t2, .LBB8_11
; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: j .LBB8_12
@@ -548,17 +548,17 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t2, 8(a1)
+; RV32I-NEXT: lw t1, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
-; RV32I-NEXT: bltu a2, t1, .LBB8_14
+; RV32I-NEXT: bltu a2, t2, .LBB8_14
; RV32I-NEXT: # %bb.13:
; RV32I-NEXT: li t5, 0
-; RV32I-NEXT: sll s1, t2, a2
+; RV32I-NEXT: sll s1, t1, a2
; RV32I-NEXT: j .LBB8_15
; RV32I-NEXT: .LBB8_14:
-; RV32I-NEXT: srl t6, t2, t5
+; RV32I-NEXT: srl t6, t1, t5
; RV32I-NEXT: sll s0, a1, a2
-; RV32I-NEXT: sll t5, t2, a2
+; RV32I-NEXT: sll t5, t1, a2
; RV32I-NEXT: or s1, t6, s0
; RV32I-NEXT: .LBB8_15:
; RV32I-NEXT: addi s0, a2, -64
@@ -567,16 +567,16 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: # %bb.16:
; RV32I-NEXT: mv t6, s1
; RV32I-NEXT: .LBB8_17:
-; RV32I-NEXT: bltu s0, t1, .LBB8_19
+; RV32I-NEXT: bltu s0, t2, .LBB8_19
; RV32I-NEXT: # %bb.18:
-; RV32I-NEXT: li t1, 0
+; RV32I-NEXT: li t2, 0
; RV32I-NEXT: sll a7, a7, s0
; RV32I-NEXT: bnez s0, .LBB8_20
; RV32I-NEXT: j .LBB8_21
; RV32I-NEXT: .LBB8_19:
-; RV32I-NEXT: neg t1, s0
-; RV32I-NEXT: srl s1, a7, t1
-; RV32I-NEXT: sll t1, a7, a2
+; RV32I-NEXT: neg t2, s0
+; RV32I-NEXT: srl s1, a7, t2
+; RV32I-NEXT: sll t2, a7, a2
; RV32I-NEXT: or a7, s1, t0
; RV32I-NEXT: beqz s0, .LBB8_21
; RV32I-NEXT: .LBB8_20:
@@ -589,16 +589,16 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: bnez a2, .LBB8_24
; RV32I-NEXT: j .LBB8_25
; RV32I-NEXT: .LBB8_23:
-; RV32I-NEXT: or t1, t3, t5
+; RV32I-NEXT: or t2, t3, t5
; RV32I-NEXT: or a3, t4, t6
; RV32I-NEXT: beqz a2, .LBB8_25
; RV32I-NEXT: .LBB8_24:
-; RV32I-NEXT: mv t2, t1
+; RV32I-NEXT: mv t1, t2
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: .LBB8_25:
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a5, 4(a0)
-; RV32I-NEXT: sw t2, 8(a0)
+; RV32I-NEXT: sw t1, 8(a0)
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll b/llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
index 0871b60b74ec3..131d90d85d810 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
@@ -2762,15 +2762,15 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: slli a6, a6, 3
; RV64I-NEXT: li t1, 64
; RV64I-NEXT: neg t3, a6
-; RV64I-NEXT: sub t5, a6, t1
-; RV64I-NEXT: sll t4, t0, t3
+; RV64I-NEXT: sub t4, a6, t1
+; RV64I-NEXT: sll t5, t0, t3
; RV64I-NEXT: bltu a6, t1, .LBB12_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: srl t6, t0, t5
+; RV64I-NEXT: srl t6, t0, t4
; RV64I-NEXT: j .LBB12_3
; RV64I-NEXT: .LBB12_2:
; RV64I-NEXT: srl t6, a3, a6
-; RV64I-NEXT: or t6, t6, t4
+; RV64I-NEXT: or t6, t6, t5
; RV64I-NEXT: .LBB12_3:
; RV64I-NEXT: or a4, a1, a4
; RV64I-NEXT: slli a5, a5, 32
@@ -2786,44 +2786,44 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: bltu a6, t1, .LBB12_7
; RV64I-NEXT: # %bb.6:
; RV64I-NEXT: li a0, 0
-; RV64I-NEXT: srl t5, a4, t5
+; RV64I-NEXT: srl t4, a4, t4
; RV64I-NEXT: j .LBB12_8
; RV64I-NEXT: .LBB12_7:
; RV64I-NEXT: srl a7, a5, a6
; RV64I-NEXT: sll t2, a4, t3
; RV64I-NEXT: srl a0, t0, a6
-; RV64I-NEXT: or t5, a7, t2
+; RV64I-NEXT: or t4, a7, t2
; RV64I-NEXT: .LBB12_8:
; RV64I-NEXT: li a7, 128
; RV64I-NEXT: mv t2, a5
; RV64I-NEXT: beqz a6, .LBB12_10
; RV64I-NEXT: # %bb.9:
-; RV64I-NEXT: mv t2, t5
+; RV64I-NEXT: mv t2, t4
; RV64I-NEXT: .LBB12_10:
; RV64I-NEXT: sub t6, a7, a6
; RV64I-NEXT: bltu a6, t1, .LBB12_13
; RV64I-NEXT: # %bb.11:
-; RV64I-NEXT: li t5, 0
+; RV64I-NEXT: li t4, 0
; RV64I-NEXT: bgeu t6, t1, .LBB12_14
; RV64I-NEXT: .LBB12_12:
; RV64I-NEXT: neg s0, t6
; RV64I-NEXT: srl s0, a3, s0
; RV64I-NEXT: sll t3, a3, t3
-; RV64I-NEXT: or s1, s0, t4
+; RV64I-NEXT: or s1, s0, t5
; RV64I-NEXT: j .LBB12_15
; RV64I-NEXT: .LBB12_13:
-; RV64I-NEXT: srl t5, a4, a6
+; RV64I-NEXT: srl t4, a4, a6
; RV64I-NEXT: bltu t6, t1, .LBB12_12
; RV64I-NEXT: .LBB12_14:
; RV64I-NEXT: li t3, 0
-; RV64I-NEXT: sub t4, t6, t1
-; RV64I-NEXT: sll s1, a3, t4
+; RV64I-NEXT: sub t5, t6, t1
+; RV64I-NEXT: sll s1, a3, t5
; RV64I-NEXT: .LBB12_15:
; RV64I-NEXT: sub s0, a6, a7
-; RV64I-NEXT: mv t4, t0
+; RV64I-NEXT: mv t5, t0
; RV64I-NEXT: beqz t6, .LBB12_17
; RV64I-NEXT: # %bb.16:
-; RV64I-NEXT: mv t4, s1
+; RV64I-NEXT: mv t5, s1
; RV64I-NEXT: .LBB12_17:
; RV64I-NEXT: bltu s0, t1, .LBB12_19
; RV64I-NEXT: # %bb.18:
@@ -2850,7 +2850,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: bgeu a6, a7, .LBB12_25
; RV64I-NEXT: .LBB12_24:
; RV64I-NEXT: or a3, t2, t3
-; RV64I-NEXT: or t0, t5, t4
+; RV64I-NEXT: or t0, t4, t5
; RV64I-NEXT: .LBB12_25:
; RV64I-NEXT: bnez a6, .LBB12_29
; RV64I-NEXT: # %bb.26:
@@ -3015,7 +3015,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: slli t2, t2, 8
; RV32I-NEXT: or t1, s0, t1
; RV32I-NEXT: or a3, t3, t0
-; RV32I-NEXT: sw a5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a7, .LBB12_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: li s0, 0
@@ -3094,42 +3094,41 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lbu s8, 29(a0)
; RV32I-NEXT: lbu s7, 30(a0)
; RV32I-NEXT: slli s10, s4, 8
-; RV32I-NEXT: or s4, s6, s2
+; RV32I-NEXT: or s2, s6, s2
; RV32I-NEXT: slli s6, s5, 16
; RV32I-NEXT: li a5, 4
-; RV32I-NEXT: sll s2, t1, s3
-; RV32I-NEXT: sw s2, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sll s9, t1, s3
; RV32I-NEXT: beqz t5, .LBB12_19
; RV32I-NEXT: # %bb.18:
-; RV32I-NEXT: lw t2, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: mv t2, s9
; RV32I-NEXT: .LBB12_19:
-; RV32I-NEXT: lbu s2, 28(a0)
+; RV32I-NEXT: lbu s4, 28(a0)
; RV32I-NEXT: slli s8, s8, 8
; RV32I-NEXT: or s5, s10, s7
; RV32I-NEXT: srl s10, t0, a4
-; RV32I-NEXT: or a0, s6, s4
+; RV32I-NEXT: or a0, s6, s2
; RV32I-NEXT: bne a7, a5, .LBB12_21
; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: or s0, s10, t2
; RV32I-NEXT: .LBB12_21:
-; RV32I-NEXT: li s4, 0
-; RV32I-NEXT: or t2, s8, s2
+; RV32I-NEXT: li s2, 0
+; RV32I-NEXT: or t2, s8, s4
; RV32I-NEXT: slli s5, s5, 16
; RV32I-NEXT: li s8, 5
; RV32I-NEXT: sll s7, a0, s3
; RV32I-NEXT: beqz t5, .LBB12_23
; RV32I-NEXT: # %bb.22:
-; RV32I-NEXT: mv s4, s7
+; RV32I-NEXT: mv s2, s7
; RV32I-NEXT: .LBB12_23:
; RV32I-NEXT: srl a5, t1, a4
; RV32I-NEXT: or t2, s5, t2
; RV32I-NEXT: beq a7, s8, .LBB12_25
; RV32I-NEXT: # %bb.24:
-; RV32I-NEXT: mv s9, a5
+; RV32I-NEXT: mv s6, a5
; RV32I-NEXT: j .LBB12_26
; RV32I-NEXT: .LBB12_25:
-; RV32I-NEXT: mv s9, a5
-; RV32I-NEXT: or s0, a5, s4
+; RV32I-NEXT: mv s6, a5
+; RV32I-NEXT: or s0, a5, s2
; RV32I-NEXT: .LBB12_26:
; RV32I-NEXT: li s4, 0
; RV32I-NEXT: li a5, 6
@@ -3138,22 +3137,22 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: # %bb.27:
; RV32I-NEXT: mv s4, s5
; RV32I-NEXT: .LBB12_28:
-; RV32I-NEXT: srl s6, a0, a4
+; RV32I-NEXT: srl s3, a0, a4
; RV32I-NEXT: bne a7, a5, .LBB12_30
; RV32I-NEXT: # %bb.29:
-; RV32I-NEXT: or s0, s6, s4
+; RV32I-NEXT: or s0, s3, s4
; RV32I-NEXT: .LBB12_30:
-; RV32I-NEXT: li s3, 7
+; RV32I-NEXT: li a5, 7
; RV32I-NEXT: srl s2, t2, a4
; RV32I-NEXT: mv s4, s2
-; RV32I-NEXT: bne a7, s3, .LBB12_35
+; RV32I-NEXT: bne a7, a5, .LBB12_35
; RV32I-NEXT: # %bb.31:
; RV32I-NEXT: bnez a4, .LBB12_36
; RV32I-NEXT: .LBB12_32:
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: bnez t5, .LBB12_37
; RV32I-NEXT: .LBB12_33:
-; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: li a5, 2
; RV32I-NEXT: beqz a7, .LBB12_38
; RV32I-NEXT: .LBB12_34:
; RV32I-NEXT: li t6, 0
@@ -3162,29 +3161,29 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: mv s4, s0
; RV32I-NEXT: beqz a4, .LBB12_32
; RV32I-NEXT: .LBB12_36:
-; RV32I-NEXT: sw s4, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB12_33
; RV32I-NEXT: .LBB12_37:
; RV32I-NEXT: mv s0, t6
-; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: li a5, 2
; RV32I-NEXT: bnez a7, .LBB12_34
; RV32I-NEXT: .LBB12_38:
; RV32I-NEXT: or t6, s1, s0
; RV32I-NEXT: .LBB12_39:
; RV32I-NEXT: li s1, 1
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB12_59
+; RV32I-NEXT: bnez t5, .LBB12_61
; RV32I-NEXT: # %bb.40:
-; RV32I-NEXT: beq a7, s1, .LBB12_60
+; RV32I-NEXT: beq a7, s1, .LBB12_62
; RV32I-NEXT: .LBB12_41:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB12_61
+; RV32I-NEXT: bnez t5, .LBB12_63
; RV32I-NEXT: .LBB12_42:
-; RV32I-NEXT: beq a7, s4, .LBB12_62
+; RV32I-NEXT: beq a7, a5, .LBB12_64
; RV32I-NEXT: .LBB12_43:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB12_63
+; RV32I-NEXT: bnez t5, .LBB12_65
; RV32I-NEXT: .LBB12_44:
; RV32I-NEXT: li a5, 3
; RV32I-NEXT: bne a7, a5, .LBB12_46
@@ -3193,457 +3192,453 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: .LBB12_46:
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a5, 4
-; RV32I-NEXT: bnez t5, .LBB12_64
+; RV32I-NEXT: bnez t5, .LBB12_66
; RV32I-NEXT: # %bb.47:
-; RV32I-NEXT: beq a7, a5, .LBB12_65
+; RV32I-NEXT: beq a7, a5, .LBB12_67
; RV32I-NEXT: .LBB12_48:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB12_66
+; RV32I-NEXT: bnez t5, .LBB12_68
; RV32I-NEXT: .LBB12_49:
; RV32I-NEXT: bne a7, s8, .LBB12_51
; RV32I-NEXT: .LBB12_50:
-; RV32I-NEXT: or t6, s6, s0
+; RV32I-NEXT: or t6, s3, s0
; RV32I-NEXT: .LBB12_51:
; RV32I-NEXT: mv s0, s2
; RV32I-NEXT: li s8, 6
-; RV32I-NEXT: bne a7, s8, .LBB12_67
+; RV32I-NEXT: beq a7, s8, .LBB12_53
; RV32I-NEXT: # %bb.52:
-; RV32I-NEXT: li t6, 0
-; RV32I-NEXT: bne a7, s3, .LBB12_68
+; RV32I-NEXT: mv s0, t6
; RV32I-NEXT: .LBB12_53:
-; RV32I-NEXT: beqz a4, .LBB12_55
-; RV32I-NEXT: .LBB12_54:
-; RV32I-NEXT: mv a1, t6
+; RV32I-NEXT: li t6, 0
+; RV32I-NEXT: li s4, 7
+; RV32I-NEXT: beq a7, s4, .LBB12_55
+; RV32I-NEXT: # %bb.54:
+; RV32I-NEXT: mv t6, s0
; RV32I-NEXT: .LBB12_55:
+; RV32I-NEXT: beqz a4, .LBB12_57
+; RV32I-NEXT: # %bb.56:
+; RV32I-NEXT: mv a1, t6
+; RV32I-NEXT: .LBB12_57:
; RV32I-NEXT: li t6, 0
; RV32I-NEXT: li s0, 5
-; RV32I-NEXT: beqz t5, .LBB12_57
-; RV32I-NEXT: # %bb.56:
+; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: beqz t5, .LBB12_59
+; RV32I-NEXT: # %bb.58:
; RV32I-NEXT: mv t6, t3
-; RV32I-NEXT: .LBB12_57:
+; RV32I-NEXT: .LBB12_59:
; RV32I-NEXT: beqz a7, .LBB12_69
-; RV32I-NEXT: # %bb.58:
+; RV32I-NEXT: # %bb.60:
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: j .LBB12_70
-; RV32I-NEXT: .LBB12_59:
+; RV32I-NEXT: .LBB12_61:
; RV32I-NEXT: mv s0, t3
; RV32I-NEXT: bne a7, s1, .LBB12_41
-; RV32I-NEXT: .LBB12_60:
+; RV32I-NEXT: .LBB12_62:
; RV32I-NEXT: or t6, t4, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB12_42
-; RV32I-NEXT: .LBB12_61:
+; RV32I-NEXT: .LBB12_63:
; RV32I-NEXT: mv s0, s11
-; RV32I-NEXT: bne a7, s4, .LBB12_43
-; RV32I-NEXT: .LBB12_62:
+; RV32I-NEXT: bne a7, a5, .LBB12_43
+; RV32I-NEXT: .LBB12_64:
; RV32I-NEXT: or t6, ra, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB12_44
-; RV32I-NEXT: .LBB12_63:
-; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .LBB12_65:
+; RV32I-NEXT: mv s0, s9
; RV32I-NEXT: li a5, 3
; RV32I-NEXT: beq a7, a5, .LBB12_45
; RV32I-NEXT: j .LBB12_46
-; RV32I-NEXT: .LBB12_64:
+; RV32I-NEXT: .LBB12_66:
; RV32I-NEXT: mv s0, s7
; RV32I-NEXT: bne a7, a5, .LBB12_48
-; RV32I-NEXT: .LBB12_65:
-; RV32I-NEXT: or t6, s9, s0
+; RV32I-NEXT: .LBB12_67:
+; RV32I-NEXT: or t6, s6, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB12_49
-; RV32I-NEXT: .LBB12_66:
+; RV32I-NEXT: .LBB12_68:
; RV32I-NEXT: mv s0, s5
; RV32I-NEXT: beq a7, s8, .LBB12_50
; RV32I-NEXT: j .LBB12_51
-; RV32I-NEXT: .LBB12_67:
-; RV32I-NEXT: mv s0, t6
-; RV32I-NEXT: li t6, 0
-; RV32I-NEXT: beq a7, s3, .LBB12_53
-; RV32I-NEXT: .LBB12_68:
-; RV32I-NEXT: mv t6, s0
-; RV32I-NEXT: bnez a4, .LBB12_54
-; RV32I-NEXT: j .LBB12_55
; RV32I-NEXT: .LBB12_69:
; RV32I-NEXT: or t3, t4, t6
; RV32I-NEXT: .LBB12_70:
; RV32I-NEXT: li t6, 3
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB12_85
+; RV32I-NEXT: bnez t5, .LBB12_89
; RV32I-NEXT: # %bb.71:
-; RV32I-NEXT: beq a7, s1, .LBB12_86
+; RV32I-NEXT: beq a7, s1, .LBB12_90
; RV32I-NEXT: .LBB12_72:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB12_87
+; RV32I-NEXT: bnez t5, .LBB12_91
; RV32I-NEXT: .LBB12_73:
-; RV32I-NEXT: beq a7, s4, .LBB12_88
+; RV32I-NEXT: beq a7, s4, .LBB12_92
; RV32I-NEXT: .LBB12_74:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB12_89
+; RV32I-NEXT: bnez t5, .LBB12_93
; RV32I-NEXT: .LBB12_75:
-; RV32I-NEXT: beq a7, t6, .LBB12_90
+; RV32I-NEXT: beq a7, t6, .LBB12_94
; RV32I-NEXT: .LBB12_76:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB12_91
+; RV32I-NEXT: bnez t5, .LBB12_95
; RV32I-NEXT: .LBB12_77:
-; RV32I-NEXT: beq a7, a5, .LBB12_92
+; RV32I-NEXT: beq a7, a5, .LBB12_96
; RV32I-NEXT: .LBB12_78:
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, s0, .LBB12_93
+; RV32I-NEXT: bne a7, s0, .LBB12_97
; RV32I-NEXT: .LBB12_79:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s8, .LBB12_94
+; RV32I-NEXT: beq a7, s8, .LBB12_81
; RV32I-NEXT: .LBB12_80:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s3, .LBB12_95
+; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: .LBB12_81:
-; RV32I-NEXT: bnez a4, .LBB12_96
-; RV32I-NEXT: .LBB12_82:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB12_97
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: li s4, 7
+; RV32I-NEXT: beq a7, s4, .LBB12_83
+; RV32I-NEXT: # %bb.82:
+; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: .LBB12_83:
+; RV32I-NEXT: beqz a4, .LBB12_85
+; RV32I-NEXT: # %bb.84:
+; RV32I-NEXT: mv a3, t4
+; RV32I-NEXT: .LBB12_85:
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: beqz t5, .LBB12_87
+; RV32I-NEXT: # %bb.86:
+; RV32I-NEXT: mv t3, s11
+; RV32I-NEXT: .LBB12_87:
; RV32I-NEXT: beqz a7, .LBB12_98
-; RV32I-NEXT: .LBB12_84:
+; RV32I-NEXT: # %bb.88:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB12_99
-; RV32I-NEXT: j .LBB12_100
-; RV32I-NEXT: .LBB12_85:
+; RV32I-NEXT: j .LBB12_99
+; RV32I-NEXT: .LBB12_89:
; RV32I-NEXT: mv t4, s11
; RV32I-NEXT: bne a7, s1, .LBB12_72
-; RV32I-NEXT: .LBB12_86:
+; RV32I-NEXT: .LBB12_90:
; RV32I-NEXT: or t3, ra, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB12_73
-; RV32I-NEXT: .LBB12_87:
-; RV32I-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .LBB12_91:
+; RV32I-NEXT: mv t4, s9
; RV32I-NEXT: bne a7, s4, .LBB12_74
-; RV32I-NEXT: .LBB12_88:
+; RV32I-NEXT: .LBB12_92:
; RV32I-NEXT: or t3, s10, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB12_75
-; RV32I-NEXT: .LBB12_89:
+; RV32I-NEXT: .LBB12_93:
; RV32I-NEXT: mv t4, s7
; RV32I-NEXT: bne a7, t6, .LBB12_76
-; RV32I-NEXT: .LBB12_90:
-; RV32I-NEXT: or t3, s9, t4
+; RV32I-NEXT: .LBB12_94:
+; RV32I-NEXT: or t3, s6, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB12_77
-; RV32I-NEXT: .LBB12_91:
+; RV32I-NEXT: .LBB12_95:
; RV32I-NEXT: mv t4, s5
; RV32I-NEXT: bne a7, a5, .LBB12_78
-; RV32I-NEXT: .LBB12_92:
-; RV32I-NEXT: or t3, s6, t4
+; RV32I-NEXT: .LBB12_96:
+; RV32I-NEXT: or t3, s3, t4
; RV32I-NEXT: mv t4, s2
; RV32I-NEXT: beq a7, s0, .LBB12_79
-; RV32I-NEXT: .LBB12_93:
-; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s8, .LBB12_80
-; RV32I-NEXT: .LBB12_94:
-; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s3, .LBB12_81
-; RV32I-NEXT: .LBB12_95:
+; RV32I-NEXT: .LBB12_97:
; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: beqz a4, .LBB12_82
-; RV32I-NEXT: .LBB12_96:
-; RV32I-NEXT: mv a3, t4
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beqz t5, .LBB12_83
-; RV32I-NEXT: .LBB12_97:
-; RV32I-NEXT: mv t3, s11
-; RV32I-NEXT: bnez a7, .LBB12_84
+; RV32I-NEXT: bne a7, s8, .LBB12_80
+; RV32I-NEXT: j .LBB12_81
; RV32I-NEXT: .LBB12_98:
; RV32I-NEXT: or t3, ra, t3
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB12_100
; RV32I-NEXT: .LBB12_99:
-; RV32I-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: .LBB12_100:
-; RV32I-NEXT: beq a7, s1, .LBB12_113
-; RV32I-NEXT: # %bb.101:
+; RV32I-NEXT: li s11, 7
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB12_114
+; RV32I-NEXT: bnez t5, .LBB12_113
+; RV32I-NEXT: # %bb.100:
+; RV32I-NEXT: beq a7, s1, .LBB12_114
+; RV32I-NEXT: .LBB12_101:
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bnez t5, .LBB12_115
; RV32I-NEXT: .LBB12_102:
-; RV32I-NEXT: beq a7, s4, .LBB12_115
+; RV32I-NEXT: beq a7, s4, .LBB12_116
; RV32I-NEXT: .LBB12_103:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB12_116
+; RV32I-NEXT: bnez t5, .LBB12_117
; RV32I-NEXT: .LBB12_104:
-; RV32I-NEXT: beq a7, t6, .LBB12_117
+; RV32I-NEXT: beq a7, t6, .LBB12_118
; RV32I-NEXT: .LBB12_105:
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, a5, .LBB12_118
+; RV32I-NEXT: bne a7, a5, .LBB12_119
; RV32I-NEXT: .LBB12_106:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s0, .LBB12_119
+; RV32I-NEXT: bne a7, s0, .LBB12_120
; RV32I-NEXT: .LBB12_107:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s8, .LBB12_120
+; RV32I-NEXT: bne a7, s8, .LBB12_121
; RV32I-NEXT: .LBB12_108:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s3, .LBB12_121
+; RV32I-NEXT: bne a7, s11, .LBB12_122
; RV32I-NEXT: .LBB12_109:
-; RV32I-NEXT: bnez a4, .LBB12_122
+; RV32I-NEXT: bnez a4, .LBB12_123
; RV32I-NEXT: .LBB12_110:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB12_123
+; RV32I-NEXT: bnez t5, .LBB12_124
; RV32I-NEXT: .LBB12_111:
-; RV32I-NEXT: beqz a7, .LBB12_124
+; RV32I-NEXT: beqz a7, .LBB12_125
; RV32I-NEXT: .LBB12_112:
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB12_125
-; RV32I-NEXT: j .LBB12_126
+; RV32I-NEXT: bnez t5, .LBB12_126
+; RV32I-NEXT: j .LBB12_127
; RV32I-NEXT: .LBB12_113:
+; RV32I-NEXT: mv t4, s9
+; RV32I-NEXT: bne a7, s1, .LBB12_101
+; RV32I-NEXT: .LBB12_114:
; RV32I-NEXT: or t3, s10, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB12_102
-; RV32I-NEXT: .LBB12_114:
+; RV32I-NEXT: .LBB12_115:
; RV32I-NEXT: mv t4, s7
; RV32I-NEXT: bne a7, s4, .LBB12_103
-; RV32I-NEXT: .LBB12_115:
-; RV32I-NEXT: or t3, s9, t4
+; RV32I-NEXT: .LBB12_116:
+; RV32I-NEXT: or t3, s6, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB12_104
-; RV32I-NEXT: .LBB12_116:
+; RV32I-NEXT: .LBB12_117:
; RV32I-NEXT: mv t4, s5
; RV32I-NEXT: bne a7, t6, .LBB12_105
-; RV32I-NEXT: .LBB12_117:
-; RV32I-NEXT: or t3, s6, t4
+; RV32I-NEXT: .LBB12_118:
+; RV32I-NEXT: or t3, s3, t4
; RV32I-NEXT: mv t4, s2
; RV32I-NEXT: beq a7, a5, .LBB12_106
-; RV32I-NEXT: .LBB12_118:
+; RV32I-NEXT: .LBB12_119:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: beq a7, s0, .LBB12_107
-; RV32I-NEXT: .LBB12_119:
+; RV32I-NEXT: .LBB12_120:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beq a7, s8, .LBB12_108
-; RV32I-NEXT: .LBB12_120:
+; RV32I-NEXT: .LBB12_121:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s3, .LBB12_109
-; RV32I-NEXT: .LBB12_121:
+; RV32I-NEXT: beq a7, s11, .LBB12_109
+; RV32I-NEXT: .LBB12_122:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: beqz a4, .LBB12_110
-; RV32I-NEXT: .LBB12_122:
+; RV32I-NEXT: .LBB12_123:
; RV32I-NEXT: mv a6, t3
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: beqz t5, .LBB12_111
-; RV32I-NEXT: .LBB12_123:
-; RV32I-NEXT: lw t3, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bnez a7, .LBB12_112
; RV32I-NEXT: .LBB12_124:
+; RV32I-NEXT: mv t3, s9
+; RV32I-NEXT: bnez a7, .LBB12_112
+; RV32I-NEXT: .LBB12_125:
; RV32I-NEXT: or t3, s10, t3
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB12_126
-; RV32I-NEXT: .LBB12_125:
-; RV32I-NEXT: mv t4, s7
+; RV32I-NEXT: beqz t5, .LBB12_127
; RV32I-NEXT: .LBB12_126:
-; RV32I-NEXT: beq a7, s1, .LBB12_138
-; RV32I-NEXT: # %bb.127:
+; RV32I-NEXT: mv t4, s7
+; RV32I-NEXT: .LBB12_127:
+; RV32I-NEXT: beq a7, s1, .LBB12_139
+; RV32I-NEXT: # %bb.128:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB12_139
-; RV32I-NEXT: .LBB12_128:
-; RV32I-NEXT: beq a7, s4, .LBB12_140
+; RV32I-NEXT: bnez t5, .LBB12_140
; RV32I-NEXT: .LBB12_129:
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, t6, .LBB12_141
+; RV32I-NEXT: beq a7, s4, .LBB12_141
; RV32I-NEXT: .LBB12_130:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, a5, .LBB12_142
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: bne a7, t6, .LBB12_142
; RV32I-NEXT: .LBB12_131:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s0, .LBB12_143
-; RV32I-NEXT: .LBB12_132:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s8, .LBB12_144
-; RV32I-NEXT: .LBB12_133:
+; RV32I-NEXT: bne a7, a5, .LBB12_143
+; RV32I-NEXT: .LBB12_132:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s3, .LBB12_145
+; RV32I-NEXT: bne a7, s0, .LBB12_144
+; RV32I-NEXT: .LBB12_133:
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s8, .LBB12_145
; RV32I-NEXT: .LBB12_134:
-; RV32I-NEXT: bnez a4, .LBB12_146
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s11, .LBB12_146
; RV32I-NEXT: .LBB12_135:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB12_147
+; RV32I-NEXT: bnez a4, .LBB12_147
; RV32I-NEXT: .LBB12_136:
-; RV32I-NEXT: beqz a7, .LBB12_148
-; RV32I-NEXT: .LBB12_137:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB12_149
-; RV32I-NEXT: j .LBB12_150
+; RV32I-NEXT: bnez t5, .LBB12_148
+; RV32I-NEXT: .LBB12_137:
+; RV32I-NEXT: beqz a7, .LBB12_149
; RV32I-NEXT: .LBB12_138:
-; RV32I-NEXT: or t3, s9, t4
+; RV32I-NEXT: li t3, 0
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB12_128
+; RV32I-NEXT: bnez t5, .LBB12_150
+; RV32I-NEXT: j .LBB12_151
; RV32I-NEXT: .LBB12_139:
-; RV32I-NEXT: mv t4, s5
-; RV32I-NEXT: bne a7, s4, .LBB12_129
-; RV32I-NEXT: .LBB12_140:
; RV32I-NEXT: or t3, s6, t4
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: beq a7, t6, .LBB12_130
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: beqz t5, .LBB12_129
+; RV32I-NEXT: .LBB12_140:
+; RV32I-NEXT: mv t4, s5
+; RV32I-NEXT: bne a7, s4, .LBB12_130
; RV32I-NEXT: .LBB12_141:
+; RV32I-NEXT: or t3, s3, t4
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: beq a7, t6, .LBB12_131
+; RV32I-NEXT: .LBB12_142:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, a5, .LBB12_131
-; RV32I-NEXT: .LBB12_142:
+; RV32I-NEXT: beq a7, a5, .LBB12_132
+; RV32I-NEXT: .LBB12_143:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s0, .LBB12_132
-; RV32I-NEXT: .LBB12_143:
+; RV32I-NEXT: beq a7, s0, .LBB12_133
+; RV32I-NEXT: .LBB12_144:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s8, .LBB12_133
-; RV32I-NEXT: .LBB12_144:
+; RV32I-NEXT: beq a7, s8, .LBB12_134
+; RV32I-NEXT: .LBB12_145:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s3, .LBB12_134
-; RV32I-NEXT: .LBB12_145:
-; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: beqz a4, .LBB12_135
+; RV32I-NEXT: beq a7, s11, .LBB12_135
; RV32I-NEXT: .LBB12_146:
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: beqz a4, .LBB12_136
+; RV32I-NEXT: .LBB12_147:
; RV32I-NEXT: mv t0, t4
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beqz t5, .LBB12_136
-; RV32I-NEXT: .LBB12_147:
-; RV32I-NEXT: mv t3, s7
-; RV32I-NEXT: bnez a7, .LBB12_137
+; RV32I-NEXT: beqz t5, .LBB12_137
; RV32I-NEXT: .LBB12_148:
-; RV32I-NEXT: or t3, s9, t3
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB12_150
+; RV32I-NEXT: mv t3, s7
+; RV32I-NEXT: bnez a7, .LBB12_138
; RV32I-NEXT: .LBB12_149:
-; RV32I-NEXT: mv t4, s5
+; RV32I-NEXT: or t3, s6, t3
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: beqz t5, .LBB12_151
; RV32I-NEXT: .LBB12_150:
-; RV32I-NEXT: beq a7, s1, .LBB12_161
-; RV32I-NEXT: # %bb.151:
+; RV32I-NEXT: mv t4, s5
+; RV32I-NEXT: .LBB12_151:
+; RV32I-NEXT: beq a7, s1, .LBB12_162
+; RV32I-NEXT: # %bb.152:
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, s4, .LBB12_162
-; RV32I-NEXT: .LBB12_152:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, t6, .LBB12_163
+; RV32I-NEXT: bne a7, s4, .LBB12_163
; RV32I-NEXT: .LBB12_153:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, a5, .LBB12_164
-; RV32I-NEXT: .LBB12_154:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s0, .LBB12_165
-; RV32I-NEXT: .LBB12_155:
+; RV32I-NEXT: bne a7, t6, .LBB12_164
+; RV32I-NEXT: .LBB12_154:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s8, .LBB12_166
-; RV32I-NEXT: .LBB12_156:
+; RV32I-NEXT: bne a7, a5, .LBB12_165
+; RV32I-NEXT: .LBB12_155:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s3, .LBB12_167
+; RV32I-NEXT: bne a7, s0, .LBB12_166
+; RV32I-NEXT: .LBB12_156:
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s8, .LBB12_167
; RV32I-NEXT: .LBB12_157:
-; RV32I-NEXT: bnez a4, .LBB12_168
-; RV32I-NEXT: .LBB12_158:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB12_169
+; RV32I-NEXT: bne a7, s11, .LBB12_168
+; RV32I-NEXT: .LBB12_158:
+; RV32I-NEXT: bnez a4, .LBB12_169
; RV32I-NEXT: .LBB12_159:
-; RV32I-NEXT: beqz a7, .LBB12_170
-; RV32I-NEXT: .LBB12_160:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, s1, .LBB12_171
-; RV32I-NEXT: j .LBB12_172
+; RV32I-NEXT: bnez t5, .LBB12_170
+; RV32I-NEXT: .LBB12_160:
+; RV32I-NEXT: beqz a7, .LBB12_171
; RV32I-NEXT: .LBB12_161:
-; RV32I-NEXT: or t3, s6, t4
+; RV32I-NEXT: li t3, 0
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: beq a7, s4, .LBB12_152
+; RV32I-NEXT: bne a7, s1, .LBB12_172
+; RV32I-NEXT: j .LBB12_173
; RV32I-NEXT: .LBB12_162:
+; RV32I-NEXT: or t3, s3, t4
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: beq a7, s4, .LBB12_153
+; RV32I-NEXT: .LBB12_163:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, t6, .LBB12_153
-; RV32I-NEXT: .LBB12_163:
+; RV32I-NEXT: beq a7, t6, .LBB12_154
+; RV32I-NEXT: .LBB12_164:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, a5, .LBB12_154
-; RV32I-NEXT: .LBB12_164:
+; RV32I-NEXT: beq a7, a5, .LBB12_155
+; RV32I-NEXT: .LBB12_165:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s0, .LBB12_155
-; RV32I-NEXT: .LBB12_165:
+; RV32I-NEXT: beq a7, s0, .LBB12_156
+; RV32I-NEXT: .LBB12_166:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s8, .LBB12_156
-; RV32I-NEXT: .LBB12_166:
+; RV32I-NEXT: beq a7, s8, .LBB12_157
+; RV32I-NEXT: .LBB12_167:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s3, .LBB12_157
-; RV32I-NEXT: .LBB12_167:
-; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: beqz a4, .LBB12_158
+; RV32I-NEXT: beq a7, s11, .LBB12_158
; RV32I-NEXT: .LBB12_168:
+; RV32I-NEXT: mv t3, t4
+; RV32I-NEXT: beqz a4, .LBB12_159
+; RV32I-NEXT: .LBB12_169:
; RV32I-NEXT: mv t1, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beqz t5, .LBB12_159
-; RV32I-NEXT: .LBB12_169:
-; RV32I-NEXT: mv t3, s5
-; RV32I-NEXT: bnez a7, .LBB12_160
+; RV32I-NEXT: beqz t5, .LBB12_160
; RV32I-NEXT: .LBB12_170:
-; RV32I-NEXT: or t3, s6, t3
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: beq a7, s1, .LBB12_172
+; RV32I-NEXT: mv t3, s5
+; RV32I-NEXT: bnez a7, .LBB12_161
; RV32I-NEXT: .LBB12_171:
-; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: or t3, s3, t3
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: beq a7, s1, .LBB12_173
; RV32I-NEXT: .LBB12_172:
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: .LBB12_173:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s4, .LBB12_192
-; RV32I-NEXT: # %bb.173:
+; RV32I-NEXT: bne a7, s4, .LBB12_193
+; RV32I-NEXT: # %bb.174:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, t6, .LBB12_193
-; RV32I-NEXT: .LBB12_174:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, a5, .LBB12_194
+; RV32I-NEXT: bne a7, t6, .LBB12_194
; RV32I-NEXT: .LBB12_175:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s0, .LBB12_195
-; RV32I-NEXT: .LBB12_176:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s8, .LBB12_196
-; RV32I-NEXT: .LBB12_177:
+; RV32I-NEXT: bne a7, a5, .LBB12_195
+; RV32I-NEXT: .LBB12_176:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s3, .LBB12_197
+; RV32I-NEXT: bne a7, s0, .LBB12_196
+; RV32I-NEXT: .LBB12_177:
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s8, .LBB12_197
; RV32I-NEXT: .LBB12_178:
-; RV32I-NEXT: bnez a4, .LBB12_198
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s11, .LBB12_198
; RV32I-NEXT: .LBB12_179:
-; RV32I-NEXT: bnez a7, .LBB12_199
+; RV32I-NEXT: bnez a4, .LBB12_199
; RV32I-NEXT: .LBB12_180:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s1, .LBB12_200
+; RV32I-NEXT: bnez a7, .LBB12_200
; RV32I-NEXT: .LBB12_181:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s4, .LBB12_183
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s1, .LBB12_201
; RV32I-NEXT: .LBB12_182:
-; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: beq a7, s4, .LBB12_184
; RV32I-NEXT: .LBB12_183:
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: .LBB12_184:
; RV32I-NEXT: li t5, 4
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, t6, .LBB12_185
-; RV32I-NEXT: # %bb.184:
+; RV32I-NEXT: beq a7, t6, .LBB12_186
+; RV32I-NEXT: # %bb.185:
; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: .LBB12_185:
+; RV32I-NEXT: .LBB12_186:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: lw a5, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne a7, t5, .LBB12_201
-; RV32I-NEXT: # %bb.186:
+; RV32I-NEXT: lw a5, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: bne a7, t5, .LBB12_202
+; RV32I-NEXT: # %bb.187:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s0, .LBB12_202
-; RV32I-NEXT: .LBB12_187:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s8, .LBB12_203
+; RV32I-NEXT: bne a7, s0, .LBB12_203
; RV32I-NEXT: .LBB12_188:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s3, .LBB12_204
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s8, .LBB12_204
; RV32I-NEXT: .LBB12_189:
-; RV32I-NEXT: beqz a4, .LBB12_191
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s11, .LBB12_205
; RV32I-NEXT: .LBB12_190:
-; RV32I-NEXT: mv t2, t3
+; RV32I-NEXT: beqz a4, .LBB12_192
; RV32I-NEXT: .LBB12_191:
+; RV32I-NEXT: mv t2, t3
+; RV32I-NEXT: .LBB12_192:
; RV32I-NEXT: lui a4, 16
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: srli a7, a5, 16
@@ -3725,57 +3720,57 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB12_192:
+; RV32I-NEXT: .LBB12_193:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, t6, .LBB12_174
-; RV32I-NEXT: .LBB12_193:
+; RV32I-NEXT: beq a7, t6, .LBB12_175
+; RV32I-NEXT: .LBB12_194:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, a5, .LBB12_175
-; RV32I-NEXT: .LBB12_194:
+; RV32I-NEXT: beq a7, a5, .LBB12_176
+; RV32I-NEXT: .LBB12_195:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s0, .LBB12_176
-; RV32I-NEXT: .LBB12_195:
+; RV32I-NEXT: beq a7, s0, .LBB12_177
+; RV32I-NEXT: .LBB12_196:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s8, .LBB12_177
-; RV32I-NEXT: .LBB12_196:
+; RV32I-NEXT: beq a7, s8, .LBB12_178
+; RV32I-NEXT: .LBB12_197:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s3, .LBB12_178
-; RV32I-NEXT: .LBB12_197:
-; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: beqz a4, .LBB12_179
+; RV32I-NEXT: beq a7, s11, .LBB12_179
; RV32I-NEXT: .LBB12_198:
-; RV32I-NEXT: mv a0, t4
-; RV32I-NEXT: beqz a7, .LBB12_180
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: beqz a4, .LBB12_180
; RV32I-NEXT: .LBB12_199:
+; RV32I-NEXT: mv a0, t4
+; RV32I-NEXT: beqz a7, .LBB12_181
+; RV32I-NEXT: .LBB12_200:
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s1, .LBB12_181
-; RV32I-NEXT: .LBB12_200:
+; RV32I-NEXT: beq a7, s1, .LBB12_182
+; RV32I-NEXT: .LBB12_201:
; RV32I-NEXT: mv t3, s2
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s4, .LBB12_182
-; RV32I-NEXT: j .LBB12_183
-; RV32I-NEXT: .LBB12_201:
+; RV32I-NEXT: bne a7, s4, .LBB12_183
+; RV32I-NEXT: j .LBB12_184
+; RV32I-NEXT: .LBB12_202:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s0, .LBB12_187
-; RV32I-NEXT: .LBB12_202:
+; RV32I-NEXT: beq a7, s0, .LBB12_188
+; RV32I-NEXT: .LBB12_203:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s8, .LBB12_188
-; RV32I-NEXT: .LBB12_203:
+; RV32I-NEXT: beq a7, s8, .LBB12_189
+; RV32I-NEXT: .LBB12_204:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s3, .LBB12_189
-; RV32I-NEXT: .LBB12_204:
+; RV32I-NEXT: beq a7, s11, .LBB12_190
+; RV32I-NEXT: .LBB12_205:
; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: bnez a4, .LBB12_190
-; RV32I-NEXT: j .LBB12_191
+; RV32I-NEXT: bnez a4, .LBB12_191
+; RV32I-NEXT: j .LBB12_192
%src = load i256, ptr %src.ptr, align 1
%byteOff = load i256, ptr %byteOff.ptr, align 1
%bitOff = shl i256 %byteOff, 3
@@ -3900,15 +3895,15 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV64I-NEXT: slli a6, a6, 5
; RV64I-NEXT: li t1, 64
; RV64I-NEXT: neg t3, a6
-; RV64I-NEXT: sub t5, a6, t1
-; RV64I-NEXT: sll t4, t0, t3
+; RV64I-NEXT: sub t4, a6, t1
+; RV64I-NEXT: sll t5, t0, t3
; RV64I-NEXT: bltu a6, t1, .LBB13_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: srl t6, t0, t5
+; RV64I-NEXT: srl t6, t0, t4
; RV64I-NEXT: j .LBB13_3
; RV64I-NEXT: .LBB13_2:
; RV64I-NEXT: srl t6, a3, a6
-; RV64I-NEXT: or t6, t6, t4
+; RV64I-NEXT: or t6, t6, t5
; RV64I-NEXT: .LBB13_3:
; RV64I-NEXT: or a4, a1, a4
; RV64I-NEXT: slli a5, a5, 32
@@ -3924,44 +3919,44 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV64I-NEXT: bltu a6, t1, .LBB13_7
; RV64I-NEXT: # %bb.6:
; RV64I-NEXT: li a0, 0
-; RV64I-NEXT: srl t5, a4, t5
+; RV64I-NEXT: srl t4, a4, t4
; RV64I-NEXT: j .LBB13_8
; RV64I-NEXT: .LBB13_7:
; RV64I-NEXT: srl a7, a5, a6
; RV64I-NEXT: sll t2, a4, t3
; RV64I-NEXT: srl a0, t0, a6
-; RV64I-NEXT: or t5, a7, t2
+; RV64I-NEXT: or t4, a7, t2
; RV64I-NEXT: .LBB13_8:
; RV64I-NEXT: li a7, 128
; RV64I-NEXT: mv t2, a5
; RV64I-NEXT: beqz a6, .LBB13_10
; RV64I-NEXT: # %bb.9:
-; RV64I-NEXT: mv t2, t5
+; RV64I-NEXT: mv t2, t4
; RV64I-NEXT: .LBB13_10:
; RV64I-NEXT: sub t6, a7, a6
; RV64I-NEXT: bltu a6, t1, .LBB13_13
; RV64I-NEXT: # %bb.11:
-; RV64I-NEXT: li t5, 0
+; RV64I-NEXT: li t4, 0
; RV64I-NEXT: bgeu t6, t1, .LBB13_14
; RV64I-NEXT: .LBB13_12:
; RV64I-NEXT: neg s0, t6
; RV64I-NEXT: srl s0, a3, s0
; RV64I-NEXT: sll t3, a3, t3
-; RV64I-NEXT: or s1, s0, t4
+; RV64I-NEXT: or s1, s0, t5
; RV64I-NEXT: j .LBB13_15
; RV64I-NEXT: .LBB13_13:
-; RV64I-NEXT: srl t5, a4, a6
+; RV64I-NEXT: srl t4, a4, a6
; RV64I-NEXT: bltu t6, t1, .LBB13_12
; RV64I-NEXT: .LBB13_14:
; RV64I-NEXT: li t3, 0
-; RV64I-NEXT: sub t4, t6, t1
-; RV64I-NEXT: sll s1, a3, t4
+; RV64I-NEXT: sub t5, t6, t1
+; RV64I-NEXT: sll s1, a3, t5
; RV64I-NEXT: .LBB13_15:
; RV64I-NEXT: sub s0, a6, a7
-; RV64I-NEXT: mv t4, t0
+; RV64I-NEXT: mv t5, t0
; RV64I-NEXT: beqz t6, .LBB13_17
; RV64I-NEXT: # %bb.16:
-; RV64I-NEXT: mv t4, s1
+; RV64I-NEXT: mv t5, s1
; RV64I-NEXT: .LBB13_17:
; RV64I-NEXT: bltu s0, t1, .LBB13_19
; RV64I-NEXT: # %bb.18:
@@ -3988,7 +3983,7 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV64I-NEXT: bgeu a6, a7, .LBB13_25
; RV64I-NEXT: .LBB13_24:
; RV64I-NEXT: or a3, t2, t3
-; RV64I-NEXT: or t0, t5, t4
+; RV64I-NEXT: or t0, t4, t5
; RV64I-NEXT: .LBB13_25:
; RV64I-NEXT: bnez a6, .LBB13_29
; RV64I-NEXT: # %bb.26:
@@ -4153,7 +4148,7 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: slli t2, t2, 8
; RV32I-NEXT: or t1, s0, t1
; RV32I-NEXT: or a3, t3, t0
-; RV32I-NEXT: sw a5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a7, .LBB13_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: li s0, 0
@@ -4232,42 +4227,41 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: lbu s8, 29(a0)
; RV32I-NEXT: lbu s7, 30(a0)
; RV32I-NEXT: slli s10, s4, 8
-; RV32I-NEXT: or s4, s6, s2
+; RV32I-NEXT: or s2, s6, s2
; RV32I-NEXT: slli s6, s5, 16
; RV32I-NEXT: li a5, 4
-; RV32I-NEXT: sll s2, t1, s3
-; RV32I-NEXT: sw s2, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sll s9, t1, s3
; RV32I-NEXT: beqz t5, .LBB13_19
; RV32I-NEXT: # %bb.18:
-; RV32I-NEXT: lw t2, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: mv t2, s9
; RV32I-NEXT: .LBB13_19:
-; RV32I-NEXT: lbu s2, 28(a0)
+; RV32I-NEXT: lbu s4, 28(a0)
; RV32I-NEXT: slli s8, s8, 8
; RV32I-NEXT: or s5, s10, s7
; RV32I-NEXT: srl s10, t0, a4
-; RV32I-NEXT: or a0, s6, s4
+; RV32I-NEXT: or a0, s6, s2
; RV32I-NEXT: bne a7, a5, .LBB13_21
; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: or s0, s10, t2
; RV32I-NEXT: .LBB13_21:
-; RV32I-NEXT: li s4, 0
-; RV32I-NEXT: or t2, s8, s2
+; RV32I-NEXT: li s2, 0
+; RV32I-NEXT: or t2, s8, s4
; RV32I-NEXT: slli s5, s5, 16
; RV32I-NEXT: li s8, 5
; RV32I-NEXT: sll s7, a0, s3
; RV32I-NEXT: beqz t5, .LBB13_23
; RV32I-NEXT: # %bb.22:
-; RV32I-NEXT: mv s4, s7
+; RV32I-NEXT: mv s2, s7
; RV32I-NEXT: .LBB13_23:
; RV32I-NEXT: srl a5, t1, a4
; RV32I-NEXT: or t2, s5, t2
; RV32I-NEXT: beq a7, s8, .LBB13_25
; RV32I-NEXT: # %bb.24:
-; RV32I-NEXT: mv s9, a5
+; RV32I-NEXT: mv s6, a5
; RV32I-NEXT: j .LBB13_26
; RV32I-NEXT: .LBB13_25:
-; RV32I-NEXT: mv s9, a5
-; RV32I-NEXT: or s0, a5, s4
+; RV32I-NEXT: mv s6, a5
+; RV32I-NEXT: or s0, a5, s2
; RV32I-NEXT: .LBB13_26:
; RV32I-NEXT: li s4, 0
; RV32I-NEXT: li a5, 6
@@ -4276,22 +4270,22 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: # %bb.27:
; RV32I-NEXT: mv s4, s5
; RV32I-NEXT: .LBB13_28:
-; RV32I-NEXT: srl s6, a0, a4
+; RV32I-NEXT: srl s3, a0, a4
; RV32I-NEXT: bne a7, a5, .LBB13_30
; RV32I-NEXT: # %bb.29:
-; RV32I-NEXT: or s0, s6, s4
+; RV32I-NEXT: or s0, s3, s4
; RV32I-NEXT: .LBB13_30:
-; RV32I-NEXT: li s3, 7
+; RV32I-NEXT: li a5, 7
; RV32I-NEXT: srl s2, t2, a4
; RV32I-NEXT: mv s4, s2
-; RV32I-NEXT: bne a7, s3, .LBB13_35
+; RV32I-NEXT: bne a7, a5, .LBB13_35
; RV32I-NEXT: # %bb.31:
; RV32I-NEXT: bnez a4, .LBB13_36
; RV32I-NEXT: .LBB13_32:
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: bnez t5, .LBB13_37
; RV32I-NEXT: .LBB13_33:
-; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: li a5, 2
; RV32I-NEXT: beqz a7, .LBB13_38
; RV32I-NEXT: .LBB13_34:
; RV32I-NEXT: li t6, 0
@@ -4300,29 +4294,29 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: mv s4, s0
; RV32I-NEXT: beqz a4, .LBB13_32
; RV32I-NEXT: .LBB13_36:
-; RV32I-NEXT: sw s4, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB13_33
; RV32I-NEXT: .LBB13_37:
; RV32I-NEXT: mv s0, t6
-; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: li a5, 2
; RV32I-NEXT: bnez a7, .LBB13_34
; RV32I-NEXT: .LBB13_38:
; RV32I-NEXT: or t6, s1, s0
; RV32I-NEXT: .LBB13_39:
; RV32I-NEXT: li s1, 1
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB13_59
+; RV32I-NEXT: bnez t5, .LBB13_61
; RV32I-NEXT: # %bb.40:
-; RV32I-NEXT: beq a7, s1, .LBB13_60
+; RV32I-NEXT: beq a7, s1, .LBB13_62
; RV32I-NEXT: .LBB13_41:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB13_61
+; RV32I-NEXT: bnez t5, .LBB13_63
; RV32I-NEXT: .LBB13_42:
-; RV32I-NEXT: beq a7, s4, .LBB13_62
+; RV32I-NEXT: beq a7, a5, .LBB13_64
; RV32I-NEXT: .LBB13_43:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB13_63
+; RV32I-NEXT: bnez t5, .LBB13_65
; RV32I-NEXT: .LBB13_44:
; RV32I-NEXT: li a5, 3
; RV32I-NEXT: bne a7, a5, .LBB13_46
@@ -4331,457 +4325,453 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: .LBB13_46:
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a5, 4
-; RV32I-NEXT: bnez t5, .LBB13_64
+; RV32I-NEXT: bnez t5, .LBB13_66
; RV32I-NEXT: # %bb.47:
-; RV32I-NEXT: beq a7, a5, .LBB13_65
+; RV32I-NEXT: beq a7, a5, .LBB13_67
; RV32I-NEXT: .LBB13_48:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB13_66
+; RV32I-NEXT: bnez t5, .LBB13_68
; RV32I-NEXT: .LBB13_49:
; RV32I-NEXT: bne a7, s8, .LBB13_51
; RV32I-NEXT: .LBB13_50:
-; RV32I-NEXT: or t6, s6, s0
+; RV32I-NEXT: or t6, s3, s0
; RV32I-NEXT: .LBB13_51:
; RV32I-NEXT: mv s0, s2
; RV32I-NEXT: li s8, 6
-; RV32I-NEXT: bne a7, s8, .LBB13_67
+; RV32I-NEXT: beq a7, s8, .LBB13_53
; RV32I-NEXT: # %bb.52:
-; RV32I-NEXT: li t6, 0
-; RV32I-NEXT: bne a7, s3, .LBB13_68
+; RV32I-NEXT: mv s0, t6
; RV32I-NEXT: .LBB13_53:
-; RV32I-NEXT: beqz a4, .LBB13_55
-; RV32I-NEXT: .LBB13_54:
-; RV32I-NEXT: mv a1, t6
+; RV32I-NEXT: li t6, 0
+; RV32I-NEXT: li s4, 7
+; RV32I-NEXT: beq a7, s4, .LBB13_55
+; RV32I-NEXT: # %bb.54:
+; RV32I-NEXT: mv t6, s0
; RV32I-NEXT: .LBB13_55:
+; RV32I-NEXT: beqz a4, .LBB13_57
+; RV32I-NEXT: # %bb.56:
+; RV32I-NEXT: mv a1, t6
+; RV32I-NEXT: .LBB13_57:
; RV32I-NEXT: li t6, 0
; RV32I-NEXT: li s0, 5
-; RV32I-NEXT: beqz t5, .LBB13_57
-; RV32I-NEXT: # %bb.56:
+; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: beqz t5, .LBB13_59
+; RV32I-NEXT: # %bb.58:
; RV32I-NEXT: mv t6, t3
-; RV32I-NEXT: .LBB13_57:
+; RV32I-NEXT: .LBB13_59:
; RV32I-NEXT: beqz a7, .LBB13_69
-; RV32I-NEXT: # %bb.58:
+; RV32I-NEXT: # %bb.60:
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: j .LBB13_70
-; RV32I-NEXT: .LBB13_59:
+; RV32I-NEXT: .LBB13_61:
; RV32I-NEXT: mv s0, t3
; RV32I-NEXT: bne a7, s1, .LBB13_41
-; RV32I-NEXT: .LBB13_60:
+; RV32I-NEXT: .LBB13_62:
; RV32I-NEXT: or t6, t4, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB13_42
-; RV32I-NEXT: .LBB13_61:
+; RV32I-NEXT: .LBB13_63:
; RV32I-NEXT: mv s0, s11
-; RV32I-NEXT: bne a7, s4, .LBB13_43
-; RV32I-NEXT: .LBB13_62:
+; RV32I-NEXT: bne a7, a5, .LBB13_43
+; RV32I-NEXT: .LBB13_64:
; RV32I-NEXT: or t6, ra, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB13_44
-; RV32I-NEXT: .LBB13_63:
-; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .LBB13_65:
+; RV32I-NEXT: mv s0, s9
; RV32I-NEXT: li a5, 3
; RV32I-NEXT: beq a7, a5, .LBB13_45
; RV32I-NEXT: j .LBB13_46
-; RV32I-NEXT: .LBB13_64:
+; RV32I-NEXT: .LBB13_66:
; RV32I-NEXT: mv s0, s7
; RV32I-NEXT: bne a7, a5, .LBB13_48
-; RV32I-NEXT: .LBB13_65:
-; RV32I-NEXT: or t6, s9, s0
+; RV32I-NEXT: .LBB13_67:
+; RV32I-NEXT: or t6, s6, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB13_49
-; RV32I-NEXT: .LBB13_66:
+; RV32I-NEXT: .LBB13_68:
; RV32I-NEXT: mv s0, s5
; RV32I-NEXT: beq a7, s8, .LBB13_50
; RV32I-NEXT: j .LBB13_51
-; RV32I-NEXT: .LBB13_67:
-; RV32I-NEXT: mv s0, t6
-; RV32I-NEXT: li t6, 0
-; RV32I-NEXT: beq a7, s3, .LBB13_53
-; RV32I-NEXT: .LBB13_68:
-; RV32I-NEXT: mv t6, s0
-; RV32I-NEXT: bnez a4, .LBB13_54
-; RV32I-NEXT: j .LBB13_55
; RV32I-NEXT: .LBB13_69:
; RV32I-NEXT: or t3, t4, t6
; RV32I-NEXT: .LBB13_70:
; RV32I-NEXT: li t6, 3
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB13_85
+; RV32I-NEXT: bnez t5, .LBB13_89
; RV32I-NEXT: # %bb.71:
-; RV32I-NEXT: beq a7, s1, .LBB13_86
+; RV32I-NEXT: beq a7, s1, .LBB13_90
; RV32I-NEXT: .LBB13_72:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB13_87
+; RV32I-NEXT: bnez t5, .LBB13_91
; RV32I-NEXT: .LBB13_73:
-; RV32I-NEXT: beq a7, s4, .LBB13_88
+; RV32I-NEXT: beq a7, s4, .LBB13_92
; RV32I-NEXT: .LBB13_74:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB13_89
+; RV32I-NEXT: bnez t5, .LBB13_93
; RV32I-NEXT: .LBB13_75:
-; RV32I-NEXT: beq a7, t6, .LBB13_90
+; RV32I-NEXT: beq a7, t6, .LBB13_94
; RV32I-NEXT: .LBB13_76:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB13_91
+; RV32I-NEXT: bnez t5, .LBB13_95
; RV32I-NEXT: .LBB13_77:
-; RV32I-NEXT: beq a7, a5, .LBB13_92
+; RV32I-NEXT: beq a7, a5, .LBB13_96
; RV32I-NEXT: .LBB13_78:
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, s0, .LBB13_93
+; RV32I-NEXT: bne a7, s0, .LBB13_97
; RV32I-NEXT: .LBB13_79:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s8, .LBB13_94
+; RV32I-NEXT: beq a7, s8, .LBB13_81
; RV32I-NEXT: .LBB13_80:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s3, .LBB13_95
+; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: .LBB13_81:
-; RV32I-NEXT: bnez a4, .LBB13_96
-; RV32I-NEXT: .LBB13_82:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB13_97
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: li s4, 7
+; RV32I-NEXT: beq a7, s4, .LBB13_83
+; RV32I-NEXT: # %bb.82:
+; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: .LBB13_83:
+; RV32I-NEXT: beqz a4, .LBB13_85
+; RV32I-NEXT: # %bb.84:
+; RV32I-NEXT: mv a3, t4
+; RV32I-NEXT: .LBB13_85:
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: beqz t5, .LBB13_87
+; RV32I-NEXT: # %bb.86:
+; RV32I-NEXT: mv t3, s11
+; RV32I-NEXT: .LBB13_87:
; RV32I-NEXT: beqz a7, .LBB13_98
-; RV32I-NEXT: .LBB13_84:
+; RV32I-NEXT: # %bb.88:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB13_99
-; RV32I-NEXT: j .LBB13_100
-; RV32I-NEXT: .LBB13_85:
+; RV32I-NEXT: j .LBB13_99
+; RV32I-NEXT: .LBB13_89:
; RV32I-NEXT: mv t4, s11
; RV32I-NEXT: bne a7, s1, .LBB13_72
-; RV32I-NEXT: .LBB13_86:
+; RV32I-NEXT: .LBB13_90:
; RV32I-NEXT: or t3, ra, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB13_73
-; RV32I-NEXT: .LBB13_87:
-; RV32I-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .LBB13_91:
+; RV32I-NEXT: mv t4, s9
; RV32I-NEXT: bne a7, s4, .LBB13_74
-; RV32I-NEXT: .LBB13_88:
+; RV32I-NEXT: .LBB13_92:
; RV32I-NEXT: or t3, s10, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB13_75
-; RV32I-NEXT: .LBB13_89:
+; RV32I-NEXT: .LBB13_93:
; RV32I-NEXT: mv t4, s7
; RV32I-NEXT: bne a7, t6, .LBB13_76
-; RV32I-NEXT: .LBB13_90:
-; RV32I-NEXT: or t3, s9, t4
+; RV32I-NEXT: .LBB13_94:
+; RV32I-NEXT: or t3, s6, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB13_77
-; RV32I-NEXT: .LBB13_91:
+; RV32I-NEXT: .LBB13_95:
; RV32I-NEXT: mv t4, s5
; RV32I-NEXT: bne a7, a5, .LBB13_78
-; RV32I-NEXT: .LBB13_92:
-; RV32I-NEXT: or t3, s6, t4
+; RV32I-NEXT: .LBB13_96:
+; RV32I-NEXT: or t3, s3, t4
; RV32I-NEXT: mv t4, s2
; RV32I-NEXT: beq a7, s0, .LBB13_79
-; RV32I-NEXT: .LBB13_93:
-; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s8, .LBB13_80
-; RV32I-NEXT: .LBB13_94:
-; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s3, .LBB13_81
-; RV32I-NEXT: .LBB13_95:
+; RV32I-NEXT: .LBB13_97:
; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: beqz a4, .LBB13_82
-; RV32I-NEXT: .LBB13_96:
-; RV32I-NEXT: mv a3, t4
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beqz t5, .LBB13_83
-; RV32I-NEXT: .LBB13_97:
-; RV32I-NEXT: mv t3, s11
-; RV32I-NEXT: bnez a7, .LBB13_84
+; RV32I-NEXT: bne a7, s8, .LBB13_80
+; RV32I-NEXT: j .LBB13_81
; RV32I-NEXT: .LBB13_98:
; RV32I-NEXT: or t3, ra, t3
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB13_100
; RV32I-NEXT: .LBB13_99:
-; RV32I-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: .LBB13_100:
-; RV32I-NEXT: beq a7, s1, .LBB13_113
-; RV32I-NEXT: # %bb.101:
+; RV32I-NEXT: li s11, 7
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB13_114
+; RV32I-NEXT: bnez t5, .LBB13_113
+; RV32I-NEXT: # %bb.100:
+; RV32I-NEXT: beq a7, s1, .LBB13_114
+; RV32I-NEXT: .LBB13_101:
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bnez t5, .LBB13_115
; RV32I-NEXT: .LBB13_102:
-; RV32I-NEXT: beq a7, s4, .LBB13_115
+; RV32I-NEXT: beq a7, s4, .LBB13_116
; RV32I-NEXT: .LBB13_103:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB13_116
+; RV32I-NEXT: bnez t5, .LBB13_117
; RV32I-NEXT: .LBB13_104:
-; RV32I-NEXT: beq a7, t6, .LBB13_117
+; RV32I-NEXT: beq a7, t6, .LBB13_118
; RV32I-NEXT: .LBB13_105:
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, a5, .LBB13_118
+; RV32I-NEXT: bne a7, a5, .LBB13_119
; RV32I-NEXT: .LBB13_106:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s0, .LBB13_119
+; RV32I-NEXT: bne a7, s0, .LBB13_120
; RV32I-NEXT: .LBB13_107:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s8, .LBB13_120
+; RV32I-NEXT: bne a7, s8, .LBB13_121
; RV32I-NEXT: .LBB13_108:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s3, .LBB13_121
+; RV32I-NEXT: bne a7, s11, .LBB13_122
; RV32I-NEXT: .LBB13_109:
-; RV32I-NEXT: bnez a4, .LBB13_122
+; RV32I-NEXT: bnez a4, .LBB13_123
; RV32I-NEXT: .LBB13_110:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB13_123
+; RV32I-NEXT: bnez t5, .LBB13_124
; RV32I-NEXT: .LBB13_111:
-; RV32I-NEXT: beqz a7, .LBB13_124
+; RV32I-NEXT: beqz a7, .LBB13_125
; RV32I-NEXT: .LBB13_112:
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB13_125
-; RV32I-NEXT: j .LBB13_126
+; RV32I-NEXT: bnez t5, .LBB13_126
+; RV32I-NEXT: j .LBB13_127
; RV32I-NEXT: .LBB13_113:
+; RV32I-NEXT: mv t4, s9
+; RV32I-NEXT: bne a7, s1, .LBB13_101
+; RV32I-NEXT: .LBB13_114:
; RV32I-NEXT: or t3, s10, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB13_102
-; RV32I-NEXT: .LBB13_114:
+; RV32I-NEXT: .LBB13_115:
; RV32I-NEXT: mv t4, s7
; RV32I-NEXT: bne a7, s4, .LBB13_103
-; RV32I-NEXT: .LBB13_115:
-; RV32I-NEXT: or t3, s9, t4
+; RV32I-NEXT: .LBB13_116:
+; RV32I-NEXT: or t3, s6, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB13_104
-; RV32I-NEXT: .LBB13_116:
+; RV32I-NEXT: .LBB13_117:
; RV32I-NEXT: mv t4, s5
; RV32I-NEXT: bne a7, t6, .LBB13_105
-; RV32I-NEXT: .LBB13_117:
-; RV32I-NEXT: or t3, s6, t4
+; RV32I-NEXT: .LBB13_118:
+; RV32I-NEXT: or t3, s3, t4
; RV32I-NEXT: mv t4, s2
; RV32I-NEXT: beq a7, a5, .LBB13_106
-; RV32I-NEXT: .LBB13_118:
+; RV32I-NEXT: .LBB13_119:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: beq a7, s0, .LBB13_107
-; RV32I-NEXT: .LBB13_119:
+; RV32I-NEXT: .LBB13_120:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beq a7, s8, .LBB13_108
-; RV32I-NEXT: .LBB13_120:
+; RV32I-NEXT: .LBB13_121:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s3, .LBB13_109
-; RV32I-NEXT: .LBB13_121:
+; RV32I-NEXT: beq a7, s11, .LBB13_109
+; RV32I-NEXT: .LBB13_122:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: beqz a4, .LBB13_110
-; RV32I-NEXT: .LBB13_122:
+; RV32I-NEXT: .LBB13_123:
; RV32I-NEXT: mv a6, t3
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: beqz t5, .LBB13_111
-; RV32I-NEXT: .LBB13_123:
-; RV32I-NEXT: lw t3, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bnez a7, .LBB13_112
; RV32I-NEXT: .LBB13_124:
+; RV32I-NEXT: mv t3, s9
+; RV32I-NEXT: bnez a7, .LBB13_112
+; RV32I-NEXT: .LBB13_125:
; RV32I-NEXT: or t3, s10, t3
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB13_126
-; RV32I-NEXT: .LBB13_125:
-; RV32I-NEXT: mv t4, s7
+; RV32I-NEXT: beqz t5, .LBB13_127
; RV32I-NEXT: .LBB13_126:
-; RV32I-NEXT: beq a7, s1, .LBB13_138
-; RV32I-NEXT: # %bb.127:
+; RV32I-NEXT: mv t4, s7
+; RV32I-NEXT: .LBB13_127:
+; RV32I-NEXT: beq a7, s1, .LBB13_139
+; RV32I-NEXT: # %bb.128:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB13_139
-; RV32I-NEXT: .LBB13_128:
-; RV32I-NEXT: beq a7, s4, .LBB13_140
+; RV32I-NEXT: bnez t5, .LBB13_140
; RV32I-NEXT: .LBB13_129:
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, t6, .LBB13_141
+; RV32I-NEXT: beq a7, s4, .LBB13_141
; RV32I-NEXT: .LBB13_130:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, a5, .LBB13_142
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: bne a7, t6, .LBB13_142
; RV32I-NEXT: .LBB13_131:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s0, .LBB13_143
-; RV32I-NEXT: .LBB13_132:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s8, .LBB13_144
-; RV32I-NEXT: .LBB13_133:
+; RV32I-NEXT: bne a7, a5, .LBB13_143
+; RV32I-NEXT: .LBB13_132:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s3, .LBB13_145
+; RV32I-NEXT: bne a7, s0, .LBB13_144
+; RV32I-NEXT: .LBB13_133:
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s8, .LBB13_145
; RV32I-NEXT: .LBB13_134:
-; RV32I-NEXT: bnez a4, .LBB13_146
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s11, .LBB13_146
; RV32I-NEXT: .LBB13_135:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB13_147
+; RV32I-NEXT: bnez a4, .LBB13_147
; RV32I-NEXT: .LBB13_136:
-; RV32I-NEXT: beqz a7, .LBB13_148
-; RV32I-NEXT: .LBB13_137:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB13_149
-; RV32I-NEXT: j .LBB13_150
+; RV32I-NEXT: bnez t5, .LBB13_148
+; RV32I-NEXT: .LBB13_137:
+; RV32I-NEXT: beqz a7, .LBB13_149
; RV32I-NEXT: .LBB13_138:
-; RV32I-NEXT: or t3, s9, t4
+; RV32I-NEXT: li t3, 0
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB13_128
+; RV32I-NEXT: bnez t5, .LBB13_150
+; RV32I-NEXT: j .LBB13_151
; RV32I-NEXT: .LBB13_139:
-; RV32I-NEXT: mv t4, s5
-; RV32I-NEXT: bne a7, s4, .LBB13_129
-; RV32I-NEXT: .LBB13_140:
; RV32I-NEXT: or t3, s6, t4
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: beq a7, t6, .LBB13_130
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: beqz t5, .LBB13_129
+; RV32I-NEXT: .LBB13_140:
+; RV32I-NEXT: mv t4, s5
+; RV32I-NEXT: bne a7, s4, .LBB13_130
; RV32I-NEXT: .LBB13_141:
+; RV32I-NEXT: or t3, s3, t4
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: beq a7, t6, .LBB13_131
+; RV32I-NEXT: .LBB13_142:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, a5, .LBB13_131
-; RV32I-NEXT: .LBB13_142:
+; RV32I-NEXT: beq a7, a5, .LBB13_132
+; RV32I-NEXT: .LBB13_143:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s0, .LBB13_132
-; RV32I-NEXT: .LBB13_143:
+; RV32I-NEXT: beq a7, s0, .LBB13_133
+; RV32I-NEXT: .LBB13_144:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s8, .LBB13_133
-; RV32I-NEXT: .LBB13_144:
+; RV32I-NEXT: beq a7, s8, .LBB13_134
+; RV32I-NEXT: .LBB13_145:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s3, .LBB13_134
-; RV32I-NEXT: .LBB13_145:
-; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: beqz a4, .LBB13_135
+; RV32I-NEXT: beq a7, s11, .LBB13_135
; RV32I-NEXT: .LBB13_146:
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: beqz a4, .LBB13_136
+; RV32I-NEXT: .LBB13_147:
; RV32I-NEXT: mv t0, t4
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beqz t5, .LBB13_136
-; RV32I-NEXT: .LBB13_147:
-; RV32I-NEXT: mv t3, s7
-; RV32I-NEXT: bnez a7, .LBB13_137
+; RV32I-NEXT: beqz t5, .LBB13_137
; RV32I-NEXT: .LBB13_148:
-; RV32I-NEXT: or t3, s9, t3
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB13_150
+; RV32I-NEXT: mv t3, s7
+; RV32I-NEXT: bnez a7, .LBB13_138
; RV32I-NEXT: .LBB13_149:
-; RV32I-NEXT: mv t4, s5
+; RV32I-NEXT: or t3, s6, t3
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: beqz t5, .LBB13_151
; RV32I-NEXT: .LBB13_150:
-; RV32I-NEXT: beq a7, s1, .LBB13_161
-; RV32I-NEXT: # %bb.151:
+; RV32I-NEXT: mv t4, s5
+; RV32I-NEXT: .LBB13_151:
+; RV32I-NEXT: beq a7, s1, .LBB13_162
+; RV32I-NEXT: # %bb.152:
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, s4, .LBB13_162
-; RV32I-NEXT: .LBB13_152:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, t6, .LBB13_163
+; RV32I-NEXT: bne a7, s4, .LBB13_163
; RV32I-NEXT: .LBB13_153:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, a5, .LBB13_164
-; RV32I-NEXT: .LBB13_154:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s0, .LBB13_165
-; RV32I-NEXT: .LBB13_155:
+; RV32I-NEXT: bne a7, t6, .LBB13_164
+; RV32I-NEXT: .LBB13_154:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s8, .LBB13_166
-; RV32I-NEXT: .LBB13_156:
+; RV32I-NEXT: bne a7, a5, .LBB13_165
+; RV32I-NEXT: .LBB13_155:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s3, .LBB13_167
+; RV32I-NEXT: bne a7, s0, .LBB13_166
+; RV32I-NEXT: .LBB13_156:
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s8, .LBB13_167
; RV32I-NEXT: .LBB13_157:
-; RV32I-NEXT: bnez a4, .LBB13_168
-; RV32I-NEXT: .LBB13_158:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB13_169
+; RV32I-NEXT: bne a7, s11, .LBB13_168
+; RV32I-NEXT: .LBB13_158:
+; RV32I-NEXT: bnez a4, .LBB13_169
; RV32I-NEXT: .LBB13_159:
-; RV32I-NEXT: beqz a7, .LBB13_170
-; RV32I-NEXT: .LBB13_160:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, s1, .LBB13_171
-; RV32I-NEXT: j .LBB13_172
+; RV32I-NEXT: bnez t5, .LBB13_170
+; RV32I-NEXT: .LBB13_160:
+; RV32I-NEXT: beqz a7, .LBB13_171
; RV32I-NEXT: .LBB13_161:
-; RV32I-NEXT: or t3, s6, t4
+; RV32I-NEXT: li t3, 0
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: beq a7, s4, .LBB13_152
+; RV32I-NEXT: bne a7, s1, .LBB13_172
+; RV32I-NEXT: j .LBB13_173
; RV32I-NEXT: .LBB13_162:
+; RV32I-NEXT: or t3, s3, t4
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: beq a7, s4, .LBB13_153
+; RV32I-NEXT: .LBB13_163:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, t6, .LBB13_153
-; RV32I-NEXT: .LBB13_163:
+; RV32I-NEXT: beq a7, t6, .LBB13_154
+; RV32I-NEXT: .LBB13_164:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, a5, .LBB13_154
-; RV32I-NEXT: .LBB13_164:
+; RV32I-NEXT: beq a7, a5, .LBB13_155
+; RV32I-NEXT: .LBB13_165:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s0, .LBB13_155
-; RV32I-NEXT: .LBB13_165:
+; RV32I-NEXT: beq a7, s0, .LBB13_156
+; RV32I-NEXT: .LBB13_166:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s8, .LBB13_156
-; RV32I-NEXT: .LBB13_166:
+; RV32I-NEXT: beq a7, s8, .LBB13_157
+; RV32I-NEXT: .LBB13_167:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s3, .LBB13_157
-; RV32I-NEXT: .LBB13_167:
-; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: beqz a4, .LBB13_158
+; RV32I-NEXT: beq a7, s11, .LBB13_158
; RV32I-NEXT: .LBB13_168:
+; RV32I-NEXT: mv t3, t4
+; RV32I-NEXT: beqz a4, .LBB13_159
+; RV32I-NEXT: .LBB13_169:
; RV32I-NEXT: mv t1, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beqz t5, .LBB13_159
-; RV32I-NEXT: .LBB13_169:
-; RV32I-NEXT: mv t3, s5
-; RV32I-NEXT: bnez a7, .LBB13_160
+; RV32I-NEXT: beqz t5, .LBB13_160
; RV32I-NEXT: .LBB13_170:
-; RV32I-NEXT: or t3, s6, t3
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: beq a7, s1, .LBB13_172
+; RV32I-NEXT: mv t3, s5
+; RV32I-NEXT: bnez a7, .LBB13_161
; RV32I-NEXT: .LBB13_171:
-; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: or t3, s3, t3
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: beq a7, s1, .LBB13_173
; RV32I-NEXT: .LBB13_172:
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: .LBB13_173:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s4, .LBB13_192
-; RV32I-NEXT: # %bb.173:
+; RV32I-NEXT: bne a7, s4, .LBB13_193
+; RV32I-NEXT: # %bb.174:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, t6, .LBB13_193
-; RV32I-NEXT: .LBB13_174:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, a5, .LBB13_194
+; RV32I-NEXT: bne a7, t6, .LBB13_194
; RV32I-NEXT: .LBB13_175:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s0, .LBB13_195
-; RV32I-NEXT: .LBB13_176:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s8, .LBB13_196
-; RV32I-NEXT: .LBB13_177:
+; RV32I-NEXT: bne a7, a5, .LBB13_195
+; RV32I-NEXT: .LBB13_176:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s3, .LBB13_197
+; RV32I-NEXT: bne a7, s0, .LBB13_196
+; RV32I-NEXT: .LBB13_177:
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s8, .LBB13_197
; RV32I-NEXT: .LBB13_178:
-; RV32I-NEXT: bnez a4, .LBB13_198
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s11, .LBB13_198
; RV32I-NEXT: .LBB13_179:
-; RV32I-NEXT: bnez a7, .LBB13_199
+; RV32I-NEXT: bnez a4, .LBB13_199
; RV32I-NEXT: .LBB13_180:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s1, .LBB13_200
+; RV32I-NEXT: bnez a7, .LBB13_200
; RV32I-NEXT: .LBB13_181:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s4, .LBB13_183
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s1, .LBB13_201
; RV32I-NEXT: .LBB13_182:
-; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: beq a7, s4, .LBB13_184
; RV32I-NEXT: .LBB13_183:
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: .LBB13_184:
; RV32I-NEXT: li t5, 4
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, t6, .LBB13_185
-; RV32I-NEXT: # %bb.184:
+; RV32I-NEXT: beq a7, t6, .LBB13_186
+; RV32I-NEXT: # %bb.185:
; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: .LBB13_185:
+; RV32I-NEXT: .LBB13_186:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: lw a5, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne a7, t5, .LBB13_201
-; RV32I-NEXT: # %bb.186:
+; RV32I-NEXT: lw a5, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: bne a7, t5, .LBB13_202
+; RV32I-NEXT: # %bb.187:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s0, .LBB13_202
-; RV32I-NEXT: .LBB13_187:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s8, .LBB13_203
+; RV32I-NEXT: bne a7, s0, .LBB13_203
; RV32I-NEXT: .LBB13_188:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s3, .LBB13_204
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s8, .LBB13_204
; RV32I-NEXT: .LBB13_189:
-; RV32I-NEXT: beqz a4, .LBB13_191
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s11, .LBB13_205
; RV32I-NEXT: .LBB13_190:
-; RV32I-NEXT: mv t2, t3
+; RV32I-NEXT: beqz a4, .LBB13_192
; RV32I-NEXT: .LBB13_191:
+; RV32I-NEXT: mv t2, t3
+; RV32I-NEXT: .LBB13_192:
; RV32I-NEXT: lui a4, 16
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: srli a7, a5, 16
@@ -4863,57 +4853,57 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB13_192:
+; RV32I-NEXT: .LBB13_193:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, t6, .LBB13_174
-; RV32I-NEXT: .LBB13_193:
+; RV32I-NEXT: beq a7, t6, .LBB13_175
+; RV32I-NEXT: .LBB13_194:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, a5, .LBB13_175
-; RV32I-NEXT: .LBB13_194:
+; RV32I-NEXT: beq a7, a5, .LBB13_176
+; RV32I-NEXT: .LBB13_195:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s0, .LBB13_176
-; RV32I-NEXT: .LBB13_195:
+; RV32I-NEXT: beq a7, s0, .LBB13_177
+; RV32I-NEXT: .LBB13_196:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s8, .LBB13_177
-; RV32I-NEXT: .LBB13_196:
+; RV32I-NEXT: beq a7, s8, .LBB13_178
+; RV32I-NEXT: .LBB13_197:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s3, .LBB13_178
-; RV32I-NEXT: .LBB13_197:
-; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: beqz a4, .LBB13_179
+; RV32I-NEXT: beq a7, s11, .LBB13_179
; RV32I-NEXT: .LBB13_198:
-; RV32I-NEXT: mv a0, t4
-; RV32I-NEXT: beqz a7, .LBB13_180
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: beqz a4, .LBB13_180
; RV32I-NEXT: .LBB13_199:
+; RV32I-NEXT: mv a0, t4
+; RV32I-NEXT: beqz a7, .LBB13_181
+; RV32I-NEXT: .LBB13_200:
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s1, .LBB13_181
-; RV32I-NEXT: .LBB13_200:
+; RV32I-NEXT: beq a7, s1, .LBB13_182
+; RV32I-NEXT: .LBB13_201:
; RV32I-NEXT: mv t3, s2
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s4, .LBB13_182
-; RV32I-NEXT: j .LBB13_183
-; RV32I-NEXT: .LBB13_201:
+; RV32I-NEXT: bne a7, s4, .LBB13_183
+; RV32I-NEXT: j .LBB13_184
+; RV32I-NEXT: .LBB13_202:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s0, .LBB13_187
-; RV32I-NEXT: .LBB13_202:
+; RV32I-NEXT: beq a7, s0, .LBB13_188
+; RV32I-NEXT: .LBB13_203:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s8, .LBB13_188
-; RV32I-NEXT: .LBB13_203:
+; RV32I-NEXT: beq a7, s8, .LBB13_189
+; RV32I-NEXT: .LBB13_204:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s3, .LBB13_189
-; RV32I-NEXT: .LBB13_204:
+; RV32I-NEXT: beq a7, s11, .LBB13_190
+; RV32I-NEXT: .LBB13_205:
; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: bnez a4, .LBB13_190
-; RV32I-NEXT: j .LBB13_191
+; RV32I-NEXT: bnez a4, .LBB13_191
+; RV32I-NEXT: j .LBB13_192
%src = load i256, ptr %src.ptr, align 1
%wordOff = load i256, ptr %wordOff.ptr, align 1
%bitOff = shl i256 %wordOff, 5
@@ -5038,15 +5028,15 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV64I-NEXT: slli a6, a6, 6
; RV64I-NEXT: li t1, 64
; RV64I-NEXT: neg t3, a6
-; RV64I-NEXT: sub t5, a6, t1
-; RV64I-NEXT: sll t4, t0, t3
+; RV64I-NEXT: sub t4, a6, t1
+; RV64I-NEXT: sll t5, t0, t3
; RV64I-NEXT: bltu a6, t1, .LBB14_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: srl t6, t0, t5
+; RV64I-NEXT: srl t6, t0, t4
; RV64I-NEXT: j .LBB14_3
; RV64I-NEXT: .LBB14_2:
; RV64I-NEXT: srl t6, a3, a6
-; RV64I-NEXT: or t6, t6, t4
+; RV64I-NEXT: or t6, t6, t5
; RV64I-NEXT: .LBB14_3:
; RV64I-NEXT: or a4, a1, a4
; RV64I-NEXT: slli a5, a5, 32
@@ -5062,44 +5052,44 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV64I-NEXT: bltu a6, t1, .LBB14_7
; RV64I-NEXT: # %bb.6:
; RV64I-NEXT: li a0, 0
-; RV64I-NEXT: srl t5, a4, t5
+; RV64I-NEXT: srl t4, a4, t4
; RV64I-NEXT: j .LBB14_8
; RV64I-NEXT: .LBB14_7:
; RV64I-NEXT: srl a7, a5, a6
; RV64I-NEXT: sll t2, a4, t3
; RV64I-NEXT: srl a0, t0, a6
-; RV64I-NEXT: or t5, a7, t2
+; RV64I-NEXT: or t4, a7, t2
; RV64I-NEXT: .LBB14_8:
; RV64I-NEXT: li a7, 128
; RV64I-NEXT: mv t2, a5
; RV64I-NEXT: beqz a6, .LBB14_10
; RV64I-NEXT: # %bb.9:
-; RV64I-NEXT: mv t2, t5
+; RV64I-NEXT: mv t2, t4
; RV64I-NEXT: .LBB14_10:
; RV64I-NEXT: sub t6, a7, a6
; RV64I-NEXT: bltu a6, t1, .LBB14_13
; RV64I-NEXT: # %bb.11:
-; RV64I-NEXT: li t5, 0
+; RV64I-NEXT: li t4, 0
; RV64I-NEXT: bgeu t6, t1, .LBB14_14
; RV64I-NEXT: .LBB14_12:
; RV64I-NEXT: neg s0, t6
; RV64I-NEXT: srl s0, a3, s0
; RV64I-NEXT: sll t3, a3, t3
-; RV64I-NEXT: or s1, s0, t4
+; RV64I-NEXT: or s1, s0, t5
; RV64I-NEXT: j .LBB14_15
; RV64I-NEXT: .LBB14_13:
-; RV64I-NEXT: srl t5, a4, a6
+; RV64I-NEXT: srl t4, a4, a6
; RV64I-NEXT: bltu t6, t1, .LBB14_12
; RV64I-NEXT: .LBB14_14:
; RV64I-NEXT: li t3, 0
-; RV64I-NEXT: sub t4, t6, t1
-; RV64I-NEXT: sll s1, a3, t4
+; RV64I-NEXT: sub t5, t6, t1
+; RV64I-NEXT: sll s1, a3, t5
; RV64I-NEXT: .LBB14_15:
; RV64I-NEXT: sub s0, a6, a7
-; RV64I-NEXT: mv t4, t0
+; RV64I-NEXT: mv t5, t0
; RV64I-NEXT: beqz t6, .LBB14_17
; RV64I-NEXT: # %bb.16:
-; RV64I-NEXT: mv t4, s1
+; RV64I-NEXT: mv t5, s1
; RV64I-NEXT: .LBB14_17:
; RV64I-NEXT: bltu s0, t1, .LBB14_19
; RV64I-NEXT: # %bb.18:
@@ -5126,7 +5116,7 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV64I-NEXT: bgeu a6, a7, .LBB14_25
; RV64I-NEXT: .LBB14_24:
; RV64I-NEXT: or a3, t2, t3
-; RV64I-NEXT: or t0, t5, t4
+; RV64I-NEXT: or t0, t4, t5
; RV64I-NEXT: .LBB14_25:
; RV64I-NEXT: bnez a6, .LBB14_29
; RV64I-NEXT: # %bb.26:
@@ -5291,7 +5281,7 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: slli t2, t2, 8
; RV32I-NEXT: or t1, s0, t1
; RV32I-NEXT: or a3, t3, t0
-; RV32I-NEXT: sw a5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a7, .LBB14_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: li s0, 0
@@ -5370,42 +5360,41 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: lbu s8, 29(a0)
; RV32I-NEXT: lbu s7, 30(a0)
; RV32I-NEXT: slli s10, s4, 8
-; RV32I-NEXT: or s4, s6, s2
+; RV32I-NEXT: or s2, s6, s2
; RV32I-NEXT: slli s6, s5, 16
; RV32I-NEXT: li a5, 4
-; RV32I-NEXT: sll s2, t1, s3
-; RV32I-NEXT: sw s2, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sll s9, t1, s3
; RV32I-NEXT: beqz t5, .LBB14_19
; RV32I-NEXT: # %bb.18:
-; RV32I-NEXT: lw t2, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: mv t2, s9
; RV32I-NEXT: .LBB14_19:
-; RV32I-NEXT: lbu s2, 28(a0)
+; RV32I-NEXT: lbu s4, 28(a0)
; RV32I-NEXT: slli s8, s8, 8
; RV32I-NEXT: or s5, s10, s7
; RV32I-NEXT: srl s10, t0, a4
-; RV32I-NEXT: or a0, s6, s4
+; RV32I-NEXT: or a0, s6, s2
; RV32I-NEXT: bne a7, a5, .LBB14_21
; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: or s0, s10, t2
; RV32I-NEXT: .LBB14_21:
-; RV32I-NEXT: li s4, 0
-; RV32I-NEXT: or t2, s8, s2
+; RV32I-NEXT: li s2, 0
+; RV32I-NEXT: or t2, s8, s4
; RV32I-NEXT: slli s5, s5, 16
; RV32I-NEXT: li s8, 5
; RV32I-NEXT: sll s7, a0, s3
; RV32I-NEXT: beqz t5, .LBB14_23
; RV32I-NEXT: # %bb.22:
-; RV32I-NEXT: mv s4, s7
+; RV32I-NEXT: mv s2, s7
; RV32I-NEXT: .LBB14_23:
; RV32I-NEXT: srl a5, t1, a4
; RV32I-NEXT: or t2, s5, t2
; RV32I-NEXT: beq a7, s8, .LBB14_25
; RV32I-NEXT: # %bb.24:
-; RV32I-NEXT: mv s9, a5
+; RV32I-NEXT: mv s6, a5
; RV32I-NEXT: j .LBB14_26
; RV32I-NEXT: .LBB14_25:
-; RV32I-NEXT: mv s9, a5
-; RV32I-NEXT: or s0, a5, s4
+; RV32I-NEXT: mv s6, a5
+; RV32I-NEXT: or s0, a5, s2
; RV32I-NEXT: .LBB14_26:
; RV32I-NEXT: li s4, 0
; RV32I-NEXT: li a5, 6
@@ -5414,22 +5403,22 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: # %bb.27:
; RV32I-NEXT: mv s4, s5
; RV32I-NEXT: .LBB14_28:
-; RV32I-NEXT: srl s6, a0, a4
+; RV32I-NEXT: srl s3, a0, a4
; RV32I-NEXT: bne a7, a5, .LBB14_30
; RV32I-NEXT: # %bb.29:
-; RV32I-NEXT: or s0, s6, s4
+; RV32I-NEXT: or s0, s3, s4
; RV32I-NEXT: .LBB14_30:
-; RV32I-NEXT: li s3, 7
+; RV32I-NEXT: li a5, 7
; RV32I-NEXT: srl s2, t2, a4
; RV32I-NEXT: mv s4, s2
-; RV32I-NEXT: bne a7, s3, .LBB14_35
+; RV32I-NEXT: bne a7, a5, .LBB14_35
; RV32I-NEXT: # %bb.31:
; RV32I-NEXT: bnez a4, .LBB14_36
; RV32I-NEXT: .LBB14_32:
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: bnez t5, .LBB14_37
; RV32I-NEXT: .LBB14_33:
-; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: li a5, 2
; RV32I-NEXT: beqz a7, .LBB14_38
; RV32I-NEXT: .LBB14_34:
; RV32I-NEXT: li t6, 0
@@ -5438,29 +5427,29 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: mv s4, s0
; RV32I-NEXT: beqz a4, .LBB14_32
; RV32I-NEXT: .LBB14_36:
-; RV32I-NEXT: sw s4, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB14_33
; RV32I-NEXT: .LBB14_37:
; RV32I-NEXT: mv s0, t6
-; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: li a5, 2
; RV32I-NEXT: bnez a7, .LBB14_34
; RV32I-NEXT: .LBB14_38:
; RV32I-NEXT: or t6, s1, s0
; RV32I-NEXT: .LBB14_39:
; RV32I-NEXT: li s1, 1
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB14_59
+; RV32I-NEXT: bnez t5, .LBB14_61
; RV32I-NEXT: # %bb.40:
-; RV32I-NEXT: beq a7, s1, .LBB14_60
+; RV32I-NEXT: beq a7, s1, .LBB14_62
; RV32I-NEXT: .LBB14_41:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB14_61
+; RV32I-NEXT: bnez t5, .LBB14_63
; RV32I-NEXT: .LBB14_42:
-; RV32I-NEXT: beq a7, s4, .LBB14_62
+; RV32I-NEXT: beq a7, a5, .LBB14_64
; RV32I-NEXT: .LBB14_43:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB14_63
+; RV32I-NEXT: bnez t5, .LBB14_65
; RV32I-NEXT: .LBB14_44:
; RV32I-NEXT: li a5, 3
; RV32I-NEXT: bne a7, a5, .LBB14_46
@@ -5469,457 +5458,453 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: .LBB14_46:
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a5, 4
-; RV32I-NEXT: bnez t5, .LBB14_64
+; RV32I-NEXT: bnez t5, .LBB14_66
; RV32I-NEXT: # %bb.47:
-; RV32I-NEXT: beq a7, a5, .LBB14_65
+; RV32I-NEXT: beq a7, a5, .LBB14_67
; RV32I-NEXT: .LBB14_48:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t5, .LBB14_66
+; RV32I-NEXT: bnez t5, .LBB14_68
; RV32I-NEXT: .LBB14_49:
; RV32I-NEXT: bne a7, s8, .LBB14_51
; RV32I-NEXT: .LBB14_50:
-; RV32I-NEXT: or t6, s6, s0
+; RV32I-NEXT: or t6, s3, s0
; RV32I-NEXT: .LBB14_51:
; RV32I-NEXT: mv s0, s2
; RV32I-NEXT: li s8, 6
-; RV32I-NEXT: bne a7, s8, .LBB14_67
+; RV32I-NEXT: beq a7, s8, .LBB14_53
; RV32I-NEXT: # %bb.52:
-; RV32I-NEXT: li t6, 0
-; RV32I-NEXT: bne a7, s3, .LBB14_68
+; RV32I-NEXT: mv s0, t6
; RV32I-NEXT: .LBB14_53:
-; RV32I-NEXT: beqz a4, .LBB14_55
-; RV32I-NEXT: .LBB14_54:
-; RV32I-NEXT: mv a1, t6
+; RV32I-NEXT: li t6, 0
+; RV32I-NEXT: li s4, 7
+; RV32I-NEXT: beq a7, s4, .LBB14_55
+; RV32I-NEXT: # %bb.54:
+; RV32I-NEXT: mv t6, s0
; RV32I-NEXT: .LBB14_55:
+; RV32I-NEXT: beqz a4, .LBB14_57
+; RV32I-NEXT: # %bb.56:
+; RV32I-NEXT: mv a1, t6
+; RV32I-NEXT: .LBB14_57:
; RV32I-NEXT: li t6, 0
; RV32I-NEXT: li s0, 5
-; RV32I-NEXT: beqz t5, .LBB14_57
-; RV32I-NEXT: # %bb.56:
+; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: beqz t5, .LBB14_59
+; RV32I-NEXT: # %bb.58:
; RV32I-NEXT: mv t6, t3
-; RV32I-NEXT: .LBB14_57:
+; RV32I-NEXT: .LBB14_59:
; RV32I-NEXT: beqz a7, .LBB14_69
-; RV32I-NEXT: # %bb.58:
+; RV32I-NEXT: # %bb.60:
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: j .LBB14_70
-; RV32I-NEXT: .LBB14_59:
+; RV32I-NEXT: .LBB14_61:
; RV32I-NEXT: mv s0, t3
; RV32I-NEXT: bne a7, s1, .LBB14_41
-; RV32I-NEXT: .LBB14_60:
+; RV32I-NEXT: .LBB14_62:
; RV32I-NEXT: or t6, t4, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB14_42
-; RV32I-NEXT: .LBB14_61:
+; RV32I-NEXT: .LBB14_63:
; RV32I-NEXT: mv s0, s11
-; RV32I-NEXT: bne a7, s4, .LBB14_43
-; RV32I-NEXT: .LBB14_62:
+; RV32I-NEXT: bne a7, a5, .LBB14_43
+; RV32I-NEXT: .LBB14_64:
; RV32I-NEXT: or t6, ra, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB14_44
-; RV32I-NEXT: .LBB14_63:
-; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .LBB14_65:
+; RV32I-NEXT: mv s0, s9
; RV32I-NEXT: li a5, 3
; RV32I-NEXT: beq a7, a5, .LBB14_45
; RV32I-NEXT: j .LBB14_46
-; RV32I-NEXT: .LBB14_64:
+; RV32I-NEXT: .LBB14_66:
; RV32I-NEXT: mv s0, s7
; RV32I-NEXT: bne a7, a5, .LBB14_48
-; RV32I-NEXT: .LBB14_65:
-; RV32I-NEXT: or t6, s9, s0
+; RV32I-NEXT: .LBB14_67:
+; RV32I-NEXT: or t6, s6, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t5, .LBB14_49
-; RV32I-NEXT: .LBB14_66:
+; RV32I-NEXT: .LBB14_68:
; RV32I-NEXT: mv s0, s5
; RV32I-NEXT: beq a7, s8, .LBB14_50
; RV32I-NEXT: j .LBB14_51
-; RV32I-NEXT: .LBB14_67:
-; RV32I-NEXT: mv s0, t6
-; RV32I-NEXT: li t6, 0
-; RV32I-NEXT: beq a7, s3, .LBB14_53
-; RV32I-NEXT: .LBB14_68:
-; RV32I-NEXT: mv t6, s0
-; RV32I-NEXT: bnez a4, .LBB14_54
-; RV32I-NEXT: j .LBB14_55
; RV32I-NEXT: .LBB14_69:
; RV32I-NEXT: or t3, t4, t6
; RV32I-NEXT: .LBB14_70:
; RV32I-NEXT: li t6, 3
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB14_85
+; RV32I-NEXT: bnez t5, .LBB14_89
; RV32I-NEXT: # %bb.71:
-; RV32I-NEXT: beq a7, s1, .LBB14_86
+; RV32I-NEXT: beq a7, s1, .LBB14_90
; RV32I-NEXT: .LBB14_72:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB14_87
+; RV32I-NEXT: bnez t5, .LBB14_91
; RV32I-NEXT: .LBB14_73:
-; RV32I-NEXT: beq a7, s4, .LBB14_88
+; RV32I-NEXT: beq a7, s4, .LBB14_92
; RV32I-NEXT: .LBB14_74:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB14_89
+; RV32I-NEXT: bnez t5, .LBB14_93
; RV32I-NEXT: .LBB14_75:
-; RV32I-NEXT: beq a7, t6, .LBB14_90
+; RV32I-NEXT: beq a7, t6, .LBB14_94
; RV32I-NEXT: .LBB14_76:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB14_91
+; RV32I-NEXT: bnez t5, .LBB14_95
; RV32I-NEXT: .LBB14_77:
-; RV32I-NEXT: beq a7, a5, .LBB14_92
+; RV32I-NEXT: beq a7, a5, .LBB14_96
; RV32I-NEXT: .LBB14_78:
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, s0, .LBB14_93
+; RV32I-NEXT: bne a7, s0, .LBB14_97
; RV32I-NEXT: .LBB14_79:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s8, .LBB14_94
+; RV32I-NEXT: beq a7, s8, .LBB14_81
; RV32I-NEXT: .LBB14_80:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s3, .LBB14_95
+; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: .LBB14_81:
-; RV32I-NEXT: bnez a4, .LBB14_96
-; RV32I-NEXT: .LBB14_82:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB14_97
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: li s4, 7
+; RV32I-NEXT: beq a7, s4, .LBB14_83
+; RV32I-NEXT: # %bb.82:
+; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: .LBB14_83:
+; RV32I-NEXT: beqz a4, .LBB14_85
+; RV32I-NEXT: # %bb.84:
+; RV32I-NEXT: mv a3, t4
+; RV32I-NEXT: .LBB14_85:
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: li s4, 2
+; RV32I-NEXT: beqz t5, .LBB14_87
+; RV32I-NEXT: # %bb.86:
+; RV32I-NEXT: mv t3, s11
+; RV32I-NEXT: .LBB14_87:
; RV32I-NEXT: beqz a7, .LBB14_98
-; RV32I-NEXT: .LBB14_84:
+; RV32I-NEXT: # %bb.88:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB14_99
-; RV32I-NEXT: j .LBB14_100
-; RV32I-NEXT: .LBB14_85:
+; RV32I-NEXT: j .LBB14_99
+; RV32I-NEXT: .LBB14_89:
; RV32I-NEXT: mv t4, s11
; RV32I-NEXT: bne a7, s1, .LBB14_72
-; RV32I-NEXT: .LBB14_86:
+; RV32I-NEXT: .LBB14_90:
; RV32I-NEXT: or t3, ra, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB14_73
-; RV32I-NEXT: .LBB14_87:
-; RV32I-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .LBB14_91:
+; RV32I-NEXT: mv t4, s9
; RV32I-NEXT: bne a7, s4, .LBB14_74
-; RV32I-NEXT: .LBB14_88:
+; RV32I-NEXT: .LBB14_92:
; RV32I-NEXT: or t3, s10, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB14_75
-; RV32I-NEXT: .LBB14_89:
+; RV32I-NEXT: .LBB14_93:
; RV32I-NEXT: mv t4, s7
; RV32I-NEXT: bne a7, t6, .LBB14_76
-; RV32I-NEXT: .LBB14_90:
-; RV32I-NEXT: or t3, s9, t4
+; RV32I-NEXT: .LBB14_94:
+; RV32I-NEXT: or t3, s6, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB14_77
-; RV32I-NEXT: .LBB14_91:
+; RV32I-NEXT: .LBB14_95:
; RV32I-NEXT: mv t4, s5
; RV32I-NEXT: bne a7, a5, .LBB14_78
-; RV32I-NEXT: .LBB14_92:
-; RV32I-NEXT: or t3, s6, t4
+; RV32I-NEXT: .LBB14_96:
+; RV32I-NEXT: or t3, s3, t4
; RV32I-NEXT: mv t4, s2
; RV32I-NEXT: beq a7, s0, .LBB14_79
-; RV32I-NEXT: .LBB14_93:
-; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s8, .LBB14_80
-; RV32I-NEXT: .LBB14_94:
-; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s3, .LBB14_81
-; RV32I-NEXT: .LBB14_95:
+; RV32I-NEXT: .LBB14_97:
; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: beqz a4, .LBB14_82
-; RV32I-NEXT: .LBB14_96:
-; RV32I-NEXT: mv a3, t4
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beqz t5, .LBB14_83
-; RV32I-NEXT: .LBB14_97:
-; RV32I-NEXT: mv t3, s11
-; RV32I-NEXT: bnez a7, .LBB14_84
+; RV32I-NEXT: bne a7, s8, .LBB14_80
+; RV32I-NEXT: j .LBB14_81
; RV32I-NEXT: .LBB14_98:
; RV32I-NEXT: or t3, ra, t3
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB14_100
; RV32I-NEXT: .LBB14_99:
-; RV32I-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: .LBB14_100:
-; RV32I-NEXT: beq a7, s1, .LBB14_113
-; RV32I-NEXT: # %bb.101:
+; RV32I-NEXT: li s11, 7
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB14_114
+; RV32I-NEXT: bnez t5, .LBB14_113
+; RV32I-NEXT: # %bb.100:
+; RV32I-NEXT: beq a7, s1, .LBB14_114
+; RV32I-NEXT: .LBB14_101:
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bnez t5, .LBB14_115
; RV32I-NEXT: .LBB14_102:
-; RV32I-NEXT: beq a7, s4, .LBB14_115
+; RV32I-NEXT: beq a7, s4, .LBB14_116
; RV32I-NEXT: .LBB14_103:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB14_116
+; RV32I-NEXT: bnez t5, .LBB14_117
; RV32I-NEXT: .LBB14_104:
-; RV32I-NEXT: beq a7, t6, .LBB14_117
+; RV32I-NEXT: beq a7, t6, .LBB14_118
; RV32I-NEXT: .LBB14_105:
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, a5, .LBB14_118
+; RV32I-NEXT: bne a7, a5, .LBB14_119
; RV32I-NEXT: .LBB14_106:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s0, .LBB14_119
+; RV32I-NEXT: bne a7, s0, .LBB14_120
; RV32I-NEXT: .LBB14_107:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s8, .LBB14_120
+; RV32I-NEXT: bne a7, s8, .LBB14_121
; RV32I-NEXT: .LBB14_108:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s3, .LBB14_121
+; RV32I-NEXT: bne a7, s11, .LBB14_122
; RV32I-NEXT: .LBB14_109:
-; RV32I-NEXT: bnez a4, .LBB14_122
+; RV32I-NEXT: bnez a4, .LBB14_123
; RV32I-NEXT: .LBB14_110:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB14_123
+; RV32I-NEXT: bnez t5, .LBB14_124
; RV32I-NEXT: .LBB14_111:
-; RV32I-NEXT: beqz a7, .LBB14_124
+; RV32I-NEXT: beqz a7, .LBB14_125
; RV32I-NEXT: .LBB14_112:
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB14_125
-; RV32I-NEXT: j .LBB14_126
+; RV32I-NEXT: bnez t5, .LBB14_126
+; RV32I-NEXT: j .LBB14_127
; RV32I-NEXT: .LBB14_113:
+; RV32I-NEXT: mv t4, s9
+; RV32I-NEXT: bne a7, s1, .LBB14_101
+; RV32I-NEXT: .LBB14_114:
; RV32I-NEXT: or t3, s10, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB14_102
-; RV32I-NEXT: .LBB14_114:
+; RV32I-NEXT: .LBB14_115:
; RV32I-NEXT: mv t4, s7
; RV32I-NEXT: bne a7, s4, .LBB14_103
-; RV32I-NEXT: .LBB14_115:
-; RV32I-NEXT: or t3, s9, t4
+; RV32I-NEXT: .LBB14_116:
+; RV32I-NEXT: or t3, s6, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beqz t5, .LBB14_104
-; RV32I-NEXT: .LBB14_116:
+; RV32I-NEXT: .LBB14_117:
; RV32I-NEXT: mv t4, s5
; RV32I-NEXT: bne a7, t6, .LBB14_105
-; RV32I-NEXT: .LBB14_117:
-; RV32I-NEXT: or t3, s6, t4
+; RV32I-NEXT: .LBB14_118:
+; RV32I-NEXT: or t3, s3, t4
; RV32I-NEXT: mv t4, s2
; RV32I-NEXT: beq a7, a5, .LBB14_106
-; RV32I-NEXT: .LBB14_118:
+; RV32I-NEXT: .LBB14_119:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: beq a7, s0, .LBB14_107
-; RV32I-NEXT: .LBB14_119:
+; RV32I-NEXT: .LBB14_120:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
; RV32I-NEXT: beq a7, s8, .LBB14_108
-; RV32I-NEXT: .LBB14_120:
+; RV32I-NEXT: .LBB14_121:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s3, .LBB14_109
-; RV32I-NEXT: .LBB14_121:
+; RV32I-NEXT: beq a7, s11, .LBB14_109
+; RV32I-NEXT: .LBB14_122:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: beqz a4, .LBB14_110
-; RV32I-NEXT: .LBB14_122:
+; RV32I-NEXT: .LBB14_123:
; RV32I-NEXT: mv a6, t3
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: beqz t5, .LBB14_111
-; RV32I-NEXT: .LBB14_123:
-; RV32I-NEXT: lw t3, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bnez a7, .LBB14_112
; RV32I-NEXT: .LBB14_124:
+; RV32I-NEXT: mv t3, s9
+; RV32I-NEXT: bnez a7, .LBB14_112
+; RV32I-NEXT: .LBB14_125:
; RV32I-NEXT: or t3, s10, t3
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB14_126
-; RV32I-NEXT: .LBB14_125:
-; RV32I-NEXT: mv t4, s7
+; RV32I-NEXT: beqz t5, .LBB14_127
; RV32I-NEXT: .LBB14_126:
-; RV32I-NEXT: beq a7, s1, .LBB14_138
-; RV32I-NEXT: # %bb.127:
+; RV32I-NEXT: mv t4, s7
+; RV32I-NEXT: .LBB14_127:
+; RV32I-NEXT: beq a7, s1, .LBB14_139
+; RV32I-NEXT: # %bb.128:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB14_139
-; RV32I-NEXT: .LBB14_128:
-; RV32I-NEXT: beq a7, s4, .LBB14_140
+; RV32I-NEXT: bnez t5, .LBB14_140
; RV32I-NEXT: .LBB14_129:
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, t6, .LBB14_141
+; RV32I-NEXT: beq a7, s4, .LBB14_141
; RV32I-NEXT: .LBB14_130:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, a5, .LBB14_142
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: bne a7, t6, .LBB14_142
; RV32I-NEXT: .LBB14_131:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s0, .LBB14_143
-; RV32I-NEXT: .LBB14_132:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s8, .LBB14_144
-; RV32I-NEXT: .LBB14_133:
+; RV32I-NEXT: bne a7, a5, .LBB14_143
+; RV32I-NEXT: .LBB14_132:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s3, .LBB14_145
+; RV32I-NEXT: bne a7, s0, .LBB14_144
+; RV32I-NEXT: .LBB14_133:
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s8, .LBB14_145
; RV32I-NEXT: .LBB14_134:
-; RV32I-NEXT: bnez a4, .LBB14_146
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s11, .LBB14_146
; RV32I-NEXT: .LBB14_135:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB14_147
+; RV32I-NEXT: bnez a4, .LBB14_147
; RV32I-NEXT: .LBB14_136:
-; RV32I-NEXT: beqz a7, .LBB14_148
-; RV32I-NEXT: .LBB14_137:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bnez t5, .LBB14_149
-; RV32I-NEXT: j .LBB14_150
+; RV32I-NEXT: bnez t5, .LBB14_148
+; RV32I-NEXT: .LBB14_137:
+; RV32I-NEXT: beqz a7, .LBB14_149
; RV32I-NEXT: .LBB14_138:
-; RV32I-NEXT: or t3, s9, t4
+; RV32I-NEXT: li t3, 0
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB14_128
+; RV32I-NEXT: bnez t5, .LBB14_150
+; RV32I-NEXT: j .LBB14_151
; RV32I-NEXT: .LBB14_139:
-; RV32I-NEXT: mv t4, s5
-; RV32I-NEXT: bne a7, s4, .LBB14_129
-; RV32I-NEXT: .LBB14_140:
; RV32I-NEXT: or t3, s6, t4
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: beq a7, t6, .LBB14_130
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: beqz t5, .LBB14_129
+; RV32I-NEXT: .LBB14_140:
+; RV32I-NEXT: mv t4, s5
+; RV32I-NEXT: bne a7, s4, .LBB14_130
; RV32I-NEXT: .LBB14_141:
+; RV32I-NEXT: or t3, s3, t4
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: beq a7, t6, .LBB14_131
+; RV32I-NEXT: .LBB14_142:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, a5, .LBB14_131
-; RV32I-NEXT: .LBB14_142:
+; RV32I-NEXT: beq a7, a5, .LBB14_132
+; RV32I-NEXT: .LBB14_143:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s0, .LBB14_132
-; RV32I-NEXT: .LBB14_143:
+; RV32I-NEXT: beq a7, s0, .LBB14_133
+; RV32I-NEXT: .LBB14_144:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s8, .LBB14_133
-; RV32I-NEXT: .LBB14_144:
+; RV32I-NEXT: beq a7, s8, .LBB14_134
+; RV32I-NEXT: .LBB14_145:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s3, .LBB14_134
-; RV32I-NEXT: .LBB14_145:
-; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: beqz a4, .LBB14_135
+; RV32I-NEXT: beq a7, s11, .LBB14_135
; RV32I-NEXT: .LBB14_146:
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: beqz a4, .LBB14_136
+; RV32I-NEXT: .LBB14_147:
; RV32I-NEXT: mv t0, t4
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beqz t5, .LBB14_136
-; RV32I-NEXT: .LBB14_147:
-; RV32I-NEXT: mv t3, s7
-; RV32I-NEXT: bnez a7, .LBB14_137
+; RV32I-NEXT: beqz t5, .LBB14_137
; RV32I-NEXT: .LBB14_148:
-; RV32I-NEXT: or t3, s9, t3
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beqz t5, .LBB14_150
+; RV32I-NEXT: mv t3, s7
+; RV32I-NEXT: bnez a7, .LBB14_138
; RV32I-NEXT: .LBB14_149:
-; RV32I-NEXT: mv t4, s5
+; RV32I-NEXT: or t3, s6, t3
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: beqz t5, .LBB14_151
; RV32I-NEXT: .LBB14_150:
-; RV32I-NEXT: beq a7, s1, .LBB14_161
-; RV32I-NEXT: # %bb.151:
+; RV32I-NEXT: mv t4, s5
+; RV32I-NEXT: .LBB14_151:
+; RV32I-NEXT: beq a7, s1, .LBB14_162
+; RV32I-NEXT: # %bb.152:
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, s4, .LBB14_162
-; RV32I-NEXT: .LBB14_152:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, t6, .LBB14_163
+; RV32I-NEXT: bne a7, s4, .LBB14_163
; RV32I-NEXT: .LBB14_153:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, a5, .LBB14_164
-; RV32I-NEXT: .LBB14_154:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s0, .LBB14_165
-; RV32I-NEXT: .LBB14_155:
+; RV32I-NEXT: bne a7, t6, .LBB14_164
+; RV32I-NEXT: .LBB14_154:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s8, .LBB14_166
-; RV32I-NEXT: .LBB14_156:
+; RV32I-NEXT: bne a7, a5, .LBB14_165
+; RV32I-NEXT: .LBB14_155:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s3, .LBB14_167
+; RV32I-NEXT: bne a7, s0, .LBB14_166
+; RV32I-NEXT: .LBB14_156:
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s8, .LBB14_167
; RV32I-NEXT: .LBB14_157:
-; RV32I-NEXT: bnez a4, .LBB14_168
-; RV32I-NEXT: .LBB14_158:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bnez t5, .LBB14_169
+; RV32I-NEXT: bne a7, s11, .LBB14_168
+; RV32I-NEXT: .LBB14_158:
+; RV32I-NEXT: bnez a4, .LBB14_169
; RV32I-NEXT: .LBB14_159:
-; RV32I-NEXT: beqz a7, .LBB14_170
-; RV32I-NEXT: .LBB14_160:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: bne a7, s1, .LBB14_171
-; RV32I-NEXT: j .LBB14_172
+; RV32I-NEXT: bnez t5, .LBB14_170
+; RV32I-NEXT: .LBB14_160:
+; RV32I-NEXT: beqz a7, .LBB14_171
; RV32I-NEXT: .LBB14_161:
-; RV32I-NEXT: or t3, s6, t4
+; RV32I-NEXT: li t3, 0
; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: beq a7, s4, .LBB14_152
+; RV32I-NEXT: bne a7, s1, .LBB14_172
+; RV32I-NEXT: j .LBB14_173
; RV32I-NEXT: .LBB14_162:
+; RV32I-NEXT: or t3, s3, t4
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: beq a7, s4, .LBB14_153
+; RV32I-NEXT: .LBB14_163:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, t6, .LBB14_153
-; RV32I-NEXT: .LBB14_163:
+; RV32I-NEXT: beq a7, t6, .LBB14_154
+; RV32I-NEXT: .LBB14_164:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, a5, .LBB14_154
-; RV32I-NEXT: .LBB14_164:
+; RV32I-NEXT: beq a7, a5, .LBB14_155
+; RV32I-NEXT: .LBB14_165:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s0, .LBB14_155
-; RV32I-NEXT: .LBB14_165:
+; RV32I-NEXT: beq a7, s0, .LBB14_156
+; RV32I-NEXT: .LBB14_166:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s8, .LBB14_156
-; RV32I-NEXT: .LBB14_166:
+; RV32I-NEXT: beq a7, s8, .LBB14_157
+; RV32I-NEXT: .LBB14_167:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s3, .LBB14_157
-; RV32I-NEXT: .LBB14_167:
-; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: beqz a4, .LBB14_158
+; RV32I-NEXT: beq a7, s11, .LBB14_158
; RV32I-NEXT: .LBB14_168:
+; RV32I-NEXT: mv t3, t4
+; RV32I-NEXT: beqz a4, .LBB14_159
+; RV32I-NEXT: .LBB14_169:
; RV32I-NEXT: mv t1, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beqz t5, .LBB14_159
-; RV32I-NEXT: .LBB14_169:
-; RV32I-NEXT: mv t3, s5
-; RV32I-NEXT: bnez a7, .LBB14_160
+; RV32I-NEXT: beqz t5, .LBB14_160
; RV32I-NEXT: .LBB14_170:
-; RV32I-NEXT: or t3, s6, t3
-; RV32I-NEXT: mv t4, s2
-; RV32I-NEXT: beq a7, s1, .LBB14_172
+; RV32I-NEXT: mv t3, s5
+; RV32I-NEXT: bnez a7, .LBB14_161
; RV32I-NEXT: .LBB14_171:
-; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: or t3, s3, t3
+; RV32I-NEXT: mv t4, s2
+; RV32I-NEXT: beq a7, s1, .LBB14_173
; RV32I-NEXT: .LBB14_172:
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: .LBB14_173:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s4, .LBB14_192
-; RV32I-NEXT: # %bb.173:
+; RV32I-NEXT: bne a7, s4, .LBB14_193
+; RV32I-NEXT: # %bb.174:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, t6, .LBB14_193
-; RV32I-NEXT: .LBB14_174:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, a5, .LBB14_194
+; RV32I-NEXT: bne a7, t6, .LBB14_194
; RV32I-NEXT: .LBB14_175:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s0, .LBB14_195
-; RV32I-NEXT: .LBB14_176:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s8, .LBB14_196
-; RV32I-NEXT: .LBB14_177:
+; RV32I-NEXT: bne a7, a5, .LBB14_195
+; RV32I-NEXT: .LBB14_176:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s3, .LBB14_197
+; RV32I-NEXT: bne a7, s0, .LBB14_196
+; RV32I-NEXT: .LBB14_177:
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s8, .LBB14_197
; RV32I-NEXT: .LBB14_178:
-; RV32I-NEXT: bnez a4, .LBB14_198
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s11, .LBB14_198
; RV32I-NEXT: .LBB14_179:
-; RV32I-NEXT: bnez a7, .LBB14_199
+; RV32I-NEXT: bnez a4, .LBB14_199
; RV32I-NEXT: .LBB14_180:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s1, .LBB14_200
+; RV32I-NEXT: bnez a7, .LBB14_200
; RV32I-NEXT: .LBB14_181:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s4, .LBB14_183
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s1, .LBB14_201
; RV32I-NEXT: .LBB14_182:
-; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: beq a7, s4, .LBB14_184
; RV32I-NEXT: .LBB14_183:
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: .LBB14_184:
; RV32I-NEXT: li t5, 4
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, t6, .LBB14_185
-; RV32I-NEXT: # %bb.184:
+; RV32I-NEXT: beq a7, t6, .LBB14_186
+; RV32I-NEXT: # %bb.185:
; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: .LBB14_185:
+; RV32I-NEXT: .LBB14_186:
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: lw a5, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne a7, t5, .LBB14_201
-; RV32I-NEXT: # %bb.186:
+; RV32I-NEXT: lw a5, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: bne a7, t5, .LBB14_202
+; RV32I-NEXT: # %bb.187:
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s0, .LBB14_202
-; RV32I-NEXT: .LBB14_187:
-; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s8, .LBB14_203
+; RV32I-NEXT: bne a7, s0, .LBB14_203
; RV32I-NEXT: .LBB14_188:
-; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: bne a7, s3, .LBB14_204
+; RV32I-NEXT: li t4, 0
+; RV32I-NEXT: bne a7, s8, .LBB14_204
; RV32I-NEXT: .LBB14_189:
-; RV32I-NEXT: beqz a4, .LBB14_191
+; RV32I-NEXT: li t3, 0
+; RV32I-NEXT: bne a7, s11, .LBB14_205
; RV32I-NEXT: .LBB14_190:
-; RV32I-NEXT: mv t2, t3
+; RV32I-NEXT: beqz a4, .LBB14_192
; RV32I-NEXT: .LBB14_191:
+; RV32I-NEXT: mv t2, t3
+; RV32I-NEXT: .LBB14_192:
; RV32I-NEXT: lui a4, 16
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: srli a7, a5, 16
@@ -6001,57 +5986,57 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB14_192:
+; RV32I-NEXT: .LBB14_193:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, t6, .LBB14_174
-; RV32I-NEXT: .LBB14_193:
+; RV32I-NEXT: beq a7, t6, .LBB14_175
+; RV32I-NEXT: .LBB14_194:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, a5, .LBB14_175
-; RV32I-NEXT: .LBB14_194:
+; RV32I-NEXT: beq a7, a5, .LBB14_176
+; RV32I-NEXT: .LBB14_195:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s0, .LBB14_176
-; RV32I-NEXT: .LBB14_195:
+; RV32I-NEXT: beq a7, s0, .LBB14_177
+; RV32I-NEXT: .LBB14_196:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s8, .LBB14_177
-; RV32I-NEXT: .LBB14_196:
+; RV32I-NEXT: beq a7, s8, .LBB14_178
+; RV32I-NEXT: .LBB14_197:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s3, .LBB14_178
-; RV32I-NEXT: .LBB14_197:
-; RV32I-NEXT: mv t4, t3
-; RV32I-NEXT: beqz a4, .LBB14_179
+; RV32I-NEXT: beq a7, s11, .LBB14_179
; RV32I-NEXT: .LBB14_198:
-; RV32I-NEXT: mv a0, t4
-; RV32I-NEXT: beqz a7, .LBB14_180
+; RV32I-NEXT: mv t4, t3
+; RV32I-NEXT: beqz a4, .LBB14_180
; RV32I-NEXT: .LBB14_199:
+; RV32I-NEXT: mv a0, t4
+; RV32I-NEXT: beqz a7, .LBB14_181
+; RV32I-NEXT: .LBB14_200:
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s1, .LBB14_181
-; RV32I-NEXT: .LBB14_200:
+; RV32I-NEXT: beq a7, s1, .LBB14_182
+; RV32I-NEXT: .LBB14_201:
; RV32I-NEXT: mv t3, s2
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: bne a7, s4, .LBB14_182
-; RV32I-NEXT: j .LBB14_183
-; RV32I-NEXT: .LBB14_201:
+; RV32I-NEXT: bne a7, s4, .LBB14_183
+; RV32I-NEXT: j .LBB14_184
+; RV32I-NEXT: .LBB14_202:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s0, .LBB14_187
-; RV32I-NEXT: .LBB14_202:
+; RV32I-NEXT: beq a7, s0, .LBB14_188
+; RV32I-NEXT: .LBB14_203:
; RV32I-NEXT: mv t3, t4
; RV32I-NEXT: li t4, 0
-; RV32I-NEXT: beq a7, s8, .LBB14_188
-; RV32I-NEXT: .LBB14_203:
+; RV32I-NEXT: beq a7, s8, .LBB14_189
+; RV32I-NEXT: .LBB14_204:
; RV32I-NEXT: mv t4, t3
; RV32I-NEXT: li t3, 0
-; RV32I-NEXT: beq a7, s3, .LBB14_189
-; RV32I-NEXT: .LBB14_204:
+; RV32I-NEXT: beq a7, s11, .LBB14_190
+; RV32I-NEXT: .LBB14_205:
; RV32I-NEXT: mv t3, t4
-; RV32I-NEXT: bnez a4, .LBB14_190
-; RV32I-NEXT: j .LBB14_191
+; RV32I-NEXT: bnez a4, .LBB14_191
+; RV32I-NEXT: j .LBB14_192
%src = load i256, ptr %src.ptr, align 1
%dwordOff = load i256, ptr %dwordOff.ptr, align 1
%bitOff = shl i256 %dwordOff, 6
@@ -7530,21 +7515,21 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw
; RV32I-NEXT: srli a4, a1, 5
; RV32I-NEXT: sll t4, a6, a1
; RV32I-NEXT: li s9, 1
-; RV32I-NEXT: mv a5, t4
+; RV32I-NEXT: mv a3, t4
; RV32I-NEXT: beqz a4, .LBB16_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: li a5, 0
-; RV32I-NEXT: .LBB16_2:
; RV32I-NEXT: li a3, 0
+; RV32I-NEXT: .LBB16_2:
+; RV32I-NEXT: li a5, 0
; RV32I-NEXT: li t6, 2
; RV32I-NEXT: beq a4, s9, .LBB16_4
; RV32I-NEXT: # %bb.3:
-; RV32I-NEXT: mv a3, a5
+; RV32I-NEXT: mv a5, a3
; RV32I-NEXT: .LBB16_4:
; RV32I-NEXT: li a7, 0
; RV32I-NEXT: beq a4, t6, .LBB16_6
; RV32I-NEXT: # %bb.5:
-; RV32I-NEXT: mv a7, a3
+; RV32I-NEXT: mv a7, a5
; RV32I-NEXT: .LBB16_6:
; RV32I-NEXT: li a5, 0
; RV32I-NEXT: li s6, 3
@@ -7969,7 +7954,7 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw
; RV32I-NEXT: # %bb.127:
; RV32I-NEXT: mv t1, t2
; RV32I-NEXT: .LBB16_128:
-; RV32I-NEXT: mv s10, a5
+; RV32I-NEXT: mv s10, s8
; RV32I-NEXT: li t2, 0
; RV32I-NEXT: lbu s0, 24(a0)
; RV32I-NEXT: or t6, t6, a3
@@ -7978,7 +7963,7 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw
; RV32I-NEXT: # %bb.129:
; RV32I-NEXT: mv t2, t1
; RV32I-NEXT: .LBB16_130:
-; RV32I-NEXT: mv a5, s8
+; RV32I-NEXT: li s8, 4
; RV32I-NEXT: or a3, a3, s0
; RV32I-NEXT: slli t6, t6, 16
; RV32I-NEXT: mv ra, t0
@@ -7986,7 +7971,7 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw
; RV32I-NEXT: # %bb.131:
; RV32I-NEXT: mv ra, t2
; RV32I-NEXT: .LBB16_132:
-; RV32I-NEXT: li s8, 4
+; RV32I-NEXT: li s3, 5
; RV32I-NEXT: li t3, 0
; RV32I-NEXT: or t2, t6, a3
; RV32I-NEXT: srl t0, t0, s2
@@ -7995,10 +7980,10 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw
; RV32I-NEXT: # %bb.133:
; RV32I-NEXT: mv t3, t0
; RV32I-NEXT: .LBB16_134:
-; RV32I-NEXT: li s3, 5
+; RV32I-NEXT: mv s11, a5
; RV32I-NEXT: sll t1, t2, a1
; RV32I-NEXT: li t6, 2
-; RV32I-NEXT: mv s11, s7
+; RV32I-NEXT: mv a5, s7
; RV32I-NEXT: beqz a4, .LBB16_142
; RV32I-NEXT: # %bb.135:
; RV32I-NEXT: li t3, 0
@@ -8065,7 +8050,7 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw
; RV32I-NEXT: li s8, 2
; RV32I-NEXT: bne a4, s3, .LBB16_156
; RV32I-NEXT: .LBB16_155:
-; RV32I-NEXT: or t3, s11, a3
+; RV32I-NEXT: or t3, a5, a3
; RV32I-NEXT: .LBB16_156:
; RV32I-NEXT: lbu t6, 31(a0)
; RV32I-NEXT: mv a3, t4
@@ -8125,7 +8110,7 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: beqz t5, .LBB16_152
; RV32I-NEXT: .LBB16_170:
-; RV32I-NEXT: mv a3, a5
+; RV32I-NEXT: mv a3, s10
; RV32I-NEXT: bne a4, s8, .LBB16_153
; RV32I-NEXT: .LBB16_171:
; RV32I-NEXT: lw t3, 8(sp) # 4-byte Folded Reload
@@ -8185,11 +8170,11 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw
; RV32I-NEXT: .LBB16_190:
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: srli a3, s10, 16
-; RV32I-NEXT: and a4, s10, a1
-; RV32I-NEXT: srli a6, s10, 24
+; RV32I-NEXT: srli a3, s11, 16
+; RV32I-NEXT: and a4, s11, a1
+; RV32I-NEXT: srli a6, s11, 24
; RV32I-NEXT: srli a4, a4, 8
-; RV32I-NEXT: sb s10, 0(a2)
+; RV32I-NEXT: sb s11, 0(a2)
; RV32I-NEXT: sb a4, 1(a2)
; RV32I-NEXT: sb a3, 2(a2)
; RV32I-NEXT: sb a6, 3(a2)
@@ -8289,18 +8274,18 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: beqz t5, .LBB16_184
; RV32I-NEXT: .LBB16_197:
-; RV32I-NEXT: mv a3, a5
+; RV32I-NEXT: mv a3, s10
; RV32I-NEXT: bne a4, t6, .LBB16_185
; RV32I-NEXT: .LBB16_198:
-; RV32I-NEXT: lw a5, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: or t2, a5, a3
+; RV32I-NEXT: lw a6, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: or t2, a6, a3
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: beqz t5, .LBB16_186
; RV32I-NEXT: .LBB16_199:
; RV32I-NEXT: mv a3, s7
; RV32I-NEXT: bne a4, s0, .LBB16_187
; RV32I-NEXT: .LBB16_200:
-; RV32I-NEXT: or t2, s11, a3
+; RV32I-NEXT: or t2, a5, a3
; RV32I-NEXT: li a3, 7
; RV32I-NEXT: beq a4, a3, .LBB16_188
; RV32I-NEXT: .LBB16_201:
@@ -8662,21 +8647,21 @@ define void @shl_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) nou
; RV32I-NEXT: srli a4, a1, 5
; RV32I-NEXT: sll t4, a5, a1
; RV32I-NEXT: li s4, 1
-; RV32I-NEXT: mv a6, t4
+; RV32I-NEXT: mv a3, t4
; RV32I-NEXT: beqz a4, .LBB17_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: .LBB17_2:
; RV32I-NEXT: li a3, 0
+; RV32I-NEXT: .LBB17_2:
+; RV32I-NEXT: li a6, 0
; RV32I-NEXT: li t6, 2
; RV32I-NEXT: beq a4, s4, .LBB17_4
; RV32I-NEXT: # %bb.3:
-; RV32I-NEXT: mv a3, a6
+; RV32I-NEXT: mv a6, a3
; RV32I-NEXT: .LBB17_4:
; RV32I-NEXT: li a7, 0
; RV32I-NEXT: beq a4, t6, .LBB17_6
; RV32I-NEXT: # %bb.5:
-; RV32I-NEXT: mv a7, a3
+; RV32I-NEXT: mv a7, a6
; RV32I-NEXT: .LBB17_6:
; RV32I-NEXT: li a6, 0
; RV32I-NEXT: li s8, 3
@@ -9550,12 +9535,12 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: or a5, t1, t3
; RV64I-NEXT: slli a7, a7, 3
; RV64I-NEXT: li t1, 64
-; RV64I-NEXT: neg t3, a7
-; RV64I-NEXT: sub t4, a7, t1
-; RV64I-NEXT: sll t5, a5, t3
+; RV64I-NEXT: neg t4, a7
+; RV64I-NEXT: sub t3, a7, t1
+; RV64I-NEXT: sll t5, a5, t4
; RV64I-NEXT: bltu a7, t1, .LBB18_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: sra t6, a5, t4
+; RV64I-NEXT: sra t6, a5, t3
; RV64I-NEXT: j .LBB18_3
; RV64I-NEXT: .LBB18_2:
; RV64I-NEXT: srl t6, a3, a7
@@ -9575,36 +9560,36 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: bltu a7, t1, .LBB18_7
; RV64I-NEXT: # %bb.6:
; RV64I-NEXT: srai a0, a5, 63
-; RV64I-NEXT: srl t4, a4, t4
+; RV64I-NEXT: srl t3, a4, t3
; RV64I-NEXT: j .LBB18_8
; RV64I-NEXT: .LBB18_7:
; RV64I-NEXT: srl t0, a6, a7
-; RV64I-NEXT: sll t2, a4, t3
+; RV64I-NEXT: sll t2, a4, t4
; RV64I-NEXT: sra a0, a5, a7
-; RV64I-NEXT: or t4, t0, t2
+; RV64I-NEXT: or t3, t0, t2
; RV64I-NEXT: .LBB18_8:
; RV64I-NEXT: li t0, 128
; RV64I-NEXT: mv t2, a6
; RV64I-NEXT: beqz a7, .LBB18_10
; RV64I-NEXT: # %bb.9:
-; RV64I-NEXT: mv t2, t4
+; RV64I-NEXT: mv t2, t3
; RV64I-NEXT: .LBB18_10:
; RV64I-NEXT: sub t6, t0, a7
; RV64I-NEXT: bltu a7, t1, .LBB18_13
; RV64I-NEXT: # %bb.11:
-; RV64I-NEXT: li t4, 0
+; RV64I-NEXT: li t3, 0
; RV64I-NEXT: bgeu t6, t1, .LBB18_14
; RV64I-NEXT: .LBB18_12:
; RV64I-NEXT: neg s0, t6
; RV64I-NEXT: srl s0, a3, s0
-; RV64I-NEXT: sll t3, a3, t3
+; RV64I-NEXT: sll t4, a3, t4
; RV64I-NEXT: or s1, s0, t5
; RV64I-NEXT: j .LBB18_15
; RV64I-NEXT: .LBB18_13:
-; RV64I-NEXT: srl t4, a4, a7
+; RV64I-NEXT: srl t3, a4, a7
; RV64I-NEXT: bltu t6, t1, .LBB18_12
; RV64I-NEXT: .LBB18_14:
-; RV64I-NEXT: li t3, 0
+; RV64I-NEXT: li t4, 0
; RV64I-NEXT: sub t5, t6, t1
; RV64I-NEXT: sll s1, a3, t5
; RV64I-NEXT: .LBB18_15:
@@ -9638,8 +9623,8 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: sra t1, a5, s0
; RV64I-NEXT: bgeu a7, t0, .LBB18_25
; RV64I-NEXT: .LBB18_24:
-; RV64I-NEXT: or a3, t2, t3
-; RV64I-NEXT: or t1, t4, t5
+; RV64I-NEXT: or a3, t2, t4
+; RV64I-NEXT: or t1, t3, t5
; RV64I-NEXT: .LBB18_25:
; RV64I-NEXT: bnez a7, .LBB18_29
; RV64I-NEXT: # %bb.26:
@@ -9871,75 +9856,75 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lbu s9, 25(a0)
; RV32I-NEXT: lbu s8, 26(a0)
; RV32I-NEXT: slli t6, t6, 8
-; RV32I-NEXT: or s7, s7, t5
-; RV32I-NEXT: slli s10, s6, 16
+; RV32I-NEXT: or s10, s7, t5
+; RV32I-NEXT: slli s6, s6, 16
; RV32I-NEXT: sll t5, t2, s3
; RV32I-NEXT: beqz t4, .LBB18_15
; RV32I-NEXT: # %bb.14:
; RV32I-NEXT: mv t3, t5
; RV32I-NEXT: .LBB18_15:
-; RV32I-NEXT: lbu s6, 24(a0)
+; RV32I-NEXT: lbu s7, 24(a0)
; RV32I-NEXT: slli s9, s9, 8
; RV32I-NEXT: or s8, t6, s8
-; RV32I-NEXT: srl t6, a7, a5
-; RV32I-NEXT: or a0, s10, s7
-; RV32I-NEXT: li s7, 3
-; RV32I-NEXT: bne t0, s7, .LBB18_17
+; RV32I-NEXT: srl s11, a7, a5
+; RV32I-NEXT: or a0, s6, s10
+; RV32I-NEXT: li t6, 3
+; RV32I-NEXT: bne t0, t6, .LBB18_17
; RV32I-NEXT: # %bb.16:
-; RV32I-NEXT: or a6, t6, t3
+; RV32I-NEXT: or a6, s11, t3
; RV32I-NEXT: .LBB18_17:
-; RV32I-NEXT: li s7, 0
-; RV32I-NEXT: or t3, s9, s6
+; RV32I-NEXT: li s6, 0
+; RV32I-NEXT: or t3, s9, s7
; RV32I-NEXT: slli s8, s8, 16
-; RV32I-NEXT: li s6, 4
-; RV32I-NEXT: sll s9, a0, s3
-; RV32I-NEXT: sw s9, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: li s7, 4
+; RV32I-NEXT: sll t6, a0, s3
+; RV32I-NEXT: sw t6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz t4, .LBB18_19
; RV32I-NEXT: # %bb.18:
-; RV32I-NEXT: lw s7, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB18_19:
; RV32I-NEXT: srl ra, t2, a5
; RV32I-NEXT: or t3, s8, t3
-; RV32I-NEXT: bne t0, s6, .LBB18_21
+; RV32I-NEXT: bne t0, s7, .LBB18_21
; RV32I-NEXT: # %bb.20:
-; RV32I-NEXT: or a6, ra, s7
+; RV32I-NEXT: or a6, ra, s6
; RV32I-NEXT: .LBB18_21:
; RV32I-NEXT: li s6, 0
-; RV32I-NEXT: li s8, 5
-; RV32I-NEXT: sll s7, t3, s3
-; RV32I-NEXT: sw s7, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: li s7, 5
+; RV32I-NEXT: sll t6, t3, s3
+; RV32I-NEXT: sw t6, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz t4, .LBB18_23
; RV32I-NEXT: # %bb.22:
; RV32I-NEXT: lw s6, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB18_23:
-; RV32I-NEXT: srl s7, a0, a5
-; RV32I-NEXT: beq t0, s8, .LBB18_25
+; RV32I-NEXT: srl t6, a0, a5
+; RV32I-NEXT: beq t0, s7, .LBB18_25
; RV32I-NEXT: # %bb.24:
-; RV32I-NEXT: mv s11, s7
+; RV32I-NEXT: mv s10, t6
; RV32I-NEXT: j .LBB18_26
; RV32I-NEXT: .LBB18_25:
-; RV32I-NEXT: mv s11, s7
-; RV32I-NEXT: or a6, s7, s6
+; RV32I-NEXT: mv s10, t6
+; RV32I-NEXT: or a6, t6, s6
; RV32I-NEXT: .LBB18_26:
; RV32I-NEXT: li s6, 0
; RV32I-NEXT: li s9, 6
-; RV32I-NEXT: sll s10, a1, s3
-; RV32I-NEXT: sw s10, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sll s8, a1, s3
+; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz t4, .LBB18_28
; RV32I-NEXT: # %bb.27:
; RV32I-NEXT: lw s6, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB18_28:
-; RV32I-NEXT: mv s10, a3
-; RV32I-NEXT: srl s7, t3, a5
+; RV32I-NEXT: mv s8, a3
+; RV32I-NEXT: srl t6, t3, a5
; RV32I-NEXT: beq t0, s9, .LBB18_30
; RV32I-NEXT: # %bb.29:
-; RV32I-NEXT: mv s9, s7
+; RV32I-NEXT: mv s9, t6
; RV32I-NEXT: mv a3, s5
; RV32I-NEXT: j .LBB18_31
; RV32I-NEXT: .LBB18_30:
; RV32I-NEXT: mv a3, s5
-; RV32I-NEXT: mv s9, s7
-; RV32I-NEXT: or a6, s7, s6
+; RV32I-NEXT: mv s9, t6
+; RV32I-NEXT: or a6, t6, s6
; RV32I-NEXT: .LBB18_31:
; RV32I-NEXT: li s5, 0
; RV32I-NEXT: sll s3, t1, s3
@@ -9948,19 +9933,19 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: mv s5, s3
; RV32I-NEXT: .LBB18_33:
; RV32I-NEXT: srl s6, a1, a5
-; RV32I-NEXT: li s7, 7
-; RV32I-NEXT: bne t0, s7, .LBB18_35
+; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: bne t0, t6, .LBB18_35
; RV32I-NEXT: # %bb.34:
; RV32I-NEXT: or a6, s6, s5
; RV32I-NEXT: .LBB18_35:
; RV32I-NEXT: mv s5, a3
-; RV32I-NEXT: mv a3, s10
+; RV32I-NEXT: mv a3, s8
; RV32I-NEXT: beqz a5, .LBB18_37
; RV32I-NEXT: # %bb.36:
; RV32I-NEXT: mv s5, a6
; RV32I-NEXT: .LBB18_37:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: li s7, 1
+; RV32I-NEXT: li t6, 1
; RV32I-NEXT: beqz t4, .LBB18_39
; RV32I-NEXT: # %bb.38:
; RV32I-NEXT: mv a6, s2
@@ -9976,7 +9961,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB18_66
; RV32I-NEXT: # %bb.43:
-; RV32I-NEXT: beq t0, s7, .LBB18_67
+; RV32I-NEXT: beq t0, t6, .LBB18_67
; RV32I-NEXT: .LBB18_44:
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB18_68
@@ -9986,37 +9971,37 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB18_70
; RV32I-NEXT: .LBB18_47:
-; RV32I-NEXT: li s10, 3
-; RV32I-NEXT: bne t0, s10, .LBB18_49
+; RV32I-NEXT: li s8, 3
+; RV32I-NEXT: bne t0, s8, .LBB18_49
; RV32I-NEXT: .LBB18_48:
; RV32I-NEXT: or a6, ra, s2
; RV32I-NEXT: .LBB18_49:
; RV32I-NEXT: li s2, 0
-; RV32I-NEXT: li s10, 4
+; RV32I-NEXT: li s8, 4
; RV32I-NEXT: bnez t4, .LBB18_71
; RV32I-NEXT: # %bb.50:
-; RV32I-NEXT: beq t0, s10, .LBB18_72
+; RV32I-NEXT: beq t0, s8, .LBB18_72
; RV32I-NEXT: .LBB18_51:
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB18_73
; RV32I-NEXT: .LBB18_52:
-; RV32I-NEXT: bne t0, s8, .LBB18_54
+; RV32I-NEXT: bne t0, s7, .LBB18_54
; RV32I-NEXT: .LBB18_53:
; RV32I-NEXT: or a6, s9, s2
; RV32I-NEXT: .LBB18_54:
; RV32I-NEXT: li s2, 0
-; RV32I-NEXT: li s8, 6
+; RV32I-NEXT: li s7, 6
; RV32I-NEXT: beqz t4, .LBB18_56
; RV32I-NEXT: # %bb.55:
; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: .LBB18_56:
-; RV32I-NEXT: bne t0, s8, .LBB18_58
+; RV32I-NEXT: bne t0, s7, .LBB18_58
; RV32I-NEXT: # %bb.57:
; RV32I-NEXT: or a6, s6, s2
; RV32I-NEXT: .LBB18_58:
; RV32I-NEXT: mv s2, t1
-; RV32I-NEXT: li s10, 7
-; RV32I-NEXT: beq t0, s10, .LBB18_60
+; RV32I-NEXT: li s8, 7
+; RV32I-NEXT: beq t0, s8, .LBB18_60
; RV32I-NEXT: # %bb.59:
; RV32I-NEXT: mv s2, a6
; RV32I-NEXT: .LBB18_60:
@@ -10025,7 +10010,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: .LBB18_62:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: li s10, 4
+; RV32I-NEXT: li s8, 4
; RV32I-NEXT: beqz t4, .LBB18_64
; RV32I-NEXT: # %bb.63:
; RV32I-NEXT: mv a6, s0
@@ -10037,7 +10022,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: j .LBB18_75
; RV32I-NEXT: .LBB18_66:
; RV32I-NEXT: mv s2, s0
-; RV32I-NEXT: bne t0, s7, .LBB18_44
+; RV32I-NEXT: bne t0, t6, .LBB18_44
; RV32I-NEXT: .LBB18_67:
; RV32I-NEXT: or a6, s1, s2
; RV32I-NEXT: li s2, 0
@@ -10046,123 +10031,129 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: mv s2, t5
; RV32I-NEXT: bne t0, s4, .LBB18_46
; RV32I-NEXT: .LBB18_69:
-; RV32I-NEXT: or a6, t6, s2
+; RV32I-NEXT: or a6, s11, s2
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: beqz t4, .LBB18_47
; RV32I-NEXT: .LBB18_70:
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
-; RV32I-NEXT: li s10, 3
-; RV32I-NEXT: beq t0, s10, .LBB18_48
+; RV32I-NEXT: li s8, 3
+; RV32I-NEXT: beq t0, s8, .LBB18_48
; RV32I-NEXT: j .LBB18_49
; RV32I-NEXT: .LBB18_71:
; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne t0, s10, .LBB18_51
+; RV32I-NEXT: bne t0, s8, .LBB18_51
; RV32I-NEXT: .LBB18_72:
-; RV32I-NEXT: or a6, s11, s2
+; RV32I-NEXT: or a6, s10, s2
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: beqz t4, .LBB18_52
; RV32I-NEXT: .LBB18_73:
; RV32I-NEXT: lw s2, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: beq t0, s8, .LBB18_53
+; RV32I-NEXT: beq t0, s7, .LBB18_53
; RV32I-NEXT: j .LBB18_54
; RV32I-NEXT: .LBB18_74:
; RV32I-NEXT: or a6, s1, a6
; RV32I-NEXT: .LBB18_75:
; RV32I-NEXT: li s1, 3
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB18_95
+; RV32I-NEXT: bnez t4, .LBB18_92
; RV32I-NEXT: # %bb.76:
-; RV32I-NEXT: beq t0, s7, .LBB18_96
+; RV32I-NEXT: beq t0, t6, .LBB18_93
; RV32I-NEXT: .LBB18_77:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB18_97
+; RV32I-NEXT: bnez t4, .LBB18_94
; RV32I-NEXT: .LBB18_78:
-; RV32I-NEXT: beq t0, s4, .LBB18_98
+; RV32I-NEXT: beq t0, s4, .LBB18_95
; RV32I-NEXT: .LBB18_79:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB18_99
+; RV32I-NEXT: bnez t4, .LBB18_96
; RV32I-NEXT: .LBB18_80:
-; RV32I-NEXT: beq t0, s1, .LBB18_100
+; RV32I-NEXT: beq t0, s1, .LBB18_97
; RV32I-NEXT: .LBB18_81:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB18_101
+; RV32I-NEXT: bnez t4, .LBB18_98
; RV32I-NEXT: .LBB18_82:
-; RV32I-NEXT: beq t0, s10, .LBB18_102
+; RV32I-NEXT: beq t0, s8, .LBB18_99
; RV32I-NEXT: .LBB18_83:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB18_103
+; RV32I-NEXT: bnez t4, .LBB18_100
; RV32I-NEXT: .LBB18_84:
-; RV32I-NEXT: beq t0, s2, .LBB18_104
+; RV32I-NEXT: beq t0, s2, .LBB18_101
; RV32I-NEXT: .LBB18_85:
; RV32I-NEXT: mv s0, t1
-; RV32I-NEXT: beq t0, s8, .LBB18_87
+; RV32I-NEXT: beq t0, s7, .LBB18_87
; RV32I-NEXT: .LBB18_86:
; RV32I-NEXT: mv s0, a6
; RV32I-NEXT: .LBB18_87:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: li s7, 7
-; RV32I-NEXT: beq t0, s7, .LBB18_89
+; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: bne t0, t6, .LBB18_102
; RV32I-NEXT: # %bb.88:
-; RV32I-NEXT: mv a6, s0
+; RV32I-NEXT: bnez a5, .LBB18_103
; RV32I-NEXT: .LBB18_89:
-; RV32I-NEXT: beqz a5, .LBB18_91
-; RV32I-NEXT: # %bb.90:
-; RV32I-NEXT: mv a4, a6
-; RV32I-NEXT: .LBB18_91:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: li s0, 1
-; RV32I-NEXT: beqz t4, .LBB18_93
-; RV32I-NEXT: # %bb.92:
-; RV32I-NEXT: mv a6, t5
-; RV32I-NEXT: .LBB18_93:
+; RV32I-NEXT: bnez t4, .LBB18_104
+; RV32I-NEXT: .LBB18_90:
+; RV32I-NEXT: li s0, 7
; RV32I-NEXT: beqz t0, .LBB18_105
-; RV32I-NEXT: # %bb.94:
+; RV32I-NEXT: .LBB18_91:
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: j .LBB18_106
-; RV32I-NEXT: .LBB18_95:
+; RV32I-NEXT: .LBB18_92:
; RV32I-NEXT: mv s0, t5
-; RV32I-NEXT: bne t0, s7, .LBB18_77
-; RV32I-NEXT: .LBB18_96:
-; RV32I-NEXT: or a6, t6, s0
+; RV32I-NEXT: bne t0, t6, .LBB18_77
+; RV32I-NEXT: .LBB18_93:
+; RV32I-NEXT: or a6, s11, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB18_78
-; RV32I-NEXT: .LBB18_97:
+; RV32I-NEXT: .LBB18_94:
; RV32I-NEXT: lw s0, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s4, .LBB18_79
-; RV32I-NEXT: .LBB18_98:
+; RV32I-NEXT: .LBB18_95:
; RV32I-NEXT: or a6, ra, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB18_80
-; RV32I-NEXT: .LBB18_99:
+; RV32I-NEXT: .LBB18_96:
; RV32I-NEXT: lw s0, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s1, .LBB18_81
-; RV32I-NEXT: .LBB18_100:
-; RV32I-NEXT: or a6, s11, s0
+; RV32I-NEXT: .LBB18_97:
+; RV32I-NEXT: or a6, s10, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB18_82
-; RV32I-NEXT: .LBB18_101:
+; RV32I-NEXT: .LBB18_98:
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne t0, s10, .LBB18_83
-; RV32I-NEXT: .LBB18_102:
+; RV32I-NEXT: bne t0, s8, .LBB18_83
+; RV32I-NEXT: .LBB18_99:
; RV32I-NEXT: or a6, s9, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB18_84
-; RV32I-NEXT: .LBB18_103:
+; RV32I-NEXT: .LBB18_100:
; RV32I-NEXT: mv s0, s3
; RV32I-NEXT: bne t0, s2, .LBB18_85
-; RV32I-NEXT: .LBB18_104:
+; RV32I-NEXT: .LBB18_101:
; RV32I-NEXT: or a6, s6, s0
; RV32I-NEXT: mv s0, t1
-; RV32I-NEXT: bne t0, s8, .LBB18_86
+; RV32I-NEXT: bne t0, s7, .LBB18_86
; RV32I-NEXT: j .LBB18_87
+; RV32I-NEXT: .LBB18_102:
+; RV32I-NEXT: mv a6, s0
+; RV32I-NEXT: beqz a5, .LBB18_89
+; RV32I-NEXT: .LBB18_103:
+; RV32I-NEXT: mv a4, a6
+; RV32I-NEXT: li a6, 0
+; RV32I-NEXT: beqz t4, .LBB18_90
+; RV32I-NEXT: .LBB18_104:
+; RV32I-NEXT: mv a6, t5
+; RV32I-NEXT: li s0, 7
+; RV32I-NEXT: bnez t0, .LBB18_91
; RV32I-NEXT: .LBB18_105:
-; RV32I-NEXT: or a6, t6, a6
+; RV32I-NEXT: or a6, s11, a6
; RV32I-NEXT: .LBB18_106:
-; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: mv t6, s9
; RV32I-NEXT: li t5, 0
+; RV32I-NEXT: li s9, 1
; RV32I-NEXT: bnez t4, .LBB18_121
; RV32I-NEXT: # %bb.107:
-; RV32I-NEXT: beq t0, s0, .LBB18_122
+; RV32I-NEXT: beq t0, s9, .LBB18_122
; RV32I-NEXT: .LBB18_108:
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB18_123
@@ -10177,16 +10168,16 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB18_127
; RV32I-NEXT: .LBB18_113:
-; RV32I-NEXT: beq t0, s10, .LBB18_128
+; RV32I-NEXT: beq t0, s8, .LBB18_128
; RV32I-NEXT: .LBB18_114:
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: bne t0, s2, .LBB18_129
; RV32I-NEXT: .LBB18_115:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s8, .LBB18_130
+; RV32I-NEXT: bne t0, s7, .LBB18_130
; RV32I-NEXT: .LBB18_116:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, t6, .LBB18_131
+; RV32I-NEXT: bne t0, s0, .LBB18_131
; RV32I-NEXT: .LBB18_117:
; RV32I-NEXT: bnez a5, .LBB18_132
; RV32I-NEXT: .LBB18_118:
@@ -10201,7 +10192,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: j .LBB18_136
; RV32I-NEXT: .LBB18_121:
; RV32I-NEXT: lw t5, 0(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne t0, s0, .LBB18_108
+; RV32I-NEXT: bne t0, s9, .LBB18_108
; RV32I-NEXT: .LBB18_122:
; RV32I-NEXT: or a6, ra, t5
; RV32I-NEXT: li t5, 0
@@ -10210,19 +10201,19 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s4, .LBB18_110
; RV32I-NEXT: .LBB18_124:
-; RV32I-NEXT: or a6, s11, t5
+; RV32I-NEXT: or a6, s10, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB18_111
; RV32I-NEXT: .LBB18_125:
; RV32I-NEXT: lw t5, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s1, .LBB18_112
; RV32I-NEXT: .LBB18_126:
-; RV32I-NEXT: or a6, s9, t5
+; RV32I-NEXT: or a6, t6, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB18_113
; RV32I-NEXT: .LBB18_127:
; RV32I-NEXT: mv t5, s3
-; RV32I-NEXT: bne t0, s10, .LBB18_114
+; RV32I-NEXT: bne t0, s8, .LBB18_114
; RV32I-NEXT: .LBB18_128:
; RV32I-NEXT: or a6, s6, t5
; RV32I-NEXT: mv t5, t1
@@ -10230,11 +10221,11 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: .LBB18_129:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s8, .LBB18_116
+; RV32I-NEXT: beq t0, s7, .LBB18_116
; RV32I-NEXT: .LBB18_130:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, t6, .LBB18_117
+; RV32I-NEXT: beq t0, s0, .LBB18_117
; RV32I-NEXT: .LBB18_131:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: beqz a5, .LBB18_118
@@ -10252,7 +10243,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: .LBB18_135:
; RV32I-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB18_136:
-; RV32I-NEXT: beq t0, s0, .LBB18_149
+; RV32I-NEXT: beq t0, s9, .LBB18_149
; RV32I-NEXT: # %bb.137:
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB18_150
@@ -10265,16 +10256,16 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: beq t0, s1, .LBB18_153
; RV32I-NEXT: .LBB18_141:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s10, .LBB18_154
+; RV32I-NEXT: bne t0, s8, .LBB18_154
; RV32I-NEXT: .LBB18_142:
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: bne t0, s2, .LBB18_155
; RV32I-NEXT: .LBB18_143:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s8, .LBB18_156
+; RV32I-NEXT: bne t0, s7, .LBB18_156
; RV32I-NEXT: .LBB18_144:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, t6, .LBB18_157
+; RV32I-NEXT: bne t0, s0, .LBB18_157
; RV32I-NEXT: .LBB18_145:
; RV32I-NEXT: bnez a5, .LBB18_158
; RV32I-NEXT: .LBB18_146:
@@ -10288,14 +10279,14 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: bnez t4, .LBB18_161
; RV32I-NEXT: j .LBB18_162
; RV32I-NEXT: .LBB18_149:
-; RV32I-NEXT: or a6, s11, t5
+; RV32I-NEXT: or a6, s10, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB18_138
; RV32I-NEXT: .LBB18_150:
; RV32I-NEXT: lw t5, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s4, .LBB18_139
; RV32I-NEXT: .LBB18_151:
-; RV32I-NEXT: or a6, s9, t5
+; RV32I-NEXT: or a6, t6, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB18_140
; RV32I-NEXT: .LBB18_152:
@@ -10304,7 +10295,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: .LBB18_153:
; RV32I-NEXT: or a6, s6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s10, .LBB18_142
+; RV32I-NEXT: beq t0, s8, .LBB18_142
; RV32I-NEXT: .LBB18_154:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
@@ -10312,11 +10303,11 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: .LBB18_155:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s8, .LBB18_144
+; RV32I-NEXT: beq t0, s7, .LBB18_144
; RV32I-NEXT: .LBB18_156:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, t6, .LBB18_145
+; RV32I-NEXT: beq t0, s0, .LBB18_145
; RV32I-NEXT: .LBB18_157:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: beqz a5, .LBB18_146
@@ -10328,13 +10319,13 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lw a6, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: bnez t0, .LBB18_148
; RV32I-NEXT: .LBB18_160:
-; RV32I-NEXT: or a6, s11, a6
+; RV32I-NEXT: or a6, s10, a6
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB18_162
; RV32I-NEXT: .LBB18_161:
; RV32I-NEXT: lw t5, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB18_162:
-; RV32I-NEXT: beq t0, s0, .LBB18_174
+; RV32I-NEXT: beq t0, s9, .LBB18_174
; RV32I-NEXT: # %bb.163:
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB18_175
@@ -10345,16 +10336,16 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: bne t0, s1, .LBB18_177
; RV32I-NEXT: .LBB18_166:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s10, .LBB18_178
+; RV32I-NEXT: bne t0, s8, .LBB18_178
; RV32I-NEXT: .LBB18_167:
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: bne t0, s2, .LBB18_179
; RV32I-NEXT: .LBB18_168:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s8, .LBB18_180
+; RV32I-NEXT: bne t0, s7, .LBB18_180
; RV32I-NEXT: .LBB18_169:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, t6, .LBB18_181
+; RV32I-NEXT: bne t0, s0, .LBB18_181
; RV32I-NEXT: .LBB18_170:
; RV32I-NEXT: bnez a5, .LBB18_182
; RV32I-NEXT: .LBB18_171:
@@ -10364,11 +10355,9 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: beqz t0, .LBB18_184
; RV32I-NEXT: .LBB18_173:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: li t5, 0
-; RV32I-NEXT: bnez t4, .LBB18_185
-; RV32I-NEXT: j .LBB18_186
+; RV32I-NEXT: j .LBB18_185
; RV32I-NEXT: .LBB18_174:
-; RV32I-NEXT: or a6, s9, t5
+; RV32I-NEXT: or a6, t6, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB18_164
; RV32I-NEXT: .LBB18_175:
@@ -10381,7 +10370,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: .LBB18_177:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s10, .LBB18_167
+; RV32I-NEXT: beq t0, s8, .LBB18_167
; RV32I-NEXT: .LBB18_178:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
@@ -10389,11 +10378,11 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: .LBB18_179:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s8, .LBB18_169
+; RV32I-NEXT: beq t0, s7, .LBB18_169
; RV32I-NEXT: .LBB18_180:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, t6, .LBB18_170
+; RV32I-NEXT: beq t0, s0, .LBB18_170
; RV32I-NEXT: .LBB18_181:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: beqz a5, .LBB18_171
@@ -10405,105 +10394,108 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lw a6, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: bnez t0, .LBB18_173
; RV32I-NEXT: .LBB18_184:
-; RV32I-NEXT: or a6, s9, a6
-; RV32I-NEXT: li t5, 0
-; RV32I-NEXT: beqz t4, .LBB18_186
+; RV32I-NEXT: or a6, t6, a6
; RV32I-NEXT: .LBB18_185:
-; RV32I-NEXT: mv t5, s3
-; RV32I-NEXT: .LBB18_186:
-; RV32I-NEXT: beq t0, s0, .LBB18_197
-; RV32I-NEXT: # %bb.187:
+; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: li t5, 0
+; RV32I-NEXT: bnez t4, .LBB18_197
+; RV32I-NEXT: # %bb.186:
+; RV32I-NEXT: beq t0, s9, .LBB18_198
+; RV32I-NEXT: .LBB18_187:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s4, .LBB18_198
+; RV32I-NEXT: bne t0, s4, .LBB18_199
; RV32I-NEXT: .LBB18_188:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s1, .LBB18_199
+; RV32I-NEXT: bne t0, s1, .LBB18_200
; RV32I-NEXT: .LBB18_189:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s10, .LBB18_200
+; RV32I-NEXT: bne t0, s8, .LBB18_201
; RV32I-NEXT: .LBB18_190:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s2, .LBB18_201
+; RV32I-NEXT: bne t0, s2, .LBB18_202
; RV32I-NEXT: .LBB18_191:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s8, .LBB18_202
+; RV32I-NEXT: bne t0, s7, .LBB18_203
; RV32I-NEXT: .LBB18_192:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, t6, .LBB18_203
+; RV32I-NEXT: bne t0, t6, .LBB18_204
; RV32I-NEXT: .LBB18_193:
-; RV32I-NEXT: bnez a5, .LBB18_204
+; RV32I-NEXT: bnez a5, .LBB18_205
; RV32I-NEXT: .LBB18_194:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: bnez t4, .LBB18_205
+; RV32I-NEXT: bnez t4, .LBB18_206
; RV32I-NEXT: .LBB18_195:
-; RV32I-NEXT: beqz t0, .LBB18_206
+; RV32I-NEXT: beqz t0, .LBB18_207
; RV32I-NEXT: .LBB18_196:
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: bne t0, s0, .LBB18_207
-; RV32I-NEXT: j .LBB18_208
+; RV32I-NEXT: bne t0, s9, .LBB18_208
+; RV32I-NEXT: j .LBB18_209
; RV32I-NEXT: .LBB18_197:
+; RV32I-NEXT: mv t5, s3
+; RV32I-NEXT: bne t0, s9, .LBB18_187
+; RV32I-NEXT: .LBB18_198:
; RV32I-NEXT: or a6, s6, t5
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: beq t0, s4, .LBB18_188
-; RV32I-NEXT: .LBB18_198:
+; RV32I-NEXT: .LBB18_199:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: beq t0, s1, .LBB18_189
-; RV32I-NEXT: .LBB18_199:
+; RV32I-NEXT: .LBB18_200:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s10, .LBB18_190
-; RV32I-NEXT: .LBB18_200:
+; RV32I-NEXT: beq t0, s8, .LBB18_190
+; RV32I-NEXT: .LBB18_201:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: beq t0, s2, .LBB18_191
-; RV32I-NEXT: .LBB18_201:
+; RV32I-NEXT: .LBB18_202:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s8, .LBB18_192
-; RV32I-NEXT: .LBB18_202:
+; RV32I-NEXT: beq t0, s7, .LBB18_192
+; RV32I-NEXT: .LBB18_203:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: beq t0, t6, .LBB18_193
-; RV32I-NEXT: .LBB18_203:
+; RV32I-NEXT: .LBB18_204:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: beqz a5, .LBB18_194
-; RV32I-NEXT: .LBB18_204:
+; RV32I-NEXT: .LBB18_205:
; RV32I-NEXT: mv t3, a6
; RV32I-NEXT: li a6, 0
; RV32I-NEXT: beqz t4, .LBB18_195
-; RV32I-NEXT: .LBB18_205:
+; RV32I-NEXT: .LBB18_206:
; RV32I-NEXT: mv a6, s3
; RV32I-NEXT: bnez t0, .LBB18_196
-; RV32I-NEXT: .LBB18_206:
+; RV32I-NEXT: .LBB18_207:
; RV32I-NEXT: or a6, s6, a6
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: beq t0, s0, .LBB18_208
-; RV32I-NEXT: .LBB18_207:
-; RV32I-NEXT: mv t4, a6
+; RV32I-NEXT: beq t0, s9, .LBB18_209
; RV32I-NEXT: .LBB18_208:
+; RV32I-NEXT: mv t4, a6
+; RV32I-NEXT: .LBB18_209:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s4, .LBB18_217
-; RV32I-NEXT: # %bb.209:
+; RV32I-NEXT: bne t0, s4, .LBB18_218
+; RV32I-NEXT: # %bb.210:
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: bne t0, s1, .LBB18_218
-; RV32I-NEXT: .LBB18_210:
-; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s10, .LBB18_219
+; RV32I-NEXT: bne t0, s1, .LBB18_219
; RV32I-NEXT: .LBB18_211:
-; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: bne t0, s2, .LBB18_220
-; RV32I-NEXT: .LBB18_212:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s8, .LBB18_221
+; RV32I-NEXT: bne t0, s8, .LBB18_220
+; RV32I-NEXT: .LBB18_212:
+; RV32I-NEXT: mv t4, t1
+; RV32I-NEXT: bne t0, s2, .LBB18_221
; RV32I-NEXT: .LBB18_213:
-; RV32I-NEXT: bne t0, t6, .LBB18_222
+; RV32I-NEXT: mv a6, t1
+; RV32I-NEXT: bne t0, s7, .LBB18_222
; RV32I-NEXT: .LBB18_214:
-; RV32I-NEXT: beqz a5, .LBB18_216
+; RV32I-NEXT: bne t0, t6, .LBB18_223
; RV32I-NEXT: .LBB18_215:
-; RV32I-NEXT: mv a1, t1
+; RV32I-NEXT: beqz a5, .LBB18_217
; RV32I-NEXT: .LBB18_216:
+; RV32I-NEXT: mv a1, t1
+; RV32I-NEXT: .LBB18_217:
; RV32I-NEXT: lui a5, 16
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: srli a6, s5, 16
@@ -10585,29 +10577,29 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB18_217:
+; RV32I-NEXT: .LBB18_218:
; RV32I-NEXT: mv a6, t4
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: beq t0, s1, .LBB18_210
-; RV32I-NEXT: .LBB18_218:
+; RV32I-NEXT: beq t0, s1, .LBB18_211
+; RV32I-NEXT: .LBB18_219:
; RV32I-NEXT: mv t4, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s10, .LBB18_211
-; RV32I-NEXT: .LBB18_219:
+; RV32I-NEXT: beq t0, s8, .LBB18_212
+; RV32I-NEXT: .LBB18_220:
; RV32I-NEXT: mv a6, t4
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: beq t0, s2, .LBB18_212
-; RV32I-NEXT: .LBB18_220:
+; RV32I-NEXT: beq t0, s2, .LBB18_213
+; RV32I-NEXT: .LBB18_221:
; RV32I-NEXT: mv t4, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s8, .LBB18_213
-; RV32I-NEXT: .LBB18_221:
-; RV32I-NEXT: mv a6, t4
-; RV32I-NEXT: beq t0, t6, .LBB18_214
+; RV32I-NEXT: beq t0, s7, .LBB18_214
; RV32I-NEXT: .LBB18_222:
+; RV32I-NEXT: mv a6, t4
+; RV32I-NEXT: beq t0, t6, .LBB18_215
+; RV32I-NEXT: .LBB18_223:
; RV32I-NEXT: mv t1, a6
-; RV32I-NEXT: bnez a5, .LBB18_215
-; RV32I-NEXT: j .LBB18_216
+; RV32I-NEXT: bnez a5, .LBB18_216
+; RV32I-NEXT: j .LBB18_217
%src = load i256, ptr %src.ptr, align 1
%byteOff = load i256, ptr %byteOff.ptr, align 1
%bitOff = shl i256 %byteOff, 3
@@ -10731,12 +10723,12 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV64I-NEXT: or a5, t1, t3
; RV64I-NEXT: slli a7, a7, 5
; RV64I-NEXT: li t1, 64
-; RV64I-NEXT: neg t3, a7
-; RV64I-NEXT: sub t4, a7, t1
-; RV64I-NEXT: sll t5, a5, t3
+; RV64I-NEXT: neg t4, a7
+; RV64I-NEXT: sub t3, a7, t1
+; RV64I-NEXT: sll t5, a5, t4
; RV64I-NEXT: bltu a7, t1, .LBB19_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: sra t6, a5, t4
+; RV64I-NEXT: sra t6, a5, t3
; RV64I-NEXT: j .LBB19_3
; RV64I-NEXT: .LBB19_2:
; RV64I-NEXT: srl t6, a3, a7
@@ -10756,36 +10748,36 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV64I-NEXT: bltu a7, t1, .LBB19_7
; RV64I-NEXT: # %bb.6:
; RV64I-NEXT: srai a0, a5, 63
-; RV64I-NEXT: srl t4, a4, t4
+; RV64I-NEXT: srl t3, a4, t3
; RV64I-NEXT: j .LBB19_8
; RV64I-NEXT: .LBB19_7:
; RV64I-NEXT: srl t0, a6, a7
-; RV64I-NEXT: sll t2, a4, t3
+; RV64I-NEXT: sll t2, a4, t4
; RV64I-NEXT: sra a0, a5, a7
-; RV64I-NEXT: or t4, t0, t2
+; RV64I-NEXT: or t3, t0, t2
; RV64I-NEXT: .LBB19_8:
; RV64I-NEXT: li t0, 128
; RV64I-NEXT: mv t2, a6
; RV64I-NEXT: beqz a7, .LBB19_10
; RV64I-NEXT: # %bb.9:
-; RV64I-NEXT: mv t2, t4
+; RV64I-NEXT: mv t2, t3
; RV64I-NEXT: .LBB19_10:
; RV64I-NEXT: sub t6, t0, a7
; RV64I-NEXT: bltu a7, t1, .LBB19_13
; RV64I-NEXT: # %bb.11:
-; RV64I-NEXT: li t4, 0
+; RV64I-NEXT: li t3, 0
; RV64I-NEXT: bgeu t6, t1, .LBB19_14
; RV64I-NEXT: .LBB19_12:
; RV64I-NEXT: neg s0, t6
; RV64I-NEXT: srl s0, a3, s0
-; RV64I-NEXT: sll t3, a3, t3
+; RV64I-NEXT: sll t4, a3, t4
; RV64I-NEXT: or s1, s0, t5
; RV64I-NEXT: j .LBB19_15
; RV64I-NEXT: .LBB19_13:
-; RV64I-NEXT: srl t4, a4, a7
+; RV64I-NEXT: srl t3, a4, a7
; RV64I-NEXT: bltu t6, t1, .LBB19_12
; RV64I-NEXT: .LBB19_14:
-; RV64I-NEXT: li t3, 0
+; RV64I-NEXT: li t4, 0
; RV64I-NEXT: sub t5, t6, t1
; RV64I-NEXT: sll s1, a3, t5
; RV64I-NEXT: .LBB19_15:
@@ -10819,8 +10811,8 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV64I-NEXT: sra t1, a5, s0
; RV64I-NEXT: bgeu a7, t0, .LBB19_25
; RV64I-NEXT: .LBB19_24:
-; RV64I-NEXT: or a3, t2, t3
-; RV64I-NEXT: or t1, t4, t5
+; RV64I-NEXT: or a3, t2, t4
+; RV64I-NEXT: or t1, t3, t5
; RV64I-NEXT: .LBB19_25:
; RV64I-NEXT: bnez a7, .LBB19_29
; RV64I-NEXT: # %bb.26:
@@ -11052,75 +11044,75 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: lbu s9, 25(a0)
; RV32I-NEXT: lbu s8, 26(a0)
; RV32I-NEXT: slli t6, t6, 8
-; RV32I-NEXT: or s7, s7, t5
-; RV32I-NEXT: slli s10, s6, 16
+; RV32I-NEXT: or s10, s7, t5
+; RV32I-NEXT: slli s6, s6, 16
; RV32I-NEXT: sll t5, t2, s3
; RV32I-NEXT: beqz t4, .LBB19_15
; RV32I-NEXT: # %bb.14:
; RV32I-NEXT: mv t3, t5
; RV32I-NEXT: .LBB19_15:
-; RV32I-NEXT: lbu s6, 24(a0)
+; RV32I-NEXT: lbu s7, 24(a0)
; RV32I-NEXT: slli s9, s9, 8
; RV32I-NEXT: or s8, t6, s8
-; RV32I-NEXT: srl t6, a7, a5
-; RV32I-NEXT: or a0, s10, s7
-; RV32I-NEXT: li s7, 3
-; RV32I-NEXT: bne t0, s7, .LBB19_17
+; RV32I-NEXT: srl s11, a7, a5
+; RV32I-NEXT: or a0, s6, s10
+; RV32I-NEXT: li t6, 3
+; RV32I-NEXT: bne t0, t6, .LBB19_17
; RV32I-NEXT: # %bb.16:
-; RV32I-NEXT: or a6, t6, t3
+; RV32I-NEXT: or a6, s11, t3
; RV32I-NEXT: .LBB19_17:
-; RV32I-NEXT: li s7, 0
-; RV32I-NEXT: or t3, s9, s6
+; RV32I-NEXT: li s6, 0
+; RV32I-NEXT: or t3, s9, s7
; RV32I-NEXT: slli s8, s8, 16
-; RV32I-NEXT: li s6, 4
-; RV32I-NEXT: sll s9, a0, s3
-; RV32I-NEXT: sw s9, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: li s7, 4
+; RV32I-NEXT: sll t6, a0, s3
+; RV32I-NEXT: sw t6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz t4, .LBB19_19
; RV32I-NEXT: # %bb.18:
-; RV32I-NEXT: lw s7, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB19_19:
; RV32I-NEXT: srl ra, t2, a5
; RV32I-NEXT: or t3, s8, t3
-; RV32I-NEXT: bne t0, s6, .LBB19_21
+; RV32I-NEXT: bne t0, s7, .LBB19_21
; RV32I-NEXT: # %bb.20:
-; RV32I-NEXT: or a6, ra, s7
+; RV32I-NEXT: or a6, ra, s6
; RV32I-NEXT: .LBB19_21:
; RV32I-NEXT: li s6, 0
-; RV32I-NEXT: li s8, 5
-; RV32I-NEXT: sll s7, t3, s3
-; RV32I-NEXT: sw s7, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: li s7, 5
+; RV32I-NEXT: sll t6, t3, s3
+; RV32I-NEXT: sw t6, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz t4, .LBB19_23
; RV32I-NEXT: # %bb.22:
; RV32I-NEXT: lw s6, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB19_23:
-; RV32I-NEXT: srl s7, a0, a5
-; RV32I-NEXT: beq t0, s8, .LBB19_25
+; RV32I-NEXT: srl t6, a0, a5
+; RV32I-NEXT: beq t0, s7, .LBB19_25
; RV32I-NEXT: # %bb.24:
-; RV32I-NEXT: mv s11, s7
+; RV32I-NEXT: mv s10, t6
; RV32I-NEXT: j .LBB19_26
; RV32I-NEXT: .LBB19_25:
-; RV32I-NEXT: mv s11, s7
-; RV32I-NEXT: or a6, s7, s6
+; RV32I-NEXT: mv s10, t6
+; RV32I-NEXT: or a6, t6, s6
; RV32I-NEXT: .LBB19_26:
; RV32I-NEXT: li s6, 0
; RV32I-NEXT: li s9, 6
-; RV32I-NEXT: sll s10, a1, s3
-; RV32I-NEXT: sw s10, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sll s8, a1, s3
+; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz t4, .LBB19_28
; RV32I-NEXT: # %bb.27:
; RV32I-NEXT: lw s6, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB19_28:
-; RV32I-NEXT: mv s10, a3
-; RV32I-NEXT: srl s7, t3, a5
+; RV32I-NEXT: mv s8, a3
+; RV32I-NEXT: srl t6, t3, a5
; RV32I-NEXT: beq t0, s9, .LBB19_30
; RV32I-NEXT: # %bb.29:
-; RV32I-NEXT: mv s9, s7
+; RV32I-NEXT: mv s9, t6
; RV32I-NEXT: mv a3, s5
; RV32I-NEXT: j .LBB19_31
; RV32I-NEXT: .LBB19_30:
; RV32I-NEXT: mv a3, s5
-; RV32I-NEXT: mv s9, s7
-; RV32I-NEXT: or a6, s7, s6
+; RV32I-NEXT: mv s9, t6
+; RV32I-NEXT: or a6, t6, s6
; RV32I-NEXT: .LBB19_31:
; RV32I-NEXT: li s5, 0
; RV32I-NEXT: sll s3, t1, s3
@@ -11129,19 +11121,19 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: mv s5, s3
; RV32I-NEXT: .LBB19_33:
; RV32I-NEXT: srl s6, a1, a5
-; RV32I-NEXT: li s7, 7
-; RV32I-NEXT: bne t0, s7, .LBB19_35
+; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: bne t0, t6, .LBB19_35
; RV32I-NEXT: # %bb.34:
; RV32I-NEXT: or a6, s6, s5
; RV32I-NEXT: .LBB19_35:
; RV32I-NEXT: mv s5, a3
-; RV32I-NEXT: mv a3, s10
+; RV32I-NEXT: mv a3, s8
; RV32I-NEXT: beqz a5, .LBB19_37
; RV32I-NEXT: # %bb.36:
; RV32I-NEXT: mv s5, a6
; RV32I-NEXT: .LBB19_37:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: li s7, 1
+; RV32I-NEXT: li t6, 1
; RV32I-NEXT: beqz t4, .LBB19_39
; RV32I-NEXT: # %bb.38:
; RV32I-NEXT: mv a6, s2
@@ -11157,7 +11149,7 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB19_66
; RV32I-NEXT: # %bb.43:
-; RV32I-NEXT: beq t0, s7, .LBB19_67
+; RV32I-NEXT: beq t0, t6, .LBB19_67
; RV32I-NEXT: .LBB19_44:
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB19_68
@@ -11167,37 +11159,37 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB19_70
; RV32I-NEXT: .LBB19_47:
-; RV32I-NEXT: li s10, 3
-; RV32I-NEXT: bne t0, s10, .LBB19_49
+; RV32I-NEXT: li s8, 3
+; RV32I-NEXT: bne t0, s8, .LBB19_49
; RV32I-NEXT: .LBB19_48:
; RV32I-NEXT: or a6, ra, s2
; RV32I-NEXT: .LBB19_49:
; RV32I-NEXT: li s2, 0
-; RV32I-NEXT: li s10, 4
+; RV32I-NEXT: li s8, 4
; RV32I-NEXT: bnez t4, .LBB19_71
; RV32I-NEXT: # %bb.50:
-; RV32I-NEXT: beq t0, s10, .LBB19_72
+; RV32I-NEXT: beq t0, s8, .LBB19_72
; RV32I-NEXT: .LBB19_51:
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB19_73
; RV32I-NEXT: .LBB19_52:
-; RV32I-NEXT: bne t0, s8, .LBB19_54
+; RV32I-NEXT: bne t0, s7, .LBB19_54
; RV32I-NEXT: .LBB19_53:
; RV32I-NEXT: or a6, s9, s2
; RV32I-NEXT: .LBB19_54:
; RV32I-NEXT: li s2, 0
-; RV32I-NEXT: li s8, 6
+; RV32I-NEXT: li s7, 6
; RV32I-NEXT: beqz t4, .LBB19_56
; RV32I-NEXT: # %bb.55:
; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: .LBB19_56:
-; RV32I-NEXT: bne t0, s8, .LBB19_58
+; RV32I-NEXT: bne t0, s7, .LBB19_58
; RV32I-NEXT: # %bb.57:
; RV32I-NEXT: or a6, s6, s2
; RV32I-NEXT: .LBB19_58:
; RV32I-NEXT: mv s2, t1
-; RV32I-NEXT: li s10, 7
-; RV32I-NEXT: beq t0, s10, .LBB19_60
+; RV32I-NEXT: li s8, 7
+; RV32I-NEXT: beq t0, s8, .LBB19_60
; RV32I-NEXT: # %bb.59:
; RV32I-NEXT: mv s2, a6
; RV32I-NEXT: .LBB19_60:
@@ -11206,7 +11198,7 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: .LBB19_62:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: li s10, 4
+; RV32I-NEXT: li s8, 4
; RV32I-NEXT: beqz t4, .LBB19_64
; RV32I-NEXT: # %bb.63:
; RV32I-NEXT: mv a6, s0
@@ -11218,7 +11210,7 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: j .LBB19_75
; RV32I-NEXT: .LBB19_66:
; RV32I-NEXT: mv s2, s0
-; RV32I-NEXT: bne t0, s7, .LBB19_44
+; RV32I-NEXT: bne t0, t6, .LBB19_44
; RV32I-NEXT: .LBB19_67:
; RV32I-NEXT: or a6, s1, s2
; RV32I-NEXT: li s2, 0
@@ -11227,123 +11219,129 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: mv s2, t5
; RV32I-NEXT: bne t0, s4, .LBB19_46
; RV32I-NEXT: .LBB19_69:
-; RV32I-NEXT: or a6, t6, s2
+; RV32I-NEXT: or a6, s11, s2
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: beqz t4, .LBB19_47
; RV32I-NEXT: .LBB19_70:
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
-; RV32I-NEXT: li s10, 3
-; RV32I-NEXT: beq t0, s10, .LBB19_48
+; RV32I-NEXT: li s8, 3
+; RV32I-NEXT: beq t0, s8, .LBB19_48
; RV32I-NEXT: j .LBB19_49
; RV32I-NEXT: .LBB19_71:
; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne t0, s10, .LBB19_51
+; RV32I-NEXT: bne t0, s8, .LBB19_51
; RV32I-NEXT: .LBB19_72:
-; RV32I-NEXT: or a6, s11, s2
+; RV32I-NEXT: or a6, s10, s2
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: beqz t4, .LBB19_52
; RV32I-NEXT: .LBB19_73:
; RV32I-NEXT: lw s2, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: beq t0, s8, .LBB19_53
+; RV32I-NEXT: beq t0, s7, .LBB19_53
; RV32I-NEXT: j .LBB19_54
; RV32I-NEXT: .LBB19_74:
; RV32I-NEXT: or a6, s1, a6
; RV32I-NEXT: .LBB19_75:
; RV32I-NEXT: li s1, 3
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB19_95
+; RV32I-NEXT: bnez t4, .LBB19_92
; RV32I-NEXT: # %bb.76:
-; RV32I-NEXT: beq t0, s7, .LBB19_96
+; RV32I-NEXT: beq t0, t6, .LBB19_93
; RV32I-NEXT: .LBB19_77:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB19_97
+; RV32I-NEXT: bnez t4, .LBB19_94
; RV32I-NEXT: .LBB19_78:
-; RV32I-NEXT: beq t0, s4, .LBB19_98
+; RV32I-NEXT: beq t0, s4, .LBB19_95
; RV32I-NEXT: .LBB19_79:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB19_99
+; RV32I-NEXT: bnez t4, .LBB19_96
; RV32I-NEXT: .LBB19_80:
-; RV32I-NEXT: beq t0, s1, .LBB19_100
+; RV32I-NEXT: beq t0, s1, .LBB19_97
; RV32I-NEXT: .LBB19_81:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB19_101
+; RV32I-NEXT: bnez t4, .LBB19_98
; RV32I-NEXT: .LBB19_82:
-; RV32I-NEXT: beq t0, s10, .LBB19_102
+; RV32I-NEXT: beq t0, s8, .LBB19_99
; RV32I-NEXT: .LBB19_83:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB19_103
+; RV32I-NEXT: bnez t4, .LBB19_100
; RV32I-NEXT: .LBB19_84:
-; RV32I-NEXT: beq t0, s2, .LBB19_104
+; RV32I-NEXT: beq t0, s2, .LBB19_101
; RV32I-NEXT: .LBB19_85:
; RV32I-NEXT: mv s0, t1
-; RV32I-NEXT: beq t0, s8, .LBB19_87
+; RV32I-NEXT: beq t0, s7, .LBB19_87
; RV32I-NEXT: .LBB19_86:
; RV32I-NEXT: mv s0, a6
; RV32I-NEXT: .LBB19_87:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: li s7, 7
-; RV32I-NEXT: beq t0, s7, .LBB19_89
+; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: bne t0, t6, .LBB19_102
; RV32I-NEXT: # %bb.88:
-; RV32I-NEXT: mv a6, s0
+; RV32I-NEXT: bnez a5, .LBB19_103
; RV32I-NEXT: .LBB19_89:
-; RV32I-NEXT: beqz a5, .LBB19_91
-; RV32I-NEXT: # %bb.90:
-; RV32I-NEXT: mv a4, a6
-; RV32I-NEXT: .LBB19_91:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: li s0, 1
-; RV32I-NEXT: beqz t4, .LBB19_93
-; RV32I-NEXT: # %bb.92:
-; RV32I-NEXT: mv a6, t5
-; RV32I-NEXT: .LBB19_93:
+; RV32I-NEXT: bnez t4, .LBB19_104
+; RV32I-NEXT: .LBB19_90:
+; RV32I-NEXT: li s0, 7
; RV32I-NEXT: beqz t0, .LBB19_105
-; RV32I-NEXT: # %bb.94:
+; RV32I-NEXT: .LBB19_91:
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: j .LBB19_106
-; RV32I-NEXT: .LBB19_95:
+; RV32I-NEXT: .LBB19_92:
; RV32I-NEXT: mv s0, t5
-; RV32I-NEXT: bne t0, s7, .LBB19_77
-; RV32I-NEXT: .LBB19_96:
-; RV32I-NEXT: or a6, t6, s0
+; RV32I-NEXT: bne t0, t6, .LBB19_77
+; RV32I-NEXT: .LBB19_93:
+; RV32I-NEXT: or a6, s11, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB19_78
-; RV32I-NEXT: .LBB19_97:
+; RV32I-NEXT: .LBB19_94:
; RV32I-NEXT: lw s0, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s4, .LBB19_79
-; RV32I-NEXT: .LBB19_98:
+; RV32I-NEXT: .LBB19_95:
; RV32I-NEXT: or a6, ra, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB19_80
-; RV32I-NEXT: .LBB19_99:
+; RV32I-NEXT: .LBB19_96:
; RV32I-NEXT: lw s0, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s1, .LBB19_81
-; RV32I-NEXT: .LBB19_100:
-; RV32I-NEXT: or a6, s11, s0
+; RV32I-NEXT: .LBB19_97:
+; RV32I-NEXT: or a6, s10, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB19_82
-; RV32I-NEXT: .LBB19_101:
+; RV32I-NEXT: .LBB19_98:
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne t0, s10, .LBB19_83
-; RV32I-NEXT: .LBB19_102:
+; RV32I-NEXT: bne t0, s8, .LBB19_83
+; RV32I-NEXT: .LBB19_99:
; RV32I-NEXT: or a6, s9, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB19_84
-; RV32I-NEXT: .LBB19_103:
+; RV32I-NEXT: .LBB19_100:
; RV32I-NEXT: mv s0, s3
; RV32I-NEXT: bne t0, s2, .LBB19_85
-; RV32I-NEXT: .LBB19_104:
+; RV32I-NEXT: .LBB19_101:
; RV32I-NEXT: or a6, s6, s0
; RV32I-NEXT: mv s0, t1
-; RV32I-NEXT: bne t0, s8, .LBB19_86
+; RV32I-NEXT: bne t0, s7, .LBB19_86
; RV32I-NEXT: j .LBB19_87
+; RV32I-NEXT: .LBB19_102:
+; RV32I-NEXT: mv a6, s0
+; RV32I-NEXT: beqz a5, .LBB19_89
+; RV32I-NEXT: .LBB19_103:
+; RV32I-NEXT: mv a4, a6
+; RV32I-NEXT: li a6, 0
+; RV32I-NEXT: beqz t4, .LBB19_90
+; RV32I-NEXT: .LBB19_104:
+; RV32I-NEXT: mv a6, t5
+; RV32I-NEXT: li s0, 7
+; RV32I-NEXT: bnez t0, .LBB19_91
; RV32I-NEXT: .LBB19_105:
-; RV32I-NEXT: or a6, t6, a6
+; RV32I-NEXT: or a6, s11, a6
; RV32I-NEXT: .LBB19_106:
-; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: mv t6, s9
; RV32I-NEXT: li t5, 0
+; RV32I-NEXT: li s9, 1
; RV32I-NEXT: bnez t4, .LBB19_121
; RV32I-NEXT: # %bb.107:
-; RV32I-NEXT: beq t0, s0, .LBB19_122
+; RV32I-NEXT: beq t0, s9, .LBB19_122
; RV32I-NEXT: .LBB19_108:
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB19_123
@@ -11358,16 +11356,16 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB19_127
; RV32I-NEXT: .LBB19_113:
-; RV32I-NEXT: beq t0, s10, .LBB19_128
+; RV32I-NEXT: beq t0, s8, .LBB19_128
; RV32I-NEXT: .LBB19_114:
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: bne t0, s2, .LBB19_129
; RV32I-NEXT: .LBB19_115:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s8, .LBB19_130
+; RV32I-NEXT: bne t0, s7, .LBB19_130
; RV32I-NEXT: .LBB19_116:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, t6, .LBB19_131
+; RV32I-NEXT: bne t0, s0, .LBB19_131
; RV32I-NEXT: .LBB19_117:
; RV32I-NEXT: bnez a5, .LBB19_132
; RV32I-NEXT: .LBB19_118:
@@ -11382,7 +11380,7 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: j .LBB19_136
; RV32I-NEXT: .LBB19_121:
; RV32I-NEXT: lw t5, 0(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne t0, s0, .LBB19_108
+; RV32I-NEXT: bne t0, s9, .LBB19_108
; RV32I-NEXT: .LBB19_122:
; RV32I-NEXT: or a6, ra, t5
; RV32I-NEXT: li t5, 0
@@ -11391,19 +11389,19 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s4, .LBB19_110
; RV32I-NEXT: .LBB19_124:
-; RV32I-NEXT: or a6, s11, t5
+; RV32I-NEXT: or a6, s10, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB19_111
; RV32I-NEXT: .LBB19_125:
; RV32I-NEXT: lw t5, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s1, .LBB19_112
; RV32I-NEXT: .LBB19_126:
-; RV32I-NEXT: or a6, s9, t5
+; RV32I-NEXT: or a6, t6, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB19_113
; RV32I-NEXT: .LBB19_127:
; RV32I-NEXT: mv t5, s3
-; RV32I-NEXT: bne t0, s10, .LBB19_114
+; RV32I-NEXT: bne t0, s8, .LBB19_114
; RV32I-NEXT: .LBB19_128:
; RV32I-NEXT: or a6, s6, t5
; RV32I-NEXT: mv t5, t1
@@ -11411,11 +11409,11 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: .LBB19_129:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s8, .LBB19_116
+; RV32I-NEXT: beq t0, s7, .LBB19_116
; RV32I-NEXT: .LBB19_130:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, t6, .LBB19_117
+; RV32I-NEXT: beq t0, s0, .LBB19_117
; RV32I-NEXT: .LBB19_131:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: beqz a5, .LBB19_118
@@ -11433,7 +11431,7 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: .LBB19_135:
; RV32I-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB19_136:
-; RV32I-NEXT: beq t0, s0, .LBB19_149
+; RV32I-NEXT: beq t0, s9, .LBB19_149
; RV32I-NEXT: # %bb.137:
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB19_150
@@ -11446,16 +11444,16 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: beq t0, s1, .LBB19_153
; RV32I-NEXT: .LBB19_141:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s10, .LBB19_154
+; RV32I-NEXT: bne t0, s8, .LBB19_154
; RV32I-NEXT: .LBB19_142:
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: bne t0, s2, .LBB19_155
; RV32I-NEXT: .LBB19_143:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s8, .LBB19_156
+; RV32I-NEXT: bne t0, s7, .LBB19_156
; RV32I-NEXT: .LBB19_144:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, t6, .LBB19_157
+; RV32I-NEXT: bne t0, s0, .LBB19_157
; RV32I-NEXT: .LBB19_145:
; RV32I-NEXT: bnez a5, .LBB19_158
; RV32I-NEXT: .LBB19_146:
@@ -11469,14 +11467,14 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: bnez t4, .LBB19_161
; RV32I-NEXT: j .LBB19_162
; RV32I-NEXT: .LBB19_149:
-; RV32I-NEXT: or a6, s11, t5
+; RV32I-NEXT: or a6, s10, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB19_138
; RV32I-NEXT: .LBB19_150:
; RV32I-NEXT: lw t5, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s4, .LBB19_139
; RV32I-NEXT: .LBB19_151:
-; RV32I-NEXT: or a6, s9, t5
+; RV32I-NEXT: or a6, t6, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB19_140
; RV32I-NEXT: .LBB19_152:
@@ -11485,7 +11483,7 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: .LBB19_153:
; RV32I-NEXT: or a6, s6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s10, .LBB19_142
+; RV32I-NEXT: beq t0, s8, .LBB19_142
; RV32I-NEXT: .LBB19_154:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
@@ -11493,11 +11491,11 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: .LBB19_155:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s8, .LBB19_144
+; RV32I-NEXT: beq t0, s7, .LBB19_144
; RV32I-NEXT: .LBB19_156:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, t6, .LBB19_145
+; RV32I-NEXT: beq t0, s0, .LBB19_145
; RV32I-NEXT: .LBB19_157:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: beqz a5, .LBB19_146
@@ -11509,13 +11507,13 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: lw a6, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: bnez t0, .LBB19_148
; RV32I-NEXT: .LBB19_160:
-; RV32I-NEXT: or a6, s11, a6
+; RV32I-NEXT: or a6, s10, a6
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB19_162
; RV32I-NEXT: .LBB19_161:
; RV32I-NEXT: lw t5, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB19_162:
-; RV32I-NEXT: beq t0, s0, .LBB19_174
+; RV32I-NEXT: beq t0, s9, .LBB19_174
; RV32I-NEXT: # %bb.163:
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB19_175
@@ -11526,16 +11524,16 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: bne t0, s1, .LBB19_177
; RV32I-NEXT: .LBB19_166:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s10, .LBB19_178
+; RV32I-NEXT: bne t0, s8, .LBB19_178
; RV32I-NEXT: .LBB19_167:
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: bne t0, s2, .LBB19_179
; RV32I-NEXT: .LBB19_168:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s8, .LBB19_180
+; RV32I-NEXT: bne t0, s7, .LBB19_180
; RV32I-NEXT: .LBB19_169:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, t6, .LBB19_181
+; RV32I-NEXT: bne t0, s0, .LBB19_181
; RV32I-NEXT: .LBB19_170:
; RV32I-NEXT: bnez a5, .LBB19_182
; RV32I-NEXT: .LBB19_171:
@@ -11545,11 +11543,9 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: beqz t0, .LBB19_184
; RV32I-NEXT: .LBB19_173:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: li t5, 0
-; RV32I-NEXT: bnez t4, .LBB19_185
-; RV32I-NEXT: j .LBB19_186
+; RV32I-NEXT: j .LBB19_185
; RV32I-NEXT: .LBB19_174:
-; RV32I-NEXT: or a6, s9, t5
+; RV32I-NEXT: or a6, t6, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB19_164
; RV32I-NEXT: .LBB19_175:
@@ -11562,7 +11558,7 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: .LBB19_177:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s10, .LBB19_167
+; RV32I-NEXT: beq t0, s8, .LBB19_167
; RV32I-NEXT: .LBB19_178:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
@@ -11570,11 +11566,11 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: .LBB19_179:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s8, .LBB19_169
+; RV32I-NEXT: beq t0, s7, .LBB19_169
; RV32I-NEXT: .LBB19_180:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, t6, .LBB19_170
+; RV32I-NEXT: beq t0, s0, .LBB19_170
; RV32I-NEXT: .LBB19_181:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: beqz a5, .LBB19_171
@@ -11586,105 +11582,108 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: lw a6, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: bnez t0, .LBB19_173
; RV32I-NEXT: .LBB19_184:
-; RV32I-NEXT: or a6, s9, a6
-; RV32I-NEXT: li t5, 0
-; RV32I-NEXT: beqz t4, .LBB19_186
+; RV32I-NEXT: or a6, t6, a6
; RV32I-NEXT: .LBB19_185:
-; RV32I-NEXT: mv t5, s3
-; RV32I-NEXT: .LBB19_186:
-; RV32I-NEXT: beq t0, s0, .LBB19_197
-; RV32I-NEXT: # %bb.187:
+; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: li t5, 0
+; RV32I-NEXT: bnez t4, .LBB19_197
+; RV32I-NEXT: # %bb.186:
+; RV32I-NEXT: beq t0, s9, .LBB19_198
+; RV32I-NEXT: .LBB19_187:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s4, .LBB19_198
+; RV32I-NEXT: bne t0, s4, .LBB19_199
; RV32I-NEXT: .LBB19_188:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s1, .LBB19_199
+; RV32I-NEXT: bne t0, s1, .LBB19_200
; RV32I-NEXT: .LBB19_189:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s10, .LBB19_200
+; RV32I-NEXT: bne t0, s8, .LBB19_201
; RV32I-NEXT: .LBB19_190:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s2, .LBB19_201
+; RV32I-NEXT: bne t0, s2, .LBB19_202
; RV32I-NEXT: .LBB19_191:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s8, .LBB19_202
+; RV32I-NEXT: bne t0, s7, .LBB19_203
; RV32I-NEXT: .LBB19_192:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, t6, .LBB19_203
+; RV32I-NEXT: bne t0, t6, .LBB19_204
; RV32I-NEXT: .LBB19_193:
-; RV32I-NEXT: bnez a5, .LBB19_204
+; RV32I-NEXT: bnez a5, .LBB19_205
; RV32I-NEXT: .LBB19_194:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: bnez t4, .LBB19_205
+; RV32I-NEXT: bnez t4, .LBB19_206
; RV32I-NEXT: .LBB19_195:
-; RV32I-NEXT: beqz t0, .LBB19_206
+; RV32I-NEXT: beqz t0, .LBB19_207
; RV32I-NEXT: .LBB19_196:
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: bne t0, s0, .LBB19_207
-; RV32I-NEXT: j .LBB19_208
+; RV32I-NEXT: bne t0, s9, .LBB19_208
+; RV32I-NEXT: j .LBB19_209
; RV32I-NEXT: .LBB19_197:
+; RV32I-NEXT: mv t5, s3
+; RV32I-NEXT: bne t0, s9, .LBB19_187
+; RV32I-NEXT: .LBB19_198:
; RV32I-NEXT: or a6, s6, t5
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: beq t0, s4, .LBB19_188
-; RV32I-NEXT: .LBB19_198:
+; RV32I-NEXT: .LBB19_199:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: beq t0, s1, .LBB19_189
-; RV32I-NEXT: .LBB19_199:
+; RV32I-NEXT: .LBB19_200:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s10, .LBB19_190
-; RV32I-NEXT: .LBB19_200:
+; RV32I-NEXT: beq t0, s8, .LBB19_190
+; RV32I-NEXT: .LBB19_201:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: beq t0, s2, .LBB19_191
-; RV32I-NEXT: .LBB19_201:
+; RV32I-NEXT: .LBB19_202:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s8, .LBB19_192
-; RV32I-NEXT: .LBB19_202:
+; RV32I-NEXT: beq t0, s7, .LBB19_192
+; RV32I-NEXT: .LBB19_203:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: beq t0, t6, .LBB19_193
-; RV32I-NEXT: .LBB19_203:
+; RV32I-NEXT: .LBB19_204:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: beqz a5, .LBB19_194
-; RV32I-NEXT: .LBB19_204:
+; RV32I-NEXT: .LBB19_205:
; RV32I-NEXT: mv t3, a6
; RV32I-NEXT: li a6, 0
; RV32I-NEXT: beqz t4, .LBB19_195
-; RV32I-NEXT: .LBB19_205:
+; RV32I-NEXT: .LBB19_206:
; RV32I-NEXT: mv a6, s3
; RV32I-NEXT: bnez t0, .LBB19_196
-; RV32I-NEXT: .LBB19_206:
+; RV32I-NEXT: .LBB19_207:
; RV32I-NEXT: or a6, s6, a6
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: beq t0, s0, .LBB19_208
-; RV32I-NEXT: .LBB19_207:
-; RV32I-NEXT: mv t4, a6
+; RV32I-NEXT: beq t0, s9, .LBB19_209
; RV32I-NEXT: .LBB19_208:
+; RV32I-NEXT: mv t4, a6
+; RV32I-NEXT: .LBB19_209:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s4, .LBB19_217
-; RV32I-NEXT: # %bb.209:
+; RV32I-NEXT: bne t0, s4, .LBB19_218
+; RV32I-NEXT: # %bb.210:
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: bne t0, s1, .LBB19_218
-; RV32I-NEXT: .LBB19_210:
-; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s10, .LBB19_219
+; RV32I-NEXT: bne t0, s1, .LBB19_219
; RV32I-NEXT: .LBB19_211:
-; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: bne t0, s2, .LBB19_220
-; RV32I-NEXT: .LBB19_212:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s8, .LBB19_221
+; RV32I-NEXT: bne t0, s8, .LBB19_220
+; RV32I-NEXT: .LBB19_212:
+; RV32I-NEXT: mv t4, t1
+; RV32I-NEXT: bne t0, s2, .LBB19_221
; RV32I-NEXT: .LBB19_213:
-; RV32I-NEXT: bne t0, t6, .LBB19_222
+; RV32I-NEXT: mv a6, t1
+; RV32I-NEXT: bne t0, s7, .LBB19_222
; RV32I-NEXT: .LBB19_214:
-; RV32I-NEXT: beqz a5, .LBB19_216
+; RV32I-NEXT: bne t0, t6, .LBB19_223
; RV32I-NEXT: .LBB19_215:
-; RV32I-NEXT: mv a1, t1
+; RV32I-NEXT: beqz a5, .LBB19_217
; RV32I-NEXT: .LBB19_216:
+; RV32I-NEXT: mv a1, t1
+; RV32I-NEXT: .LBB19_217:
; RV32I-NEXT: lui a5, 16
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: srli a6, s5, 16
@@ -11766,29 +11765,29 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB19_217:
+; RV32I-NEXT: .LBB19_218:
; RV32I-NEXT: mv a6, t4
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: beq t0, s1, .LBB19_210
-; RV32I-NEXT: .LBB19_218:
+; RV32I-NEXT: beq t0, s1, .LBB19_211
+; RV32I-NEXT: .LBB19_219:
; RV32I-NEXT: mv t4, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s10, .LBB19_211
-; RV32I-NEXT: .LBB19_219:
+; RV32I-NEXT: beq t0, s8, .LBB19_212
+; RV32I-NEXT: .LBB19_220:
; RV32I-NEXT: mv a6, t4
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: beq t0, s2, .LBB19_212
-; RV32I-NEXT: .LBB19_220:
+; RV32I-NEXT: beq t0, s2, .LBB19_213
+; RV32I-NEXT: .LBB19_221:
; RV32I-NEXT: mv t4, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s8, .LBB19_213
-; RV32I-NEXT: .LBB19_221:
-; RV32I-NEXT: mv a6, t4
-; RV32I-NEXT: beq t0, t6, .LBB19_214
+; RV32I-NEXT: beq t0, s7, .LBB19_214
; RV32I-NEXT: .LBB19_222:
+; RV32I-NEXT: mv a6, t4
+; RV32I-NEXT: beq t0, t6, .LBB19_215
+; RV32I-NEXT: .LBB19_223:
; RV32I-NEXT: mv t1, a6
-; RV32I-NEXT: bnez a5, .LBB19_215
-; RV32I-NEXT: j .LBB19_216
+; RV32I-NEXT: bnez a5, .LBB19_216
+; RV32I-NEXT: j .LBB19_217
%src = load i256, ptr %src.ptr, align 1
%wordOff = load i256, ptr %wordOff.ptr, align 1
%bitOff = shl i256 %wordOff, 5
@@ -11912,12 +11911,12 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV64I-NEXT: or a5, t1, t3
; RV64I-NEXT: slli a7, a7, 6
; RV64I-NEXT: li t1, 64
-; RV64I-NEXT: neg t3, a7
-; RV64I-NEXT: sub t4, a7, t1
-; RV64I-NEXT: sll t5, a5, t3
+; RV64I-NEXT: neg t4, a7
+; RV64I-NEXT: sub t3, a7, t1
+; RV64I-NEXT: sll t5, a5, t4
; RV64I-NEXT: bltu a7, t1, .LBB20_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: sra t6, a5, t4
+; RV64I-NEXT: sra t6, a5, t3
; RV64I-NEXT: j .LBB20_3
; RV64I-NEXT: .LBB20_2:
; RV64I-NEXT: srl t6, a3, a7
@@ -11937,36 +11936,36 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV64I-NEXT: bltu a7, t1, .LBB20_7
; RV64I-NEXT: # %bb.6:
; RV64I-NEXT: srai a0, a5, 63
-; RV64I-NEXT: srl t4, a4, t4
+; RV64I-NEXT: srl t3, a4, t3
; RV64I-NEXT: j .LBB20_8
; RV64I-NEXT: .LBB20_7:
; RV64I-NEXT: srl t0, a6, a7
-; RV64I-NEXT: sll t2, a4, t3
+; RV64I-NEXT: sll t2, a4, t4
; RV64I-NEXT: sra a0, a5, a7
-; RV64I-NEXT: or t4, t0, t2
+; RV64I-NEXT: or t3, t0, t2
; RV64I-NEXT: .LBB20_8:
; RV64I-NEXT: li t0, 128
; RV64I-NEXT: mv t2, a6
; RV64I-NEXT: beqz a7, .LBB20_10
; RV64I-NEXT: # %bb.9:
-; RV64I-NEXT: mv t2, t4
+; RV64I-NEXT: mv t2, t3
; RV64I-NEXT: .LBB20_10:
; RV64I-NEXT: sub t6, t0, a7
; RV64I-NEXT: bltu a7, t1, .LBB20_13
; RV64I-NEXT: # %bb.11:
-; RV64I-NEXT: li t4, 0
+; RV64I-NEXT: li t3, 0
; RV64I-NEXT: bgeu t6, t1, .LBB20_14
; RV64I-NEXT: .LBB20_12:
; RV64I-NEXT: neg s0, t6
; RV64I-NEXT: srl s0, a3, s0
-; RV64I-NEXT: sll t3, a3, t3
+; RV64I-NEXT: sll t4, a3, t4
; RV64I-NEXT: or s1, s0, t5
; RV64I-NEXT: j .LBB20_15
; RV64I-NEXT: .LBB20_13:
-; RV64I-NEXT: srl t4, a4, a7
+; RV64I-NEXT: srl t3, a4, a7
; RV64I-NEXT: bltu t6, t1, .LBB20_12
; RV64I-NEXT: .LBB20_14:
-; RV64I-NEXT: li t3, 0
+; RV64I-NEXT: li t4, 0
; RV64I-NEXT: sub t5, t6, t1
; RV64I-NEXT: sll s1, a3, t5
; RV64I-NEXT: .LBB20_15:
@@ -12000,8 +11999,8 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV64I-NEXT: sra t1, a5, s0
; RV64I-NEXT: bgeu a7, t0, .LBB20_25
; RV64I-NEXT: .LBB20_24:
-; RV64I-NEXT: or a3, t2, t3
-; RV64I-NEXT: or t1, t4, t5
+; RV64I-NEXT: or a3, t2, t4
+; RV64I-NEXT: or t1, t3, t5
; RV64I-NEXT: .LBB20_25:
; RV64I-NEXT: bnez a7, .LBB20_29
; RV64I-NEXT: # %bb.26:
@@ -12233,75 +12232,75 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: lbu s9, 25(a0)
; RV32I-NEXT: lbu s8, 26(a0)
; RV32I-NEXT: slli t6, t6, 8
-; RV32I-NEXT: or s7, s7, t5
-; RV32I-NEXT: slli s10, s6, 16
+; RV32I-NEXT: or s10, s7, t5
+; RV32I-NEXT: slli s6, s6, 16
; RV32I-NEXT: sll t5, t2, s3
; RV32I-NEXT: beqz t4, .LBB20_15
; RV32I-NEXT: # %bb.14:
; RV32I-NEXT: mv t3, t5
; RV32I-NEXT: .LBB20_15:
-; RV32I-NEXT: lbu s6, 24(a0)
+; RV32I-NEXT: lbu s7, 24(a0)
; RV32I-NEXT: slli s9, s9, 8
; RV32I-NEXT: or s8, t6, s8
-; RV32I-NEXT: srl t6, a7, a5
-; RV32I-NEXT: or a0, s10, s7
-; RV32I-NEXT: li s7, 3
-; RV32I-NEXT: bne t0, s7, .LBB20_17
+; RV32I-NEXT: srl s11, a7, a5
+; RV32I-NEXT: or a0, s6, s10
+; RV32I-NEXT: li t6, 3
+; RV32I-NEXT: bne t0, t6, .LBB20_17
; RV32I-NEXT: # %bb.16:
-; RV32I-NEXT: or a6, t6, t3
+; RV32I-NEXT: or a6, s11, t3
; RV32I-NEXT: .LBB20_17:
-; RV32I-NEXT: li s7, 0
-; RV32I-NEXT: or t3, s9, s6
+; RV32I-NEXT: li s6, 0
+; RV32I-NEXT: or t3, s9, s7
; RV32I-NEXT: slli s8, s8, 16
-; RV32I-NEXT: li s6, 4
-; RV32I-NEXT: sll s9, a0, s3
-; RV32I-NEXT: sw s9, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: li s7, 4
+; RV32I-NEXT: sll t6, a0, s3
+; RV32I-NEXT: sw t6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz t4, .LBB20_19
; RV32I-NEXT: # %bb.18:
-; RV32I-NEXT: lw s7, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB20_19:
; RV32I-NEXT: srl ra, t2, a5
; RV32I-NEXT: or t3, s8, t3
-; RV32I-NEXT: bne t0, s6, .LBB20_21
+; RV32I-NEXT: bne t0, s7, .LBB20_21
; RV32I-NEXT: # %bb.20:
-; RV32I-NEXT: or a6, ra, s7
+; RV32I-NEXT: or a6, ra, s6
; RV32I-NEXT: .LBB20_21:
; RV32I-NEXT: li s6, 0
-; RV32I-NEXT: li s8, 5
-; RV32I-NEXT: sll s7, t3, s3
-; RV32I-NEXT: sw s7, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: li s7, 5
+; RV32I-NEXT: sll t6, t3, s3
+; RV32I-NEXT: sw t6, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz t4, .LBB20_23
; RV32I-NEXT: # %bb.22:
; RV32I-NEXT: lw s6, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB20_23:
-; RV32I-NEXT: srl s7, a0, a5
-; RV32I-NEXT: beq t0, s8, .LBB20_25
+; RV32I-NEXT: srl t6, a0, a5
+; RV32I-NEXT: beq t0, s7, .LBB20_25
; RV32I-NEXT: # %bb.24:
-; RV32I-NEXT: mv s11, s7
+; RV32I-NEXT: mv s10, t6
; RV32I-NEXT: j .LBB20_26
; RV32I-NEXT: .LBB20_25:
-; RV32I-NEXT: mv s11, s7
-; RV32I-NEXT: or a6, s7, s6
+; RV32I-NEXT: mv s10, t6
+; RV32I-NEXT: or a6, t6, s6
; RV32I-NEXT: .LBB20_26:
; RV32I-NEXT: li s6, 0
; RV32I-NEXT: li s9, 6
-; RV32I-NEXT: sll s10, a1, s3
-; RV32I-NEXT: sw s10, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sll s8, a1, s3
+; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz t4, .LBB20_28
; RV32I-NEXT: # %bb.27:
; RV32I-NEXT: lw s6, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB20_28:
-; RV32I-NEXT: mv s10, a3
-; RV32I-NEXT: srl s7, t3, a5
+; RV32I-NEXT: mv s8, a3
+; RV32I-NEXT: srl t6, t3, a5
; RV32I-NEXT: beq t0, s9, .LBB20_30
; RV32I-NEXT: # %bb.29:
-; RV32I-NEXT: mv s9, s7
+; RV32I-NEXT: mv s9, t6
; RV32I-NEXT: mv a3, s5
; RV32I-NEXT: j .LBB20_31
; RV32I-NEXT: .LBB20_30:
; RV32I-NEXT: mv a3, s5
-; RV32I-NEXT: mv s9, s7
-; RV32I-NEXT: or a6, s7, s6
+; RV32I-NEXT: mv s9, t6
+; RV32I-NEXT: or a6, t6, s6
; RV32I-NEXT: .LBB20_31:
; RV32I-NEXT: li s5, 0
; RV32I-NEXT: sll s3, t1, s3
@@ -12310,19 +12309,19 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: mv s5, s3
; RV32I-NEXT: .LBB20_33:
; RV32I-NEXT: srl s6, a1, a5
-; RV32I-NEXT: li s7, 7
-; RV32I-NEXT: bne t0, s7, .LBB20_35
+; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: bne t0, t6, .LBB20_35
; RV32I-NEXT: # %bb.34:
; RV32I-NEXT: or a6, s6, s5
; RV32I-NEXT: .LBB20_35:
; RV32I-NEXT: mv s5, a3
-; RV32I-NEXT: mv a3, s10
+; RV32I-NEXT: mv a3, s8
; RV32I-NEXT: beqz a5, .LBB20_37
; RV32I-NEXT: # %bb.36:
; RV32I-NEXT: mv s5, a6
; RV32I-NEXT: .LBB20_37:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: li s7, 1
+; RV32I-NEXT: li t6, 1
; RV32I-NEXT: beqz t4, .LBB20_39
; RV32I-NEXT: # %bb.38:
; RV32I-NEXT: mv a6, s2
@@ -12338,7 +12337,7 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB20_66
; RV32I-NEXT: # %bb.43:
-; RV32I-NEXT: beq t0, s7, .LBB20_67
+; RV32I-NEXT: beq t0, t6, .LBB20_67
; RV32I-NEXT: .LBB20_44:
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB20_68
@@ -12348,37 +12347,37 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB20_70
; RV32I-NEXT: .LBB20_47:
-; RV32I-NEXT: li s10, 3
-; RV32I-NEXT: bne t0, s10, .LBB20_49
+; RV32I-NEXT: li s8, 3
+; RV32I-NEXT: bne t0, s8, .LBB20_49
; RV32I-NEXT: .LBB20_48:
; RV32I-NEXT: or a6, ra, s2
; RV32I-NEXT: .LBB20_49:
; RV32I-NEXT: li s2, 0
-; RV32I-NEXT: li s10, 4
+; RV32I-NEXT: li s8, 4
; RV32I-NEXT: bnez t4, .LBB20_71
; RV32I-NEXT: # %bb.50:
-; RV32I-NEXT: beq t0, s10, .LBB20_72
+; RV32I-NEXT: beq t0, s8, .LBB20_72
; RV32I-NEXT: .LBB20_51:
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bnez t4, .LBB20_73
; RV32I-NEXT: .LBB20_52:
-; RV32I-NEXT: bne t0, s8, .LBB20_54
+; RV32I-NEXT: bne t0, s7, .LBB20_54
; RV32I-NEXT: .LBB20_53:
; RV32I-NEXT: or a6, s9, s2
; RV32I-NEXT: .LBB20_54:
; RV32I-NEXT: li s2, 0
-; RV32I-NEXT: li s8, 6
+; RV32I-NEXT: li s7, 6
; RV32I-NEXT: beqz t4, .LBB20_56
; RV32I-NEXT: # %bb.55:
; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: .LBB20_56:
-; RV32I-NEXT: bne t0, s8, .LBB20_58
+; RV32I-NEXT: bne t0, s7, .LBB20_58
; RV32I-NEXT: # %bb.57:
; RV32I-NEXT: or a6, s6, s2
; RV32I-NEXT: .LBB20_58:
; RV32I-NEXT: mv s2, t1
-; RV32I-NEXT: li s10, 7
-; RV32I-NEXT: beq t0, s10, .LBB20_60
+; RV32I-NEXT: li s8, 7
+; RV32I-NEXT: beq t0, s8, .LBB20_60
; RV32I-NEXT: # %bb.59:
; RV32I-NEXT: mv s2, a6
; RV32I-NEXT: .LBB20_60:
@@ -12387,7 +12386,7 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: .LBB20_62:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: li s10, 4
+; RV32I-NEXT: li s8, 4
; RV32I-NEXT: beqz t4, .LBB20_64
; RV32I-NEXT: # %bb.63:
; RV32I-NEXT: mv a6, s0
@@ -12399,7 +12398,7 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: j .LBB20_75
; RV32I-NEXT: .LBB20_66:
; RV32I-NEXT: mv s2, s0
-; RV32I-NEXT: bne t0, s7, .LBB20_44
+; RV32I-NEXT: bne t0, t6, .LBB20_44
; RV32I-NEXT: .LBB20_67:
; RV32I-NEXT: or a6, s1, s2
; RV32I-NEXT: li s2, 0
@@ -12408,123 +12407,129 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: mv s2, t5
; RV32I-NEXT: bne t0, s4, .LBB20_46
; RV32I-NEXT: .LBB20_69:
-; RV32I-NEXT: or a6, t6, s2
+; RV32I-NEXT: or a6, s11, s2
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: beqz t4, .LBB20_47
; RV32I-NEXT: .LBB20_70:
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
-; RV32I-NEXT: li s10, 3
-; RV32I-NEXT: beq t0, s10, .LBB20_48
+; RV32I-NEXT: li s8, 3
+; RV32I-NEXT: beq t0, s8, .LBB20_48
; RV32I-NEXT: j .LBB20_49
; RV32I-NEXT: .LBB20_71:
; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne t0, s10, .LBB20_51
+; RV32I-NEXT: bne t0, s8, .LBB20_51
; RV32I-NEXT: .LBB20_72:
-; RV32I-NEXT: or a6, s11, s2
+; RV32I-NEXT: or a6, s10, s2
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: beqz t4, .LBB20_52
; RV32I-NEXT: .LBB20_73:
; RV32I-NEXT: lw s2, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: beq t0, s8, .LBB20_53
+; RV32I-NEXT: beq t0, s7, .LBB20_53
; RV32I-NEXT: j .LBB20_54
; RV32I-NEXT: .LBB20_74:
; RV32I-NEXT: or a6, s1, a6
; RV32I-NEXT: .LBB20_75:
; RV32I-NEXT: li s1, 3
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB20_95
+; RV32I-NEXT: bnez t4, .LBB20_92
; RV32I-NEXT: # %bb.76:
-; RV32I-NEXT: beq t0, s7, .LBB20_96
+; RV32I-NEXT: beq t0, t6, .LBB20_93
; RV32I-NEXT: .LBB20_77:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB20_97
+; RV32I-NEXT: bnez t4, .LBB20_94
; RV32I-NEXT: .LBB20_78:
-; RV32I-NEXT: beq t0, s4, .LBB20_98
+; RV32I-NEXT: beq t0, s4, .LBB20_95
; RV32I-NEXT: .LBB20_79:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB20_99
+; RV32I-NEXT: bnez t4, .LBB20_96
; RV32I-NEXT: .LBB20_80:
-; RV32I-NEXT: beq t0, s1, .LBB20_100
+; RV32I-NEXT: beq t0, s1, .LBB20_97
; RV32I-NEXT: .LBB20_81:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB20_101
+; RV32I-NEXT: bnez t4, .LBB20_98
; RV32I-NEXT: .LBB20_82:
-; RV32I-NEXT: beq t0, s10, .LBB20_102
+; RV32I-NEXT: beq t0, s8, .LBB20_99
; RV32I-NEXT: .LBB20_83:
; RV32I-NEXT: li s0, 0
-; RV32I-NEXT: bnez t4, .LBB20_103
+; RV32I-NEXT: bnez t4, .LBB20_100
; RV32I-NEXT: .LBB20_84:
-; RV32I-NEXT: beq t0, s2, .LBB20_104
+; RV32I-NEXT: beq t0, s2, .LBB20_101
; RV32I-NEXT: .LBB20_85:
; RV32I-NEXT: mv s0, t1
-; RV32I-NEXT: beq t0, s8, .LBB20_87
+; RV32I-NEXT: beq t0, s7, .LBB20_87
; RV32I-NEXT: .LBB20_86:
; RV32I-NEXT: mv s0, a6
; RV32I-NEXT: .LBB20_87:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: li s7, 7
-; RV32I-NEXT: beq t0, s7, .LBB20_89
+; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: bne t0, t6, .LBB20_102
; RV32I-NEXT: # %bb.88:
-; RV32I-NEXT: mv a6, s0
+; RV32I-NEXT: bnez a5, .LBB20_103
; RV32I-NEXT: .LBB20_89:
-; RV32I-NEXT: beqz a5, .LBB20_91
-; RV32I-NEXT: # %bb.90:
-; RV32I-NEXT: mv a4, a6
-; RV32I-NEXT: .LBB20_91:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: li s0, 1
-; RV32I-NEXT: beqz t4, .LBB20_93
-; RV32I-NEXT: # %bb.92:
-; RV32I-NEXT: mv a6, t5
-; RV32I-NEXT: .LBB20_93:
+; RV32I-NEXT: bnez t4, .LBB20_104
+; RV32I-NEXT: .LBB20_90:
+; RV32I-NEXT: li s0, 7
; RV32I-NEXT: beqz t0, .LBB20_105
-; RV32I-NEXT: # %bb.94:
+; RV32I-NEXT: .LBB20_91:
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: j .LBB20_106
-; RV32I-NEXT: .LBB20_95:
+; RV32I-NEXT: .LBB20_92:
; RV32I-NEXT: mv s0, t5
-; RV32I-NEXT: bne t0, s7, .LBB20_77
-; RV32I-NEXT: .LBB20_96:
-; RV32I-NEXT: or a6, t6, s0
+; RV32I-NEXT: bne t0, t6, .LBB20_77
+; RV32I-NEXT: .LBB20_93:
+; RV32I-NEXT: or a6, s11, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB20_78
-; RV32I-NEXT: .LBB20_97:
+; RV32I-NEXT: .LBB20_94:
; RV32I-NEXT: lw s0, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s4, .LBB20_79
-; RV32I-NEXT: .LBB20_98:
+; RV32I-NEXT: .LBB20_95:
; RV32I-NEXT: or a6, ra, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB20_80
-; RV32I-NEXT: .LBB20_99:
+; RV32I-NEXT: .LBB20_96:
; RV32I-NEXT: lw s0, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s1, .LBB20_81
-; RV32I-NEXT: .LBB20_100:
-; RV32I-NEXT: or a6, s11, s0
+; RV32I-NEXT: .LBB20_97:
+; RV32I-NEXT: or a6, s10, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB20_82
-; RV32I-NEXT: .LBB20_101:
+; RV32I-NEXT: .LBB20_98:
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne t0, s10, .LBB20_83
-; RV32I-NEXT: .LBB20_102:
+; RV32I-NEXT: bne t0, s8, .LBB20_83
+; RV32I-NEXT: .LBB20_99:
; RV32I-NEXT: or a6, s9, s0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: beqz t4, .LBB20_84
-; RV32I-NEXT: .LBB20_103:
+; RV32I-NEXT: .LBB20_100:
; RV32I-NEXT: mv s0, s3
; RV32I-NEXT: bne t0, s2, .LBB20_85
-; RV32I-NEXT: .LBB20_104:
+; RV32I-NEXT: .LBB20_101:
; RV32I-NEXT: or a6, s6, s0
; RV32I-NEXT: mv s0, t1
-; RV32I-NEXT: bne t0, s8, .LBB20_86
+; RV32I-NEXT: bne t0, s7, .LBB20_86
; RV32I-NEXT: j .LBB20_87
+; RV32I-NEXT: .LBB20_102:
+; RV32I-NEXT: mv a6, s0
+; RV32I-NEXT: beqz a5, .LBB20_89
+; RV32I-NEXT: .LBB20_103:
+; RV32I-NEXT: mv a4, a6
+; RV32I-NEXT: li a6, 0
+; RV32I-NEXT: beqz t4, .LBB20_90
+; RV32I-NEXT: .LBB20_104:
+; RV32I-NEXT: mv a6, t5
+; RV32I-NEXT: li s0, 7
+; RV32I-NEXT: bnez t0, .LBB20_91
; RV32I-NEXT: .LBB20_105:
-; RV32I-NEXT: or a6, t6, a6
+; RV32I-NEXT: or a6, s11, a6
; RV32I-NEXT: .LBB20_106:
-; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: mv t6, s9
; RV32I-NEXT: li t5, 0
+; RV32I-NEXT: li s9, 1
; RV32I-NEXT: bnez t4, .LBB20_121
; RV32I-NEXT: # %bb.107:
-; RV32I-NEXT: beq t0, s0, .LBB20_122
+; RV32I-NEXT: beq t0, s9, .LBB20_122
; RV32I-NEXT: .LBB20_108:
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB20_123
@@ -12539,16 +12544,16 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB20_127
; RV32I-NEXT: .LBB20_113:
-; RV32I-NEXT: beq t0, s10, .LBB20_128
+; RV32I-NEXT: beq t0, s8, .LBB20_128
; RV32I-NEXT: .LBB20_114:
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: bne t0, s2, .LBB20_129
; RV32I-NEXT: .LBB20_115:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s8, .LBB20_130
+; RV32I-NEXT: bne t0, s7, .LBB20_130
; RV32I-NEXT: .LBB20_116:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, t6, .LBB20_131
+; RV32I-NEXT: bne t0, s0, .LBB20_131
; RV32I-NEXT: .LBB20_117:
; RV32I-NEXT: bnez a5, .LBB20_132
; RV32I-NEXT: .LBB20_118:
@@ -12563,7 +12568,7 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: j .LBB20_136
; RV32I-NEXT: .LBB20_121:
; RV32I-NEXT: lw t5, 0(sp) # 4-byte Folded Reload
-; RV32I-NEXT: bne t0, s0, .LBB20_108
+; RV32I-NEXT: bne t0, s9, .LBB20_108
; RV32I-NEXT: .LBB20_122:
; RV32I-NEXT: or a6, ra, t5
; RV32I-NEXT: li t5, 0
@@ -12572,19 +12577,19 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s4, .LBB20_110
; RV32I-NEXT: .LBB20_124:
-; RV32I-NEXT: or a6, s11, t5
+; RV32I-NEXT: or a6, s10, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB20_111
; RV32I-NEXT: .LBB20_125:
; RV32I-NEXT: lw t5, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s1, .LBB20_112
; RV32I-NEXT: .LBB20_126:
-; RV32I-NEXT: or a6, s9, t5
+; RV32I-NEXT: or a6, t6, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB20_113
; RV32I-NEXT: .LBB20_127:
; RV32I-NEXT: mv t5, s3
-; RV32I-NEXT: bne t0, s10, .LBB20_114
+; RV32I-NEXT: bne t0, s8, .LBB20_114
; RV32I-NEXT: .LBB20_128:
; RV32I-NEXT: or a6, s6, t5
; RV32I-NEXT: mv t5, t1
@@ -12592,11 +12597,11 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: .LBB20_129:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s8, .LBB20_116
+; RV32I-NEXT: beq t0, s7, .LBB20_116
; RV32I-NEXT: .LBB20_130:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, t6, .LBB20_117
+; RV32I-NEXT: beq t0, s0, .LBB20_117
; RV32I-NEXT: .LBB20_131:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: beqz a5, .LBB20_118
@@ -12614,7 +12619,7 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: .LBB20_135:
; RV32I-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB20_136:
-; RV32I-NEXT: beq t0, s0, .LBB20_149
+; RV32I-NEXT: beq t0, s9, .LBB20_149
; RV32I-NEXT: # %bb.137:
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB20_150
@@ -12627,16 +12632,16 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: beq t0, s1, .LBB20_153
; RV32I-NEXT: .LBB20_141:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s10, .LBB20_154
+; RV32I-NEXT: bne t0, s8, .LBB20_154
; RV32I-NEXT: .LBB20_142:
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: bne t0, s2, .LBB20_155
; RV32I-NEXT: .LBB20_143:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s8, .LBB20_156
+; RV32I-NEXT: bne t0, s7, .LBB20_156
; RV32I-NEXT: .LBB20_144:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, t6, .LBB20_157
+; RV32I-NEXT: bne t0, s0, .LBB20_157
; RV32I-NEXT: .LBB20_145:
; RV32I-NEXT: bnez a5, .LBB20_158
; RV32I-NEXT: .LBB20_146:
@@ -12650,14 +12655,14 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: bnez t4, .LBB20_161
; RV32I-NEXT: j .LBB20_162
; RV32I-NEXT: .LBB20_149:
-; RV32I-NEXT: or a6, s11, t5
+; RV32I-NEXT: or a6, s10, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB20_138
; RV32I-NEXT: .LBB20_150:
; RV32I-NEXT: lw t5, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: bne t0, s4, .LBB20_139
; RV32I-NEXT: .LBB20_151:
-; RV32I-NEXT: or a6, s9, t5
+; RV32I-NEXT: or a6, t6, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB20_140
; RV32I-NEXT: .LBB20_152:
@@ -12666,7 +12671,7 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: .LBB20_153:
; RV32I-NEXT: or a6, s6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s10, .LBB20_142
+; RV32I-NEXT: beq t0, s8, .LBB20_142
; RV32I-NEXT: .LBB20_154:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
@@ -12674,11 +12679,11 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: .LBB20_155:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s8, .LBB20_144
+; RV32I-NEXT: beq t0, s7, .LBB20_144
; RV32I-NEXT: .LBB20_156:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, t6, .LBB20_145
+; RV32I-NEXT: beq t0, s0, .LBB20_145
; RV32I-NEXT: .LBB20_157:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: beqz a5, .LBB20_146
@@ -12690,13 +12695,13 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: lw a6, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: bnez t0, .LBB20_148
; RV32I-NEXT: .LBB20_160:
-; RV32I-NEXT: or a6, s11, a6
+; RV32I-NEXT: or a6, s10, a6
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB20_162
; RV32I-NEXT: .LBB20_161:
; RV32I-NEXT: lw t5, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: .LBB20_162:
-; RV32I-NEXT: beq t0, s0, .LBB20_174
+; RV32I-NEXT: beq t0, s9, .LBB20_174
; RV32I-NEXT: # %bb.163:
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: bnez t4, .LBB20_175
@@ -12707,16 +12712,16 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: bne t0, s1, .LBB20_177
; RV32I-NEXT: .LBB20_166:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s10, .LBB20_178
+; RV32I-NEXT: bne t0, s8, .LBB20_178
; RV32I-NEXT: .LBB20_167:
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: bne t0, s2, .LBB20_179
; RV32I-NEXT: .LBB20_168:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s8, .LBB20_180
+; RV32I-NEXT: bne t0, s7, .LBB20_180
; RV32I-NEXT: .LBB20_169:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, t6, .LBB20_181
+; RV32I-NEXT: bne t0, s0, .LBB20_181
; RV32I-NEXT: .LBB20_170:
; RV32I-NEXT: bnez a5, .LBB20_182
; RV32I-NEXT: .LBB20_171:
@@ -12726,11 +12731,9 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: beqz t0, .LBB20_184
; RV32I-NEXT: .LBB20_173:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: li t5, 0
-; RV32I-NEXT: bnez t4, .LBB20_185
-; RV32I-NEXT: j .LBB20_186
+; RV32I-NEXT: j .LBB20_185
; RV32I-NEXT: .LBB20_174:
-; RV32I-NEXT: or a6, s9, t5
+; RV32I-NEXT: or a6, t6, t5
; RV32I-NEXT: li t5, 0
; RV32I-NEXT: beqz t4, .LBB20_164
; RV32I-NEXT: .LBB20_175:
@@ -12743,7 +12746,7 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: .LBB20_177:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s10, .LBB20_167
+; RV32I-NEXT: beq t0, s8, .LBB20_167
; RV32I-NEXT: .LBB20_178:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
@@ -12751,11 +12754,11 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: .LBB20_179:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s8, .LBB20_169
+; RV32I-NEXT: beq t0, s7, .LBB20_169
; RV32I-NEXT: .LBB20_180:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, t6, .LBB20_170
+; RV32I-NEXT: beq t0, s0, .LBB20_170
; RV32I-NEXT: .LBB20_181:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: beqz a5, .LBB20_171
@@ -12767,105 +12770,108 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: lw a6, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: bnez t0, .LBB20_173
; RV32I-NEXT: .LBB20_184:
-; RV32I-NEXT: or a6, s9, a6
-; RV32I-NEXT: li t5, 0
-; RV32I-NEXT: beqz t4, .LBB20_186
+; RV32I-NEXT: or a6, t6, a6
; RV32I-NEXT: .LBB20_185:
-; RV32I-NEXT: mv t5, s3
-; RV32I-NEXT: .LBB20_186:
-; RV32I-NEXT: beq t0, s0, .LBB20_197
-; RV32I-NEXT: # %bb.187:
+; RV32I-NEXT: li t6, 7
+; RV32I-NEXT: li t5, 0
+; RV32I-NEXT: bnez t4, .LBB20_197
+; RV32I-NEXT: # %bb.186:
+; RV32I-NEXT: beq t0, s9, .LBB20_198
+; RV32I-NEXT: .LBB20_187:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s4, .LBB20_198
+; RV32I-NEXT: bne t0, s4, .LBB20_199
; RV32I-NEXT: .LBB20_188:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s1, .LBB20_199
+; RV32I-NEXT: bne t0, s1, .LBB20_200
; RV32I-NEXT: .LBB20_189:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s10, .LBB20_200
+; RV32I-NEXT: bne t0, s8, .LBB20_201
; RV32I-NEXT: .LBB20_190:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s2, .LBB20_201
+; RV32I-NEXT: bne t0, s2, .LBB20_202
; RV32I-NEXT: .LBB20_191:
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: bne t0, s8, .LBB20_202
+; RV32I-NEXT: bne t0, s7, .LBB20_203
; RV32I-NEXT: .LBB20_192:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, t6, .LBB20_203
+; RV32I-NEXT: bne t0, t6, .LBB20_204
; RV32I-NEXT: .LBB20_193:
-; RV32I-NEXT: bnez a5, .LBB20_204
+; RV32I-NEXT: bnez a5, .LBB20_205
; RV32I-NEXT: .LBB20_194:
; RV32I-NEXT: li a6, 0
-; RV32I-NEXT: bnez t4, .LBB20_205
+; RV32I-NEXT: bnez t4, .LBB20_206
; RV32I-NEXT: .LBB20_195:
-; RV32I-NEXT: beqz t0, .LBB20_206
+; RV32I-NEXT: beqz t0, .LBB20_207
; RV32I-NEXT: .LBB20_196:
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: bne t0, s0, .LBB20_207
-; RV32I-NEXT: j .LBB20_208
+; RV32I-NEXT: bne t0, s9, .LBB20_208
+; RV32I-NEXT: j .LBB20_209
; RV32I-NEXT: .LBB20_197:
+; RV32I-NEXT: mv t5, s3
+; RV32I-NEXT: bne t0, s9, .LBB20_187
+; RV32I-NEXT: .LBB20_198:
; RV32I-NEXT: or a6, s6, t5
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: beq t0, s4, .LBB20_188
-; RV32I-NEXT: .LBB20_198:
+; RV32I-NEXT: .LBB20_199:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: beq t0, s1, .LBB20_189
-; RV32I-NEXT: .LBB20_199:
+; RV32I-NEXT: .LBB20_200:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s10, .LBB20_190
-; RV32I-NEXT: .LBB20_200:
+; RV32I-NEXT: beq t0, s8, .LBB20_190
+; RV32I-NEXT: .LBB20_201:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: beq t0, s2, .LBB20_191
-; RV32I-NEXT: .LBB20_201:
+; RV32I-NEXT: .LBB20_202:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: mv t5, t1
-; RV32I-NEXT: beq t0, s8, .LBB20_192
-; RV32I-NEXT: .LBB20_202:
+; RV32I-NEXT: beq t0, s7, .LBB20_192
+; RV32I-NEXT: .LBB20_203:
; RV32I-NEXT: mv t5, a6
; RV32I-NEXT: mv a6, t1
; RV32I-NEXT: beq t0, t6, .LBB20_193
-; RV32I-NEXT: .LBB20_203:
+; RV32I-NEXT: .LBB20_204:
; RV32I-NEXT: mv a6, t5
; RV32I-NEXT: beqz a5, .LBB20_194
-; RV32I-NEXT: .LBB20_204:
+; RV32I-NEXT: .LBB20_205:
; RV32I-NEXT: mv t3, a6
; RV32I-NEXT: li a6, 0
; RV32I-NEXT: beqz t4, .LBB20_195
-; RV32I-NEXT: .LBB20_205:
+; RV32I-NEXT: .LBB20_206:
; RV32I-NEXT: mv a6, s3
; RV32I-NEXT: bnez t0, .LBB20_196
-; RV32I-NEXT: .LBB20_206:
+; RV32I-NEXT: .LBB20_207:
; RV32I-NEXT: or a6, s6, a6
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: beq t0, s0, .LBB20_208
-; RV32I-NEXT: .LBB20_207:
-; RV32I-NEXT: mv t4, a6
+; RV32I-NEXT: beq t0, s9, .LBB20_209
; RV32I-NEXT: .LBB20_208:
+; RV32I-NEXT: mv t4, a6
+; RV32I-NEXT: .LBB20_209:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s4, .LBB20_217
-; RV32I-NEXT: # %bb.209:
+; RV32I-NEXT: bne t0, s4, .LBB20_218
+; RV32I-NEXT: # %bb.210:
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: bne t0, s1, .LBB20_218
-; RV32I-NEXT: .LBB20_210:
-; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s10, .LBB20_219
+; RV32I-NEXT: bne t0, s1, .LBB20_219
; RV32I-NEXT: .LBB20_211:
-; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: bne t0, s2, .LBB20_220
-; RV32I-NEXT: .LBB20_212:
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: bne t0, s8, .LBB20_221
+; RV32I-NEXT: bne t0, s8, .LBB20_220
+; RV32I-NEXT: .LBB20_212:
+; RV32I-NEXT: mv t4, t1
+; RV32I-NEXT: bne t0, s2, .LBB20_221
; RV32I-NEXT: .LBB20_213:
-; RV32I-NEXT: bne t0, t6, .LBB20_222
+; RV32I-NEXT: mv a6, t1
+; RV32I-NEXT: bne t0, s7, .LBB20_222
; RV32I-NEXT: .LBB20_214:
-; RV32I-NEXT: beqz a5, .LBB20_216
+; RV32I-NEXT: bne t0, t6, .LBB20_223
; RV32I-NEXT: .LBB20_215:
-; RV32I-NEXT: mv a1, t1
+; RV32I-NEXT: beqz a5, .LBB20_217
; RV32I-NEXT: .LBB20_216:
+; RV32I-NEXT: mv a1, t1
+; RV32I-NEXT: .LBB20_217:
; RV32I-NEXT: lui a5, 16
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: srli a6, s5, 16
@@ -12947,29 +12953,29 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB20_217:
+; RV32I-NEXT: .LBB20_218:
; RV32I-NEXT: mv a6, t4
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: beq t0, s1, .LBB20_210
-; RV32I-NEXT: .LBB20_218:
+; RV32I-NEXT: beq t0, s1, .LBB20_211
+; RV32I-NEXT: .LBB20_219:
; RV32I-NEXT: mv t4, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s10, .LBB20_211
-; RV32I-NEXT: .LBB20_219:
+; RV32I-NEXT: beq t0, s8, .LBB20_212
+; RV32I-NEXT: .LBB20_220:
; RV32I-NEXT: mv a6, t4
; RV32I-NEXT: mv t4, t1
-; RV32I-NEXT: beq t0, s2, .LBB20_212
-; RV32I-NEXT: .LBB20_220:
+; RV32I-NEXT: beq t0, s2, .LBB20_213
+; RV32I-NEXT: .LBB20_221:
; RV32I-NEXT: mv t4, a6
; RV32I-NEXT: mv a6, t1
-; RV32I-NEXT: beq t0, s8, .LBB20_213
-; RV32I-NEXT: .LBB20_221:
-; RV32I-NEXT: mv a6, t4
-; RV32I-NEXT: beq t0, t6, .LBB20_214
+; RV32I-NEXT: beq t0, s7, .LBB20_214
; RV32I-NEXT: .LBB20_222:
+; RV32I-NEXT: mv a6, t4
+; RV32I-NEXT: beq t0, t6, .LBB20_215
+; RV32I-NEXT: .LBB20_223:
; RV32I-NEXT: mv t1, a6
-; RV32I-NEXT: bnez a5, .LBB20_215
-; RV32I-NEXT: j .LBB20_216
+; RV32I-NEXT: bnez a5, .LBB20_216
+; RV32I-NEXT: j .LBB20_217
%src = load i256, ptr %src.ptr, align 1
%dwordOff = load i256, ptr %dwordOff.ptr, align 1
%bitOff = shl i256 %dwordOff, 6
diff --git a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
index 940ba2132d8c9..1efbb4244adcc 100644
--- a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
@@ -68,9 +68,9 @@
; CHECK-NEXT: process-imp-defs
; CHECK-NEXT: unreachable-mbb-elimination
; CHECK-NEXT: require<live-vars>
+; CHECK-NEXT: require<live-intervals>
; CHECK-NEXT: require<machine-loops>
; CHECK-NEXT: phi-node-elimination
-; CHECK-NEXT: require<live-intervals>
; CHECK-NEXT: two-address-instruction
; CHECK-NEXT: register-coalescer
; CHECK-NEXT: rename-independent-subregs
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 7cec9e83c13b6..896ba5a678ff8 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -155,9 +155,9 @@
; CHECK-NEXT: Process Implicit Definitions
; CHECK-NEXT: Remove unreachable machine basic blocks
; CHECK-NEXT: Live Variable Analysis
-; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
+; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
diff --git a/llvm/test/CodeGen/RISCV/abdu-neg.ll b/llvm/test/CodeGen/RISCV/abdu-neg.ll
index bee5fdffe5581..4e2fd01c56e24 100644
--- a/llvm/test/CodeGen/RISCV/abdu-neg.ll
+++ b/llvm/test/CodeGen/RISCV/abdu-neg.ll
@@ -624,24 +624,24 @@ define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_ext_i128:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a4, 0(a1)
+; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: lw t1, 8(a2)
; RV32I-NEXT: lw a6, 0(a2)
; RV32I-NEXT: lw t2, 12(a2)
; RV32I-NEXT: lw t0, 4(a2)
; RV32I-NEXT: lw a7, 4(a1)
-; RV32I-NEXT: sltu a1, a4, t1
+; RV32I-NEXT: sltu a1, a3, t1
; RV32I-NEXT: sub a2, a5, t2
-; RV32I-NEXT: sltu t2, a3, a6
+; RV32I-NEXT: sltu t2, a4, a6
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: mv a2, t2
; RV32I-NEXT: beq a7, t0, .LBB11_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a7, t0
; RV32I-NEXT: .LBB11_2:
-; RV32I-NEXT: sub t1, a4, t1
+; RV32I-NEXT: sub t1, a3, t1
; RV32I-NEXT: sltu t3, t1, a2
; RV32I-NEXT: sub a1, a1, t3
; RV32I-NEXT: sub a2, t1, a2
@@ -650,46 +650,46 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sltu t1, a5, a1
; RV32I-NEXT: j .LBB11_5
; RV32I-NEXT: .LBB11_4:
-; RV32I-NEXT: sltu t1, a4, a2
+; RV32I-NEXT: sltu t1, a3, a2
; RV32I-NEXT: .LBB11_5:
; RV32I-NEXT: sub t0, a7, t0
; RV32I-NEXT: sub t0, t0, t2
-; RV32I-NEXT: sub a6, a3, a6
+; RV32I-NEXT: sub a6, a4, a6
; RV32I-NEXT: beq t0, a7, .LBB11_7
; RV32I-NEXT: # %bb.6:
-; RV32I-NEXT: sltu a3, a7, t0
+; RV32I-NEXT: sltu a4, a7, t0
; RV32I-NEXT: j .LBB11_8
; RV32I-NEXT: .LBB11_7:
-; RV32I-NEXT: sltu a3, a3, a6
+; RV32I-NEXT: sltu a4, a4, a6
; RV32I-NEXT: .LBB11_8:
; RV32I-NEXT: xor a5, a1, a5
-; RV32I-NEXT: xor a4, a2, a4
-; RV32I-NEXT: or a4, a4, a5
-; RV32I-NEXT: beqz a4, .LBB11_10
+; RV32I-NEXT: xor a3, a2, a3
+; RV32I-NEXT: or a3, a3, a5
+; RV32I-NEXT: beqz a3, .LBB11_10
; RV32I-NEXT: # %bb.9:
-; RV32I-NEXT: mv a3, t1
+; RV32I-NEXT: mv a4, t1
; RV32I-NEXT: .LBB11_10:
-; RV32I-NEXT: neg a4, a3
-; RV32I-NEXT: xor a7, a6, a4
-; RV32I-NEXT: sltu a6, a7, a4
-; RV32I-NEXT: xor t1, t0, a4
+; RV32I-NEXT: neg a3, a4
+; RV32I-NEXT: xor a7, a6, a3
+; RV32I-NEXT: sltu a6, a7, a3
+; RV32I-NEXT: xor t1, t0, a3
; RV32I-NEXT: mv a5, a6
; RV32I-NEXT: beqz t0, .LBB11_12
; RV32I-NEXT: # %bb.11:
-; RV32I-NEXT: sltu a5, t1, a4
+; RV32I-NEXT: sltu a5, t1, a3
; RV32I-NEXT: .LBB11_12:
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: add t1, t1, a3
-; RV32I-NEXT: add a7, a7, a3
-; RV32I-NEXT: add t0, a2, a3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: add t1, t1, a4
+; RV32I-NEXT: add a7, a7, a4
+; RV32I-NEXT: add t0, a2, a4
; RV32I-NEXT: sub a6, t1, a6
; RV32I-NEXT: sub t1, t0, a5
; RV32I-NEXT: or t2, a7, a6
; RV32I-NEXT: neg t3, t1
; RV32I-NEXT: snez t2, t2
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: sltu a2, a2, a4
-; RV32I-NEXT: add a1, a1, a3
+; RV32I-NEXT: xor a1, a1, a3
+; RV32I-NEXT: sltu a2, a2, a3
+; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: sltu a2, t0, a5
; RV32I-NEXT: sub a1, a1, a2
@@ -737,24 +737,24 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
;
; RV32ZBB-LABEL: abd_ext_i128:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a1)
-; RV32ZBB-NEXT: lw a4, 8(a1)
+; RV32ZBB-NEXT: lw a4, 0(a1)
+; RV32ZBB-NEXT: lw a3, 8(a1)
; RV32ZBB-NEXT: lw a5, 12(a1)
; RV32ZBB-NEXT: lw t1, 8(a2)
; RV32ZBB-NEXT: lw a6, 0(a2)
; RV32ZBB-NEXT: lw t2, 12(a2)
; RV32ZBB-NEXT: lw t0, 4(a2)
; RV32ZBB-NEXT: lw a7, 4(a1)
-; RV32ZBB-NEXT: sltu a1, a4, t1
+; RV32ZBB-NEXT: sltu a1, a3, t1
; RV32ZBB-NEXT: sub a2, a5, t2
-; RV32ZBB-NEXT: sltu t2, a3, a6
+; RV32ZBB-NEXT: sltu t2, a4, a6
; RV32ZBB-NEXT: sub a1, a2, a1
; RV32ZBB-NEXT: mv a2, t2
; RV32ZBB-NEXT: beq a7, t0, .LBB11_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: sltu a2, a7, t0
; RV32ZBB-NEXT: .LBB11_2:
-; RV32ZBB-NEXT: sub t1, a4, t1
+; RV32ZBB-NEXT: sub t1, a3, t1
; RV32ZBB-NEXT: sltu t3, t1, a2
; RV32ZBB-NEXT: sub a1, a1, t3
; RV32ZBB-NEXT: sub a2, t1, a2
@@ -763,46 +763,46 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sltu t1, a5, a1
; RV32ZBB-NEXT: j .LBB11_5
; RV32ZBB-NEXT: .LBB11_4:
-; RV32ZBB-NEXT: sltu t1, a4, a2
+; RV32ZBB-NEXT: sltu t1, a3, a2
; RV32ZBB-NEXT: .LBB11_5:
; RV32ZBB-NEXT: sub t0, a7, t0
; RV32ZBB-NEXT: sub t0, t0, t2
-; RV32ZBB-NEXT: sub a6, a3, a6
+; RV32ZBB-NEXT: sub a6, a4, a6
; RV32ZBB-NEXT: beq t0, a7, .LBB11_7
; RV32ZBB-NEXT: # %bb.6:
-; RV32ZBB-NEXT: sltu a3, a7, t0
+; RV32ZBB-NEXT: sltu a4, a7, t0
; RV32ZBB-NEXT: j .LBB11_8
; RV32ZBB-NEXT: .LBB11_7:
-; RV32ZBB-NEXT: sltu a3, a3, a6
+; RV32ZBB-NEXT: sltu a4, a4, a6
; RV32ZBB-NEXT: .LBB11_8:
; RV32ZBB-NEXT: xor a5, a1, a5
-; RV32ZBB-NEXT: xor a4, a2, a4
-; RV32ZBB-NEXT: or a4, a4, a5
-; RV32ZBB-NEXT: beqz a4, .LBB11_10
+; RV32ZBB-NEXT: xor a3, a2, a3
+; RV32ZBB-NEXT: or a3, a3, a5
+; RV32ZBB-NEXT: beqz a3, .LBB11_10
; RV32ZBB-NEXT: # %bb.9:
-; RV32ZBB-NEXT: mv a3, t1
+; RV32ZBB-NEXT: mv a4, t1
; RV32ZBB-NEXT: .LBB11_10:
-; RV32ZBB-NEXT: neg a4, a3
-; RV32ZBB-NEXT: xor a7, a6, a4
-; RV32ZBB-NEXT: sltu a6, a7, a4
-; RV32ZBB-NEXT: xor t1, t0, a4
+; RV32ZBB-NEXT: neg a3, a4
+; RV32ZBB-NEXT: xor a7, a6, a3
+; RV32ZBB-NEXT: sltu a6, a7, a3
+; RV32ZBB-NEXT: xor t1, t0, a3
; RV32ZBB-NEXT: mv a5, a6
; RV32ZBB-NEXT: beqz t0, .LBB11_12
; RV32ZBB-NEXT: # %bb.11:
-; RV32ZBB-NEXT: sltu a5, t1, a4
+; RV32ZBB-NEXT: sltu a5, t1, a3
; RV32ZBB-NEXT: .LBB11_12:
-; RV32ZBB-NEXT: xor a2, a2, a4
-; RV32ZBB-NEXT: add t1, t1, a3
-; RV32ZBB-NEXT: add a7, a7, a3
-; RV32ZBB-NEXT: add t0, a2, a3
+; RV32ZBB-NEXT: xor a2, a2, a3
+; RV32ZBB-NEXT: add t1, t1, a4
+; RV32ZBB-NEXT: add a7, a7, a4
+; RV32ZBB-NEXT: add t0, a2, a4
; RV32ZBB-NEXT: sub a6, t1, a6
; RV32ZBB-NEXT: sub t1, t0, a5
; RV32ZBB-NEXT: or t2, a7, a6
; RV32ZBB-NEXT: neg t3, t1
; RV32ZBB-NEXT: snez t2, t2
-; RV32ZBB-NEXT: xor a1, a1, a4
-; RV32ZBB-NEXT: sltu a2, a2, a4
-; RV32ZBB-NEXT: add a1, a1, a3
+; RV32ZBB-NEXT: xor a1, a1, a3
+; RV32ZBB-NEXT: sltu a2, a2, a3
+; RV32ZBB-NEXT: add a1, a1, a4
; RV32ZBB-NEXT: sub a1, a1, a2
; RV32ZBB-NEXT: sltu a2, t0, a5
; RV32ZBB-NEXT: sub a1, a1, a2
@@ -859,24 +859,24 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_ext_i128_undef:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a4, 0(a1)
+; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: lw t1, 8(a2)
; RV32I-NEXT: lw a6, 0(a2)
; RV32I-NEXT: lw t2, 12(a2)
; RV32I-NEXT: lw t0, 4(a2)
; RV32I-NEXT: lw a7, 4(a1)
-; RV32I-NEXT: sltu a1, a4, t1
+; RV32I-NEXT: sltu a1, a3, t1
; RV32I-NEXT: sub a2, a5, t2
-; RV32I-NEXT: sltu t2, a3, a6
+; RV32I-NEXT: sltu t2, a4, a6
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: mv a2, t2
; RV32I-NEXT: beq a7, t0, .LBB12_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a7, t0
; RV32I-NEXT: .LBB12_2:
-; RV32I-NEXT: sub t1, a4, t1
+; RV32I-NEXT: sub t1, a3, t1
; RV32I-NEXT: sltu t3, t1, a2
; RV32I-NEXT: sub a1, a1, t3
; RV32I-NEXT: sub a2, t1, a2
@@ -885,46 +885,46 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sltu t1, a5, a1
; RV32I-NEXT: j .LBB12_5
; RV32I-NEXT: .LBB12_4:
-; RV32I-NEXT: sltu t1, a4, a2
+; RV32I-NEXT: sltu t1, a3, a2
; RV32I-NEXT: .LBB12_5:
; RV32I-NEXT: sub t0, a7, t0
; RV32I-NEXT: sub t0, t0, t2
-; RV32I-NEXT: sub a6, a3, a6
+; RV32I-NEXT: sub a6, a4, a6
; RV32I-NEXT: beq t0, a7, .LBB12_7
; RV32I-NEXT: # %bb.6:
-; RV32I-NEXT: sltu a3, a7, t0
+; RV32I-NEXT: sltu a4, a7, t0
; RV32I-NEXT: j .LBB12_8
; RV32I-NEXT: .LBB12_7:
-; RV32I-NEXT: sltu a3, a3, a6
+; RV32I-NEXT: sltu a4, a4, a6
; RV32I-NEXT: .LBB12_8:
; RV32I-NEXT: xor a5, a1, a5
-; RV32I-NEXT: xor a4, a2, a4
-; RV32I-NEXT: or a4, a4, a5
-; RV32I-NEXT: beqz a4, .LBB12_10
+; RV32I-NEXT: xor a3, a2, a3
+; RV32I-NEXT: or a3, a3, a5
+; RV32I-NEXT: beqz a3, .LBB12_10
; RV32I-NEXT: # %bb.9:
-; RV32I-NEXT: mv a3, t1
+; RV32I-NEXT: mv a4, t1
; RV32I-NEXT: .LBB12_10:
-; RV32I-NEXT: neg a4, a3
-; RV32I-NEXT: xor a7, a6, a4
-; RV32I-NEXT: sltu a6, a7, a4
-; RV32I-NEXT: xor t1, t0, a4
+; RV32I-NEXT: neg a3, a4
+; RV32I-NEXT: xor a7, a6, a3
+; RV32I-NEXT: sltu a6, a7, a3
+; RV32I-NEXT: xor t1, t0, a3
; RV32I-NEXT: mv a5, a6
; RV32I-NEXT: beqz t0, .LBB12_12
; RV32I-NEXT: # %bb.11:
-; RV32I-NEXT: sltu a5, t1, a4
+; RV32I-NEXT: sltu a5, t1, a3
; RV32I-NEXT: .LBB12_12:
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: add t1, t1, a3
-; RV32I-NEXT: add a7, a7, a3
-; RV32I-NEXT: add t0, a2, a3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: add t1, t1, a4
+; RV32I-NEXT: add a7, a7, a4
+; RV32I-NEXT: add t0, a2, a4
; RV32I-NEXT: sub a6, t1, a6
; RV32I-NEXT: sub t1, t0, a5
; RV32I-NEXT: or t2, a7, a6
; RV32I-NEXT: neg t3, t1
; RV32I-NEXT: snez t2, t2
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: sltu a2, a2, a4
-; RV32I-NEXT: add a1, a1, a3
+; RV32I-NEXT: xor a1, a1, a3
+; RV32I-NEXT: sltu a2, a2, a3
+; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: sltu a2, t0, a5
; RV32I-NEXT: sub a1, a1, a2
@@ -972,24 +972,24 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
;
; RV32ZBB-LABEL: abd_ext_i128_undef:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a1)
-; RV32ZBB-NEXT: lw a4, 8(a1)
+; RV32ZBB-NEXT: lw a4, 0(a1)
+; RV32ZBB-NEXT: lw a3, 8(a1)
; RV32ZBB-NEXT: lw a5, 12(a1)
; RV32ZBB-NEXT: lw t1, 8(a2)
; RV32ZBB-NEXT: lw a6, 0(a2)
; RV32ZBB-NEXT: lw t2, 12(a2)
; RV32ZBB-NEXT: lw t0, 4(a2)
; RV32ZBB-NEXT: lw a7, 4(a1)
-; RV32ZBB-NEXT: sltu a1, a4, t1
+; RV32ZBB-NEXT: sltu a1, a3, t1
; RV32ZBB-NEXT: sub a2, a5, t2
-; RV32ZBB-NEXT: sltu t2, a3, a6
+; RV32ZBB-NEXT: sltu t2, a4, a6
; RV32ZBB-NEXT: sub a1, a2, a1
; RV32ZBB-NEXT: mv a2, t2
; RV32ZBB-NEXT: beq a7, t0, .LBB12_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: sltu a2, a7, t0
; RV32ZBB-NEXT: .LBB12_2:
-; RV32ZBB-NEXT: sub t1, a4, t1
+; RV32ZBB-NEXT: sub t1, a3, t1
; RV32ZBB-NEXT: sltu t3, t1, a2
; RV32ZBB-NEXT: sub a1, a1, t3
; RV32ZBB-NEXT: sub a2, t1, a2
@@ -998,46 +998,46 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sltu t1, a5, a1
; RV32ZBB-NEXT: j .LBB12_5
; RV32ZBB-NEXT: .LBB12_4:
-; RV32ZBB-NEXT: sltu t1, a4, a2
+; RV32ZBB-NEXT: sltu t1, a3, a2
; RV32ZBB-NEXT: .LBB12_5:
; RV32ZBB-NEXT: sub t0, a7, t0
; RV32ZBB-NEXT: sub t0, t0, t2
-; RV32ZBB-NEXT: sub a6, a3, a6
+; RV32ZBB-NEXT: sub a6, a4, a6
; RV32ZBB-NEXT: beq t0, a7, .LBB12_7
; RV32ZBB-NEXT: # %bb.6:
-; RV32ZBB-NEXT: sltu a3, a7, t0
+; RV32ZBB-NEXT: sltu a4, a7, t0
; RV32ZBB-NEXT: j .LBB12_8
; RV32ZBB-NEXT: .LBB12_7:
-; RV32ZBB-NEXT: sltu a3, a3, a6
+; RV32ZBB-NEXT: sltu a4, a4, a6
; RV32ZBB-NEXT: .LBB12_8:
; RV32ZBB-NEXT: xor a5, a1, a5
-; RV32ZBB-NEXT: xor a4, a2, a4
-; RV32ZBB-NEXT: or a4, a4, a5
-; RV32ZBB-NEXT: beqz a4, .LBB12_10
+; RV32ZBB-NEXT: xor a3, a2, a3
+; RV32ZBB-NEXT: or a3, a3, a5
+; RV32ZBB-NEXT: beqz a3, .LBB12_10
; RV32ZBB-NEXT: # %bb.9:
-; RV32ZBB-NEXT: mv a3, t1
+; RV32ZBB-NEXT: mv a4, t1
; RV32ZBB-NEXT: .LBB12_10:
-; RV32ZBB-NEXT: neg a4, a3
-; RV32ZBB-NEXT: xor a7, a6, a4
-; RV32ZBB-NEXT: sltu a6, a7, a4
-; RV32ZBB-NEXT: xor t1, t0, a4
+; RV32ZBB-NEXT: neg a3, a4
+; RV32ZBB-NEXT: xor a7, a6, a3
+; RV32ZBB-NEXT: sltu a6, a7, a3
+; RV32ZBB-NEXT: xor t1, t0, a3
; RV32ZBB-NEXT: mv a5, a6
; RV32ZBB-NEXT: beqz t0, .LBB12_12
; RV32ZBB-NEXT: # %bb.11:
-; RV32ZBB-NEXT: sltu a5, t1, a4
+; RV32ZBB-NEXT: sltu a5, t1, a3
; RV32ZBB-NEXT: .LBB12_12:
-; RV32ZBB-NEXT: xor a2, a2, a4
-; RV32ZBB-NEXT: add t1, t1, a3
-; RV32ZBB-NEXT: add a7, a7, a3
-; RV32ZBB-NEXT: add t0, a2, a3
+; RV32ZBB-NEXT: xor a2, a2, a3
+; RV32ZBB-NEXT: add t1, t1, a4
+; RV32ZBB-NEXT: add a7, a7, a4
+; RV32ZBB-NEXT: add t0, a2, a4
; RV32ZBB-NEXT: sub a6, t1, a6
; RV32ZBB-NEXT: sub t1, t0, a5
; RV32ZBB-NEXT: or t2, a7, a6
; RV32ZBB-NEXT: neg t3, t1
; RV32ZBB-NEXT: snez t2, t2
-; RV32ZBB-NEXT: xor a1, a1, a4
-; RV32ZBB-NEXT: sltu a2, a2, a4
-; RV32ZBB-NEXT: add a1, a1, a3
+; RV32ZBB-NEXT: xor a1, a1, a3
+; RV32ZBB-NEXT: sltu a2, a2, a3
+; RV32ZBB-NEXT: add a1, a1, a4
; RV32ZBB-NEXT: sub a1, a1, a2
; RV32ZBB-NEXT: sltu a2, t0, a5
; RV32ZBB-NEXT: sub a1, a1, a2
@@ -1297,24 +1297,24 @@ define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_minmax_i128:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a4, 0(a1)
+; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: lw t1, 8(a2)
; RV32I-NEXT: lw a6, 0(a2)
; RV32I-NEXT: lw t2, 12(a2)
; RV32I-NEXT: lw t0, 4(a2)
; RV32I-NEXT: lw a7, 4(a1)
-; RV32I-NEXT: sltu a1, a4, t1
+; RV32I-NEXT: sltu a1, a3, t1
; RV32I-NEXT: sub a2, a5, t2
-; RV32I-NEXT: sltu t2, a3, a6
+; RV32I-NEXT: sltu t2, a4, a6
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: mv a2, t2
; RV32I-NEXT: beq a7, t0, .LBB17_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a7, t0
; RV32I-NEXT: .LBB17_2:
-; RV32I-NEXT: sub t1, a4, t1
+; RV32I-NEXT: sub t1, a3, t1
; RV32I-NEXT: sltu t3, t1, a2
; RV32I-NEXT: sub a1, a1, t3
; RV32I-NEXT: sub a2, t1, a2
@@ -1323,46 +1323,46 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sltu t1, a5, a1
; RV32I-NEXT: j .LBB17_5
; RV32I-NEXT: .LBB17_4:
-; RV32I-NEXT: sltu t1, a4, a2
+; RV32I-NEXT: sltu t1, a3, a2
; RV32I-NEXT: .LBB17_5:
; RV32I-NEXT: sub t0, a7, t0
; RV32I-NEXT: sub t0, t0, t2
-; RV32I-NEXT: sub a6, a3, a6
+; RV32I-NEXT: sub a6, a4, a6
; RV32I-NEXT: beq t0, a7, .LBB17_7
; RV32I-NEXT: # %bb.6:
-; RV32I-NEXT: sltu a3, a7, t0
+; RV32I-NEXT: sltu a4, a7, t0
; RV32I-NEXT: j .LBB17_8
; RV32I-NEXT: .LBB17_7:
-; RV32I-NEXT: sltu a3, a3, a6
+; RV32I-NEXT: sltu a4, a4, a6
; RV32I-NEXT: .LBB17_8:
; RV32I-NEXT: xor a5, a1, a5
-; RV32I-NEXT: xor a4, a2, a4
-; RV32I-NEXT: or a4, a4, a5
-; RV32I-NEXT: beqz a4, .LBB17_10
+; RV32I-NEXT: xor a3, a2, a3
+; RV32I-NEXT: or a3, a3, a5
+; RV32I-NEXT: beqz a3, .LBB17_10
; RV32I-NEXT: # %bb.9:
-; RV32I-NEXT: mv a3, t1
+; RV32I-NEXT: mv a4, t1
; RV32I-NEXT: .LBB17_10:
-; RV32I-NEXT: neg a4, a3
-; RV32I-NEXT: xor a7, a6, a4
-; RV32I-NEXT: sltu a6, a7, a4
-; RV32I-NEXT: xor t1, t0, a4
+; RV32I-NEXT: neg a3, a4
+; RV32I-NEXT: xor a7, a6, a3
+; RV32I-NEXT: sltu a6, a7, a3
+; RV32I-NEXT: xor t1, t0, a3
; RV32I-NEXT: mv a5, a6
; RV32I-NEXT: beqz t0, .LBB17_12
; RV32I-NEXT: # %bb.11:
-; RV32I-NEXT: sltu a5, t1, a4
+; RV32I-NEXT: sltu a5, t1, a3
; RV32I-NEXT: .LBB17_12:
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: add t1, t1, a3
-; RV32I-NEXT: add a7, a7, a3
-; RV32I-NEXT: add t0, a2, a3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: add t1, t1, a4
+; RV32I-NEXT: add a7, a7, a4
+; RV32I-NEXT: add t0, a2, a4
; RV32I-NEXT: sub a6, t1, a6
; RV32I-NEXT: sub t1, t0, a5
; RV32I-NEXT: or t2, a7, a6
; RV32I-NEXT: neg t3, t1
; RV32I-NEXT: snez t2, t2
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: sltu a2, a2, a4
-; RV32I-NEXT: add a1, a1, a3
+; RV32I-NEXT: xor a1, a1, a3
+; RV32I-NEXT: sltu a2, a2, a3
+; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: sltu a2, t0, a5
; RV32I-NEXT: sub a1, a1, a2
@@ -1410,24 +1410,24 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
;
; RV32ZBB-LABEL: abd_minmax_i128:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a1)
-; RV32ZBB-NEXT: lw a4, 8(a1)
+; RV32ZBB-NEXT: lw a4, 0(a1)
+; RV32ZBB-NEXT: lw a3, 8(a1)
; RV32ZBB-NEXT: lw a5, 12(a1)
; RV32ZBB-NEXT: lw t1, 8(a2)
; RV32ZBB-NEXT: lw a6, 0(a2)
; RV32ZBB-NEXT: lw t2, 12(a2)
; RV32ZBB-NEXT: lw t0, 4(a2)
; RV32ZBB-NEXT: lw a7, 4(a1)
-; RV32ZBB-NEXT: sltu a1, a4, t1
+; RV32ZBB-NEXT: sltu a1, a3, t1
; RV32ZBB-NEXT: sub a2, a5, t2
-; RV32ZBB-NEXT: sltu t2, a3, a6
+; RV32ZBB-NEXT: sltu t2, a4, a6
; RV32ZBB-NEXT: sub a1, a2, a1
; RV32ZBB-NEXT: mv a2, t2
; RV32ZBB-NEXT: beq a7, t0, .LBB17_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: sltu a2, a7, t0
; RV32ZBB-NEXT: .LBB17_2:
-; RV32ZBB-NEXT: sub t1, a4, t1
+; RV32ZBB-NEXT: sub t1, a3, t1
; RV32ZBB-NEXT: sltu t3, t1, a2
; RV32ZBB-NEXT: sub a1, a1, t3
; RV32ZBB-NEXT: sub a2, t1, a2
@@ -1436,46 +1436,46 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sltu t1, a5, a1
; RV32ZBB-NEXT: j .LBB17_5
; RV32ZBB-NEXT: .LBB17_4:
-; RV32ZBB-NEXT: sltu t1, a4, a2
+; RV32ZBB-NEXT: sltu t1, a3, a2
; RV32ZBB-NEXT: .LBB17_5:
; RV32ZBB-NEXT: sub t0, a7, t0
; RV32ZBB-NEXT: sub t0, t0, t2
-; RV32ZBB-NEXT: sub a6, a3, a6
+; RV32ZBB-NEXT: sub a6, a4, a6
; RV32ZBB-NEXT: beq t0, a7, .LBB17_7
; RV32ZBB-NEXT: # %bb.6:
-; RV32ZBB-NEXT: sltu a3, a7, t0
+; RV32ZBB-NEXT: sltu a4, a7, t0
; RV32ZBB-NEXT: j .LBB17_8
; RV32ZBB-NEXT: .LBB17_7:
-; RV32ZBB-NEXT: sltu a3, a3, a6
+; RV32ZBB-NEXT: sltu a4, a4, a6
; RV32ZBB-NEXT: .LBB17_8:
; RV32ZBB-NEXT: xor a5, a1, a5
-; RV32ZBB-NEXT: xor a4, a2, a4
-; RV32ZBB-NEXT: or a4, a4, a5
-; RV32ZBB-NEXT: beqz a4, .LBB17_10
+; RV32ZBB-NEXT: xor a3, a2, a3
+; RV32ZBB-NEXT: or a3, a3, a5
+; RV32ZBB-NEXT: beqz a3, .LBB17_10
; RV32ZBB-NEXT: # %bb.9:
-; RV32ZBB-NEXT: mv a3, t1
+; RV32ZBB-NEXT: mv a4, t1
; RV32ZBB-NEXT: .LBB17_10:
-; RV32ZBB-NEXT: neg a4, a3
-; RV32ZBB-NEXT: xor a7, a6, a4
-; RV32ZBB-NEXT: sltu a6, a7, a4
-; RV32ZBB-NEXT: xor t1, t0, a4
+; RV32ZBB-NEXT: neg a3, a4
+; RV32ZBB-NEXT: xor a7, a6, a3
+; RV32ZBB-NEXT: sltu a6, a7, a3
+; RV32ZBB-NEXT: xor t1, t0, a3
; RV32ZBB-NEXT: mv a5, a6
; RV32ZBB-NEXT: beqz t0, .LBB17_12
; RV32ZBB-NEXT: # %bb.11:
-; RV32ZBB-NEXT: sltu a5, t1, a4
+; RV32ZBB-NEXT: sltu a5, t1, a3
; RV32ZBB-NEXT: .LBB17_12:
-; RV32ZBB-NEXT: xor a2, a2, a4
-; RV32ZBB-NEXT: add t1, t1, a3
-; RV32ZBB-NEXT: add a7, a7, a3
-; RV32ZBB-NEXT: add t0, a2, a3
+; RV32ZBB-NEXT: xor a2, a2, a3
+; RV32ZBB-NEXT: add t1, t1, a4
+; RV32ZBB-NEXT: add a7, a7, a4
+; RV32ZBB-NEXT: add t0, a2, a4
; RV32ZBB-NEXT: sub a6, t1, a6
; RV32ZBB-NEXT: sub t1, t0, a5
; RV32ZBB-NEXT: or t2, a7, a6
; RV32ZBB-NEXT: neg t3, t1
; RV32ZBB-NEXT: snez t2, t2
-; RV32ZBB-NEXT: xor a1, a1, a4
-; RV32ZBB-NEXT: sltu a2, a2, a4
-; RV32ZBB-NEXT: add a1, a1, a3
+; RV32ZBB-NEXT: xor a1, a1, a3
+; RV32ZBB-NEXT: sltu a2, a2, a3
+; RV32ZBB-NEXT: add a1, a1, a4
; RV32ZBB-NEXT: sub a1, a1, a2
; RV32ZBB-NEXT: sltu a2, t0, a5
; RV32ZBB-NEXT: sub a1, a1, a2
diff --git a/llvm/test/CodeGen/RISCV/abdu.ll b/llvm/test/CodeGen/RISCV/abdu.ll
index 745a0724c701c..017435f404317 100644
--- a/llvm/test/CodeGen/RISCV/abdu.ll
+++ b/llvm/test/CodeGen/RISCV/abdu.ll
@@ -540,71 +540,71 @@ define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_ext_i128:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a4, 0(a1)
+; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
-; RV32I-NEXT: lw a7, 8(a2)
+; RV32I-NEXT: lw a6, 8(a2)
; RV32I-NEXT: lw t0, 0(a2)
; RV32I-NEXT: lw t1, 12(a2)
-; RV32I-NEXT: lw a6, 4(a2)
+; RV32I-NEXT: lw a7, 4(a2)
; RV32I-NEXT: lw a1, 4(a1)
-; RV32I-NEXT: sltu a2, a4, a7
+; RV32I-NEXT: sltu a2, a3, a6
; RV32I-NEXT: sub t1, a5, t1
-; RV32I-NEXT: sltu t2, a3, t0
+; RV32I-NEXT: sltu t2, a4, t0
; RV32I-NEXT: sub a2, t1, a2
; RV32I-NEXT: mv t1, t2
-; RV32I-NEXT: beq a1, a6, .LBB11_2
+; RV32I-NEXT: beq a1, a7, .LBB11_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: sltu t1, a1, a6
+; RV32I-NEXT: sltu t1, a1, a7
; RV32I-NEXT: .LBB11_2:
-; RV32I-NEXT: sub a7, a4, a7
-; RV32I-NEXT: sltu t3, a7, t1
+; RV32I-NEXT: sub a6, a3, a6
+; RV32I-NEXT: sltu t3, a6, t1
; RV32I-NEXT: sub a2, a2, t3
-; RV32I-NEXT: sub a7, a7, t1
+; RV32I-NEXT: sub a6, a6, t1
; RV32I-NEXT: beq a2, a5, .LBB11_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sltu t1, a5, a2
; RV32I-NEXT: j .LBB11_5
; RV32I-NEXT: .LBB11_4:
-; RV32I-NEXT: sltu t1, a4, a7
+; RV32I-NEXT: sltu t1, a3, a6
; RV32I-NEXT: .LBB11_5:
-; RV32I-NEXT: sub a6, a1, a6
-; RV32I-NEXT: sub a6, a6, t2
-; RV32I-NEXT: sub t0, a3, t0
-; RV32I-NEXT: beq a6, a1, .LBB11_7
+; RV32I-NEXT: sub a7, a1, a7
+; RV32I-NEXT: sub a7, a7, t2
+; RV32I-NEXT: sub t0, a4, t0
+; RV32I-NEXT: beq a7, a1, .LBB11_7
; RV32I-NEXT: # %bb.6:
-; RV32I-NEXT: sltu a1, a1, a6
+; RV32I-NEXT: sltu a1, a1, a7
; RV32I-NEXT: j .LBB11_8
; RV32I-NEXT: .LBB11_7:
-; RV32I-NEXT: sltu a1, a3, t0
+; RV32I-NEXT: sltu a1, a4, t0
; RV32I-NEXT: .LBB11_8:
; RV32I-NEXT: xor a5, a2, a5
-; RV32I-NEXT: xor a3, a7, a4
+; RV32I-NEXT: xor a3, a6, a3
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: beqz a3, .LBB11_10
; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: mv a1, t1
; RV32I-NEXT: .LBB11_10:
; RV32I-NEXT: neg t1, a1
-; RV32I-NEXT: xor a3, a7, t1
+; RV32I-NEXT: xor a3, a6, t1
; RV32I-NEXT: xor a4, a2, t1
; RV32I-NEXT: xor a2, t0, t1
-; RV32I-NEXT: sltu a7, a3, t1
+; RV32I-NEXT: sltu a6, a3, t1
; RV32I-NEXT: add a4, a4, a1
; RV32I-NEXT: sltu a5, a2, t1
-; RV32I-NEXT: sub a4, a4, a7
-; RV32I-NEXT: xor a7, a6, t1
+; RV32I-NEXT: sub a4, a4, a6
+; RV32I-NEXT: xor a6, a7, t1
; RV32I-NEXT: mv t0, a5
-; RV32I-NEXT: beqz a6, .LBB11_12
+; RV32I-NEXT: beqz a7, .LBB11_12
; RV32I-NEXT: # %bb.11:
-; RV32I-NEXT: sltu t0, a7, t1
+; RV32I-NEXT: sltu t0, a6, t1
; RV32I-NEXT: .LBB11_12:
; RV32I-NEXT: add a3, a3, a1
-; RV32I-NEXT: add a7, a7, a1
-; RV32I-NEXT: sltu a6, a3, t0
+; RV32I-NEXT: add a6, a6, a1
+; RV32I-NEXT: sltu a7, a3, t0
; RV32I-NEXT: sub a3, a3, t0
-; RV32I-NEXT: sub a5, a7, a5
-; RV32I-NEXT: sub a4, a4, a6
+; RV32I-NEXT: sub a5, a6, a5
+; RV32I-NEXT: sub a4, a4, a7
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a5, 4(a0)
@@ -636,71 +636,71 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
;
; RV32ZBB-LABEL: abd_ext_i128:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a1)
-; RV32ZBB-NEXT: lw a4, 8(a1)
+; RV32ZBB-NEXT: lw a4, 0(a1)
+; RV32ZBB-NEXT: lw a3, 8(a1)
; RV32ZBB-NEXT: lw a5, 12(a1)
-; RV32ZBB-NEXT: lw a7, 8(a2)
+; RV32ZBB-NEXT: lw a6, 8(a2)
; RV32ZBB-NEXT: lw t0, 0(a2)
; RV32ZBB-NEXT: lw t1, 12(a2)
-; RV32ZBB-NEXT: lw a6, 4(a2)
+; RV32ZBB-NEXT: lw a7, 4(a2)
; RV32ZBB-NEXT: lw a1, 4(a1)
-; RV32ZBB-NEXT: sltu a2, a4, a7
+; RV32ZBB-NEXT: sltu a2, a3, a6
; RV32ZBB-NEXT: sub t1, a5, t1
-; RV32ZBB-NEXT: sltu t2, a3, t0
+; RV32ZBB-NEXT: sltu t2, a4, t0
; RV32ZBB-NEXT: sub a2, t1, a2
; RV32ZBB-NEXT: mv t1, t2
-; RV32ZBB-NEXT: beq a1, a6, .LBB11_2
+; RV32ZBB-NEXT: beq a1, a7, .LBB11_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: sltu t1, a1, a6
+; RV32ZBB-NEXT: sltu t1, a1, a7
; RV32ZBB-NEXT: .LBB11_2:
-; RV32ZBB-NEXT: sub a7, a4, a7
-; RV32ZBB-NEXT: sltu t3, a7, t1
+; RV32ZBB-NEXT: sub a6, a3, a6
+; RV32ZBB-NEXT: sltu t3, a6, t1
; RV32ZBB-NEXT: sub a2, a2, t3
-; RV32ZBB-NEXT: sub a7, a7, t1
+; RV32ZBB-NEXT: sub a6, a6, t1
; RV32ZBB-NEXT: beq a2, a5, .LBB11_4
; RV32ZBB-NEXT: # %bb.3:
; RV32ZBB-NEXT: sltu t1, a5, a2
; RV32ZBB-NEXT: j .LBB11_5
; RV32ZBB-NEXT: .LBB11_4:
-; RV32ZBB-NEXT: sltu t1, a4, a7
+; RV32ZBB-NEXT: sltu t1, a3, a6
; RV32ZBB-NEXT: .LBB11_5:
-; RV32ZBB-NEXT: sub a6, a1, a6
-; RV32ZBB-NEXT: sub a6, a6, t2
-; RV32ZBB-NEXT: sub t0, a3, t0
-; RV32ZBB-NEXT: beq a6, a1, .LBB11_7
+; RV32ZBB-NEXT: sub a7, a1, a7
+; RV32ZBB-NEXT: sub a7, a7, t2
+; RV32ZBB-NEXT: sub t0, a4, t0
+; RV32ZBB-NEXT: beq a7, a1, .LBB11_7
; RV32ZBB-NEXT: # %bb.6:
-; RV32ZBB-NEXT: sltu a1, a1, a6
+; RV32ZBB-NEXT: sltu a1, a1, a7
; RV32ZBB-NEXT: j .LBB11_8
; RV32ZBB-NEXT: .LBB11_7:
-; RV32ZBB-NEXT: sltu a1, a3, t0
+; RV32ZBB-NEXT: sltu a1, a4, t0
; RV32ZBB-NEXT: .LBB11_8:
; RV32ZBB-NEXT: xor a5, a2, a5
-; RV32ZBB-NEXT: xor a3, a7, a4
+; RV32ZBB-NEXT: xor a3, a6, a3
; RV32ZBB-NEXT: or a3, a3, a5
; RV32ZBB-NEXT: beqz a3, .LBB11_10
; RV32ZBB-NEXT: # %bb.9:
; RV32ZBB-NEXT: mv a1, t1
; RV32ZBB-NEXT: .LBB11_10:
; RV32ZBB-NEXT: neg t1, a1
-; RV32ZBB-NEXT: xor a3, a7, t1
+; RV32ZBB-NEXT: xor a3, a6, t1
; RV32ZBB-NEXT: xor a4, a2, t1
; RV32ZBB-NEXT: xor a2, t0, t1
-; RV32ZBB-NEXT: sltu a7, a3, t1
+; RV32ZBB-NEXT: sltu a6, a3, t1
; RV32ZBB-NEXT: add a4, a4, a1
; RV32ZBB-NEXT: sltu a5, a2, t1
-; RV32ZBB-NEXT: sub a4, a4, a7
-; RV32ZBB-NEXT: xor a7, a6, t1
+; RV32ZBB-NEXT: sub a4, a4, a6
+; RV32ZBB-NEXT: xor a6, a7, t1
; RV32ZBB-NEXT: mv t0, a5
-; RV32ZBB-NEXT: beqz a6, .LBB11_12
+; RV32ZBB-NEXT: beqz a7, .LBB11_12
; RV32ZBB-NEXT: # %bb.11:
-; RV32ZBB-NEXT: sltu t0, a7, t1
+; RV32ZBB-NEXT: sltu t0, a6, t1
; RV32ZBB-NEXT: .LBB11_12:
; RV32ZBB-NEXT: add a3, a3, a1
-; RV32ZBB-NEXT: add a7, a7, a1
-; RV32ZBB-NEXT: sltu a6, a3, t0
+; RV32ZBB-NEXT: add a6, a6, a1
+; RV32ZBB-NEXT: sltu a7, a3, t0
; RV32ZBB-NEXT: sub a3, a3, t0
-; RV32ZBB-NEXT: sub a5, a7, a5
-; RV32ZBB-NEXT: sub a4, a4, a6
+; RV32ZBB-NEXT: sub a5, a6, a5
+; RV32ZBB-NEXT: sub a4, a4, a7
; RV32ZBB-NEXT: add a1, a2, a1
; RV32ZBB-NEXT: sw a1, 0(a0)
; RV32ZBB-NEXT: sw a5, 4(a0)
@@ -740,71 +740,71 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_ext_i128_undef:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a4, 0(a1)
+; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
-; RV32I-NEXT: lw a7, 8(a2)
+; RV32I-NEXT: lw a6, 8(a2)
; RV32I-NEXT: lw t0, 0(a2)
; RV32I-NEXT: lw t1, 12(a2)
-; RV32I-NEXT: lw a6, 4(a2)
+; RV32I-NEXT: lw a7, 4(a2)
; RV32I-NEXT: lw a1, 4(a1)
-; RV32I-NEXT: sltu a2, a4, a7
+; RV32I-NEXT: sltu a2, a3, a6
; RV32I-NEXT: sub t1, a5, t1
-; RV32I-NEXT: sltu t2, a3, t0
+; RV32I-NEXT: sltu t2, a4, t0
; RV32I-NEXT: sub a2, t1, a2
; RV32I-NEXT: mv t1, t2
-; RV32I-NEXT: beq a1, a6, .LBB12_2
+; RV32I-NEXT: beq a1, a7, .LBB12_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: sltu t1, a1, a6
+; RV32I-NEXT: sltu t1, a1, a7
; RV32I-NEXT: .LBB12_2:
-; RV32I-NEXT: sub a7, a4, a7
-; RV32I-NEXT: sltu t3, a7, t1
+; RV32I-NEXT: sub a6, a3, a6
+; RV32I-NEXT: sltu t3, a6, t1
; RV32I-NEXT: sub a2, a2, t3
-; RV32I-NEXT: sub a7, a7, t1
+; RV32I-NEXT: sub a6, a6, t1
; RV32I-NEXT: beq a2, a5, .LBB12_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sltu t1, a5, a2
; RV32I-NEXT: j .LBB12_5
; RV32I-NEXT: .LBB12_4:
-; RV32I-NEXT: sltu t1, a4, a7
+; RV32I-NEXT: sltu t1, a3, a6
; RV32I-NEXT: .LBB12_5:
-; RV32I-NEXT: sub a6, a1, a6
-; RV32I-NEXT: sub a6, a6, t2
-; RV32I-NEXT: sub t0, a3, t0
-; RV32I-NEXT: beq a6, a1, .LBB12_7
+; RV32I-NEXT: sub a7, a1, a7
+; RV32I-NEXT: sub a7, a7, t2
+; RV32I-NEXT: sub t0, a4, t0
+; RV32I-NEXT: beq a7, a1, .LBB12_7
; RV32I-NEXT: # %bb.6:
-; RV32I-NEXT: sltu a1, a1, a6
+; RV32I-NEXT: sltu a1, a1, a7
; RV32I-NEXT: j .LBB12_8
; RV32I-NEXT: .LBB12_7:
-; RV32I-NEXT: sltu a1, a3, t0
+; RV32I-NEXT: sltu a1, a4, t0
; RV32I-NEXT: .LBB12_8:
; RV32I-NEXT: xor a5, a2, a5
-; RV32I-NEXT: xor a3, a7, a4
+; RV32I-NEXT: xor a3, a6, a3
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: beqz a3, .LBB12_10
; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: mv a1, t1
; RV32I-NEXT: .LBB12_10:
; RV32I-NEXT: neg t1, a1
-; RV32I-NEXT: xor a3, a7, t1
+; RV32I-NEXT: xor a3, a6, t1
; RV32I-NEXT: xor a4, a2, t1
; RV32I-NEXT: xor a2, t0, t1
-; RV32I-NEXT: sltu a7, a3, t1
+; RV32I-NEXT: sltu a6, a3, t1
; RV32I-NEXT: add a4, a4, a1
; RV32I-NEXT: sltu a5, a2, t1
-; RV32I-NEXT: sub a4, a4, a7
-; RV32I-NEXT: xor a7, a6, t1
+; RV32I-NEXT: sub a4, a4, a6
+; RV32I-NEXT: xor a6, a7, t1
; RV32I-NEXT: mv t0, a5
-; RV32I-NEXT: beqz a6, .LBB12_12
+; RV32I-NEXT: beqz a7, .LBB12_12
; RV32I-NEXT: # %bb.11:
-; RV32I-NEXT: sltu t0, a7, t1
+; RV32I-NEXT: sltu t0, a6, t1
; RV32I-NEXT: .LBB12_12:
; RV32I-NEXT: add a3, a3, a1
-; RV32I-NEXT: add a7, a7, a1
-; RV32I-NEXT: sltu a6, a3, t0
+; RV32I-NEXT: add a6, a6, a1
+; RV32I-NEXT: sltu a7, a3, t0
; RV32I-NEXT: sub a3, a3, t0
-; RV32I-NEXT: sub a5, a7, a5
-; RV32I-NEXT: sub a4, a4, a6
+; RV32I-NEXT: sub a5, a6, a5
+; RV32I-NEXT: sub a4, a4, a7
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a5, 4(a0)
@@ -836,71 +836,71 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
;
; RV32ZBB-LABEL: abd_ext_i128_undef:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a1)
-; RV32ZBB-NEXT: lw a4, 8(a1)
+; RV32ZBB-NEXT: lw a4, 0(a1)
+; RV32ZBB-NEXT: lw a3, 8(a1)
; RV32ZBB-NEXT: lw a5, 12(a1)
-; RV32ZBB-NEXT: lw a7, 8(a2)
+; RV32ZBB-NEXT: lw a6, 8(a2)
; RV32ZBB-NEXT: lw t0, 0(a2)
; RV32ZBB-NEXT: lw t1, 12(a2)
-; RV32ZBB-NEXT: lw a6, 4(a2)
+; RV32ZBB-NEXT: lw a7, 4(a2)
; RV32ZBB-NEXT: lw a1, 4(a1)
-; RV32ZBB-NEXT: sltu a2, a4, a7
+; RV32ZBB-NEXT: sltu a2, a3, a6
; RV32ZBB-NEXT: sub t1, a5, t1
-; RV32ZBB-NEXT: sltu t2, a3, t0
+; RV32ZBB-NEXT: sltu t2, a4, t0
; RV32ZBB-NEXT: sub a2, t1, a2
; RV32ZBB-NEXT: mv t1, t2
-; RV32ZBB-NEXT: beq a1, a6, .LBB12_2
+; RV32ZBB-NEXT: beq a1, a7, .LBB12_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: sltu t1, a1, a6
+; RV32ZBB-NEXT: sltu t1, a1, a7
; RV32ZBB-NEXT: .LBB12_2:
-; RV32ZBB-NEXT: sub a7, a4, a7
-; RV32ZBB-NEXT: sltu t3, a7, t1
+; RV32ZBB-NEXT: sub a6, a3, a6
+; RV32ZBB-NEXT: sltu t3, a6, t1
; RV32ZBB-NEXT: sub a2, a2, t3
-; RV32ZBB-NEXT: sub a7, a7, t1
+; RV32ZBB-NEXT: sub a6, a6, t1
; RV32ZBB-NEXT: beq a2, a5, .LBB12_4
; RV32ZBB-NEXT: # %bb.3:
; RV32ZBB-NEXT: sltu t1, a5, a2
; RV32ZBB-NEXT: j .LBB12_5
; RV32ZBB-NEXT: .LBB12_4:
-; RV32ZBB-NEXT: sltu t1, a4, a7
+; RV32ZBB-NEXT: sltu t1, a3, a6
; RV32ZBB-NEXT: .LBB12_5:
-; RV32ZBB-NEXT: sub a6, a1, a6
-; RV32ZBB-NEXT: sub a6, a6, t2
-; RV32ZBB-NEXT: sub t0, a3, t0
-; RV32ZBB-NEXT: beq a6, a1, .LBB12_7
+; RV32ZBB-NEXT: sub a7, a1, a7
+; RV32ZBB-NEXT: sub a7, a7, t2
+; RV32ZBB-NEXT: sub t0, a4, t0
+; RV32ZBB-NEXT: beq a7, a1, .LBB12_7
; RV32ZBB-NEXT: # %bb.6:
-; RV32ZBB-NEXT: sltu a1, a1, a6
+; RV32ZBB-NEXT: sltu a1, a1, a7
; RV32ZBB-NEXT: j .LBB12_8
; RV32ZBB-NEXT: .LBB12_7:
-; RV32ZBB-NEXT: sltu a1, a3, t0
+; RV32ZBB-NEXT: sltu a1, a4, t0
; RV32ZBB-NEXT: .LBB12_8:
; RV32ZBB-NEXT: xor a5, a2, a5
-; RV32ZBB-NEXT: xor a3, a7, a4
+; RV32ZBB-NEXT: xor a3, a6, a3
; RV32ZBB-NEXT: or a3, a3, a5
; RV32ZBB-NEXT: beqz a3, .LBB12_10
; RV32ZBB-NEXT: # %bb.9:
; RV32ZBB-NEXT: mv a1, t1
; RV32ZBB-NEXT: .LBB12_10:
; RV32ZBB-NEXT: neg t1, a1
-; RV32ZBB-NEXT: xor a3, a7, t1
+; RV32ZBB-NEXT: xor a3, a6, t1
; RV32ZBB-NEXT: xor a4, a2, t1
; RV32ZBB-NEXT: xor a2, t0, t1
-; RV32ZBB-NEXT: sltu a7, a3, t1
+; RV32ZBB-NEXT: sltu a6, a3, t1
; RV32ZBB-NEXT: add a4, a4, a1
; RV32ZBB-NEXT: sltu a5, a2, t1
-; RV32ZBB-NEXT: sub a4, a4, a7
-; RV32ZBB-NEXT: xor a7, a6, t1
+; RV32ZBB-NEXT: sub a4, a4, a6
+; RV32ZBB-NEXT: xor a6, a7, t1
; RV32ZBB-NEXT: mv t0, a5
-; RV32ZBB-NEXT: beqz a6, .LBB12_12
+; RV32ZBB-NEXT: beqz a7, .LBB12_12
; RV32ZBB-NEXT: # %bb.11:
-; RV32ZBB-NEXT: sltu t0, a7, t1
+; RV32ZBB-NEXT: sltu t0, a6, t1
; RV32ZBB-NEXT: .LBB12_12:
; RV32ZBB-NEXT: add a3, a3, a1
-; RV32ZBB-NEXT: add a7, a7, a1
-; RV32ZBB-NEXT: sltu a6, a3, t0
+; RV32ZBB-NEXT: add a6, a6, a1
+; RV32ZBB-NEXT: sltu a7, a3, t0
; RV32ZBB-NEXT: sub a3, a3, t0
-; RV32ZBB-NEXT: sub a5, a7, a5
-; RV32ZBB-NEXT: sub a4, a4, a6
+; RV32ZBB-NEXT: sub a5, a6, a5
+; RV32ZBB-NEXT: sub a4, a4, a7
; RV32ZBB-NEXT: add a1, a2, a1
; RV32ZBB-NEXT: sw a1, 0(a0)
; RV32ZBB-NEXT: sw a5, 4(a0)
@@ -1131,71 +1131,71 @@ define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_minmax_i128:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a4, 0(a1)
+; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
-; RV32I-NEXT: lw a7, 8(a2)
+; RV32I-NEXT: lw a6, 8(a2)
; RV32I-NEXT: lw t0, 0(a2)
; RV32I-NEXT: lw t1, 12(a2)
-; RV32I-NEXT: lw a6, 4(a2)
+; RV32I-NEXT: lw a7, 4(a2)
; RV32I-NEXT: lw a1, 4(a1)
-; RV32I-NEXT: sltu a2, a4, a7
+; RV32I-NEXT: sltu a2, a3, a6
; RV32I-NEXT: sub t1, a5, t1
-; RV32I-NEXT: sltu t2, a3, t0
+; RV32I-NEXT: sltu t2, a4, t0
; RV32I-NEXT: sub a2, t1, a2
; RV32I-NEXT: mv t1, t2
-; RV32I-NEXT: beq a1, a6, .LBB17_2
+; RV32I-NEXT: beq a1, a7, .LBB17_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: sltu t1, a1, a6
+; RV32I-NEXT: sltu t1, a1, a7
; RV32I-NEXT: .LBB17_2:
-; RV32I-NEXT: sub a7, a4, a7
-; RV32I-NEXT: sltu t3, a7, t1
+; RV32I-NEXT: sub a6, a3, a6
+; RV32I-NEXT: sltu t3, a6, t1
; RV32I-NEXT: sub a2, a2, t3
-; RV32I-NEXT: sub a7, a7, t1
+; RV32I-NEXT: sub a6, a6, t1
; RV32I-NEXT: beq a2, a5, .LBB17_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sltu t1, a5, a2
; RV32I-NEXT: j .LBB17_5
; RV32I-NEXT: .LBB17_4:
-; RV32I-NEXT: sltu t1, a4, a7
+; RV32I-NEXT: sltu t1, a3, a6
; RV32I-NEXT: .LBB17_5:
-; RV32I-NEXT: sub a6, a1, a6
-; RV32I-NEXT: sub a6, a6, t2
-; RV32I-NEXT: sub t0, a3, t0
-; RV32I-NEXT: beq a6, a1, .LBB17_7
+; RV32I-NEXT: sub a7, a1, a7
+; RV32I-NEXT: sub a7, a7, t2
+; RV32I-NEXT: sub t0, a4, t0
+; RV32I-NEXT: beq a7, a1, .LBB17_7
; RV32I-NEXT: # %bb.6:
-; RV32I-NEXT: sltu a1, a1, a6
+; RV32I-NEXT: sltu a1, a1, a7
; RV32I-NEXT: j .LBB17_8
; RV32I-NEXT: .LBB17_7:
-; RV32I-NEXT: sltu a1, a3, t0
+; RV32I-NEXT: sltu a1, a4, t0
; RV32I-NEXT: .LBB17_8:
; RV32I-NEXT: xor a5, a2, a5
-; RV32I-NEXT: xor a3, a7, a4
+; RV32I-NEXT: xor a3, a6, a3
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: beqz a3, .LBB17_10
; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: mv a1, t1
; RV32I-NEXT: .LBB17_10:
; RV32I-NEXT: neg t1, a1
-; RV32I-NEXT: xor a3, a7, t1
+; RV32I-NEXT: xor a3, a6, t1
; RV32I-NEXT: xor a4, a2, t1
; RV32I-NEXT: xor a2, t0, t1
-; RV32I-NEXT: sltu a7, a3, t1
+; RV32I-NEXT: sltu a6, a3, t1
; RV32I-NEXT: add a4, a4, a1
; RV32I-NEXT: sltu a5, a2, t1
-; RV32I-NEXT: sub a4, a4, a7
-; RV32I-NEXT: xor a7, a6, t1
+; RV32I-NEXT: sub a4, a4, a6
+; RV32I-NEXT: xor a6, a7, t1
; RV32I-NEXT: mv t0, a5
-; RV32I-NEXT: beqz a6, .LBB17_12
+; RV32I-NEXT: beqz a7, .LBB17_12
; RV32I-NEXT: # %bb.11:
-; RV32I-NEXT: sltu t0, a7, t1
+; RV32I-NEXT: sltu t0, a6, t1
; RV32I-NEXT: .LBB17_12:
; RV32I-NEXT: add a3, a3, a1
-; RV32I-NEXT: add a7, a7, a1
-; RV32I-NEXT: sltu a6, a3, t0
+; RV32I-NEXT: add a6, a6, a1
+; RV32I-NEXT: sltu a7, a3, t0
; RV32I-NEXT: sub a3, a3, t0
-; RV32I-NEXT: sub a5, a7, a5
-; RV32I-NEXT: sub a4, a4, a6
+; RV32I-NEXT: sub a5, a6, a5
+; RV32I-NEXT: sub a4, a4, a7
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a5, 4(a0)
@@ -1227,71 +1227,71 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
;
; RV32ZBB-LABEL: abd_minmax_i128:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a1)
-; RV32ZBB-NEXT: lw a4, 8(a1)
+; RV32ZBB-NEXT: lw a4, 0(a1)
+; RV32ZBB-NEXT: lw a3, 8(a1)
; RV32ZBB-NEXT: lw a5, 12(a1)
-; RV32ZBB-NEXT: lw a7, 8(a2)
+; RV32ZBB-NEXT: lw a6, 8(a2)
; RV32ZBB-NEXT: lw t0, 0(a2)
; RV32ZBB-NEXT: lw t1, 12(a2)
-; RV32ZBB-NEXT: lw a6, 4(a2)
+; RV32ZBB-NEXT: lw a7, 4(a2)
; RV32ZBB-NEXT: lw a1, 4(a1)
-; RV32ZBB-NEXT: sltu a2, a4, a7
+; RV32ZBB-NEXT: sltu a2, a3, a6
; RV32ZBB-NEXT: sub t1, a5, t1
-; RV32ZBB-NEXT: sltu t2, a3, t0
+; RV32ZBB-NEXT: sltu t2, a4, t0
; RV32ZBB-NEXT: sub a2, t1, a2
; RV32ZBB-NEXT: mv t1, t2
-; RV32ZBB-NEXT: beq a1, a6, .LBB17_2
+; RV32ZBB-NEXT: beq a1, a7, .LBB17_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: sltu t1, a1, a6
+; RV32ZBB-NEXT: sltu t1, a1, a7
; RV32ZBB-NEXT: .LBB17_2:
-; RV32ZBB-NEXT: sub a7, a4, a7
-; RV32ZBB-NEXT: sltu t3, a7, t1
+; RV32ZBB-NEXT: sub a6, a3, a6
+; RV32ZBB-NEXT: sltu t3, a6, t1
; RV32ZBB-NEXT: sub a2, a2, t3
-; RV32ZBB-NEXT: sub a7, a7, t1
+; RV32ZBB-NEXT: sub a6, a6, t1
; RV32ZBB-NEXT: beq a2, a5, .LBB17_4
; RV32ZBB-NEXT: # %bb.3:
; RV32ZBB-NEXT: sltu t1, a5, a2
; RV32ZBB-NEXT: j .LBB17_5
; RV32ZBB-NEXT: .LBB17_4:
-; RV32ZBB-NEXT: sltu t1, a4, a7
+; RV32ZBB-NEXT: sltu t1, a3, a6
; RV32ZBB-NEXT: .LBB17_5:
-; RV32ZBB-NEXT: sub a6, a1, a6
-; RV32ZBB-NEXT: sub a6, a6, t2
-; RV32ZBB-NEXT: sub t0, a3, t0
-; RV32ZBB-NEXT: beq a6, a1, .LBB17_7
+; RV32ZBB-NEXT: sub a7, a1, a7
+; RV32ZBB-NEXT: sub a7, a7, t2
+; RV32ZBB-NEXT: sub t0, a4, t0
+; RV32ZBB-NEXT: beq a7, a1, .LBB17_7
; RV32ZBB-NEXT: # %bb.6:
-; RV32ZBB-NEXT: sltu a1, a1, a6
+; RV32ZBB-NEXT: sltu a1, a1, a7
; RV32ZBB-NEXT: j .LBB17_8
; RV32ZBB-NEXT: .LBB17_7:
-; RV32ZBB-NEXT: sltu a1, a3, t0
+; RV32ZBB-NEXT: sltu a1, a4, t0
; RV32ZBB-NEXT: .LBB17_8:
; RV32ZBB-NEXT: xor a5, a2, a5
-; RV32ZBB-NEXT: xor a3, a7, a4
+; RV32ZBB-NEXT: xor a3, a6, a3
; RV32ZBB-NEXT: or a3, a3, a5
; RV32ZBB-NEXT: beqz a3, .LBB17_10
; RV32ZBB-NEXT: # %bb.9:
; RV32ZBB-NEXT: mv a1, t1
; RV32ZBB-NEXT: .LBB17_10:
; RV32ZBB-NEXT: neg t1, a1
-; RV32ZBB-NEXT: xor a3, a7, t1
+; RV32ZBB-NEXT: xor a3, a6, t1
; RV32ZBB-NEXT: xor a4, a2, t1
; RV32ZBB-NEXT: xor a2, t0, t1
-; RV32ZBB-NEXT: sltu a7, a3, t1
+; RV32ZBB-NEXT: sltu a6, a3, t1
; RV32ZBB-NEXT: add a4, a4, a1
; RV32ZBB-NEXT: sltu a5, a2, t1
-; RV32ZBB-NEXT: sub a4, a4, a7
-; RV32ZBB-NEXT: xor a7, a6, t1
+; RV32ZBB-NEXT: sub a4, a4, a6
+; RV32ZBB-NEXT: xor a6, a7, t1
; RV32ZBB-NEXT: mv t0, a5
-; RV32ZBB-NEXT: beqz a6, .LBB17_12
+; RV32ZBB-NEXT: beqz a7, .LBB17_12
; RV32ZBB-NEXT: # %bb.11:
-; RV32ZBB-NEXT: sltu t0, a7, t1
+; RV32ZBB-NEXT: sltu t0, a6, t1
; RV32ZBB-NEXT: .LBB17_12:
; RV32ZBB-NEXT: add a3, a3, a1
-; RV32ZBB-NEXT: add a7, a7, a1
-; RV32ZBB-NEXT: sltu a6, a3, t0
+; RV32ZBB-NEXT: add a6, a6, a1
+; RV32ZBB-NEXT: sltu a7, a3, t0
; RV32ZBB-NEXT: sub a3, a3, t0
-; RV32ZBB-NEXT: sub a5, a7, a5
-; RV32ZBB-NEXT: sub a4, a4, a6
+; RV32ZBB-NEXT: sub a5, a6, a5
+; RV32ZBB-NEXT: sub a4, a4, a7
; RV32ZBB-NEXT: add a1, a2, a1
; RV32ZBB-NEXT: sw a1, 0(a0)
; RV32ZBB-NEXT: sw a5, 4(a0)
@@ -1524,71 +1524,71 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_cmp_i128:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a4, 0(a1)
+; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
-; RV32I-NEXT: lw a7, 8(a2)
+; RV32I-NEXT: lw a6, 8(a2)
; RV32I-NEXT: lw t0, 0(a2)
; RV32I-NEXT: lw t1, 12(a2)
-; RV32I-NEXT: lw a6, 4(a2)
+; RV32I-NEXT: lw a7, 4(a2)
; RV32I-NEXT: lw a1, 4(a1)
-; RV32I-NEXT: sltu a2, a4, a7
+; RV32I-NEXT: sltu a2, a3, a6
; RV32I-NEXT: sub t1, a5, t1
-; RV32I-NEXT: sltu t2, a3, t0
+; RV32I-NEXT: sltu t2, a4, t0
; RV32I-NEXT: sub a2, t1, a2
; RV32I-NEXT: mv t1, t2
-; RV32I-NEXT: beq a1, a6, .LBB22_2
+; RV32I-NEXT: beq a1, a7, .LBB22_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: sltu t1, a1, a6
+; RV32I-NEXT: sltu t1, a1, a7
; RV32I-NEXT: .LBB22_2:
-; RV32I-NEXT: sub a7, a4, a7
-; RV32I-NEXT: sltu t3, a7, t1
+; RV32I-NEXT: sub a6, a3, a6
+; RV32I-NEXT: sltu t3, a6, t1
; RV32I-NEXT: sub a2, a2, t3
-; RV32I-NEXT: sub a7, a7, t1
+; RV32I-NEXT: sub a6, a6, t1
; RV32I-NEXT: beq a2, a5, .LBB22_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sltu t1, a5, a2
; RV32I-NEXT: j .LBB22_5
; RV32I-NEXT: .LBB22_4:
-; RV32I-NEXT: sltu t1, a4, a7
+; RV32I-NEXT: sltu t1, a3, a6
; RV32I-NEXT: .LBB22_5:
-; RV32I-NEXT: sub a6, a1, a6
-; RV32I-NEXT: sub a6, a6, t2
-; RV32I-NEXT: sub t0, a3, t0
-; RV32I-NEXT: beq a6, a1, .LBB22_7
+; RV32I-NEXT: sub a7, a1, a7
+; RV32I-NEXT: sub a7, a7, t2
+; RV32I-NEXT: sub t0, a4, t0
+; RV32I-NEXT: beq a7, a1, .LBB22_7
; RV32I-NEXT: # %bb.6:
-; RV32I-NEXT: sltu a1, a1, a6
+; RV32I-NEXT: sltu a1, a1, a7
; RV32I-NEXT: j .LBB22_8
; RV32I-NEXT: .LBB22_7:
-; RV32I-NEXT: sltu a1, a3, t0
+; RV32I-NEXT: sltu a1, a4, t0
; RV32I-NEXT: .LBB22_8:
; RV32I-NEXT: xor a5, a2, a5
-; RV32I-NEXT: xor a3, a7, a4
+; RV32I-NEXT: xor a3, a6, a3
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: beqz a3, .LBB22_10
; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: mv a1, t1
; RV32I-NEXT: .LBB22_10:
; RV32I-NEXT: neg t1, a1
-; RV32I-NEXT: xor a3, a7, t1
+; RV32I-NEXT: xor a3, a6, t1
; RV32I-NEXT: xor a4, a2, t1
; RV32I-NEXT: xor a2, t0, t1
-; RV32I-NEXT: sltu a7, a3, t1
+; RV32I-NEXT: sltu a6, a3, t1
; RV32I-NEXT: add a4, a4, a1
; RV32I-NEXT: sltu a5, a2, t1
-; RV32I-NEXT: sub a4, a4, a7
-; RV32I-NEXT: xor a7, a6, t1
+; RV32I-NEXT: sub a4, a4, a6
+; RV32I-NEXT: xor a6, a7, t1
; RV32I-NEXT: mv t0, a5
-; RV32I-NEXT: beqz a6, .LBB22_12
+; RV32I-NEXT: beqz a7, .LBB22_12
; RV32I-NEXT: # %bb.11:
-; RV32I-NEXT: sltu t0, a7, t1
+; RV32I-NEXT: sltu t0, a6, t1
; RV32I-NEXT: .LBB22_12:
; RV32I-NEXT: add a3, a3, a1
-; RV32I-NEXT: add a7, a7, a1
-; RV32I-NEXT: sltu a6, a3, t0
+; RV32I-NEXT: add a6, a6, a1
+; RV32I-NEXT: sltu a7, a3, t0
; RV32I-NEXT: sub a3, a3, t0
-; RV32I-NEXT: sub a5, a7, a5
-; RV32I-NEXT: sub a4, a4, a6
+; RV32I-NEXT: sub a5, a6, a5
+; RV32I-NEXT: sub a4, a4, a7
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a5, 4(a0)
@@ -1620,71 +1620,71 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
;
; RV32ZBB-LABEL: abd_cmp_i128:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a1)
-; RV32ZBB-NEXT: lw a4, 8(a1)
+; RV32ZBB-NEXT: lw a4, 0(a1)
+; RV32ZBB-NEXT: lw a3, 8(a1)
; RV32ZBB-NEXT: lw a5, 12(a1)
-; RV32ZBB-NEXT: lw a7, 8(a2)
+; RV32ZBB-NEXT: lw a6, 8(a2)
; RV32ZBB-NEXT: lw t0, 0(a2)
; RV32ZBB-NEXT: lw t1, 12(a2)
-; RV32ZBB-NEXT: lw a6, 4(a2)
+; RV32ZBB-NEXT: lw a7, 4(a2)
; RV32ZBB-NEXT: lw a1, 4(a1)
-; RV32ZBB-NEXT: sltu a2, a4, a7
+; RV32ZBB-NEXT: sltu a2, a3, a6
; RV32ZBB-NEXT: sub t1, a5, t1
-; RV32ZBB-NEXT: sltu t2, a3, t0
+; RV32ZBB-NEXT: sltu t2, a4, t0
; RV32ZBB-NEXT: sub a2, t1, a2
; RV32ZBB-NEXT: mv t1, t2
-; RV32ZBB-NEXT: beq a1, a6, .LBB22_2
+; RV32ZBB-NEXT: beq a1, a7, .LBB22_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: sltu t1, a1, a6
+; RV32ZBB-NEXT: sltu t1, a1, a7
; RV32ZBB-NEXT: .LBB22_2:
-; RV32ZBB-NEXT: sub a7, a4, a7
-; RV32ZBB-NEXT: sltu t3, a7, t1
+; RV32ZBB-NEXT: sub a6, a3, a6
+; RV32ZBB-NEXT: sltu t3, a6, t1
; RV32ZBB-NEXT: sub a2, a2, t3
-; RV32ZBB-NEXT: sub a7, a7, t1
+; RV32ZBB-NEXT: sub a6, a6, t1
; RV32ZBB-NEXT: beq a2, a5, .LBB22_4
; RV32ZBB-NEXT: # %bb.3:
; RV32ZBB-NEXT: sltu t1, a5, a2
; RV32ZBB-NEXT: j .LBB22_5
; RV32ZBB-NEXT: .LBB22_4:
-; RV32ZBB-NEXT: sltu t1, a4, a7
+; RV32ZBB-NEXT: sltu t1, a3, a6
; RV32ZBB-NEXT: .LBB22_5:
-; RV32ZBB-NEXT: sub a6, a1, a6
-; RV32ZBB-NEXT: sub a6, a6, t2
-; RV32ZBB-NEXT: sub t0, a3, t0
-; RV32ZBB-NEXT: beq a6, a1, .LBB22_7
+; RV32ZBB-NEXT: sub a7, a1, a7
+; RV32ZBB-NEXT: sub a7, a7, t2
+; RV32ZBB-NEXT: sub t0, a4, t0
+; RV32ZBB-NEXT: beq a7, a1, .LBB22_7
; RV32ZBB-NEXT: # %bb.6:
-; RV32ZBB-NEXT: sltu a1, a1, a6
+; RV32ZBB-NEXT: sltu a1, a1, a7
; RV32ZBB-NEXT: j .LBB22_8
; RV32ZBB-NEXT: .LBB22_7:
-; RV32ZBB-NEXT: sltu a1, a3, t0
+; RV32ZBB-NEXT: sltu a1, a4, t0
; RV32ZBB-NEXT: .LBB22_8:
; RV32ZBB-NEXT: xor a5, a2, a5
-; RV32ZBB-NEXT: xor a3, a7, a4
+; RV32ZBB-NEXT: xor a3, a6, a3
; RV32ZBB-NEXT: or a3, a3, a5
; RV32ZBB-NEXT: beqz a3, .LBB22_10
; RV32ZBB-NEXT: # %bb.9:
; RV32ZBB-NEXT: mv a1, t1
; RV32ZBB-NEXT: .LBB22_10:
; RV32ZBB-NEXT: neg t1, a1
-; RV32ZBB-NEXT: xor a3, a7, t1
+; RV32ZBB-NEXT: xor a3, a6, t1
; RV32ZBB-NEXT: xor a4, a2, t1
; RV32ZBB-NEXT: xor a2, t0, t1
-; RV32ZBB-NEXT: sltu a7, a3, t1
+; RV32ZBB-NEXT: sltu a6, a3, t1
; RV32ZBB-NEXT: add a4, a4, a1
; RV32ZBB-NEXT: sltu a5, a2, t1
-; RV32ZBB-NEXT: sub a4, a4, a7
-; RV32ZBB-NEXT: xor a7, a6, t1
+; RV32ZBB-NEXT: sub a4, a4, a6
+; RV32ZBB-NEXT: xor a6, a7, t1
; RV32ZBB-NEXT: mv t0, a5
-; RV32ZBB-NEXT: beqz a6, .LBB22_12
+; RV32ZBB-NEXT: beqz a7, .LBB22_12
; RV32ZBB-NEXT: # %bb.11:
-; RV32ZBB-NEXT: sltu t0, a7, t1
+; RV32ZBB-NEXT: sltu t0, a6, t1
; RV32ZBB-NEXT: .LBB22_12:
; RV32ZBB-NEXT: add a3, a3, a1
-; RV32ZBB-NEXT: add a7, a7, a1
-; RV32ZBB-NEXT: sltu a6, a3, t0
+; RV32ZBB-NEXT: add a6, a6, a1
+; RV32ZBB-NEXT: sltu a7, a3, t0
; RV32ZBB-NEXT: sub a3, a3, t0
-; RV32ZBB-NEXT: sub a5, a7, a5
-; RV32ZBB-NEXT: sub a4, a4, a6
+; RV32ZBB-NEXT: sub a5, a6, a5
+; RV32ZBB-NEXT: sub a4, a4, a7
; RV32ZBB-NEXT: add a1, a2, a1
; RV32ZBB-NEXT: sw a1, 0(a0)
; RV32ZBB-NEXT: sw a5, 4(a0)
@@ -1918,71 +1918,71 @@ define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_select_i128:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a4, 0(a1)
+; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
-; RV32I-NEXT: lw a7, 8(a2)
+; RV32I-NEXT: lw a6, 8(a2)
; RV32I-NEXT: lw t0, 0(a2)
; RV32I-NEXT: lw t1, 12(a2)
-; RV32I-NEXT: lw a6, 4(a2)
+; RV32I-NEXT: lw a7, 4(a2)
; RV32I-NEXT: lw a1, 4(a1)
-; RV32I-NEXT: sltu a2, a4, a7
+; RV32I-NEXT: sltu a2, a3, a6
; RV32I-NEXT: sub t1, a5, t1
-; RV32I-NEXT: sltu t2, a3, t0
+; RV32I-NEXT: sltu t2, a4, t0
; RV32I-NEXT: sub a2, t1, a2
; RV32I-NEXT: mv t1, t2
-; RV32I-NEXT: beq a1, a6, .LBB27_2
+; RV32I-NEXT: beq a1, a7, .LBB27_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: sltu t1, a1, a6
+; RV32I-NEXT: sltu t1, a1, a7
; RV32I-NEXT: .LBB27_2:
-; RV32I-NEXT: sub a7, a4, a7
-; RV32I-NEXT: sltu t3, a7, t1
+; RV32I-NEXT: sub a6, a3, a6
+; RV32I-NEXT: sltu t3, a6, t1
; RV32I-NEXT: sub a2, a2, t3
-; RV32I-NEXT: sub a7, a7, t1
+; RV32I-NEXT: sub a6, a6, t1
; RV32I-NEXT: beq a2, a5, .LBB27_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sltu t1, a5, a2
; RV32I-NEXT: j .LBB27_5
; RV32I-NEXT: .LBB27_4:
-; RV32I-NEXT: sltu t1, a4, a7
+; RV32I-NEXT: sltu t1, a3, a6
; RV32I-NEXT: .LBB27_5:
-; RV32I-NEXT: sub a6, a1, a6
-; RV32I-NEXT: sub a6, a6, t2
-; RV32I-NEXT: sub t0, a3, t0
-; RV32I-NEXT: beq a6, a1, .LBB27_7
+; RV32I-NEXT: sub a7, a1, a7
+; RV32I-NEXT: sub a7, a7, t2
+; RV32I-NEXT: sub t0, a4, t0
+; RV32I-NEXT: beq a7, a1, .LBB27_7
; RV32I-NEXT: # %bb.6:
-; RV32I-NEXT: sltu a1, a1, a6
+; RV32I-NEXT: sltu a1, a1, a7
; RV32I-NEXT: j .LBB27_8
; RV32I-NEXT: .LBB27_7:
-; RV32I-NEXT: sltu a1, a3, t0
+; RV32I-NEXT: sltu a1, a4, t0
; RV32I-NEXT: .LBB27_8:
; RV32I-NEXT: xor a5, a2, a5
-; RV32I-NEXT: xor a3, a7, a4
+; RV32I-NEXT: xor a3, a6, a3
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: beqz a3, .LBB27_10
; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: mv a1, t1
; RV32I-NEXT: .LBB27_10:
; RV32I-NEXT: neg t1, a1
-; RV32I-NEXT: xor a3, a7, t1
+; RV32I-NEXT: xor a3, a6, t1
; RV32I-NEXT: xor a4, a2, t1
; RV32I-NEXT: xor a2, t0, t1
-; RV32I-NEXT: sltu a7, a3, t1
+; RV32I-NEXT: sltu a6, a3, t1
; RV32I-NEXT: add a4, a4, a1
; RV32I-NEXT: sltu a5, a2, t1
-; RV32I-NEXT: sub a4, a4, a7
-; RV32I-NEXT: xor a7, a6, t1
+; RV32I-NEXT: sub a4, a4, a6
+; RV32I-NEXT: xor a6, a7, t1
; RV32I-NEXT: mv t0, a5
-; RV32I-NEXT: beqz a6, .LBB27_12
+; RV32I-NEXT: beqz a7, .LBB27_12
; RV32I-NEXT: # %bb.11:
-; RV32I-NEXT: sltu t0, a7, t1
+; RV32I-NEXT: sltu t0, a6, t1
; RV32I-NEXT: .LBB27_12:
; RV32I-NEXT: add a3, a3, a1
-; RV32I-NEXT: add a7, a7, a1
-; RV32I-NEXT: sltu a6, a3, t0
+; RV32I-NEXT: add a6, a6, a1
+; RV32I-NEXT: sltu a7, a3, t0
; RV32I-NEXT: sub a3, a3, t0
-; RV32I-NEXT: sub a5, a7, a5
-; RV32I-NEXT: sub a4, a4, a6
+; RV32I-NEXT: sub a5, a6, a5
+; RV32I-NEXT: sub a4, a4, a7
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a5, 4(a0)
@@ -2014,71 +2014,71 @@ define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
;
; RV32ZBB-LABEL: abd_select_i128:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a1)
-; RV32ZBB-NEXT: lw a4, 8(a1)
+; RV32ZBB-NEXT: lw a4, 0(a1)
+; RV32ZBB-NEXT: lw a3, 8(a1)
; RV32ZBB-NEXT: lw a5, 12(a1)
-; RV32ZBB-NEXT: lw a7, 8(a2)
+; RV32ZBB-NEXT: lw a6, 8(a2)
; RV32ZBB-NEXT: lw t0, 0(a2)
; RV32ZBB-NEXT: lw t1, 12(a2)
-; RV32ZBB-NEXT: lw a6, 4(a2)
+; RV32ZBB-NEXT: lw a7, 4(a2)
; RV32ZBB-NEXT: lw a1, 4(a1)
-; RV32ZBB-NEXT: sltu a2, a4, a7
+; RV32ZBB-NEXT: sltu a2, a3, a6
; RV32ZBB-NEXT: sub t1, a5, t1
-; RV32ZBB-NEXT: sltu t2, a3, t0
+; RV32ZBB-NEXT: sltu t2, a4, t0
; RV32ZBB-NEXT: sub a2, t1, a2
; RV32ZBB-NEXT: mv t1, t2
-; RV32ZBB-NEXT: beq a1, a6, .LBB27_2
+; RV32ZBB-NEXT: beq a1, a7, .LBB27_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: sltu t1, a1, a6
+; RV32ZBB-NEXT: sltu t1, a1, a7
; RV32ZBB-NEXT: .LBB27_2:
-; RV32ZBB-NEXT: sub a7, a4, a7
-; RV32ZBB-NEXT: sltu t3, a7, t1
+; RV32ZBB-NEXT: sub a6, a3, a6
+; RV32ZBB-NEXT: sltu t3, a6, t1
; RV32ZBB-NEXT: sub a2, a2, t3
-; RV32ZBB-NEXT: sub a7, a7, t1
+; RV32ZBB-NEXT: sub a6, a6, t1
; RV32ZBB-NEXT: beq a2, a5, .LBB27_4
; RV32ZBB-NEXT: # %bb.3:
; RV32ZBB-NEXT: sltu t1, a5, a2
; RV32ZBB-NEXT: j .LBB27_5
; RV32ZBB-NEXT: .LBB27_4:
-; RV32ZBB-NEXT: sltu t1, a4, a7
+; RV32ZBB-NEXT: sltu t1, a3, a6
; RV32ZBB-NEXT: .LBB27_5:
-; RV32ZBB-NEXT: sub a6, a1, a6
-; RV32ZBB-NEXT: sub a6, a6, t2
-; RV32ZBB-NEXT: sub t0, a3, t0
-; RV32ZBB-NEXT: beq a6, a1, .LBB27_7
+; RV32ZBB-NEXT: sub a7, a1, a7
+; RV32ZBB-NEXT: sub a7, a7, t2
+; RV32ZBB-NEXT: sub t0, a4, t0
+; RV32ZBB-NEXT: beq a7, a1, .LBB27_7
; RV32ZBB-NEXT: # %bb.6:
-; RV32ZBB-NEXT: sltu a1, a1, a6
+; RV32ZBB-NEXT: sltu a1, a1, a7
; RV32ZBB-NEXT: j .LBB27_8
; RV32ZBB-NEXT: .LBB27_7:
-; RV32ZBB-NEXT: sltu a1, a3, t0
+; RV32ZBB-NEXT: sltu a1, a4, t0
; RV32ZBB-NEXT: .LBB27_8:
; RV32ZBB-NEXT: xor a5, a2, a5
-; RV32ZBB-NEXT: xor a3, a7, a4
+; RV32ZBB-NEXT: xor a3, a6, a3
; RV32ZBB-NEXT: or a3, a3, a5
; RV32ZBB-NEXT: beqz a3, .LBB27_10
; RV32ZBB-NEXT: # %bb.9:
; RV32ZBB-NEXT: mv a1, t1
; RV32ZBB-NEXT: .LBB27_10:
; RV32ZBB-NEXT: neg t1, a1
-; RV32ZBB-NEXT: xor a3, a7, t1
+; RV32ZBB-NEXT: xor a3, a6, t1
; RV32ZBB-NEXT: xor a4, a2, t1
; RV32ZBB-NEXT: xor a2, t0, t1
-; RV32ZBB-NEXT: sltu a7, a3, t1
+; RV32ZBB-NEXT: sltu a6, a3, t1
; RV32ZBB-NEXT: add a4, a4, a1
; RV32ZBB-NEXT: sltu a5, a2, t1
-; RV32ZBB-NEXT: sub a4, a4, a7
-; RV32ZBB-NEXT: xor a7, a6, t1
+; RV32ZBB-NEXT: sub a4, a4, a6
+; RV32ZBB-NEXT: xor a6, a7, t1
; RV32ZBB-NEXT: mv t0, a5
-; RV32ZBB-NEXT: beqz a6, .LBB27_12
+; RV32ZBB-NEXT: beqz a7, .LBB27_12
; RV32ZBB-NEXT: # %bb.11:
-; RV32ZBB-NEXT: sltu t0, a7, t1
+; RV32ZBB-NEXT: sltu t0, a6, t1
; RV32ZBB-NEXT: .LBB27_12:
; RV32ZBB-NEXT: add a3, a3, a1
-; RV32ZBB-NEXT: add a7, a7, a1
-; RV32ZBB-NEXT: sltu a6, a3, t0
+; RV32ZBB-NEXT: add a6, a6, a1
+; RV32ZBB-NEXT: sltu a7, a3, t0
; RV32ZBB-NEXT: sub a3, a3, t0
-; RV32ZBB-NEXT: sub a5, a7, a5
-; RV32ZBB-NEXT: sub a4, a4, a6
+; RV32ZBB-NEXT: sub a5, a6, a5
+; RV32ZBB-NEXT: sub a4, a4, a7
; RV32ZBB-NEXT: add a1, a2, a1
; RV32ZBB-NEXT: sw a1, 0(a0)
; RV32ZBB-NEXT: sw a5, 4(a0)
diff --git a/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll b/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
index 068eb0cb14bfc..11f0813f3f525 100644
--- a/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
+++ b/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
@@ -1203,20 +1203,19 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: li a2, 0
; RV32-NEXT: li a3, 0
; RV32-NEXT: li a4, 0
+; RV32-NEXT: li s8, 0
; RV32-NEXT: li s10, 0
-; RV32-NEXT: li s11, 0
; RV32-NEXT: li a0, 0
-; RV32-NEXT: j .LBB2_22
+; RV32-NEXT: j .LBB2_21
; RV32-NEXT: .LBB2_2: # %fp-to-i-if-check.exp.size
; RV32-NEXT: srai s1, a2, 31
; RV32-NEXT: slli a2, a2, 9
-; RV32-NEXT: zext.b a1, s1
-; RV32-NEXT: sw a1, 120(sp) # 4-byte Folded Spill
+; RV32-NEXT: zext.b s11, s1
; RV32-NEXT: srli a2, a2, 9
; RV32-NEXT: lui a1, 2048
; RV32-NEXT: li a3, 149
; RV32-NEXT: or a1, a2, a1
-; RV32-NEXT: ori s10, s1, 1
+; RV32-NEXT: ori s3, s1, 1
; RV32-NEXT: bltu a3, a0, .LBB2_8
; RV32-NEXT: # %bb.3: # %fp-to-i-if-exp.small
; RV32-NEXT: li a2, 150
@@ -1224,14 +1223,14 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: srl s5, a1, a2
; RV32-NEXT: mv a0, s5
; RV32-NEXT: li a1, 0
-; RV32-NEXT: mv a2, s10
+; RV32-NEXT: mv a2, s3
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: sw a0, 116(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a0, 120(sp) # 4-byte Folded Spill
; RV32-NEXT: mv s2, a1
; RV32-NEXT: li a0, 0
; RV32-NEXT: li a1, 0
-; RV32-NEXT: mv a2, s10
+; RV32-NEXT: mv a2, s3
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
; RV32-NEXT: add s2, a0, s2
@@ -1243,7 +1242,7 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
; RV32-NEXT: add s2, a0, s2
-; RV32-NEXT: sw s2, 112(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s2, 116(sp) # 4-byte Folded Spill
; RV32-NEXT: sltu a0, s2, a0
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: add s2, s3, a0
@@ -1280,14 +1279,14 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: add s7, s4, s7
; RV32-NEXT: add a2, a0, s6
; RV32-NEXT: add s8, a2, s8
-; RV32-NEXT: sw s7, 108(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s7, 112(sp) # 4-byte Folded Spill
; RV32-NEXT: sltu s4, s7, s4
; RV32-NEXT: add s8, s8, s4
; RV32-NEXT: beq s8, a2, .LBB2_5
; RV32-NEXT: # %bb.4: # %fp-to-i-if-exp.small
; RV32-NEXT: sltu s4, s8, a2
; RV32-NEXT: .LBB2_5: # %fp-to-i-if-exp.small
-; RV32-NEXT: sw s8, 104(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s8, 108(sp) # 4-byte Folded Spill
; RV32-NEXT: sltu a3, s6, s3
; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add s6, s2, a3
@@ -1309,13 +1308,14 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: call __muldi3
; RV32-NEXT: mv s4, a1
; RV32-NEXT: sltu a1, s7, s6
-; RV32-NEXT: add s10, s9, a0
+; RV32-NEXT: add a2, s9, a0
; RV32-NEXT: sltu a0, s8, s2
; RV32-NEXT: add a1, s3, a1
-; RV32-NEXT: sltu s8, s9, s8
+; RV32-NEXT: sltu s7, s9, s8
; RV32-NEXT: add a0, a1, a0
-; RV32-NEXT: sltu s6, s10, s9
-; RV32-NEXT: add s8, a0, s8
+; RV32-NEXT: sltu s6, a2, s9
+; RV32-NEXT: mv s8, a2
+; RV32-NEXT: add s7, a0, s7
; RV32-NEXT: mv a0, s1
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s5
@@ -1330,11 +1330,11 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
; RV32-NEXT: add a2, a0, s4
-; RV32-NEXT: add s11, s8, a2
-; RV32-NEXT: add s11, s11, s6
-; RV32-NEXT: beq s11, s8, .LBB2_7
+; RV32-NEXT: add s10, s7, a2
+; RV32-NEXT: add s10, s10, s6
+; RV32-NEXT: beq s10, s7, .LBB2_7
; RV32-NEXT: # %bb.6: # %fp-to-i-if-exp.small
-; RV32-NEXT: sltu s6, s11, s8
+; RV32-NEXT: sltu s6, s10, s7
; RV32-NEXT: .LBB2_7: # %fp-to-i-if-exp.small
; RV32-NEXT: sltu a3, s4, s3
; RV32-NEXT: sltu a0, a2, a0
@@ -1349,14 +1349,20 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: mv s1, a0
; RV32-NEXT: mv a0, s5
; RV32-NEXT: li a1, 0
-; RV32-NEXT: lw a2, 120(sp) # 4-byte Folded Reload
+; RV32-NEXT: mv a2, s11
; RV32-NEXT: # implicit-def: $x13
; RV32-NEXT: call __muldi3
; RV32-NEXT: add a0, s1, a0
; RV32-NEXT: add a0, a0, s6
; RV32-NEXT: add a0, a0, s2
+; RV32-NEXT: zext.b a0, a0
+; RV32-NEXT: lw a1, 120(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 116(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a3, 112(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a4, 108(sp) # 4-byte Folded Reload
; RV32-NEXT: j .LBB2_21
; RV32-NEXT: .LBB2_8: # %fp-to-i-if-exp.large
+; RV32-NEXT: sw s11, 88(sp) # 4-byte Folded Spill
; RV32-NEXT: addi a7, a0, -150
; RV32-NEXT: sw zero, 184(sp)
; RV32-NEXT: sw zero, 188(sp)
@@ -1387,19 +1393,19 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: lw a6, 12(a1)
; RV32-NEXT: xori a2, a2, 31
; RV32-NEXT: lw t1, 24(a1)
-; RV32-NEXT: sw t1, 64(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw t1, 68(sp) # 4-byte Folded Spill
; RV32-NEXT: lw a1, 28(a1)
-; RV32-NEXT: sw a1, 68(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a1, 72(sp) # 4-byte Folded Spill
; RV32-NEXT: srli a1, a0, 1
-; RV32-NEXT: sw t0, 76(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw t0, 80(sp) # 4-byte Folded Spill
; RV32-NEXT: sll t0, t0, a7
-; RV32-NEXT: sw t0, 100(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw t0, 104(sp) # 4-byte Folded Spill
; RV32-NEXT: srl s7, a1, a2
; RV32-NEXT: sll a0, a0, a7
-; RV32-NEXT: sw a0, 108(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a0, 112(sp) # 4-byte Folded Spill
; RV32-NEXT: srli a0, a6, 1
; RV32-NEXT: srl a0, a0, a2
-; RV32-NEXT: sw a0, 104(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a0, 108(sp) # 4-byte Folded Spill
; RV32-NEXT: srli a0, a5, 1
; RV32-NEXT: sll a1, a6, a7
; RV32-NEXT: srl a0, a0, a2
@@ -1410,52 +1416,53 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: or s9, a1, a0
; RV32-NEXT: srli a0, a3, 1
; RV32-NEXT: sll a1, a4, a7
-; RV32-NEXT: sw a2, 72(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a2, 76(sp) # 4-byte Folded Spill
; RV32-NEXT: srl a0, a0, a2
-; RV32-NEXT: or s5, a1, a0
-; RV32-NEXT: sw a7, 80(sp) # 4-byte Folded Spill
-; RV32-NEXT: sll s6, a3, a7
-; RV32-NEXT: mv a0, s5
+; RV32-NEXT: or s6, a1, a0
+; RV32-NEXT: sw a7, 84(sp) # 4-byte Folded Spill
+; RV32-NEXT: sll s10, a3, a7
+; RV32-NEXT: mv a0, s6
; RV32-NEXT: li a1, 0
-; RV32-NEXT: mv a2, s10
+; RV32-NEXT: mv a2, s3
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
; RV32-NEXT: mv s2, a0
+; RV32-NEXT: mv s5, s3
; RV32-NEXT: mv s3, a1
-; RV32-NEXT: mv a0, s6
+; RV32-NEXT: mv a0, s10
; RV32-NEXT: li a1, 0
-; RV32-NEXT: mv a2, s10
+; RV32-NEXT: mv a2, s5
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: sw a0, 116(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a0, 120(sp) # 4-byte Folded Spill
; RV32-NEXT: add s4, s2, a1
; RV32-NEXT: sltu a0, s4, s2
; RV32-NEXT: add s3, s3, a0
-; RV32-NEXT: sw s6, 124(sp) # 4-byte Folded Spill
-; RV32-NEXT: mv a0, s6
+; RV32-NEXT: sw s10, 124(sp) # 4-byte Folded Spill
+; RV32-NEXT: mv a0, s10
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
; RV32-NEXT: add s4, a0, s4
-; RV32-NEXT: sw s4, 112(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s4, 116(sp) # 4-byte Folded Spill
; RV32-NEXT: sltu a0, s4, a0
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: add s2, s3, a0
; RV32-NEXT: sltu s3, s2, s3
-; RV32-NEXT: sw s5, 132(sp) # 4-byte Folded Spill
-; RV32-NEXT: mv a0, s5
+; RV32-NEXT: sw s6, 132(sp) # 4-byte Folded Spill
+; RV32-NEXT: mv a0, s6
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: add s5, a0, s2
+; RV32-NEXT: add s11, a0, s2
; RV32-NEXT: add a1, a1, s3
-; RV32-NEXT: sltu a0, s5, a0
-; RV32-NEXT: add s11, a1, a0
+; RV32-NEXT: sltu a0, s11, a0
+; RV32-NEXT: add s10, a1, a0
; RV32-NEXT: mv a0, s9
; RV32-NEXT: li a1, 0
-; RV32-NEXT: mv a2, s10
+; RV32-NEXT: mv a2, s5
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
; RV32-NEXT: mv s4, a0
@@ -1463,39 +1470,39 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: sw s8, 128(sp) # 4-byte Folded Spill
; RV32-NEXT: mv a0, s8
; RV32-NEXT: li a1, 0
-; RV32-NEXT: mv a2, s10
+; RV32-NEXT: mv a2, s5
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: mv s10, a0
+; RV32-NEXT: mv s5, a0
; RV32-NEXT: mv s2, a1
; RV32-NEXT: add s3, a0, s6
-; RV32-NEXT: sw s9, 96(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s9, 100(sp) # 4-byte Folded Spill
; RV32-NEXT: mv a0, s9
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: add s5, s4, s5
+; RV32-NEXT: add s11, s4, s11
; RV32-NEXT: add a2, a0, s3
-; RV32-NEXT: add s11, a2, s11
-; RV32-NEXT: sltu s6, s5, s4
-; RV32-NEXT: add s11, s11, s6
-; RV32-NEXT: beq s11, a2, .LBB2_10
+; RV32-NEXT: add s10, a2, s10
+; RV32-NEXT: sltu s6, s11, s4
+; RV32-NEXT: add s10, s10, s6
+; RV32-NEXT: beq s10, a2, .LBB2_10
; RV32-NEXT: # %bb.9: # %fp-to-i-if-exp.large
-; RV32-NEXT: sltu s6, s11, a2
+; RV32-NEXT: sltu s6, s10, a2
; RV32-NEXT: .LBB2_10: # %fp-to-i-if-exp.large
-; RV32-NEXT: lw a3, 100(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a3, 104(sp) # 4-byte Folded Reload
; RV32-NEXT: or a3, a3, s7
-; RV32-NEXT: sw a3, 92(sp) # 4-byte Folded Spill
-; RV32-NEXT: sltu a3, s3, s10
+; RV32-NEXT: sw a3, 96(sp) # 4-byte Folded Spill
+; RV32-NEXT: sltu a3, s3, s5
; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a3, s2, a3
; RV32-NEXT: add a0, a1, a0
-; RV32-NEXT: lw a1, 108(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a2, 104(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a1, 112(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 108(sp) # 4-byte Folded Reload
; RV32-NEXT: or a1, a1, a2
-; RV32-NEXT: sw a1, 100(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw a3, 88(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a1, 104(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a3, 92(sp) # 4-byte Folded Spill
; RV32-NEXT: add s2, a3, a0
; RV32-NEXT: lw a0, 128(sp) # 4-byte Folded Reload
; RV32-NEXT: li a1, 0
@@ -1503,7 +1510,7 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
; RV32-NEXT: sw a1, 60(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s2, 84(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s2, 64(sp) # 4-byte Folded Spill
; RV32-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
; RV32-NEXT: add s2, a0, s2
; RV32-NEXT: sw s2, 56(sp) # 4-byte Folded Spill
@@ -1514,125 +1521,124 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
; RV32-NEXT: mv s6, a0
-; RV32-NEXT: mv s3, a1
-; RV32-NEXT: lw s2, 124(sp) # 4-byte Folded Reload
-; RV32-NEXT: mv a0, s2
+; RV32-NEXT: mv s2, a1
+; RV32-NEXT: lw s3, 124(sp) # 4-byte Folded Reload
+; RV32-NEXT: mv a0, s3
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
; RV32-NEXT: mv s8, a0
-; RV32-NEXT: add s9, s6, a1
-; RV32-NEXT: mv a0, s2
+; RV32-NEXT: add s7, s6, a1
+; RV32-NEXT: mv a0, s3
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: add s5, s8, s5
-; RV32-NEXT: add a2, a0, s9
-; RV32-NEXT: add s11, a2, s11
-; RV32-NEXT: sw s5, 108(sp) # 4-byte Folded Spill
-; RV32-NEXT: sltu s5, s5, s8
-; RV32-NEXT: add s11, s11, s5
-; RV32-NEXT: beq s11, a2, .LBB2_12
+; RV32-NEXT: add s11, s8, s11
+; RV32-NEXT: add a2, a0, s7
+; RV32-NEXT: add s10, a2, s10
+; RV32-NEXT: sw s11, 112(sp) # 4-byte Folded Spill
+; RV32-NEXT: sltu s3, s11, s8
+; RV32-NEXT: add s10, s10, s3
+; RV32-NEXT: beq s10, a2, .LBB2_12
; RV32-NEXT: # %bb.11: # %fp-to-i-if-exp.large
-; RV32-NEXT: sltu s5, s11, a2
+; RV32-NEXT: sltu s3, s10, a2
; RV32-NEXT: .LBB2_12: # %fp-to-i-if-exp.large
-; RV32-NEXT: sw s11, 104(sp) # 4-byte Folded Spill
-; RV32-NEXT: sltu a3, s9, s6
+; RV32-NEXT: sw s10, 108(sp) # 4-byte Folded Spill
+; RV32-NEXT: sltu a3, s7, s6
; RV32-NEXT: sltu a0, a2, a0
-; RV32-NEXT: add s9, s3, a3
+; RV32-NEXT: add s10, s2, a3
; RV32-NEXT: add a0, a1, a0
-; RV32-NEXT: add s6, s9, a0
+; RV32-NEXT: add s6, s10, a0
; RV32-NEXT: lw a0, 132(sp) # 4-byte Folded Reload
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: mv s8, a0
-; RV32-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
-; RV32-NEXT: add s3, a0, s6
-; RV32-NEXT: add s2, s3, s5
-; RV32-NEXT: add s7, s4, s2
-; RV32-NEXT: lw s11, 96(sp) # 4-byte Folded Reload
+; RV32-NEXT: mv s9, a0
+; RV32-NEXT: sw a1, 36(sp) # 4-byte Folded Spill
+; RV32-NEXT: add s8, a0, s6
+; RV32-NEXT: add s3, s8, s3
+; RV32-NEXT: add s5, s4, s3
+; RV32-NEXT: lw s11, 100(sp) # 4-byte Folded Reload
; RV32-NEXT: mv a0, s11
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
; RV32-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw a1, 36(sp) # 4-byte Folded Spill
-; RV32-NEXT: add s5, a0, s7
+; RV32-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32-NEXT: add s7, a0, s5
; RV32-NEXT: ori a0, s1, 1
; RV32-NEXT: li a1, 0
-; RV32-NEXT: lw a2, 100(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 104(sp) # 4-byte Folded Reload
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: mv s10, a0
-; RV32-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32-NEXT: mv s2, a0
+; RV32-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
; RV32-NEXT: mv a0, s1
; RV32-NEXT: li a1, 0
; RV32-NEXT: lw a2, 124(sp) # 4-byte Folded Reload
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: mv a4, a0
-; RV32-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
+; RV32-NEXT: mv a2, a0
+; RV32-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw a1, 44(sp) # 4-byte Folded Spill
; RV32-NEXT: lw a3, 56(sp) # 4-byte Folded Reload
; RV32-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
; RV32-NEXT: sltu a0, a3, a0
-; RV32-NEXT: add a4, a4, s10
-; RV32-NEXT: sw a4, 4(sp) # 4-byte Folded Spill
-; RV32-NEXT: lw a1, 88(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a2, 84(sp) # 4-byte Folded Reload
+; RV32-NEXT: add s2, a2, s2
+; RV32-NEXT: lw a1, 92(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 64(sp) # 4-byte Folded Reload
; RV32-NEXT: sltu a1, a2, a1
-; RV32-NEXT: add s10, s5, a4
+; RV32-NEXT: add a5, s7, s2
; RV32-NEXT: lw a2, 60(sp) # 4-byte Folded Reload
; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: sltu a2, s4, a3
; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: sltu a2, s6, s9
-; RV32-NEXT: lw a3, 40(sp) # 4-byte Folded Reload
+; RV32-NEXT: sltu a2, s6, s10
+; RV32-NEXT: lw a3, 36(sp) # 4-byte Folded Reload
; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: sltu a3, s3, s8
-; RV32-NEXT: sltu a4, s2, s3
+; RV32-NEXT: sltu a3, s8, s9
+; RV32-NEXT: sltu a4, s3, s8
; RV32-NEXT: add a2, a2, a3
-; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add s8, a1, a0
; RV32-NEXT: add a2, a2, a4
-; RV32-NEXT: sltu s6, s7, s4
-; RV32-NEXT: mv s4, a0
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: sltu s7, s10, s5
-; RV32-NEXT: sw s6, 84(sp) # 4-byte Folded Spill
+; RV32-NEXT: sltu s6, s5, s4
+; RV32-NEXT: add a2, s8, a2
+; RV32-NEXT: sw a5, 64(sp) # 4-byte Folded Spill
+; RV32-NEXT: sltu s10, a5, s7
+; RV32-NEXT: sw s6, 36(sp) # 4-byte Folded Spill
; RV32-NEXT: add s6, a2, s6
; RV32-NEXT: lw a0, 128(sp) # 4-byte Folded Reload
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32-NEXT: lw s3, 36(sp) # 4-byte Folded Reload
+; RV32-NEXT: sw a1, 32(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
+; RV32-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: add s3, a0, s3
; RV32-NEXT: mv a0, s11
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s3, 24(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: mv s9, a0
+; RV32-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s3, 16(sp) # 4-byte Folded Spill
; RV32-NEXT: add s3, a0, s3
; RV32-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; RV32-NEXT: sltu s5, s5, a0
-; RV32-NEXT: add s2, s3, s5
-; RV32-NEXT: add s2, s2, s6
+; RV32-NEXT: sltu s5, s7, a0
+; RV32-NEXT: add s7, s3, s5
+; RV32-NEXT: add s7, s7, s6
; RV32-NEXT: mv a0, s1
; RV32-NEXT: li a1, 0
; RV32-NEXT: lw a2, 132(sp) # 4-byte Folded Reload
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: mv s9, a0
+; RV32-NEXT: mv s11, a0
; RV32-NEXT: sw a1, 60(sp) # 4-byte Folded Spill
; RV32-NEXT: mv a0, s1
; RV32-NEXT: li a1, 0
@@ -1643,120 +1649,115 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
; RV32-NEXT: lw a1, 44(sp) # 4-byte Folded Reload
; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: sw s9, 56(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s11, 56(sp) # 4-byte Folded Spill
; RV32-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; RV32-NEXT: add s9, s9, a0
+; RV32-NEXT: add s11, s11, a0
; RV32-NEXT: mv a0, s1
; RV32-NEXT: li a1, 0
-; RV32-NEXT: lw a2, 100(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 104(sp) # 4-byte Folded Reload
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: sw a1, 36(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32-NEXT: lw s8, 20(sp) # 4-byte Folded Reload
-; RV32-NEXT: add s8, a0, s8
+; RV32-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
+; RV32-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
+; RV32-NEXT: add s4, a0, s4
; RV32-NEXT: ori a0, s1, 1
; RV32-NEXT: li a1, 0
-; RV32-NEXT: lw a2, 92(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 96(sp) # 4-byte Folded Reload
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: lw a2, 8(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a3, 4(sp) # 4-byte Folded Reload
-; RV32-NEXT: sltu a2, a3, a2
-; RV32-NEXT: sw s8, 20(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32-NEXT: add a0, a0, s8
+; RV32-NEXT: lw a2, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: sltu a2, s2, a2
+; RV32-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32-NEXT: add s8, s9, a0
-; RV32-NEXT: mv a6, a2
-; RV32-NEXT: add s8, s8, a2
-; RV32-NEXT: sw s7, 88(sp) # 4-byte Folded Spill
-; RV32-NEXT: add s11, s8, s7
-; RV32-NEXT: add s11, s2, s11
+; RV32-NEXT: add s4, a0, s4
+; RV32-NEXT: add s2, s11, s4
+; RV32-NEXT: sw a2, 40(sp) # 4-byte Folded Spill
+; RV32-NEXT: add s2, s2, a2
+; RV32-NEXT: sw s10, 92(sp) # 4-byte Folded Spill
+; RV32-NEXT: add s10, s2, s10
+; RV32-NEXT: add s10, s7, s10
; RV32-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; RV32-NEXT: beq s11, s2, .LBB2_14
+; RV32-NEXT: beq s10, s7, .LBB2_14
; RV32-NEXT: # %bb.13: # %fp-to-i-if-exp.large
-; RV32-NEXT: sltu a0, s11, s2
-; RV32-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
+; RV32-NEXT: sltu a0, s10, s7
+; RV32-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
; RV32-NEXT: .LBB2_14: # %fp-to-i-if-exp.large
-; RV32-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
; RV32-NEXT: srli a0, a0, 1
-; RV32-NEXT: lw a2, 64(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 68(sp) # 4-byte Folded Reload
; RV32-NEXT: srli a1, a2, 1
-; RV32-NEXT: beq s2, s3, .LBB2_16
+; RV32-NEXT: beq s7, s3, .LBB2_16
; RV32-NEXT: # %bb.15: # %fp-to-i-if-exp.large
-; RV32-NEXT: sltu s5, s2, s3
+; RV32-NEXT: sltu s5, s7, s3
; RV32-NEXT: .LBB2_16: # %fp-to-i-if-exp.large
-; RV32-NEXT: lw a4, 80(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a4, 84(sp) # 4-byte Folded Reload
; RV32-NEXT: sll a2, a2, a4
-; RV32-NEXT: lw a5, 72(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a5, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: srl a3, a0, a5
-; RV32-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
; RV32-NEXT: sll a0, a0, a4
; RV32-NEXT: srl a1, a1, a5
-; RV32-NEXT: mv s7, a6
-; RV32-NEXT: beq s6, s4, .LBB2_18
+; RV32-NEXT: lw s7, 36(sp) # 4-byte Folded Reload
+; RV32-NEXT: beq s6, s8, .LBB2_18
; RV32-NEXT: # %bb.17: # %fp-to-i-if-exp.large
-; RV32-NEXT: sltu a4, s6, s4
-; RV32-NEXT: sw a4, 84(sp) # 4-byte Folded Spill
+; RV32-NEXT: sltu s7, s6, s8
; RV32-NEXT: .LBB2_18: # %fp-to-i-if-exp.large
-; RV32-NEXT: or s2, a2, a3
-; RV32-NEXT: lw a2, 32(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a3, 24(sp) # 4-byte Folded Reload
+; RV32-NEXT: or s8, a2, a3
+; RV32-NEXT: lw a2, 24(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a3, 16(sp) # 4-byte Folded Reload
; RV32-NEXT: sltu a2, a3, a2
-; RV32-NEXT: lw a3, 12(sp) # 4-byte Folded Reload
-; RV32-NEXT: sltu a3, s3, a3
-; RV32-NEXT: lw a4, 40(sp) # 4-byte Folded Reload
+; RV32-NEXT: sltu a3, s3, s9
+; RV32-NEXT: lw a4, 32(sp) # 4-byte Folded Reload
; RV32-NEXT: add a2, a4, a2
-; RV32-NEXT: lw a4, 16(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a4, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: add a3, a4, a3
; RV32-NEXT: or s3, a0, a1
-; RV32-NEXT: add s4, a2, a3
+; RV32-NEXT: add s6, a2, a3
; RV32-NEXT: lw a0, 128(sp) # 4-byte Folded Reload
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: lw a1, 84(sp) # 4-byte Folded Reload
-; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: add a0, a0, s7
; RV32-NEXT: add a0, a0, s5
-; RV32-NEXT: add s5, a0, s4
-; RV32-NEXT: beq s8, s9, .LBB2_20
+; RV32-NEXT: add s5, a0, s6
+; RV32-NEXT: lw s7, 40(sp) # 4-byte Folded Reload
+; RV32-NEXT: beq s2, s11, .LBB2_20
; RV32-NEXT: # %bb.19: # %fp-to-i-if-exp.large
-; RV32-NEXT: sltu s7, s8, s9
+; RV32-NEXT: sltu s7, s2, s11
; RV32-NEXT: .LBB2_20: # %fp-to-i-if-exp.large
-; RV32-NEXT: lw a0, 100(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s6, 92(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a0, 104(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw s6, 96(sp) # 4-byte Folded Reload
; RV32-NEXT: mv a1, s6
; RV32-NEXT: mv a2, s1
; RV32-NEXT: mv a3, s1
; RV32-NEXT: call __muldi3
-; RV32-NEXT: mv s4, a0
-; RV32-NEXT: mv a0, s2
+; RV32-NEXT: mv s9, a0
+; RV32-NEXT: mv a0, s8
; RV32-NEXT: mv a1, s3
; RV32-NEXT: ori a2, s1, 1
; RV32-NEXT: mv a3, s1
; RV32-NEXT: call __muldi3
-; RV32-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a2, 20(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: sltu a1, a2, a1
-; RV32-NEXT: lw a2, 8(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a3, 4(sp) # 4-byte Folded Reload
-; RV32-NEXT: sltu a2, a3, a2
-; RV32-NEXT: lw a3, 36(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 4(sp) # 4-byte Folded Reload
+; RV32-NEXT: sltu a2, s4, a2
+; RV32-NEXT: lw a3, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: lw a3, 0(sp) # 4-byte Folded Reload
; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add s4, a0, s4
+; RV32-NEXT: add s9, a0, s9
; RV32-NEXT: add s2, a1, a2
; RV32-NEXT: mv a0, s1
; RV32-NEXT: li a1, 0
; RV32-NEXT: mv a2, s6
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: add a0, a0, s4
+; RV32-NEXT: add a0, a0, s9
; RV32-NEXT: add s3, a0, s2
-; RV32-NEXT: lw a0, 96(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a0, 100(sp) # 4-byte Folded Reload
; RV32-NEXT: lw a1, 128(sp) # 4-byte Folded Reload
; RV32-NEXT: mv a2, s1
; RV32-NEXT: mv a3, s1
@@ -1765,10 +1766,10 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: lw a0, 124(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s6, 132(sp) # 4-byte Folded Reload
; RV32-NEXT: mv a1, s6
-; RV32-NEXT: lw a2, 120(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 88(sp) # 4-byte Folded Reload
; RV32-NEXT: call __muldi3
; RV32-NEXT: lw a1, 56(sp) # 4-byte Folded Reload
-; RV32-NEXT: sltu a1, s9, a1
+; RV32-NEXT: sltu a1, s11, a1
; RV32-NEXT: lw a2, 48(sp) # 4-byte Folded Reload
; RV32-NEXT: lw a3, 44(sp) # 4-byte Folded Reload
; RV32-NEXT: sltu a2, a3, a2
@@ -1783,26 +1784,26 @@ define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind {
; RV32-NEXT: mv a2, s6
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __muldi3
-; RV32-NEXT: lw a1, 88(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a1, 92(sp) # 4-byte Folded Reload
; RV32-NEXT: add s5, s5, a1
; RV32-NEXT: add a0, a0, s2
; RV32-NEXT: add a0, a0, s4
; RV32-NEXT: add a0, a0, s3
; RV32-NEXT: add a0, a0, s7
; RV32-NEXT: add a0, s5, a0
-; RV32-NEXT: .LBB2_21: # %fp-to-i-cleanup
; RV32-NEXT: zext.b a0, a0
-; RV32-NEXT: lw a1, 116(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a2, 112(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a3, 108(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a4, 104(sp) # 4-byte Folded Reload
-; RV32-NEXT: .LBB2_22: # %fp-to-i-cleanup
+; RV32-NEXT: lw a1, 120(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 116(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a3, 112(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a4, 108(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw s8, 64(sp) # 4-byte Folded Reload
+; RV32-NEXT: .LBB2_21: # %fp-to-i-cleanup
; RV32-NEXT: sw a1, 0(s0)
; RV32-NEXT: sw a2, 4(s0)
; RV32-NEXT: sw a3, 8(s0)
; RV32-NEXT: sw a4, 12(s0)
-; RV32-NEXT: sw s10, 16(s0)
-; RV32-NEXT: sw s11, 20(s0)
+; RV32-NEXT: sw s8, 16(s0)
+; RV32-NEXT: sw s10, 20(s0)
; RV32-NEXT: sb a0, 24(s0)
; RV32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
index 47b258b6fdb70..16a54c24c58da 100644
--- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll
+++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
@@ -1694,99 +1694,99 @@ entry:
define i64 @utest_f64i64(double %x) {
; RV32IF-LABEL: utest_f64i64:
; RV32IF: # %bb.0: # %entryfp-to-i-entry
-; RV32IF-NEXT: li a3, 1023
-; RV32IF-NEXT: slli a2, a1, 1
-; RV32IF-NEXT: srli a2, a2, 21
-; RV32IF-NEXT: bgeu a2, a3, .LBB19_2
+; RV32IF-NEXT: li a2, 1023
+; RV32IF-NEXT: slli a3, a1, 1
+; RV32IF-NEXT: srli a3, a3, 21
+; RV32IF-NEXT: bgeu a3, a2, .LBB19_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: li a1, 0
-; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: li a2, 0
+; RV32IF-NEXT: li a3, 0
+; RV32IF-NEXT: li a1, 0
; RV32IF-NEXT: j .LBB19_8
; RV32IF-NEXT: .LBB19_2: # %fp-to-i-if-check.exp.size
-; RV32IF-NEXT: lui a3, 256
+; RV32IF-NEXT: lui a2, 256
; RV32IF-NEXT: snez a4, a0
; RV32IF-NEXT: addi a0, a0, -1
-; RV32IF-NEXT: addi a3, a3, -1
+; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: addi a0, a0, 1
-; RV32IF-NEXT: and a1, a1, a3
+; RV32IF-NEXT: and a1, a1, a2
; RV32IF-NEXT: add a1, a1, a4
; RV32IF-NEXT: seqz a4, a0
-; RV32IF-NEXT: add a3, a4, a3
+; RV32IF-NEXT: add a2, a4, a2
; RV32IF-NEXT: li a4, 1074
-; RV32IF-NEXT: add a1, a1, a3
-; RV32IF-NEXT: bltu a4, a2, .LBB19_5
+; RV32IF-NEXT: add a2, a1, a2
+; RV32IF-NEXT: bltu a4, a3, .LBB19_5
; RV32IF-NEXT: # %bb.3: # %fp-to-i-if-exp.small
; RV32IF-NEXT: li a4, 1043
; RV32IF-NEXT: li a5, 1075
-; RV32IF-NEXT: sub a4, a4, a2
-; RV32IF-NEXT: sub a5, a5, a2
+; RV32IF-NEXT: sub a4, a4, a3
+; RV32IF-NEXT: sub a5, a5, a3
; RV32IF-NEXT: bltz a4, .LBB19_6
; RV32IF-NEXT: # %bb.4: # %fp-to-i-if-exp.small
-; RV32IF-NEXT: srl a0, a1, a4
+; RV32IF-NEXT: srl a0, a2, a4
; RV32IF-NEXT: j .LBB19_7
; RV32IF-NEXT: .LBB19_5: # %fp-to-i-if-exp.large
; RV32IF-NEXT: addi sp, sp, -32
; RV32IF-NEXT: .cfi_def_cfa_offset 32
-; RV32IF-NEXT: addi a4, a2, -1075
-; RV32IF-NEXT: srli a2, a4, 3
+; RV32IF-NEXT: addi a4, a3, -1075
+; RV32IF-NEXT: srli a1, a4, 3
; RV32IF-NEXT: sw a0, 16(sp)
-; RV32IF-NEXT: sw a1, 20(sp)
+; RV32IF-NEXT: sw a2, 20(sp)
; RV32IF-NEXT: sw zero, 24(sp)
; RV32IF-NEXT: sw zero, 28(sp)
-; RV32IF-NEXT: andi a2, a2, 12
+; RV32IF-NEXT: andi a1, a1, 12
; RV32IF-NEXT: addi a0, sp, 16
; RV32IF-NEXT: sw zero, 0(sp)
; RV32IF-NEXT: sw zero, 4(sp)
; RV32IF-NEXT: sw zero, 8(sp)
; RV32IF-NEXT: sw zero, 12(sp)
-; RV32IF-NEXT: sub a0, a0, a2
-; RV32IF-NEXT: lw a1, 8(a0)
-; RV32IF-NEXT: lw a2, 12(a0)
+; RV32IF-NEXT: sub a0, a0, a1
+; RV32IF-NEXT: lw a2, 8(a0)
+; RV32IF-NEXT: lw a1, 12(a0)
; RV32IF-NEXT: lw a5, 4(a0)
; RV32IF-NEXT: lw a0, 0(a0)
; RV32IF-NEXT: andi a3, a4, 31
-; RV32IF-NEXT: srli a6, a1, 1
+; RV32IF-NEXT: srli a6, a2, 1
; RV32IF-NEXT: xori a7, a3, 31
-; RV32IF-NEXT: sll a2, a2, a4
+; RV32IF-NEXT: sll a1, a1, a4
; RV32IF-NEXT: srl a3, a6, a7
-; RV32IF-NEXT: or a2, a2, a3
+; RV32IF-NEXT: or a1, a1, a3
; RV32IF-NEXT: srli a3, a5, 1
-; RV32IF-NEXT: sll a1, a1, a4
+; RV32IF-NEXT: sll a2, a2, a4
; RV32IF-NEXT: srl a3, a3, a7
-; RV32IF-NEXT: or a3, a1, a3
-; RV32IF-NEXT: srli a1, a0, 1
+; RV32IF-NEXT: or a3, a2, a3
+; RV32IF-NEXT: srli a2, a0, 1
; RV32IF-NEXT: sll a5, a5, a4
-; RV32IF-NEXT: srl a1, a1, a7
-; RV32IF-NEXT: or a1, a5, a1
+; RV32IF-NEXT: srl a2, a2, a7
+; RV32IF-NEXT: or a2, a5, a2
; RV32IF-NEXT: sll a0, a0, a4
; RV32IF-NEXT: addi sp, sp, 32
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: j .LBB19_8
; RV32IF-NEXT: .LBB19_6:
-; RV32IF-NEXT: not a2, a5
-; RV32IF-NEXT: slli a3, a1, 1
+; RV32IF-NEXT: not a1, a5
+; RV32IF-NEXT: slli a3, a2, 1
; RV32IF-NEXT: srl a0, a0, a5
-; RV32IF-NEXT: sll a2, a3, a2
-; RV32IF-NEXT: or a0, a0, a2
+; RV32IF-NEXT: sll a1, a3, a1
+; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: .LBB19_7: # %fp-to-i-if-exp.small
; RV32IF-NEXT: li a3, 0
-; RV32IF-NEXT: li a2, 0
-; RV32IF-NEXT: srl a1, a1, a5
+; RV32IF-NEXT: li a1, 0
+; RV32IF-NEXT: srl a2, a2, a5
; RV32IF-NEXT: srai a4, a4, 31
-; RV32IF-NEXT: and a1, a4, a1
+; RV32IF-NEXT: and a2, a4, a2
; RV32IF-NEXT: .LBB19_8: # %fp-to-i-cleanup
; RV32IF-NEXT: xori a4, a3, 1
-; RV32IF-NEXT: or a4, a4, a2
-; RV32IF-NEXT: or a2, a2, a3
+; RV32IF-NEXT: or a4, a4, a1
+; RV32IF-NEXT: or a1, a1, a3
; RV32IF-NEXT: seqz a3, a4
-; RV32IF-NEXT: seqz a2, a2
+; RV32IF-NEXT: seqz a1, a1
; RV32IF-NEXT: addi a3, a3, -1
-; RV32IF-NEXT: and a2, a3, a2
-; RV32IF-NEXT: neg a2, a2
-; RV32IF-NEXT: and a0, a2, a0
-; RV32IF-NEXT: and a1, a2, a1
+; RV32IF-NEXT: and a1, a3, a1
+; RV32IF-NEXT: neg a1, a1
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: and a1, a1, a2
; RV32IF-NEXT: ret
;
; RV64-LABEL: utest_f64i64:
@@ -1817,23 +1817,23 @@ define i64 @utest_f64i64(double %x) {
; RV32IFD-NEXT: bgeu a0, a2, .LBB19_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: li a1, 0
-; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: li a2, 0
+; RV32IFD-NEXT: li a3, 0
+; RV32IFD-NEXT: li a1, 0
; RV32IFD-NEXT: j .LBB19_8
; RV32IFD-NEXT: .LBB19_2: # %fp-to-i-if-check.exp.size
; RV32IFD-NEXT: lw a2, 8(sp)
; RV32IFD-NEXT: lui a3, 256
; RV32IFD-NEXT: addi a3, a3, -1
-; RV32IFD-NEXT: and a1, a1, a3
-; RV32IFD-NEXT: addi a4, a2, -1
-; RV32IFD-NEXT: snez a5, a2
-; RV32IFD-NEXT: addi a2, a4, 1
-; RV32IFD-NEXT: add a1, a1, a5
-; RV32IFD-NEXT: seqz a4, a2
-; RV32IFD-NEXT: add a1, a1, a3
+; RV32IFD-NEXT: and a4, a1, a3
+; RV32IFD-NEXT: addi a1, a2, -1
+; RV32IFD-NEXT: snez a2, a2
+; RV32IFD-NEXT: addi a1, a1, 1
+; RV32IFD-NEXT: add a2, a4, a2
+; RV32IFD-NEXT: seqz a4, a1
+; RV32IFD-NEXT: add a2, a2, a3
; RV32IFD-NEXT: li a3, 1074
-; RV32IFD-NEXT: add a1, a1, a4
+; RV32IFD-NEXT: add a2, a2, a4
; RV32IFD-NEXT: bltu a3, a0, .LBB19_5
; RV32IFD-NEXT: # %bb.3: # %fp-to-i-if-exp.small
; RV32IFD-NEXT: li a4, 1043
@@ -1842,13 +1842,13 @@ define i64 @utest_f64i64(double %x) {
; RV32IFD-NEXT: sub a5, a5, a0
; RV32IFD-NEXT: bltz a4, .LBB19_6
; RV32IFD-NEXT: # %bb.4: # %fp-to-i-if-exp.small
-; RV32IFD-NEXT: srl a0, a1, a4
+; RV32IFD-NEXT: srl a0, a2, a4
; RV32IFD-NEXT: j .LBB19_7
; RV32IFD-NEXT: .LBB19_5: # %fp-to-i-if-exp.large
; RV32IFD-NEXT: addi a0, a0, -1075
; RV32IFD-NEXT: srli a3, a0, 3
-; RV32IFD-NEXT: sw a2, 32(sp)
-; RV32IFD-NEXT: sw a1, 36(sp)
+; RV32IFD-NEXT: sw a1, 32(sp)
+; RV32IFD-NEXT: sw a2, 36(sp)
; RV32IFD-NEXT: sw zero, 40(sp)
; RV32IFD-NEXT: sw zero, 44(sp)
; RV32IFD-NEXT: andi a3, a3, 12
@@ -1858,49 +1858,49 @@ define i64 @utest_f64i64(double %x) {
; RV32IFD-NEXT: sw zero, 24(sp)
; RV32IFD-NEXT: sw zero, 28(sp)
; RV32IFD-NEXT: sub a1, a1, a3
-; RV32IFD-NEXT: lw a3, 8(a1)
-; RV32IFD-NEXT: lw a2, 12(a1)
+; RV32IFD-NEXT: lw a2, 8(a1)
+; RV32IFD-NEXT: lw a3, 12(a1)
; RV32IFD-NEXT: lw a4, 4(a1)
; RV32IFD-NEXT: lw a5, 0(a1)
; RV32IFD-NEXT: andi a1, a0, 31
-; RV32IFD-NEXT: srli a6, a3, 1
-; RV32IFD-NEXT: xori a1, a1, 31
+; RV32IFD-NEXT: srli a6, a2, 1
+; RV32IFD-NEXT: xori a7, a1, 31
+; RV32IFD-NEXT: sll a1, a3, a0
+; RV32IFD-NEXT: srl a3, a6, a7
+; RV32IFD-NEXT: or a1, a1, a3
+; RV32IFD-NEXT: srli a3, a4, 1
; RV32IFD-NEXT: sll a2, a2, a0
-; RV32IFD-NEXT: srl a6, a6, a1
-; RV32IFD-NEXT: or a2, a2, a6
-; RV32IFD-NEXT: srli a6, a4, 1
-; RV32IFD-NEXT: sll a3, a3, a0
-; RV32IFD-NEXT: srl a6, a6, a1
-; RV32IFD-NEXT: or a3, a3, a6
-; RV32IFD-NEXT: srli a6, a5, 1
+; RV32IFD-NEXT: srl a3, a3, a7
+; RV32IFD-NEXT: or a3, a2, a3
+; RV32IFD-NEXT: srli a2, a5, 1
; RV32IFD-NEXT: sll a4, a4, a0
-; RV32IFD-NEXT: srl a1, a6, a1
-; RV32IFD-NEXT: or a1, a4, a1
+; RV32IFD-NEXT: srl a2, a2, a7
+; RV32IFD-NEXT: or a2, a4, a2
; RV32IFD-NEXT: sll a0, a5, a0
; RV32IFD-NEXT: j .LBB19_8
; RV32IFD-NEXT: .LBB19_6:
; RV32IFD-NEXT: not a0, a5
-; RV32IFD-NEXT: slli a3, a1, 1
-; RV32IFD-NEXT: srl a2, a2, a5
+; RV32IFD-NEXT: slli a3, a2, 1
+; RV32IFD-NEXT: srl a1, a1, a5
; RV32IFD-NEXT: sll a0, a3, a0
-; RV32IFD-NEXT: or a0, a2, a0
+; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: .LBB19_7: # %fp-to-i-if-exp.small
; RV32IFD-NEXT: li a3, 0
-; RV32IFD-NEXT: li a2, 0
-; RV32IFD-NEXT: srl a1, a1, a5
+; RV32IFD-NEXT: li a1, 0
+; RV32IFD-NEXT: srl a2, a2, a5
; RV32IFD-NEXT: srai a4, a4, 31
-; RV32IFD-NEXT: and a1, a4, a1
+; RV32IFD-NEXT: and a2, a4, a2
; RV32IFD-NEXT: .LBB19_8: # %fp-to-i-cleanup
; RV32IFD-NEXT: xori a4, a3, 1
-; RV32IFD-NEXT: or a4, a4, a2
-; RV32IFD-NEXT: or a2, a2, a3
+; RV32IFD-NEXT: or a4, a4, a1
+; RV32IFD-NEXT: or a1, a1, a3
; RV32IFD-NEXT: seqz a3, a4
-; RV32IFD-NEXT: seqz a2, a2
+; RV32IFD-NEXT: seqz a1, a1
; RV32IFD-NEXT: addi a3, a3, -1
-; RV32IFD-NEXT: and a2, a3, a2
-; RV32IFD-NEXT: neg a2, a2
-; RV32IFD-NEXT: and a0, a2, a0
-; RV32IFD-NEXT: and a1, a2, a1
+; RV32IFD-NEXT: and a1, a3, a1
+; RV32IFD-NEXT: neg a1, a1
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: and a1, a1, a2
; RV32IFD-NEXT: addi sp, sp, 48
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
@@ -5005,99 +5005,99 @@ entry:
define i64 @utest_f64i64_mm(double %x) {
; RV32IF-LABEL: utest_f64i64_mm:
; RV32IF: # %bb.0: # %entryfp-to-i-entry
-; RV32IF-NEXT: li a3, 1023
-; RV32IF-NEXT: slli a2, a1, 1
-; RV32IF-NEXT: srli a2, a2, 21
-; RV32IF-NEXT: bgeu a2, a3, .LBB46_2
+; RV32IF-NEXT: li a2, 1023
+; RV32IF-NEXT: slli a3, a1, 1
+; RV32IF-NEXT: srli a3, a3, 21
+; RV32IF-NEXT: bgeu a3, a2, .LBB46_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: li a1, 0
-; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: li a2, 0
+; RV32IF-NEXT: li a3, 0
+; RV32IF-NEXT: li a1, 0
; RV32IF-NEXT: j .LBB46_8
; RV32IF-NEXT: .LBB46_2: # %fp-to-i-if-check.exp.size
-; RV32IF-NEXT: lui a3, 256
+; RV32IF-NEXT: lui a2, 256
; RV32IF-NEXT: snez a4, a0
; RV32IF-NEXT: addi a0, a0, -1
-; RV32IF-NEXT: addi a3, a3, -1
+; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: addi a0, a0, 1
-; RV32IF-NEXT: and a1, a1, a3
+; RV32IF-NEXT: and a1, a1, a2
; RV32IF-NEXT: add a1, a1, a4
; RV32IF-NEXT: seqz a4, a0
-; RV32IF-NEXT: add a3, a4, a3
+; RV32IF-NEXT: add a2, a4, a2
; RV32IF-NEXT: li a4, 1074
-; RV32IF-NEXT: add a1, a1, a3
-; RV32IF-NEXT: bltu a4, a2, .LBB46_5
+; RV32IF-NEXT: add a2, a1, a2
+; RV32IF-NEXT: bltu a4, a3, .LBB46_5
; RV32IF-NEXT: # %bb.3: # %fp-to-i-if-exp.small
; RV32IF-NEXT: li a4, 1043
; RV32IF-NEXT: li a5, 1075
-; RV32IF-NEXT: sub a4, a4, a2
-; RV32IF-NEXT: sub a5, a5, a2
+; RV32IF-NEXT: sub a4, a4, a3
+; RV32IF-NEXT: sub a5, a5, a3
; RV32IF-NEXT: bltz a4, .LBB46_6
; RV32IF-NEXT: # %bb.4: # %fp-to-i-if-exp.small
-; RV32IF-NEXT: srl a0, a1, a4
+; RV32IF-NEXT: srl a0, a2, a4
; RV32IF-NEXT: j .LBB46_7
; RV32IF-NEXT: .LBB46_5: # %fp-to-i-if-exp.large
; RV32IF-NEXT: addi sp, sp, -32
; RV32IF-NEXT: .cfi_def_cfa_offset 32
-; RV32IF-NEXT: addi a4, a2, -1075
-; RV32IF-NEXT: srli a2, a4, 3
+; RV32IF-NEXT: addi a4, a3, -1075
+; RV32IF-NEXT: srli a1, a4, 3
; RV32IF-NEXT: sw a0, 16(sp)
-; RV32IF-NEXT: sw a1, 20(sp)
+; RV32IF-NEXT: sw a2, 20(sp)
; RV32IF-NEXT: sw zero, 24(sp)
; RV32IF-NEXT: sw zero, 28(sp)
-; RV32IF-NEXT: andi a2, a2, 12
+; RV32IF-NEXT: andi a1, a1, 12
; RV32IF-NEXT: addi a0, sp, 16
; RV32IF-NEXT: sw zero, 0(sp)
; RV32IF-NEXT: sw zero, 4(sp)
; RV32IF-NEXT: sw zero, 8(sp)
; RV32IF-NEXT: sw zero, 12(sp)
-; RV32IF-NEXT: sub a0, a0, a2
-; RV32IF-NEXT: lw a1, 8(a0)
-; RV32IF-NEXT: lw a2, 12(a0)
+; RV32IF-NEXT: sub a0, a0, a1
+; RV32IF-NEXT: lw a2, 8(a0)
+; RV32IF-NEXT: lw a1, 12(a0)
; RV32IF-NEXT: lw a5, 4(a0)
; RV32IF-NEXT: lw a0, 0(a0)
; RV32IF-NEXT: andi a3, a4, 31
-; RV32IF-NEXT: srli a6, a1, 1
+; RV32IF-NEXT: srli a6, a2, 1
; RV32IF-NEXT: xori a7, a3, 31
-; RV32IF-NEXT: sll a2, a2, a4
+; RV32IF-NEXT: sll a1, a1, a4
; RV32IF-NEXT: srl a3, a6, a7
-; RV32IF-NEXT: or a2, a2, a3
+; RV32IF-NEXT: or a1, a1, a3
; RV32IF-NEXT: srli a3, a5, 1
-; RV32IF-NEXT: sll a1, a1, a4
+; RV32IF-NEXT: sll a2, a2, a4
; RV32IF-NEXT: srl a3, a3, a7
-; RV32IF-NEXT: or a3, a1, a3
-; RV32IF-NEXT: srli a1, a0, 1
+; RV32IF-NEXT: or a3, a2, a3
+; RV32IF-NEXT: srli a2, a0, 1
; RV32IF-NEXT: sll a5, a5, a4
-; RV32IF-NEXT: srl a1, a1, a7
-; RV32IF-NEXT: or a1, a5, a1
+; RV32IF-NEXT: srl a2, a2, a7
+; RV32IF-NEXT: or a2, a5, a2
; RV32IF-NEXT: sll a0, a0, a4
; RV32IF-NEXT: addi sp, sp, 32
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: j .LBB46_8
; RV32IF-NEXT: .LBB46_6:
-; RV32IF-NEXT: not a2, a5
-; RV32IF-NEXT: slli a3, a1, 1
+; RV32IF-NEXT: not a1, a5
+; RV32IF-NEXT: slli a3, a2, 1
; RV32IF-NEXT: srl a0, a0, a5
-; RV32IF-NEXT: sll a2, a3, a2
-; RV32IF-NEXT: or a0, a0, a2
+; RV32IF-NEXT: sll a1, a3, a1
+; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: .LBB46_7: # %fp-to-i-if-exp.small
; RV32IF-NEXT: li a3, 0
-; RV32IF-NEXT: li a2, 0
-; RV32IF-NEXT: srl a1, a1, a5
+; RV32IF-NEXT: li a1, 0
+; RV32IF-NEXT: srl a2, a2, a5
; RV32IF-NEXT: srai a4, a4, 31
-; RV32IF-NEXT: and a1, a4, a1
+; RV32IF-NEXT: and a2, a4, a2
; RV32IF-NEXT: .LBB46_8: # %fp-to-i-cleanup
; RV32IF-NEXT: xori a4, a3, 1
-; RV32IF-NEXT: or a4, a4, a2
-; RV32IF-NEXT: or a2, a2, a3
+; RV32IF-NEXT: or a4, a4, a1
+; RV32IF-NEXT: or a1, a1, a3
; RV32IF-NEXT: seqz a3, a4
-; RV32IF-NEXT: seqz a2, a2
+; RV32IF-NEXT: seqz a1, a1
; RV32IF-NEXT: addi a3, a3, -1
-; RV32IF-NEXT: and a2, a3, a2
-; RV32IF-NEXT: neg a2, a2
-; RV32IF-NEXT: and a0, a2, a0
-; RV32IF-NEXT: and a1, a2, a1
+; RV32IF-NEXT: and a1, a3, a1
+; RV32IF-NEXT: neg a1, a1
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: and a1, a1, a2
; RV32IF-NEXT: ret
;
; RV64-LABEL: utest_f64i64_mm:
@@ -5128,23 +5128,23 @@ define i64 @utest_f64i64_mm(double %x) {
; RV32IFD-NEXT: bgeu a0, a2, .LBB46_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: li a1, 0
-; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: li a2, 0
+; RV32IFD-NEXT: li a3, 0
+; RV32IFD-NEXT: li a1, 0
; RV32IFD-NEXT: j .LBB46_8
; RV32IFD-NEXT: .LBB46_2: # %fp-to-i-if-check.exp.size
; RV32IFD-NEXT: lw a2, 8(sp)
; RV32IFD-NEXT: lui a3, 256
; RV32IFD-NEXT: addi a3, a3, -1
-; RV32IFD-NEXT: and a1, a1, a3
-; RV32IFD-NEXT: addi a4, a2, -1
-; RV32IFD-NEXT: snez a5, a2
-; RV32IFD-NEXT: addi a2, a4, 1
-; RV32IFD-NEXT: add a1, a1, a5
-; RV32IFD-NEXT: seqz a4, a2
-; RV32IFD-NEXT: add a1, a1, a3
+; RV32IFD-NEXT: and a4, a1, a3
+; RV32IFD-NEXT: addi a1, a2, -1
+; RV32IFD-NEXT: snez a2, a2
+; RV32IFD-NEXT: addi a1, a1, 1
+; RV32IFD-NEXT: add a2, a4, a2
+; RV32IFD-NEXT: seqz a4, a1
+; RV32IFD-NEXT: add a2, a2, a3
; RV32IFD-NEXT: li a3, 1074
-; RV32IFD-NEXT: add a1, a1, a4
+; RV32IFD-NEXT: add a2, a2, a4
; RV32IFD-NEXT: bltu a3, a0, .LBB46_5
; RV32IFD-NEXT: # %bb.3: # %fp-to-i-if-exp.small
; RV32IFD-NEXT: li a4, 1043
@@ -5153,13 +5153,13 @@ define i64 @utest_f64i64_mm(double %x) {
; RV32IFD-NEXT: sub a5, a5, a0
; RV32IFD-NEXT: bltz a4, .LBB46_6
; RV32IFD-NEXT: # %bb.4: # %fp-to-i-if-exp.small
-; RV32IFD-NEXT: srl a0, a1, a4
+; RV32IFD-NEXT: srl a0, a2, a4
; RV32IFD-NEXT: j .LBB46_7
; RV32IFD-NEXT: .LBB46_5: # %fp-to-i-if-exp.large
; RV32IFD-NEXT: addi a0, a0, -1075
; RV32IFD-NEXT: srli a3, a0, 3
-; RV32IFD-NEXT: sw a2, 32(sp)
-; RV32IFD-NEXT: sw a1, 36(sp)
+; RV32IFD-NEXT: sw a1, 32(sp)
+; RV32IFD-NEXT: sw a2, 36(sp)
; RV32IFD-NEXT: sw zero, 40(sp)
; RV32IFD-NEXT: sw zero, 44(sp)
; RV32IFD-NEXT: andi a3, a3, 12
@@ -5169,49 +5169,49 @@ define i64 @utest_f64i64_mm(double %x) {
; RV32IFD-NEXT: sw zero, 24(sp)
; RV32IFD-NEXT: sw zero, 28(sp)
; RV32IFD-NEXT: sub a1, a1, a3
-; RV32IFD-NEXT: lw a3, 8(a1)
-; RV32IFD-NEXT: lw a2, 12(a1)
+; RV32IFD-NEXT: lw a2, 8(a1)
+; RV32IFD-NEXT: lw a3, 12(a1)
; RV32IFD-NEXT: lw a4, 4(a1)
; RV32IFD-NEXT: lw a5, 0(a1)
; RV32IFD-NEXT: andi a1, a0, 31
-; RV32IFD-NEXT: srli a6, a3, 1
-; RV32IFD-NEXT: xori a1, a1, 31
+; RV32IFD-NEXT: srli a6, a2, 1
+; RV32IFD-NEXT: xori a7, a1, 31
+; RV32IFD-NEXT: sll a1, a3, a0
+; RV32IFD-NEXT: srl a3, a6, a7
+; RV32IFD-NEXT: or a1, a1, a3
+; RV32IFD-NEXT: srli a3, a4, 1
; RV32IFD-NEXT: sll a2, a2, a0
-; RV32IFD-NEXT: srl a6, a6, a1
-; RV32IFD-NEXT: or a2, a2, a6
-; RV32IFD-NEXT: srli a6, a4, 1
-; RV32IFD-NEXT: sll a3, a3, a0
-; RV32IFD-NEXT: srl a6, a6, a1
-; RV32IFD-NEXT: or a3, a3, a6
-; RV32IFD-NEXT: srli a6, a5, 1
+; RV32IFD-NEXT: srl a3, a3, a7
+; RV32IFD-NEXT: or a3, a2, a3
+; RV32IFD-NEXT: srli a2, a5, 1
; RV32IFD-NEXT: sll a4, a4, a0
-; RV32IFD-NEXT: srl a1, a6, a1
-; RV32IFD-NEXT: or a1, a4, a1
+; RV32IFD-NEXT: srl a2, a2, a7
+; RV32IFD-NEXT: or a2, a4, a2
; RV32IFD-NEXT: sll a0, a5, a0
; RV32IFD-NEXT: j .LBB46_8
; RV32IFD-NEXT: .LBB46_6:
; RV32IFD-NEXT: not a0, a5
-; RV32IFD-NEXT: slli a3, a1, 1
-; RV32IFD-NEXT: srl a2, a2, a5
+; RV32IFD-NEXT: slli a3, a2, 1
+; RV32IFD-NEXT: srl a1, a1, a5
; RV32IFD-NEXT: sll a0, a3, a0
-; RV32IFD-NEXT: or a0, a2, a0
+; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: .LBB46_7: # %fp-to-i-if-exp.small
; RV32IFD-NEXT: li a3, 0
-; RV32IFD-NEXT: li a2, 0
-; RV32IFD-NEXT: srl a1, a1, a5
+; RV32IFD-NEXT: li a1, 0
+; RV32IFD-NEXT: srl a2, a2, a5
; RV32IFD-NEXT: srai a4, a4, 31
-; RV32IFD-NEXT: and a1, a4, a1
+; RV32IFD-NEXT: and a2, a4, a2
; RV32IFD-NEXT: .LBB46_8: # %fp-to-i-cleanup
; RV32IFD-NEXT: xori a4, a3, 1
-; RV32IFD-NEXT: or a4, a4, a2
-; RV32IFD-NEXT: or a2, a2, a3
+; RV32IFD-NEXT: or a4, a4, a1
+; RV32IFD-NEXT: or a1, a1, a3
; RV32IFD-NEXT: seqz a3, a4
-; RV32IFD-NEXT: seqz a2, a2
+; RV32IFD-NEXT: seqz a1, a1
; RV32IFD-NEXT: addi a3, a3, -1
-; RV32IFD-NEXT: and a2, a3, a2
-; RV32IFD-NEXT: neg a2, a2
-; RV32IFD-NEXT: and a0, a2, a0
-; RV32IFD-NEXT: and a1, a2, a1
+; RV32IFD-NEXT: and a1, a3, a1
+; RV32IFD-NEXT: neg a1, a1
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: and a1, a1, a2
; RV32IFD-NEXT: addi sp, sp, 48
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/idiv_large.ll b/llvm/test/CodeGen/RISCV/idiv_large.ll
index 27aefeaff7a91..82042aa44d6fc 100644
--- a/llvm/test/CodeGen/RISCV/idiv_large.ll
+++ b/llvm/test/CodeGen/RISCV/idiv_large.ll
@@ -23,24 +23,24 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-LABEL: udiv_i65:
; RV32: # %bb.0: # %_udiv-special-cases
; RV32-NEXT: lw a3, 4(a2)
-; RV32-NEXT: lw t1, 8(a2)
+; RV32-NEXT: lw a6, 8(a2)
; RV32-NEXT: lw a2, 0(a2)
; RV32-NEXT: lui a4, 349525
; RV32-NEXT: lui a5, 209715
-; RV32-NEXT: lui a7, 61681
-; RV32-NEXT: addi t0, a4, 1365
+; RV32-NEXT: lui t1, 61681
+; RV32-NEXT: addi t2, a4, 1365
; RV32-NEXT: srli a4, a3, 1
-; RV32-NEXT: slli t2, t1, 31
-; RV32-NEXT: addi a6, a5, 819
-; RV32-NEXT: or t3, t2, a4
+; RV32-NEXT: slli t0, a6, 31
+; RV32-NEXT: addi a7, a5, 819
+; RV32-NEXT: or t0, t0, a4
; RV32-NEXT: slli a4, a3, 31
; RV32-NEXT: srli a5, a2, 1
-; RV32-NEXT: addi a7, a7, -241
-; RV32-NEXT: or t5, a5, a4
-; RV32-NEXT: bnez t3, .LBB1_2
+; RV32-NEXT: addi t1, t1, -241
+; RV32-NEXT: or t4, a5, a4
+; RV32-NEXT: bnez t0, .LBB1_2
; RV32-NEXT: # %bb.1: # %_udiv-special-cases
-; RV32-NEXT: srli a4, t5, 1
-; RV32-NEXT: or a4, t5, a4
+; RV32-NEXT: srli a4, t4, 1
+; RV32-NEXT: or a4, t4, a4
; RV32-NEXT: srli a5, a4, 2
; RV32-NEXT: or a4, a4, a5
; RV32-NEXT: srli a5, a4, 4
@@ -51,25 +51,25 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: or a4, a4, a5
; RV32-NEXT: not a4, a4
; RV32-NEXT: srli a5, a4, 1
-; RV32-NEXT: and a5, a5, t0
+; RV32-NEXT: and a5, a5, t2
; RV32-NEXT: sub a4, a4, a5
; RV32-NEXT: srli a5, a4, 2
-; RV32-NEXT: and a4, a4, a6
-; RV32-NEXT: and a5, a5, a6
+; RV32-NEXT: and a4, a4, a7
+; RV32-NEXT: and a5, a5, a7
; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: srli a5, a4, 4
; RV32-NEXT: add a4, a4, a5
-; RV32-NEXT: and a4, a4, a7
+; RV32-NEXT: and a4, a4, t1
; RV32-NEXT: slli a5, a4, 8
; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: slli a5, a4, 16
; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: srli a4, a4, 24
-; RV32-NEXT: addi t2, a4, 32
+; RV32-NEXT: addi t3, a4, 32
; RV32-NEXT: j .LBB1_3
; RV32-NEXT: .LBB1_2:
-; RV32-NEXT: srli a4, t3, 1
-; RV32-NEXT: or a4, t3, a4
+; RV32-NEXT: srli a4, t0, 1
+; RV32-NEXT: or a4, t0, a4
; RV32-NEXT: srli a5, a4, 2
; RV32-NEXT: or a4, a4, a5
; RV32-NEXT: srli a5, a4, 4
@@ -80,20 +80,20 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: or a4, a4, a5
; RV32-NEXT: not a4, a4
; RV32-NEXT: srli a5, a4, 1
-; RV32-NEXT: and a5, a5, t0
+; RV32-NEXT: and a5, a5, t2
; RV32-NEXT: sub a4, a4, a5
; RV32-NEXT: srli a5, a4, 2
-; RV32-NEXT: and a4, a4, a6
-; RV32-NEXT: and a5, a5, a6
+; RV32-NEXT: and a4, a4, a7
+; RV32-NEXT: and a5, a5, a7
; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: srli a5, a4, 4
; RV32-NEXT: add a4, a4, a5
-; RV32-NEXT: and a4, a4, a7
+; RV32-NEXT: and a4, a4, t1
; RV32-NEXT: slli a5, a4, 8
; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: slli a5, a4, 16
; RV32-NEXT: add a4, a4, a5
-; RV32-NEXT: srli t2, a4, 24
+; RV32-NEXT: srli t3, a4, 24
; RV32-NEXT: .LBB1_3: # %_udiv-special-cases
; RV32-NEXT: addi sp, sp, -96
; RV32-NEXT: sw s0, 92(sp) # 4-byte Folded Spill
@@ -104,7 +104,7 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: sw s5, 72(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s6, 68(sp) # 4-byte Folded Spill
; RV32-NEXT: slli a4, a2, 31
-; RV32-NEXT: li t4, 64
+; RV32-NEXT: li t5, 64
; RV32-NEXT: bnez a4, .LBB1_5
; RV32-NEXT: # %bb.4: # %_udiv-special-cases
; RV32-NEXT: li s0, 64
@@ -122,15 +122,15 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: or a4, a4, a5
; RV32-NEXT: not a4, a4
; RV32-NEXT: srli a5, a4, 1
-; RV32-NEXT: and a5, a5, t0
+; RV32-NEXT: and a5, a5, t2
; RV32-NEXT: sub a4, a4, a5
; RV32-NEXT: srli a5, a4, 2
-; RV32-NEXT: and a4, a4, a6
-; RV32-NEXT: and a5, a5, a6
+; RV32-NEXT: and a4, a4, a7
+; RV32-NEXT: and a5, a5, a7
; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: srli a5, a4, 4
; RV32-NEXT: add a4, a4, a5
-; RV32-NEXT: and a4, a4, a7
+; RV32-NEXT: and a4, a4, t1
; RV32-NEXT: slli a5, a4, 8
; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: slli a5, a4, 16
@@ -139,200 +139,200 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: .LBB1_6: # %_udiv-special-cases
; RV32-NEXT: lw a5, 0(a1)
; RV32-NEXT: lw a4, 4(a1)
-; RV32-NEXT: lw a1, 8(a1)
-; RV32-NEXT: or t3, t5, t3
+; RV32-NEXT: lw s3, 8(a1)
+; RV32-NEXT: or t0, t4, t0
; RV32-NEXT: addi s2, s0, 64
-; RV32-NEXT: bnez t3, .LBB1_8
+; RV32-NEXT: bnez t0, .LBB1_8
; RV32-NEXT: # %bb.7: # %_udiv-special-cases
-; RV32-NEXT: mv t2, s2
+; RV32-NEXT: mv t3, s2
; RV32-NEXT: .LBB1_8: # %_udiv-special-cases
-; RV32-NEXT: srli t5, a4, 1
-; RV32-NEXT: slli t6, a1, 31
-; RV32-NEXT: or t5, t6, t5
-; RV32-NEXT: slli t6, a4, 31
-; RV32-NEXT: srli s1, a5, 1
-; RV32-NEXT: snez s3, t3
-; RV32-NEXT: or t6, s1, t6
-; RV32-NEXT: bnez t5, .LBB1_10
+; RV32-NEXT: srli a1, a4, 1
+; RV32-NEXT: slli t4, s3, 31
+; RV32-NEXT: or a1, t4, a1
+; RV32-NEXT: slli t4, a4, 31
+; RV32-NEXT: srli t6, a5, 1
+; RV32-NEXT: snez s4, t0
+; RV32-NEXT: or t6, t6, t4
+; RV32-NEXT: bnez a1, .LBB1_10
; RV32-NEXT: # %bb.9: # %_udiv-special-cases
-; RV32-NEXT: srli t3, t6, 1
-; RV32-NEXT: or t3, t6, t3
-; RV32-NEXT: srli s1, t3, 2
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 4
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 8
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 16
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: not t3, t3
-; RV32-NEXT: srli s1, t3, 1
-; RV32-NEXT: and s1, s1, t0
-; RV32-NEXT: sub t3, t3, s1
-; RV32-NEXT: srli s1, t3, 2
-; RV32-NEXT: and t3, t3, a6
-; RV32-NEXT: and s1, s1, a6
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: srli s1, t3, 4
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: and t3, t3, a7
-; RV32-NEXT: slli s1, t3, 8
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: slli s1, t3, 16
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: srli t3, t3, 24
-; RV32-NEXT: addi s1, t3, 32
+; RV32-NEXT: srli t0, t6, 1
+; RV32-NEXT: or t0, t6, t0
+; RV32-NEXT: srli t4, t0, 2
+; RV32-NEXT: or t0, t0, t4
+; RV32-NEXT: srli t4, t0, 4
+; RV32-NEXT: or t0, t0, t4
+; RV32-NEXT: srli t4, t0, 8
+; RV32-NEXT: or t0, t0, t4
+; RV32-NEXT: srli t4, t0, 16
+; RV32-NEXT: or t0, t0, t4
+; RV32-NEXT: not t0, t0
+; RV32-NEXT: srli t4, t0, 1
+; RV32-NEXT: and t4, t4, t2
+; RV32-NEXT: sub t0, t0, t4
+; RV32-NEXT: srli t4, t0, 2
+; RV32-NEXT: and t0, t0, a7
+; RV32-NEXT: and t4, t4, a7
+; RV32-NEXT: add t0, t0, t4
+; RV32-NEXT: srli t4, t0, 4
+; RV32-NEXT: add t0, t0, t4
+; RV32-NEXT: and t0, t0, t1
+; RV32-NEXT: slli t4, t0, 8
+; RV32-NEXT: add t0, t0, t4
+; RV32-NEXT: slli t4, t0, 16
+; RV32-NEXT: add t0, t0, t4
+; RV32-NEXT: srli t0, t0, 24
+; RV32-NEXT: addi s1, t0, 32
; RV32-NEXT: j .LBB1_11
; RV32-NEXT: .LBB1_10:
-; RV32-NEXT: srli t3, t5, 1
-; RV32-NEXT: or t3, t5, t3
-; RV32-NEXT: srli s1, t3, 2
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 4
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 8
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 16
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: not t3, t3
-; RV32-NEXT: srli s1, t3, 1
-; RV32-NEXT: and s1, s1, t0
-; RV32-NEXT: sub t3, t3, s1
-; RV32-NEXT: srli s1, t3, 2
-; RV32-NEXT: and t3, t3, a6
-; RV32-NEXT: and s1, s1, a6
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: srli s1, t3, 4
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: and t3, t3, a7
-; RV32-NEXT: slli s1, t3, 8
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: slli s1, t3, 16
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: srli s1, t3, 24
+; RV32-NEXT: srli t0, a1, 1
+; RV32-NEXT: or t0, a1, t0
+; RV32-NEXT: srli t4, t0, 2
+; RV32-NEXT: or t0, t0, t4
+; RV32-NEXT: srli t4, t0, 4
+; RV32-NEXT: or t0, t0, t4
+; RV32-NEXT: srli t4, t0, 8
+; RV32-NEXT: or t0, t0, t4
+; RV32-NEXT: srli t4, t0, 16
+; RV32-NEXT: or t0, t0, t4
+; RV32-NEXT: not t0, t0
+; RV32-NEXT: srli t4, t0, 1
+; RV32-NEXT: and t4, t4, t2
+; RV32-NEXT: sub t0, t0, t4
+; RV32-NEXT: srli t4, t0, 2
+; RV32-NEXT: and t0, t0, a7
+; RV32-NEXT: and t4, t4, a7
+; RV32-NEXT: add t0, t0, t4
+; RV32-NEXT: srli t4, t0, 4
+; RV32-NEXT: add t0, t0, t4
+; RV32-NEXT: and t0, t0, t1
+; RV32-NEXT: slli t4, t0, 8
+; RV32-NEXT: add t0, t0, t4
+; RV32-NEXT: slli t4, t0, 16
+; RV32-NEXT: add t0, t0, t4
+; RV32-NEXT: srli s1, t0, 24
; RV32-NEXT: .LBB1_11: # %_udiv-special-cases
-; RV32-NEXT: andi t3, a1, 1
-; RV32-NEXT: andi a1, t1, 1
-; RV32-NEXT: or t1, a2, a3
+; RV32-NEXT: andi t4, s3, 1
+; RV32-NEXT: andi a6, a6, 1
+; RV32-NEXT: or t0, a2, a3
; RV32-NEXT: sltu s0, s2, s0
-; RV32-NEXT: slli s4, a5, 31
+; RV32-NEXT: slli s3, a5, 31
; RV32-NEXT: or s2, a5, a4
-; RV32-NEXT: addi s3, s3, -1
-; RV32-NEXT: beqz s4, .LBB1_13
+; RV32-NEXT: addi s4, s4, -1
+; RV32-NEXT: beqz s3, .LBB1_13
; RV32-NEXT: # %bb.12:
-; RV32-NEXT: srli t4, s4, 1
-; RV32-NEXT: or t4, s4, t4
-; RV32-NEXT: srli s4, t4, 2
-; RV32-NEXT: or t4, t4, s4
-; RV32-NEXT: srli s4, t4, 4
-; RV32-NEXT: or t4, t4, s4
-; RV32-NEXT: srli s4, t4, 8
-; RV32-NEXT: or t4, t4, s4
-; RV32-NEXT: srli s4, t4, 16
-; RV32-NEXT: or t4, t4, s4
-; RV32-NEXT: not t4, t4
-; RV32-NEXT: srli s4, t4, 1
-; RV32-NEXT: and t0, s4, t0
-; RV32-NEXT: sub t0, t4, t0
-; RV32-NEXT: srli t4, t0, 2
-; RV32-NEXT: and t0, t0, a6
-; RV32-NEXT: and a6, t4, a6
-; RV32-NEXT: add a6, t0, a6
-; RV32-NEXT: srli t0, a6, 4
-; RV32-NEXT: add a6, a6, t0
-; RV32-NEXT: and a6, a6, a7
-; RV32-NEXT: slli a7, a6, 8
-; RV32-NEXT: add a6, a6, a7
-; RV32-NEXT: slli a7, a6, 16
-; RV32-NEXT: add a6, a6, a7
-; RV32-NEXT: srli t4, a6, 24
+; RV32-NEXT: srli t5, s3, 1
+; RV32-NEXT: or t5, s3, t5
+; RV32-NEXT: srli s3, t5, 2
+; RV32-NEXT: or t5, t5, s3
+; RV32-NEXT: srli s3, t5, 4
+; RV32-NEXT: or t5, t5, s3
+; RV32-NEXT: srli s3, t5, 8
+; RV32-NEXT: or t5, t5, s3
+; RV32-NEXT: srli s3, t5, 16
+; RV32-NEXT: or t5, t5, s3
+; RV32-NEXT: not t5, t5
+; RV32-NEXT: srli s3, t5, 1
+; RV32-NEXT: and t2, s3, t2
+; RV32-NEXT: sub t2, t5, t2
+; RV32-NEXT: srli t5, t2, 2
+; RV32-NEXT: and t2, t2, a7
+; RV32-NEXT: and a7, t5, a7
+; RV32-NEXT: add a7, t2, a7
+; RV32-NEXT: srli t2, a7, 4
+; RV32-NEXT: add a7, a7, t2
+; RV32-NEXT: and a7, a7, t1
+; RV32-NEXT: slli t1, a7, 8
+; RV32-NEXT: add a7, a7, t1
+; RV32-NEXT: slli t1, a7, 16
+; RV32-NEXT: add a7, a7, t1
+; RV32-NEXT: srli t5, a7, 24
; RV32-NEXT: .LBB1_13: # %_udiv-special-cases
-; RV32-NEXT: or t0, t1, a1
-; RV32-NEXT: or a7, s2, t3
-; RV32-NEXT: or t5, t6, t5
-; RV32-NEXT: and a6, s3, s0
-; RV32-NEXT: addi t6, t4, 64
-; RV32-NEXT: bnez t5, .LBB1_15
+; RV32-NEXT: or t1, t0, a6
+; RV32-NEXT: or a7, s2, t4
+; RV32-NEXT: or t2, t6, a1
+; RV32-NEXT: and a1, s4, s0
+; RV32-NEXT: addi t6, t5, 64
+; RV32-NEXT: bnez t2, .LBB1_15
; RV32-NEXT: # %bb.14: # %_udiv-special-cases
; RV32-NEXT: mv s1, t6
; RV32-NEXT: .LBB1_15: # %_udiv-special-cases
-; RV32-NEXT: seqz t0, t0
-; RV32-NEXT: snez t5, t5
-; RV32-NEXT: sltu t4, t6, t4
-; RV32-NEXT: addi t5, t5, -1
-; RV32-NEXT: and t6, t5, t4
-; RV32-NEXT: sltu s0, t2, s1
+; RV32-NEXT: seqz t1, t1
+; RV32-NEXT: snez t2, t2
+; RV32-NEXT: sltu t5, t6, t5
+; RV32-NEXT: addi t2, t2, -1
+; RV32-NEXT: and t6, t2, t5
+; RV32-NEXT: sltu s0, t3, s1
; RV32-NEXT: seqz a7, a7
-; RV32-NEXT: mv t4, s0
-; RV32-NEXT: beq a6, t6, .LBB1_17
+; RV32-NEXT: mv t2, s0
+; RV32-NEXT: beq a1, t6, .LBB1_17
; RV32-NEXT: # %bb.16: # %_udiv-special-cases
-; RV32-NEXT: sltu t4, a6, t6
+; RV32-NEXT: sltu t2, a1, t6
; RV32-NEXT: .LBB1_17: # %_udiv-special-cases
-; RV32-NEXT: or t5, t0, a7
-; RV32-NEXT: andi t4, t4, 1
-; RV32-NEXT: sub a6, a6, t6
-; RV32-NEXT: sub a7, a6, s0
-; RV32-NEXT: sub t0, t2, s1
-; RV32-NEXT: beqz t4, .LBB1_19
+; RV32-NEXT: or t5, t1, a7
+; RV32-NEXT: andi t2, t2, 1
+; RV32-NEXT: sub a1, a1, t6
+; RV32-NEXT: sub t1, a1, s0
+; RV32-NEXT: sub a7, t3, s1
+; RV32-NEXT: beqz t2, .LBB1_19
; RV32-NEXT: # %bb.18: # %_udiv-special-cases
-; RV32-NEXT: mv a6, t4
+; RV32-NEXT: mv a1, t2
; RV32-NEXT: j .LBB1_20
; RV32-NEXT: .LBB1_19:
-; RV32-NEXT: sltiu a6, t0, 65
-; RV32-NEXT: xori a6, a6, 1
-; RV32-NEXT: snez t2, a7
-; RV32-NEXT: or a6, a6, t2
+; RV32-NEXT: sltiu a1, a7, 65
+; RV32-NEXT: xori a1, a1, 1
+; RV32-NEXT: snez t3, t1
+; RV32-NEXT: or a1, a1, t3
; RV32-NEXT: .LBB1_20: # %_udiv-special-cases
-; RV32-NEXT: or t6, t5, a6
+; RV32-NEXT: or t6, t5, a1
; RV32-NEXT: addi t5, t6, -1
-; RV32-NEXT: and a6, t3, t5
-; RV32-NEXT: and t2, t5, a4
+; RV32-NEXT: and a1, t4, t5
+; RV32-NEXT: and t3, t5, a4
; RV32-NEXT: and t5, t5, a5
; RV32-NEXT: bnez t6, .LBB1_29
; RV32-NEXT: # %bb.21: # %_udiv-special-cases
-; RV32-NEXT: xori t6, t0, 64
-; RV32-NEXT: or s0, t4, a7
+; RV32-NEXT: xori t6, a7, 64
+; RV32-NEXT: or s0, t2, t1
; RV32-NEXT: or t6, t6, s0
; RV32-NEXT: beqz t6, .LBB1_29
; RV32-NEXT: # %bb.22: # %udiv-bb1
-; RV32-NEXT: addi a6, t0, 1
-; RV32-NEXT: li t2, 64
-; RV32-NEXT: seqz t5, a6
-; RV32-NEXT: sub t2, t2, t0
-; RV32-NEXT: add a7, a7, t5
+; RV32-NEXT: addi a1, a7, 1
+; RV32-NEXT: li t3, 64
+; RV32-NEXT: seqz t5, a1
+; RV32-NEXT: sub t6, t3, a7
+; RV32-NEXT: add t1, t1, t5
; RV32-NEXT: sw zero, 32(sp)
; RV32-NEXT: sw zero, 36(sp)
; RV32-NEXT: sw zero, 40(sp)
; RV32-NEXT: sw zero, 44(sp)
-; RV32-NEXT: srli t5, t2, 3
-; RV32-NEXT: andi t5, t5, 12
-; RV32-NEXT: addi t6, sp, 48
+; RV32-NEXT: srli t3, t6, 3
+; RV32-NEXT: andi t3, t3, 12
+; RV32-NEXT: addi t5, sp, 48
; RV32-NEXT: sw a5, 48(sp)
; RV32-NEXT: sw a4, 52(sp)
-; RV32-NEXT: sw t3, 56(sp)
-; RV32-NEXT: sub s4, t6, t5
-; RV32-NEXT: or t5, a6, a7
-; RV32-NEXT: lw t6, 0(s4)
-; RV32-NEXT: seqz s0, t5
-; RV32-NEXT: add t4, t4, s0
+; RV32-NEXT: sw t4, 56(sp)
+; RV32-NEXT: sub s4, t5, t3
+; RV32-NEXT: or t5, a1, t1
+; RV32-NEXT: lw s0, 0(s4)
+; RV32-NEXT: seqz t3, t5
+; RV32-NEXT: add t2, t2, t3
; RV32-NEXT: lw s2, 4(s4)
-; RV32-NEXT: andi t4, t4, 1
-; RV32-NEXT: andi t2, t2, 31
+; RV32-NEXT: andi t3, t2, 1
+; RV32-NEXT: andi t2, t6, 31
; RV32-NEXT: xori s1, t2, 31
-; RV32-NEXT: srli t2, t6, 1
+; RV32-NEXT: srli t2, s0, 1
; RV32-NEXT: srl t2, t2, s1
-; RV32-NEXT: neg s3, t0
-; RV32-NEXT: sll t0, s2, s3
-; RV32-NEXT: or t5, t5, t4
-; RV32-NEXT: or t0, t0, t2
-; RV32-NEXT: sll t2, t6, s3
+; RV32-NEXT: neg s3, a7
+; RV32-NEXT: sll a7, s2, s3
+; RV32-NEXT: or t5, t5, t3
+; RV32-NEXT: or a7, a7, t2
+; RV32-NEXT: sll t2, s0, s3
; RV32-NEXT: beqz t5, .LBB1_28
; RV32-NEXT: # %bb.23: # %udiv-preheader
; RV32-NEXT: li t5, 0
; RV32-NEXT: li t6, 0
; RV32-NEXT: li s0, 0
; RV32-NEXT: lw s4, 8(s4)
-; RV32-NEXT: srli s5, a6, 3
+; RV32-NEXT: srli s5, a1, 3
; RV32-NEXT: sw zero, 16(sp)
; RV32-NEXT: sw zero, 20(sp)
; RV32-NEXT: sw zero, 24(sp)
@@ -341,97 +341,97 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: mv s6, sp
; RV32-NEXT: sw a5, 0(sp)
; RV32-NEXT: sw a4, 4(sp)
-; RV32-NEXT: sw t3, 8(sp)
+; RV32-NEXT: sw t4, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: add s5, s6, s5
; RV32-NEXT: lw a4, 4(s5)
; RV32-NEXT: srli a5, s2, 1
-; RV32-NEXT: lw t3, 8(s5)
+; RV32-NEXT: lw t4, 8(s5)
; RV32-NEXT: srl a5, a5, s1
; RV32-NEXT: sll s1, s4, s3
; RV32-NEXT: lw s2, 0(s5)
; RV32-NEXT: or a5, s1, a5
-; RV32-NEXT: srl s1, a4, a6
-; RV32-NEXT: andi s3, a6, 31
-; RV32-NEXT: slli t3, t3, 1
+; RV32-NEXT: srl s1, a4, a1
+; RV32-NEXT: andi s3, a1, 31
+; RV32-NEXT: slli t4, t4, 1
; RV32-NEXT: xori s3, s3, 31
-; RV32-NEXT: sll t3, t3, s3
+; RV32-NEXT: sll t4, t4, s3
; RV32-NEXT: slli a4, a4, 1
-; RV32-NEXT: or t3, s1, t3
+; RV32-NEXT: or t4, s1, t4
; RV32-NEXT: sll a4, a4, s3
; RV32-NEXT: andi s1, a5, 1
-; RV32-NEXT: srl a5, s2, a6
+; RV32-NEXT: srl a5, s2, a1
; RV32-NEXT: or s2, a5, a4
-; RV32-NEXT: snez a4, t1
+; RV32-NEXT: snez a4, t0
; RV32-NEXT: seqz a5, a2
-; RV32-NEXT: add a4, a1, a4
-; RV32-NEXT: sub a1, a3, a5
-; RV32-NEXT: not a4, a4
-; RV32-NEXT: andi a4, a4, 1
-; RV32-NEXT: addi a5, a2, -1
+; RV32-NEXT: add a6, a6, a4
+; RV32-NEXT: sub a4, a3, a5
+; RV32-NEXT: not a5, a6
+; RV32-NEXT: andi a5, a5, 1
+; RV32-NEXT: addi a6, a2, -1
; RV32-NEXT: j .LBB1_26
; RV32-NEXT: .LBB1_24: # %udiv-do-while
; RV32-NEXT: # in Loop: Header=BB1_26 Depth=1
-; RV32-NEXT: sltu s1, a1, t1
+; RV32-NEXT: sltu s1, a4, t0
; RV32-NEXT: .LBB1_25: # %udiv-do-while
; RV32-NEXT: # in Loop: Header=BB1_26 Depth=1
-; RV32-NEXT: srli t3, t3, 31
-; RV32-NEXT: sub t3, a4, t3
-; RV32-NEXT: sub t3, t3, s1
-; RV32-NEXT: slli t3, t3, 31
-; RV32-NEXT: srai t3, t3, 31
-; RV32-NEXT: and s3, t3, a3
+; RV32-NEXT: srli t4, t4, 31
+; RV32-NEXT: sub t4, a5, t4
+; RV32-NEXT: sub t4, t4, s1
+; RV32-NEXT: slli t4, t4, 31
+; RV32-NEXT: srai t4, t4, 31
+; RV32-NEXT: and s3, t4, a3
; RV32-NEXT: srli s1, t2, 31
-; RV32-NEXT: slli s4, t0, 1
+; RV32-NEXT: slli s4, a7, 1
; RV32-NEXT: slli t2, t2, 1
; RV32-NEXT: or s1, s4, s1
-; RV32-NEXT: srli s4, t0, 31
+; RV32-NEXT: srli s4, a7, 31
; RV32-NEXT: or t2, t5, t2
-; RV32-NEXT: or t0, t6, s1
+; RV32-NEXT: or a7, t6, s1
; RV32-NEXT: or s1, s0, s4
; RV32-NEXT: andi s1, s1, 1
-; RV32-NEXT: and t6, t3, a2
+; RV32-NEXT: and t6, t4, a2
; RV32-NEXT: sltu s0, s2, t6
-; RV32-NEXT: sub t1, t1, s3
-; RV32-NEXT: andi t5, t3, 1
-; RV32-NEXT: sub t3, t1, s0
+; RV32-NEXT: sub t0, t0, s3
+; RV32-NEXT: andi t5, t4, 1
+; RV32-NEXT: sub t4, t0, s0
; RV32-NEXT: sub s2, s2, t6
-; RV32-NEXT: or t1, a6, a7
-; RV32-NEXT: seqz t6, a6
-; RV32-NEXT: snez t1, t1
-; RV32-NEXT: sub a7, a7, t6
-; RV32-NEXT: add t1, t4, t1
-; RV32-NEXT: not t1, t1
-; RV32-NEXT: addi a6, a6, -1
-; RV32-NEXT: andi t4, t1, 1
-; RV32-NEXT: or t1, a6, a7
-; RV32-NEXT: or t1, t1, t4
+; RV32-NEXT: or t0, a1, t1
+; RV32-NEXT: seqz t6, a1
+; RV32-NEXT: snez t0, t0
+; RV32-NEXT: sub t1, t1, t6
+; RV32-NEXT: add t0, t3, t0
+; RV32-NEXT: not t0, t0
+; RV32-NEXT: addi a1, a1, -1
+; RV32-NEXT: andi t3, t0, 1
+; RV32-NEXT: or t0, a1, t1
+; RV32-NEXT: or t0, t0, t3
; RV32-NEXT: li t6, 0
; RV32-NEXT: li s0, 0
-; RV32-NEXT: beqz t1, .LBB1_28
+; RV32-NEXT: beqz t0, .LBB1_28
; RV32-NEXT: .LBB1_26: # %udiv-do-while
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32-NEXT: srli t1, s2, 31
-; RV32-NEXT: slli s3, t3, 1
-; RV32-NEXT: or t1, s3, t1
+; RV32-NEXT: srli t0, s2, 31
+; RV32-NEXT: slli s3, t4, 1
+; RV32-NEXT: or t0, s3, t0
; RV32-NEXT: slli s2, s2, 1
; RV32-NEXT: andi s1, s1, 1
; RV32-NEXT: or s2, s2, s1
-; RV32-NEXT: bne a1, t1, .LBB1_24
+; RV32-NEXT: bne a4, t0, .LBB1_24
; RV32-NEXT: # %bb.27: # in Loop: Header=BB1_26 Depth=1
-; RV32-NEXT: sltu s1, a5, s2
+; RV32-NEXT: sltu s1, a6, s2
; RV32-NEXT: j .LBB1_25
; RV32-NEXT: .LBB1_28: # %udiv-loop-exit
; RV32-NEXT: srli a1, t2, 31
-; RV32-NEXT: slli a2, t0, 1
-; RV32-NEXT: slli a3, t2, 1
-; RV32-NEXT: or t2, a2, a1
-; RV32-NEXT: srli a6, t0, 31
-; RV32-NEXT: or t5, t5, a3
+; RV32-NEXT: slli a2, a7, 1
+; RV32-NEXT: slli t2, t2, 1
+; RV32-NEXT: or t3, a2, a1
+; RV32-NEXT: srli a1, a7, 31
+; RV32-NEXT: or t5, t5, t2
; RV32-NEXT: .LBB1_29: # %udiv-end
; RV32-NEXT: sw t5, 0(a0)
-; RV32-NEXT: sw t2, 4(a0)
-; RV32-NEXT: sb a6, 8(a0)
+; RV32-NEXT: sw t3, 4(a0)
+; RV32-NEXT: sb a1, 8(a0)
; RV32-NEXT: lw s0, 92(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 88(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s2, 84(sp) # 4-byte Folded Reload
@@ -761,33 +761,33 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: sub t2, s0, t2
; RV32-NEXT: or s0, t6, t3
; RV32-NEXT: or a0, a0, t5
-; RV32-NEXT: sub t5, t4, t1
+; RV32-NEXT: sub t4, t4, t1
; RV32-NEXT: beqz s0, .LBB2_20
; RV32-NEXT: # %bb.19: # %_udiv-special-cases
; RV32-NEXT: snez t1, s0
; RV32-NEXT: j .LBB2_21
; RV32-NEXT: .LBB2_20:
-; RV32-NEXT: sltiu t1, t5, 128
-; RV32-NEXT: snez t4, t2
+; RV32-NEXT: sltiu t1, t4, 128
+; RV32-NEXT: snez t5, t2
; RV32-NEXT: xori t1, t1, 1
-; RV32-NEXT: or t1, t1, t4
+; RV32-NEXT: or t1, t1, t5
; RV32-NEXT: .LBB2_21: # %_udiv-special-cases
-; RV32-NEXT: or s1, a0, t1
-; RV32-NEXT: addi a0, s1, -1
-; RV32-NEXT: and s0, a0, a7
-; RV32-NEXT: and t4, a0, a1
-; RV32-NEXT: and t1, a0, a6
-; RV32-NEXT: and a0, a0, t0
-; RV32-NEXT: bnez s1, .LBB2_32
+; RV32-NEXT: or a0, a0, t1
+; RV32-NEXT: addi s1, a0, -1
+; RV32-NEXT: and s0, s1, a7
+; RV32-NEXT: and t5, s1, a1
+; RV32-NEXT: and t1, s1, a6
+; RV32-NEXT: and s1, s1, t0
+; RV32-NEXT: bnez a0, .LBB2_32
; RV32-NEXT: # %bb.22: # %_udiv-special-cases
-; RV32-NEXT: xori s1, t5, 127
-; RV32-NEXT: or s1, s1, t6
+; RV32-NEXT: xori a0, t4, 127
+; RV32-NEXT: or a0, a0, t6
; RV32-NEXT: or s2, t2, t3
-; RV32-NEXT: or s1, s1, s2
-; RV32-NEXT: beqz s1, .LBB2_32
+; RV32-NEXT: or a0, a0, s2
+; RV32-NEXT: beqz a0, .LBB2_32
; RV32-NEXT: # %bb.23: # %udiv-bb1
; RV32-NEXT: sw a3, 8(sp) # 4-byte Folded Spill
-; RV32-NEXT: addi t1, t5, 1
+; RV32-NEXT: addi t1, t4, 1
; RV32-NEXT: seqz a0, t1
; RV32-NEXT: add t2, t2, a0
; RV32-NEXT: sw zero, 56(sp)
@@ -796,11 +796,11 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: sw zero, 68(sp)
; RV32-NEXT: or a0, t1, t2
; RV32-NEXT: li a3, 127
-; RV32-NEXT: seqz t4, a0
-; RV32-NEXT: sub a0, a3, t5
-; RV32-NEXT: add t4, t6, t4
+; RV32-NEXT: seqz t5, a0
+; RV32-NEXT: sub a0, a3, t4
+; RV32-NEXT: add t5, t6, t5
; RV32-NEXT: srli a3, a0, 3
-; RV32-NEXT: sltu a4, t4, t6
+; RV32-NEXT: sltu a4, t5, t6
; RV32-NEXT: andi a3, a3, 12
; RV32-NEXT: add t3, t3, a4
; RV32-NEXT: addi a4, sp, 72
@@ -814,24 +814,24 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: lw a3, 8(a4)
; RV32-NEXT: lw s1, 0(a4)
; RV32-NEXT: lw a4, 12(a4)
-; RV32-NEXT: or s2, t1, t4
+; RV32-NEXT: or s2, t1, t5
; RV32-NEXT: andi a0, a0, 31
; RV32-NEXT: or s3, s2, t6
; RV32-NEXT: xori a0, a0, 31
; RV32-NEXT: srli t6, a3, 1
-; RV32-NEXT: not t5, t5
+; RV32-NEXT: not t4, t4
; RV32-NEXT: srl t6, t6, a0
-; RV32-NEXT: sll a4, a4, t5
+; RV32-NEXT: sll a4, a4, t4
; RV32-NEXT: or t6, a4, t6
; RV32-NEXT: srli a4, s0, 1
; RV32-NEXT: srl a4, a4, a0
-; RV32-NEXT: sll a3, a3, t5
+; RV32-NEXT: sll a3, a3, t4
; RV32-NEXT: or a3, a3, a4
; RV32-NEXT: srli a4, s1, 1
; RV32-NEXT: srl a0, a4, a0
-; RV32-NEXT: sll a4, s0, t5
+; RV32-NEXT: sll a4, s0, t4
; RV32-NEXT: or s2, a4, a0
-; RV32-NEXT: sll t5, s1, t5
+; RV32-NEXT: sll t4, s1, t4
; RV32-NEXT: li a0, 0
; RV32-NEXT: beqz s3, .LBB2_31
; RV32-NEXT: # %bb.24: # %udiv-preheader
@@ -891,11 +891,11 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: slli a3, a3, 1
; RV32-NEXT: or t6, t6, s0
; RV32-NEXT: or a3, a3, a4
-; RV32-NEXT: srli a4, t5, 31
+; RV32-NEXT: srli a4, t4, 31
; RV32-NEXT: slli s2, s2, 1
; RV32-NEXT: or a4, s2, a4
-; RV32-NEXT: slli t5, t5, 1
-; RV32-NEXT: or t5, a0, t5
+; RV32-NEXT: slli t4, t4, 1
+; RV32-NEXT: or t4, a0, t4
; RV32-NEXT: or s2, s3, a4
; RV32-NEXT: or a3, s4, a3
; RV32-NEXT: or t6, s5, t6
@@ -914,13 +914,13 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: sub s8, a4, t0
; RV32-NEXT: seqz a4, s0
; RV32-NEXT: seqz t0, t1
-; RV32-NEXT: sltu s0, t4, a4
-; RV32-NEXT: sub t4, t4, a4
+; RV32-NEXT: sltu s0, t5, a4
+; RV32-NEXT: sub t5, t5, a4
; RV32-NEXT: sub t2, t2, t0
; RV32-NEXT: sub t3, t3, s0
; RV32-NEXT: addi t1, t1, -1
; RV32-NEXT: or a4, t2, t3
-; RV32-NEXT: or t0, t1, t4
+; RV32-NEXT: or t0, t1, t5
; RV32-NEXT: sub s9, s9, s11
; RV32-NEXT: or a4, t0, a4
; RV32-NEXT: li s3, 0
@@ -972,22 +972,22 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: sltu s8, s10, ra
; RV32-NEXT: j .LBB2_25
; RV32-NEXT: .LBB2_31: # %udiv-loop-exit
-; RV32-NEXT: srli a1, t5, 31
+; RV32-NEXT: srli a1, t4, 31
; RV32-NEXT: slli a2, s2, 1
; RV32-NEXT: srli a4, s2, 31
; RV32-NEXT: or t1, a2, a1
; RV32-NEXT: slli a1, a3, 1
-; RV32-NEXT: or t4, a1, a4
+; RV32-NEXT: or t5, a1, a4
; RV32-NEXT: srli s0, a3, 31
; RV32-NEXT: slli t6, t6, 1
-; RV32-NEXT: slli t5, t5, 1
+; RV32-NEXT: slli t4, t4, 1
; RV32-NEXT: or s0, t6, s0
-; RV32-NEXT: or a0, a0, t5
+; RV32-NEXT: or s1, a0, t4
; RV32-NEXT: lw a3, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: .LBB2_32: # %udiv-end
-; RV32-NEXT: sw a0, 0(a3)
+; RV32-NEXT: sw s1, 0(a3)
; RV32-NEXT: sw t1, 4(a3)
-; RV32-NEXT: sw t4, 8(a3)
+; RV32-NEXT: sw t5, 8(a3)
; RV32-NEXT: sw s0, 12(a3)
; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
@@ -1042,17 +1042,17 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: lw t2, 16(a2)
; RV32-NEXT: lw a6, 0(a2)
; RV32-NEXT: lw a2, 12(a2)
-; RV32-NEXT: sw a2, 20(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a2, 24(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a4, 32(sp) # 4-byte Folded Spill
; RV32-NEXT: slli a2, a4, 31
; RV32-NEXT: srli a4, a5, 1
; RV32-NEXT: addi t5, a0, 1365
; RV32-NEXT: or a0, a4, a2
; RV32-NEXT: addi t4, a3, 819
; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: sw a5, 16(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a5, 20(sp) # 4-byte Folded Spill
; RV32-NEXT: slli a3, a5, 31
-; RV32-NEXT: sw a6, 24(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a6, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: srli a4, a6, 1
; RV32-NEXT: addi t3, a2, -241
; RV32-NEXT: or a6, a4, a3
@@ -1114,13 +1114,13 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: add a2, a2, a3
; RV32-NEXT: srli t0, a2, 24
; RV32-NEXT: .LBB3_3: # %_udiv-special-cases
-; RV32-NEXT: lw a5, 20(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a5, 24(sp) # 4-byte Folded Reload
; RV32-NEXT: srli a2, a5, 1
; RV32-NEXT: slli a4, t2, 31
; RV32-NEXT: slli a5, a5, 31
-; RV32-NEXT: lw a3, 24(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a3, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: slli a3, a3, 31
-; RV32-NEXT: lw a7, 28(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a7, 32(sp) # 4-byte Folded Reload
; RV32-NEXT: srli a7, a7, 1
; RV32-NEXT: li s1, 64
; RV32-NEXT: bnez a3, .LBB3_5
@@ -1426,28 +1426,28 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: .LBB3_28: # %_udiv-special-cases
; RV32-NEXT: andi s11, a1, 1
; RV32-NEXT: andi s4, t2, 1
-; RV32-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s1, 24(sp) # 4-byte Folded Reload
-; RV32-NEXT: or s1, s1, a1
+; RV32-NEXT: lw a1, 32(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a5, 28(sp) # 4-byte Folded Reload
+; RV32-NEXT: or a5, a5, a1
; RV32-NEXT: or a1, a7, a6
; RV32-NEXT: bnez s5, .LBB3_30
; RV32-NEXT: # %bb.29: # %_udiv-special-cases
; RV32-NEXT: mv a4, a3
; RV32-NEXT: .LBB3_30: # %_udiv-special-cases
-; RV32-NEXT: lw a2, 16(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a3, 20(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 20(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a3, 24(sp) # 4-byte Folded Reload
; RV32-NEXT: or s6, a2, a3
-; RV32-NEXT: or a5, s1, s4
+; RV32-NEXT: or t2, a5, s4
; RV32-NEXT: or a2, t0, t1
; RV32-NEXT: or a3, a1, s11
; RV32-NEXT: bnez s3, .LBB3_32
; RV32-NEXT: # %bb.31: # %_udiv-special-cases
; RV32-NEXT: mv a4, s2
; RV32-NEXT: .LBB3_32: # %_udiv-special-cases
-; RV32-NEXT: or a1, a5, s6
-; RV32-NEXT: sltu a5, s0, a4
+; RV32-NEXT: or a1, t2, s6
+; RV32-NEXT: sltu t2, s0, a4
; RV32-NEXT: or a2, a3, a2
-; RV32-NEXT: mv t4, a5
+; RV32-NEXT: mv t4, t2
; RV32-NEXT: beq t6, a0, .LBB3_34
; RV32-NEXT: # %bb.33: # %_udiv-special-cases
; RV32-NEXT: sltu t4, t6, a0
@@ -1455,44 +1455,44 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: seqz a1, a1
; RV32-NEXT: seqz a2, a2
; RV32-NEXT: sub a0, t6, a0
-; RV32-NEXT: snez t2, t4
+; RV32-NEXT: snez t3, t4
; RV32-NEXT: neg a3, t4
-; RV32-NEXT: neg t3, t2
-; RV32-NEXT: sub t2, a0, a5
-; RV32-NEXT: or a5, a3, t3
+; RV32-NEXT: neg t3, t3
+; RV32-NEXT: sub t2, a0, t2
+; RV32-NEXT: or t6, a3, t3
; RV32-NEXT: andi t5, t4, 1
; RV32-NEXT: sub a0, s0, a4
-; RV32-NEXT: beqz a5, .LBB3_36
+; RV32-NEXT: beqz t6, .LBB3_36
; RV32-NEXT: # %bb.35: # %_udiv-special-cases
-; RV32-NEXT: snez a4, a5
+; RV32-NEXT: snez a4, t6
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: bnez t5, .LBB3_37
; RV32-NEXT: j .LBB3_38
; RV32-NEXT: .LBB3_36:
; RV32-NEXT: sltiu a4, a0, 129
-; RV32-NEXT: snez a5, t2
+; RV32-NEXT: snez t4, t2
; RV32-NEXT: xori a4, a4, 1
-; RV32-NEXT: or a4, a4, a5
+; RV32-NEXT: or a4, a4, t4
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: beqz t5, .LBB3_38
; RV32-NEXT: .LBB3_37: # %_udiv-special-cases
; RV32-NEXT: mv a4, t5
; RV32-NEXT: .LBB3_38: # %_udiv-special-cases
-; RV32-NEXT: or t6, a1, a4
-; RV32-NEXT: addi t4, t6, -1
-; RV32-NEXT: and a5, s11, t4
-; RV32-NEXT: and a4, t4, t1
-; RV32-NEXT: and a1, t4, a6
-; RV32-NEXT: and a2, t4, t0
-; RV32-NEXT: and t4, t4, a7
-; RV32-NEXT: bnez t6, .LBB3_55
+; RV32-NEXT: or s0, a1, a4
+; RV32-NEXT: addi a2, s0, -1
+; RV32-NEXT: and t6, s11, a2
+; RV32-NEXT: and t4, a2, t1
+; RV32-NEXT: and a1, a2, a6
+; RV32-NEXT: and a4, a2, t0
+; RV32-NEXT: and a2, a2, a7
+; RV32-NEXT: bnez s0, .LBB3_55
; RV32-NEXT: # %bb.39: # %_udiv-special-cases
-; RV32-NEXT: xori t6, a0, 128
-; RV32-NEXT: or s0, t5, a3
+; RV32-NEXT: xori s0, a0, 128
+; RV32-NEXT: or s1, t5, a3
; RV32-NEXT: or s2, t2, t3
-; RV32-NEXT: or t6, t6, s0
-; RV32-NEXT: or t6, t6, s2
-; RV32-NEXT: beqz t6, .LBB3_55
+; RV32-NEXT: or s0, s0, s1
+; RV32-NEXT: or s0, s0, s2
+; RV32-NEXT: beqz s0, .LBB3_55
; RV32-NEXT: # %bb.40: # %udiv-bb1
; RV32-NEXT: sw s4, 36(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s7, 0(sp) # 4-byte Folded Spill
@@ -1515,7 +1515,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: or a2, a1, t4
; RV32-NEXT: or a3, t2, t3
; RV32-NEXT: li a4, 128
-; RV32-NEXT: or a5, a2, a3
+; RV32-NEXT: or t6, a2, a3
; RV32-NEXT: sub a3, a4, a0
; RV32-NEXT: sw a7, 136(sp)
; RV32-NEXT: sw t0, 140(sp)
@@ -1526,11 +1526,11 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: addi a4, sp, 136
; RV32-NEXT: sw s11, 152(sp)
; RV32-NEXT: sub a4, a4, a2
-; RV32-NEXT: lw t6, 4(a4)
+; RV32-NEXT: lw s1, 4(a4)
; RV32-NEXT: lw s0, 8(a4)
; RV32-NEXT: lw s4, 0(a4)
; RV32-NEXT: lw a2, 12(a4)
-; RV32-NEXT: seqz s2, a5
+; RV32-NEXT: seqz s2, t6
; RV32-NEXT: andi a3, a3, 31
; RV32-NEXT: add s2, t5, s2
; RV32-NEXT: xori a3, a3, 31
@@ -1539,18 +1539,18 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: srl t5, t5, a3
; RV32-NEXT: sll s3, a2, a0
; RV32-NEXT: or t5, s3, t5
-; RV32-NEXT: srli s3, t6, 1
+; RV32-NEXT: srli s3, s1, 1
; RV32-NEXT: srl s3, s3, a3
; RV32-NEXT: sll s0, s0, a0
; RV32-NEXT: or s0, s0, s3
; RV32-NEXT: srli s5, s4, 1
; RV32-NEXT: andi s3, s2, 1
; RV32-NEXT: srl s2, s5, a3
-; RV32-NEXT: sll t6, t6, a0
-; RV32-NEXT: or a5, a5, s3
-; RV32-NEXT: or s2, t6, s2
+; RV32-NEXT: sll s1, s1, a0
+; RV32-NEXT: or s5, t6, s3
+; RV32-NEXT: or s2, s1, s2
; RV32-NEXT: sll t6, s4, a0
-; RV32-NEXT: beqz a5, .LBB3_53
+; RV32-NEXT: beqz s5, .LBB3_53
; RV32-NEXT: # %bb.41: # %udiv-preheader
; RV32-NEXT: li s7, 0
; RV32-NEXT: li s8, 0
@@ -1579,61 +1579,62 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sw t1, 52(sp)
; RV32-NEXT: add a2, a4, a2
; RV32-NEXT: lw a4, 16(a2)
-; RV32-NEXT: lw a5, 4(a2)
-; RV32-NEXT: lw a6, 8(a2)
-; RV32-NEXT: lw a7, 12(a2)
+; RV32-NEXT: lw a6, 4(a2)
+; RV32-NEXT: lw a7, 8(a2)
+; RV32-NEXT: lw t0, 12(a2)
; RV32-NEXT: lw a2, 0(a2)
; RV32-NEXT: srl a3, s5, a3
; RV32-NEXT: sll a0, ra, a0
-; RV32-NEXT: andi t0, a1, 31
+; RV32-NEXT: andi t1, a1, 31
; RV32-NEXT: slli a4, a4, 1
-; RV32-NEXT: xori t0, t0, 31
-; RV32-NEXT: srl t1, a7, a1
-; RV32-NEXT: sll a4, a4, t0
+; RV32-NEXT: xori t1, t1, 31
+; RV32-NEXT: srl s1, t0, a1
+; RV32-NEXT: sll a4, a4, t1
; RV32-NEXT: or a3, a0, a3
-; RV32-NEXT: or s11, t1, a4
-; RV32-NEXT: srl a0, a6, a1
+; RV32-NEXT: or s11, s1, a4
+; RV32-NEXT: li s1, 0
+; RV32-NEXT: srl a0, a7, a1
+; RV32-NEXT: slli t0, t0, 1
+; RV32-NEXT: sll a4, t0, t1
; RV32-NEXT: slli a7, a7, 1
-; RV32-NEXT: sll a4, a7, t0
-; RV32-NEXT: slli a6, a6, 1
-; RV32-NEXT: srl a7, a5, a1
-; RV32-NEXT: sll a6, a6, t0
+; RV32-NEXT: srl t0, a6, a1
+; RV32-NEXT: sll a7, a7, t1
; RV32-NEXT: or a0, a0, a4
-; RV32-NEXT: or s5, a7, a6
+; RV32-NEXT: or s5, t0, a7
; RV32-NEXT: andi ra, a3, 1
-; RV32-NEXT: or a3, s1, s6
-; RV32-NEXT: li s1, 0
+; RV32-NEXT: or a3, a5, s6
; RV32-NEXT: srl a2, a2, a1
; RV32-NEXT: snez a3, a3
-; RV32-NEXT: slli a5, a5, 1
+; RV32-NEXT: slli a6, a6, 1
; RV32-NEXT: lw a4, 36(sp) # 4-byte Folded Reload
; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: sll a4, a5, t0
+; RV32-NEXT: sll a4, a6, t1
; RV32-NEXT: not a3, a3
; RV32-NEXT: or s6, a2, a4
; RV32-NEXT: andi a3, a3, 1
-; RV32-NEXT: sw a3, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: lw a5, 24(sp) # 4-byte Folded Reload
+; RV32-NEXT: sw a3, 16(sp) # 4-byte Folded Spill
+; RV32-NEXT: lw a5, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: seqz a2, a5
-; RV32-NEXT: lw a4, 16(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a4, 20(sp) # 4-byte Folded Reload
; RV32-NEXT: or a3, a5, a4
; RV32-NEXT: sub a6, a4, a2
; RV32-NEXT: seqz a2, a3
-; RV32-NEXT: lw a3, 28(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a3, 32(sp) # 4-byte Folded Reload
; RV32-NEXT: sub a4, a3, a2
-; RV32-NEXT: sw a4, 32(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a4, 36(sp) # 4-byte Folded Spill
; RV32-NEXT: sltu a2, a3, a2
-; RV32-NEXT: lw a3, 20(sp) # 4-byte Folded Reload
-; RV32-NEXT: sub s4, a3, a2
+; RV32-NEXT: lw a3, 24(sp) # 4-byte Folded Reload
+; RV32-NEXT: sub a7, a3, a2
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: sw a5, 4(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw a6, 8(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a6, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: mv t1, t5
+; RV32-NEXT: sw a7, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: j .LBB3_43
; RV32-NEXT: .LBB3_42: # %udiv-do-while
; RV32-NEXT: # in Loop: Header=BB3_43 Depth=1
; RV32-NEXT: mv s8, s7
-; RV32-NEXT: lw a7, 28(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a7, 32(sp) # 4-byte Folded Reload
; RV32-NEXT: and a7, s1, a7
; RV32-NEXT: xor ra, a3, s11
; RV32-NEXT: xor t0, a0, a7
@@ -1665,20 +1666,19 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sub a3, a3, t0
; RV32-NEXT: sub s11, a3, a5
; RV32-NEXT: sub a2, s5, a2
-; RV32-NEXT: lw a7, 36(sp) # 4-byte Folded Reload
-; RV32-NEXT: or a3, a1, a7
+; RV32-NEXT: or a3, a1, t4
; RV32-NEXT: or a5, t2, t3
; RV32-NEXT: sub s5, a2, a6
; RV32-NEXT: or a3, a3, a5
; RV32-NEXT: sub s6, s6, a4
; RV32-NEXT: snez a2, a3
-; RV32-NEXT: add a2, t4, a2
+; RV32-NEXT: add a2, s4, a2
; RV32-NEXT: or a3, a1, t2
; RV32-NEXT: not a2, a2
; RV32-NEXT: seqz a3, a3
; RV32-NEXT: seqz a4, a1
-; RV32-NEXT: sltu a5, a7, a3
-; RV32-NEXT: sub t4, a7, a3
+; RV32-NEXT: sltu a5, t4, a3
+; RV32-NEXT: sub t4, t4, a3
; RV32-NEXT: sub t2, t2, a4
; RV32-NEXT: sub t3, t3, a5
; RV32-NEXT: addi a1, a1, -1
@@ -1691,7 +1691,8 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: li s8, 0
; RV32-NEXT: li s9, 0
; RV32-NEXT: li s10, 0
-; RV32-NEXT: lw a6, 8(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a6, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a7, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: beqz a2, .LBB3_54
; RV32-NEXT: .LBB3_43: # %udiv-do-while
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1701,24 +1702,23 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: srli a2, s5, 31
; RV32-NEXT: slli a0, a0, 1
; RV32-NEXT: or a0, a0, a2
-; RV32-NEXT: beq s4, a3, .LBB3_45
+; RV32-NEXT: beq a7, a3, .LBB3_45
; RV32-NEXT: # %bb.44: # %udiv-do-while
; RV32-NEXT: # in Loop: Header=BB3_43 Depth=1
-; RV32-NEXT: sltu a2, s4, a3
+; RV32-NEXT: sltu a2, a7, a3
; RV32-NEXT: j .LBB3_46
; RV32-NEXT: .LBB3_45: # in Loop: Header=BB3_43 Depth=1
-; RV32-NEXT: lw a2, 32(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
; RV32-NEXT: sltu a2, a2, a0
; RV32-NEXT: .LBB3_46: # %udiv-do-while
; RV32-NEXT: # in Loop: Header=BB3_43 Depth=1
-; RV32-NEXT: sw t4, 36(sp) # 4-byte Folded Spill
; RV32-NEXT: srli a4, s6, 31
; RV32-NEXT: slli s5, s5, 1
; RV32-NEXT: or s5, s5, a4
; RV32-NEXT: slli s6, s6, 1
; RV32-NEXT: andi a4, ra, 1
; RV32-NEXT: or s6, s6, a4
-; RV32-NEXT: mv t4, s3
+; RV32-NEXT: mv s4, s3
; RV32-NEXT: beq a6, s5, .LBB3_48
; RV32-NEXT: # %bb.47: # %udiv-do-while
; RV32-NEXT: # in Loop: Header=BB3_43 Depth=1
@@ -1731,9 +1731,9 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: # in Loop: Header=BB3_43 Depth=1
; RV32-NEXT: mv s3, s10
; RV32-NEXT: mv t5, s1
-; RV32-NEXT: lw a5, 32(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a5, 36(sp) # 4-byte Folded Reload
; RV32-NEXT: xor a5, a5, a0
-; RV32-NEXT: xor a6, s4, a3
+; RV32-NEXT: xor a6, a7, a3
; RV32-NEXT: or a5, a5, a6
; RV32-NEXT: beqz a5, .LBB3_51
; RV32-NEXT: # %bb.50: # %udiv-do-while
@@ -1743,17 +1743,17 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: # in Loop: Header=BB3_43 Depth=1
; RV32-NEXT: mv s10, s9
; RV32-NEXT: srli a2, s11, 31
-; RV32-NEXT: lw a5, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a5, 16(sp) # 4-byte Folded Reload
; RV32-NEXT: sub a2, a5, a2
; RV32-NEXT: sub a2, a2, a4
; RV32-NEXT: slli a2, a2, 31
; RV32-NEXT: srai s1, a2, 31
-; RV32-NEXT: lw a2, 20(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 24(sp) # 4-byte Folded Reload
; RV32-NEXT: and s11, s1, a2
; RV32-NEXT: mv s9, s8
-; RV32-NEXT: lw a4, 24(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: and a4, s1, a4
-; RV32-NEXT: lw a2, 16(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a2, 20(sp) # 4-byte Folded Reload
; RV32-NEXT: and a2, s1, a2
; RV32-NEXT: sltu a6, s6, a4
; RV32-NEXT: mv a5, a6
@@ -1767,24 +1767,24 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: mv t1, t5
; RV32-NEXT: .LBB3_54: # %udiv-loop-exit
; RV32-NEXT: srli a0, t6, 31
-; RV32-NEXT: slli a2, s2, 1
+; RV32-NEXT: slli a4, s2, 1
; RV32-NEXT: srli a1, s2, 31
-; RV32-NEXT: slli a3, s0, 1
-; RV32-NEXT: or a2, a2, a0
-; RV32-NEXT: or a1, a3, a1
+; RV32-NEXT: slli a2, s0, 1
+; RV32-NEXT: or a4, a4, a0
+; RV32-NEXT: or a1, a2, a1
; RV32-NEXT: srli s0, s0, 31
-; RV32-NEXT: slli a4, t1, 1
-; RV32-NEXT: or a4, a4, s0
-; RV32-NEXT: slli t6, t6, 1
-; RV32-NEXT: srli a5, t1, 31
-; RV32-NEXT: or t4, s1, t6
+; RV32-NEXT: slli a0, t1, 1
+; RV32-NEXT: or t4, a0, s0
+; RV32-NEXT: slli a0, t6, 1
+; RV32-NEXT: srli t6, t1, 31
+; RV32-NEXT: or a2, s1, a0
; RV32-NEXT: lw s7, 0(sp) # 4-byte Folded Reload
; RV32-NEXT: .LBB3_55: # %udiv-end
-; RV32-NEXT: sw t4, 0(s7)
-; RV32-NEXT: sw a2, 4(s7)
+; RV32-NEXT: sw a2, 0(s7)
+; RV32-NEXT: sw a4, 4(s7)
; RV32-NEXT: sw a1, 8(s7)
-; RV32-NEXT: sw a4, 12(s7)
-; RV32-NEXT: sb a5, 16(s7)
+; RV32-NEXT: sw t4, 12(s7)
+; RV32-NEXT: sb t6, 16(s7)
; RV32-NEXT: lw ra, 220(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 216(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 212(sp) # 4-byte Folded Reload
@@ -2082,16 +2082,16 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV64-NEXT: or t5, t0, a7
; RV64-NEXT: andi t4, t4, 1
; RV64-NEXT: sub a6, a6, t6
-; RV64-NEXT: sub a7, a6, s0
-; RV64-NEXT: sub t0, t2, s2
+; RV64-NEXT: sub t0, a6, s0
+; RV64-NEXT: sub a7, t2, s2
; RV64-NEXT: beqz t4, .LBB3_19
; RV64-NEXT: # %bb.18: # %_udiv-special-cases
; RV64-NEXT: mv a6, t4
; RV64-NEXT: j .LBB3_20
; RV64-NEXT: .LBB3_19:
-; RV64-NEXT: sltiu a6, t0, 129
+; RV64-NEXT: sltiu a6, a7, 129
; RV64-NEXT: xori a6, a6, 1
-; RV64-NEXT: snez t2, a7
+; RV64-NEXT: snez t2, t0
; RV64-NEXT: or a6, a6, t2
; RV64-NEXT: .LBB3_20: # %_udiv-special-cases
; RV64-NEXT: or t6, t5, a6
@@ -2101,16 +2101,16 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV64-NEXT: and t5, t5, a5
; RV64-NEXT: bnez t6, .LBB3_29
; RV64-NEXT: # %bb.21: # %_udiv-special-cases
-; RV64-NEXT: xori t6, t0, 128
-; RV64-NEXT: or s0, t4, a7
+; RV64-NEXT: xori t6, a7, 128
+; RV64-NEXT: or s0, t4, t0
; RV64-NEXT: or t6, t6, s0
; RV64-NEXT: beqz t6, .LBB3_29
; RV64-NEXT: # %bb.22: # %udiv-bb1
-; RV64-NEXT: addi a6, t0, 1
+; RV64-NEXT: addi a6, a7, 1
; RV64-NEXT: li t2, 128
; RV64-NEXT: seqz t5, a6
-; RV64-NEXT: sub t2, t2, t0
-; RV64-NEXT: add a7, a7, t5
+; RV64-NEXT: sub t2, t2, a7
+; RV64-NEXT: add t0, t0, t5
; RV64-NEXT: sd zero, 64(sp)
; RV64-NEXT: sd zero, 72(sp)
; RV64-NEXT: sd zero, 80(sp)
@@ -2122,7 +2122,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV64-NEXT: sd a4, 104(sp)
; RV64-NEXT: sd t3, 112(sp)
; RV64-NEXT: sub s4, t6, t5
-; RV64-NEXT: or t5, a6, a7
+; RV64-NEXT: or t5, a6, t0
; RV64-NEXT: ld t6, 0(s4)
; RV64-NEXT: seqz s0, t5
; RV64-NEXT: add t4, t4, s0
@@ -2132,10 +2132,10 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV64-NEXT: xori s1, t2, 63
; RV64-NEXT: srli t2, t6, 1
; RV64-NEXT: srl t2, t2, s1
-; RV64-NEXT: neg s3, t0
-; RV64-NEXT: sll t0, s2, s3
+; RV64-NEXT: neg s3, a7
+; RV64-NEXT: sll a7, s2, s3
; RV64-NEXT: or t5, t5, t4
-; RV64-NEXT: or t0, t0, t2
+; RV64-NEXT: or a7, a7, t2
; RV64-NEXT: sll t2, t6, s3
; RV64-NEXT: beqz t5, .LBB3_28
; RV64-NEXT: # %bb.23: # %udiv-preheader
@@ -2193,12 +2193,12 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV64-NEXT: srai t3, t3, 63
; RV64-NEXT: and s3, t3, a3
; RV64-NEXT: srli s1, t2, 63
-; RV64-NEXT: slli s4, t0, 1
+; RV64-NEXT: slli s4, a7, 1
; RV64-NEXT: slli t2, t2, 1
; RV64-NEXT: or s1, s4, s1
-; RV64-NEXT: srli s4, t0, 63
+; RV64-NEXT: srli s4, a7, 63
; RV64-NEXT: or t2, t5, t2
-; RV64-NEXT: or t0, t6, s1
+; RV64-NEXT: or a7, t6, s1
; RV64-NEXT: or s1, s0, s4
; RV64-NEXT: andi s1, s1, 1
; RV64-NEXT: and t6, t3, a2
@@ -2207,15 +2207,15 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV64-NEXT: andi t5, t3, 1
; RV64-NEXT: sub t3, t1, s0
; RV64-NEXT: sub s2, s2, t6
-; RV64-NEXT: or t1, a6, a7
+; RV64-NEXT: or t1, a6, t0
; RV64-NEXT: seqz t6, a6
; RV64-NEXT: snez t1, t1
-; RV64-NEXT: sub a7, a7, t6
+; RV64-NEXT: sub t0, t0, t6
; RV64-NEXT: add t1, t4, t1
; RV64-NEXT: not t1, t1
; RV64-NEXT: addi a6, a6, -1
; RV64-NEXT: andi t4, t1, 1
-; RV64-NEXT: or t1, a6, a7
+; RV64-NEXT: or t1, a6, t0
; RV64-NEXT: or t1, t1, t4
; RV64-NEXT: li t6, 0
; RV64-NEXT: li s0, 0
@@ -2234,10 +2234,10 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV64-NEXT: j .LBB3_25
; RV64-NEXT: .LBB3_28: # %udiv-loop-exit
; RV64-NEXT: srli a1, t2, 63
-; RV64-NEXT: slli a2, t0, 1
+; RV64-NEXT: slli a2, a7, 1
; RV64-NEXT: slli a3, t2, 1
; RV64-NEXT: or t2, a2, a1
-; RV64-NEXT: srli a6, t0, 63
+; RV64-NEXT: srli a6, a7, 63
; RV64-NEXT: or t5, t5, a3
; RV64-NEXT: .LBB3_29: # %udiv-end
; RV64-NEXT: sd t5, 0(a0)
diff --git a/llvm/test/CodeGen/RISCV/machine-pipeliner.ll b/llvm/test/CodeGen/RISCV/machine-pipeliner.ll
index ce2e6aed75135..35bf14bb0c8f1 100644
--- a/llvm/test/CodeGen/RISCV/machine-pipeliner.ll
+++ b/llvm/test/CodeGen/RISCV/machine-pipeliner.ll
@@ -54,37 +54,37 @@ define void @test_pipelined_1(ptr noalias %in, ptr noalias %out, i32 signext %cn
; CHECK-PIPELINED: # %bb.0: # %entry
; CHECK-PIPELINED-NEXT: blez a2, .LBB1_6
; CHECK-PIPELINED-NEXT: # %bb.1: # %for.body.preheader
+; CHECK-PIPELINED-NEXT: lw a3, 0(a1)
; CHECK-PIPELINED-NEXT: addi a2, a2, -1
-; CHECK-PIPELINED-NEXT: addi a3, a0, 4
; CHECK-PIPELINED-NEXT: addi a5, a1, 4
; CHECK-PIPELINED-NEXT: sh2add.uw a4, a2, a1
-; CHECK-PIPELINED-NEXT: lw a2, 0(a1)
+; CHECK-PIPELINED-NEXT: addi a2, a0, 4
; CHECK-PIPELINED-NEXT: addi a4, a4, 4
; CHECK-PIPELINED-NEXT: beq a5, a4, .LBB1_5
; CHECK-PIPELINED-NEXT: # %bb.2: # %for.body
; CHECK-PIPELINED-NEXT: lw a1, 0(a5)
-; CHECK-PIPELINED-NEXT: addi a6, a3, 4
+; CHECK-PIPELINED-NEXT: addi a6, a2, 4
; CHECK-PIPELINED-NEXT: addi a5, a5, 4
; CHECK-PIPELINED-NEXT: beq a5, a4, .LBB1_4
; CHECK-PIPELINED-NEXT: .LBB1_3: # %for.body
; CHECK-PIPELINED-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-PIPELINED-NEXT: addi a7, a2, 1
-; CHECK-PIPELINED-NEXT: mv a2, a1
+; CHECK-PIPELINED-NEXT: addi a7, a3, 1
+; CHECK-PIPELINED-NEXT: mv a3, a1
; CHECK-PIPELINED-NEXT: lw a1, 0(a5)
; CHECK-PIPELINED-NEXT: sw a7, 0(a0)
-; CHECK-PIPELINED-NEXT: mv a0, a3
-; CHECK-PIPELINED-NEXT: mv a3, a6
+; CHECK-PIPELINED-NEXT: mv a0, a2
+; CHECK-PIPELINED-NEXT: mv a2, a6
; CHECK-PIPELINED-NEXT: addi a6, a6, 4
; CHECK-PIPELINED-NEXT: addi a5, a5, 4
; CHECK-PIPELINED-NEXT: bne a5, a4, .LBB1_3
; CHECK-PIPELINED-NEXT: .LBB1_4:
-; CHECK-PIPELINED-NEXT: addi a2, a2, 1
-; CHECK-PIPELINED-NEXT: sw a2, 0(a0)
-; CHECK-PIPELINED-NEXT: mv a0, a3
-; CHECK-PIPELINED-NEXT: mv a2, a1
+; CHECK-PIPELINED-NEXT: addi a3, a3, 1
+; CHECK-PIPELINED-NEXT: sw a3, 0(a0)
+; CHECK-PIPELINED-NEXT: mv a0, a2
+; CHECK-PIPELINED-NEXT: mv a3, a1
; CHECK-PIPELINED-NEXT: .LBB1_5:
-; CHECK-PIPELINED-NEXT: addi a2, a2, 1
-; CHECK-PIPELINED-NEXT: sw a2, 0(a0)
+; CHECK-PIPELINED-NEXT: addi a3, a3, 1
+; CHECK-PIPELINED-NEXT: sw a3, 0(a0)
; CHECK-PIPELINED-NEXT: .LBB1_6: # %for.end
; CHECK-PIPELINED-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll b/llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
index a2c572e07ff7d..04af3c1c3e7a3 100644
--- a/llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
+++ b/llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
@@ -4,15 +4,19 @@
define signext i32 @mulw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind {
; CHECK-LABEL: mulw:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a2, 1
-; CHECK-NEXT: bge a0, a1, .LBB0_2
-; CHECK-NEXT: .LBB0_1: # %for.body
+; CHECK-NEXT: bge a0, a1, .LBB0_4
+; CHECK-NEXT: # %bb.1: # %for.body.preheader
+; CHECK-NEXT: mv a2, a0
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: .LBB0_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: mulw a2, a0, a2
-; CHECK-NEXT: addiw a0, a0, 1
-; CHECK-NEXT: blt a0, a1, .LBB0_1
-; CHECK-NEXT: .LBB0_2: # %for.cond.cleanup
-; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mulw a0, a2, a0
+; CHECK-NEXT: addiw a2, a2, 1
+; CHECK-NEXT: blt a2, a1, .LBB0_2
+; CHECK-NEXT: # %bb.3: # %for.cond.cleanup
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB0_4:
+; CHECK-NEXT: li a0, 1
; CHECK-NEXT: ret
entry:
%cmp6 = icmp slt i32 %s, %n
diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
index 888a373bd3791..ab07a3996d90b 100644
--- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
@@ -130,13 +130,13 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-LABEL: log2_ceil_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a1, a0, -1
+; RV64I-NEXT: addiw a2, a0, -1
; RV64I-NEXT: li a0, 32
-; RV64I-NEXT: li a2, 32
-; RV64I-NEXT: beqz a1, .LBB2_2
+; RV64I-NEXT: li a1, 32
+; RV64I-NEXT: beqz a2, .LBB2_2
; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: srliw a2, a1, 1
-; RV64I-NEXT: or a1, a1, a2
+; RV64I-NEXT: srliw a1, a2, 1
+; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srliw a2, a1, 2
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: srliw a2, a1, 4
@@ -166,9 +166,9 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a1, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: srliw a2, a1, 24
+; RV64I-NEXT: srliw a1, a1, 24
; RV64I-NEXT: .LBB2_2: # %cond.end
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: log2_ceil_i32:
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index b9a1fee5f0946..ea817c215bc6e 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -113,13 +113,13 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-LABEL: log2_ceil_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a1, a0, -1
+; RV64I-NEXT: addiw a2, a0, -1
; RV64I-NEXT: li a0, 32
-; RV64I-NEXT: li a2, 32
-; RV64I-NEXT: beqz a1, .LBB2_2
+; RV64I-NEXT: li a1, 32
+; RV64I-NEXT: beqz a2, .LBB2_2
; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: srliw a2, a1, 1
-; RV64I-NEXT: or a1, a1, a2
+; RV64I-NEXT: srliw a1, a2, 1
+; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srliw a2, a1, 2
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: srliw a2, a1, 4
@@ -149,9 +149,9 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a1, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: srliw a2, a1, 24
+; RV64I-NEXT: srliw a1, a1, 24
; RV64I-NEXT: .LBB2_2: # %cond.end
-; RV64I-NEXT: sub a0, a0, a2
+; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: log2_ceil_i32:
diff --git a/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
index e5e677d5a8e8d..7426ea6cd75d5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
@@ -438,19 +438,19 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
;
; SINK-LABEL: sink_splat_fadd_scalable:
; SINK: # %bb.0: # %entry
-; SINK-NEXT: li a2, 1024
-; SINK-NEXT: csrr a1, vlenb
-; SINK-NEXT: srli a3, a1, 2
-; SINK-NEXT: bgeu a2, a3, .LBB4_2
+; SINK-NEXT: li a1, 1024
+; SINK-NEXT: csrr a2, vlenb
+; SINK-NEXT: srli a3, a2, 2
+; SINK-NEXT: bgeu a1, a3, .LBB4_2
; SINK-NEXT: # %bb.1:
-; SINK-NEXT: li a2, 0
+; SINK-NEXT: li a1, 0
; SINK-NEXT: j .LBB4_5
; SINK-NEXT: .LBB4_2: # %vector.ph
-; SINK-NEXT: addi a2, a3, -1
-; SINK-NEXT: andi a4, a2, 1024
-; SINK-NEXT: xori a2, a4, 1024
+; SINK-NEXT: addi a1, a3, -1
+; SINK-NEXT: andi a4, a1, 1024
+; SINK-NEXT: xori a1, a4, 1024
; SINK-NEXT: mv a5, a0
-; SINK-NEXT: mv a6, a2
+; SINK-NEXT: mv a6, a1
; SINK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; SINK-NEXT: .LBB4_3: # %vector.body
; SINK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -458,12 +458,12 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
; SINK-NEXT: vfadd.vf v8, v8, fa0
; SINK-NEXT: sub a6, a6, a3
; SINK-NEXT: vs1r.v v8, (a5)
-; SINK-NEXT: add a5, a5, a1
+; SINK-NEXT: add a5, a5, a2
; SINK-NEXT: bnez a6, .LBB4_3
; SINK-NEXT: # %bb.4: # %middle.block
; SINK-NEXT: beqz a4, .LBB4_7
; SINK-NEXT: .LBB4_5: # %for.body.preheader
-; SINK-NEXT: slli a1, a2, 2
+; SINK-NEXT: slli a1, a1, 2
; SINK-NEXT: lui a2, 1
; SINK-NEXT: add a1, a0, a1
; SINK-NEXT: add a0, a0, a2
@@ -479,19 +479,19 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
;
; DEFAULT-LABEL: sink_splat_fadd_scalable:
; DEFAULT: # %bb.0: # %entry
-; DEFAULT-NEXT: li a2, 1024
-; DEFAULT-NEXT: csrr a1, vlenb
-; DEFAULT-NEXT: srli a3, a1, 2
-; DEFAULT-NEXT: bgeu a2, a3, .LBB4_2
+; DEFAULT-NEXT: li a1, 1024
+; DEFAULT-NEXT: csrr a2, vlenb
+; DEFAULT-NEXT: srli a3, a2, 2
+; DEFAULT-NEXT: bgeu a1, a3, .LBB4_2
; DEFAULT-NEXT: # %bb.1:
-; DEFAULT-NEXT: li a2, 0
+; DEFAULT-NEXT: li a1, 0
; DEFAULT-NEXT: j .LBB4_5
; DEFAULT-NEXT: .LBB4_2: # %vector.ph
-; DEFAULT-NEXT: addi a2, a3, -1
-; DEFAULT-NEXT: andi a4, a2, 1024
-; DEFAULT-NEXT: xori a2, a4, 1024
+; DEFAULT-NEXT: addi a1, a3, -1
+; DEFAULT-NEXT: andi a4, a1, 1024
+; DEFAULT-NEXT: xori a1, a4, 1024
; DEFAULT-NEXT: mv a5, a0
-; DEFAULT-NEXT: mv a6, a2
+; DEFAULT-NEXT: mv a6, a1
; DEFAULT-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; DEFAULT-NEXT: .LBB4_3: # %vector.body
; DEFAULT-NEXT: # =>This Inner Loop Header: Depth=1
@@ -499,12 +499,12 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
; DEFAULT-NEXT: vfadd.vf v8, v8, fa0
; DEFAULT-NEXT: sub a6, a6, a3
; DEFAULT-NEXT: vs1r.v v8, (a5)
-; DEFAULT-NEXT: add a5, a5, a1
+; DEFAULT-NEXT: add a5, a5, a2
; DEFAULT-NEXT: bnez a6, .LBB4_3
; DEFAULT-NEXT: # %bb.4: # %middle.block
; DEFAULT-NEXT: beqz a4, .LBB4_7
; DEFAULT-NEXT: .LBB4_5: # %for.body.preheader
-; DEFAULT-NEXT: slli a1, a2, 2
+; DEFAULT-NEXT: slli a1, a1, 2
; DEFAULT-NEXT: lui a2, 1
; DEFAULT-NEXT: add a1, a0, a1
; DEFAULT-NEXT: add a0, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-convert-from-arbitrary-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-convert-from-arbitrary-fp.ll
index 1e39b4d846831..dedb87e3ddff9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-convert-from-arbitrary-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-convert-from-arbitrary-fp.ll
@@ -172,11 +172,11 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: slli a5, a4, 57
; CHECK-NEXT: andi a3, a4, 3
; CHECK-NEXT: srli a5, a5, 59
-; CHECK-NEXT: snez a2, a3
-; CHECK-NEXT: seqz a1, a5
-; CHECK-NEXT: and a6, a1, a2
+; CHECK-NEXT: snez a1, a3
+; CHECK-NEXT: seqz a2, a5
+; CHECK-NEXT: and a6, a2, a1
; CHECK-NEXT: and a4, a4, a0
-; CHECK-NEXT: li a1, 174
+; CHECK-NEXT: li a2, 174
; CHECK-NEXT: bnez a6, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: addi a6, a5, 112
@@ -186,7 +186,7 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: j .LBB1_3
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: clz a6, a3
-; CHECK-NEXT: sub a7, a1, a6
+; CHECK-NEXT: sub a7, a2, a6
; CHECK-NEXT: not t0, a6
; CHECK-NEXT: slli a7, a7, 23
; CHECK-NEXT: binv t0, a3, t0
@@ -210,8 +210,8 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: # %bb.6:
; CHECK-NEXT: or a6, a4, a3
; CHECK-NEXT: .LBB1_7:
-; CHECK-NEXT: and a5, a5, a2
-; CHECK-NEXT: lui a2, 523264
+; CHECK-NEXT: and a5, a5, a1
+; CHECK-NEXT: lui a1, 523264
; CHECK-NEXT: lui t0, 523264
; CHECK-NEXT: bnez a5, .LBB1_9
; CHECK-NEXT: # %bb.8:
@@ -237,7 +237,7 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: j .LBB1_12
; CHECK-NEXT: .LBB1_11:
; CHECK-NEXT: clz t0, a5
-; CHECK-NEXT: sub t1, a1, t0
+; CHECK-NEXT: sub t1, a2, t0
; CHECK-NEXT: not t2, t0
; CHECK-NEXT: slli t1, t1, 23
; CHECK-NEXT: binv t2, a5, t2
@@ -285,7 +285,7 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: j .LBB1_21
; CHECK-NEXT: .LBB1_20:
; CHECK-NEXT: clz t0, a5
-; CHECK-NEXT: sub t1, a1, t0
+; CHECK-NEXT: sub t1, a2, t0
; CHECK-NEXT: not t2, t0
; CHECK-NEXT: slli t1, t1, 23
; CHECK-NEXT: binv t2, a5, t2
@@ -334,7 +334,7 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: j .LBB1_30
; CHECK-NEXT: .LBB1_29:
; CHECK-NEXT: clz t0, a5
-; CHECK-NEXT: sub t1, a1, t0
+; CHECK-NEXT: sub t1, a2, t0
; CHECK-NEXT: not t2, t0
; CHECK-NEXT: slli t1, t1, 23
; CHECK-NEXT: binv t2, a5, t2
@@ -382,7 +382,7 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: j .LBB1_39
; CHECK-NEXT: .LBB1_38:
; CHECK-NEXT: clz t0, a5
-; CHECK-NEXT: sub t1, a1, t0
+; CHECK-NEXT: sub t1, a2, t0
; CHECK-NEXT: not t2, t0
; CHECK-NEXT: slli t1, t1, 23
; CHECK-NEXT: binv t2, a5, t2
@@ -431,7 +431,7 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: j .LBB1_48
; CHECK-NEXT: .LBB1_47:
; CHECK-NEXT: clz t0, a5
-; CHECK-NEXT: sub t1, a1, t0
+; CHECK-NEXT: sub t1, a2, t0
; CHECK-NEXT: not t2, t0
; CHECK-NEXT: slli t1, t1, 23
; CHECK-NEXT: binv t2, a5, t2
@@ -479,7 +479,7 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: j .LBB1_57
; CHECK-NEXT: .LBB1_56:
; CHECK-NEXT: clz t0, a5
-; CHECK-NEXT: sub t1, a1, t0
+; CHECK-NEXT: sub t1, a2, t0
; CHECK-NEXT: not t2, t0
; CHECK-NEXT: slli t1, t1, 23
; CHECK-NEXT: binv t2, a5, t2
@@ -519,28 +519,28 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: and a0, t0, a0
; CHECK-NEXT: bnez t1, .LBB1_65
; CHECK-NEXT: # %bb.64:
-; CHECK-NEXT: addi a1, a6, 112
+; CHECK-NEXT: addi a2, a6, 112
; CHECK-NEXT: slli a7, a5, 21
-; CHECK-NEXT: slli a1, a1, 23
+; CHECK-NEXT: slli a2, a2, 23
; CHECK-NEXT: or a7, a0, a7
-; CHECK-NEXT: or a7, a7, a1
+; CHECK-NEXT: or a7, a7, a2
; CHECK-NEXT: j .LBB1_66
; CHECK-NEXT: .LBB1_65:
; CHECK-NEXT: clz a7, a5
-; CHECK-NEXT: sub a1, a1, a7
+; CHECK-NEXT: sub a2, a2, a7
; CHECK-NEXT: not t0, a7
-; CHECK-NEXT: slli a1, a1, 23
+; CHECK-NEXT: slli a2, a2, 23
; CHECK-NEXT: binv t0, a5, t0
; CHECK-NEXT: addi a7, a7, -40
-; CHECK-NEXT: or a1, a0, a1
+; CHECK-NEXT: or a2, a0, a2
; CHECK-NEXT: sll a7, t0, a7
-; CHECK-NEXT: or a7, a1, a7
+; CHECK-NEXT: or a7, a2, a7
; CHECK-NEXT: .LBB1_66:
; CHECK-NEXT: or t0, a6, a5
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: beqz t0, .LBB1_68
; CHECK-NEXT: # %bb.67:
-; CHECK-NEXT: mv a1, a7
+; CHECK-NEXT: mv a2, a7
; CHECK-NEXT: .LBB1_68:
; CHECK-NEXT: addi a6, a6, -31
; CHECK-NEXT: seqz a7, a5
@@ -548,14 +548,14 @@ define <8 x bfloat> @v8fp8e5m2_to_v8bf16(<8 x i8> %x) nounwind {
; CHECK-NEXT: and a6, a5, a7
; CHECK-NEXT: beqz a6, .LBB1_70
; CHECK-NEXT: # %bb.69:
-; CHECK-NEXT: or a1, a0, a3
+; CHECK-NEXT: or a2, a0, a3
; CHECK-NEXT: .LBB1_70:
; CHECK-NEXT: and a4, a5, a4
; CHECK-NEXT: bnez a4, .LBB1_72
; CHECK-NEXT: # %bb.71:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB1_72:
-; CHECK-NEXT: sw a2, 32(sp)
+; CHECK-NEXT: sw a1, 32(sp)
; CHECK-NEXT: flw fa0, 16(sp)
; CHECK-NEXT: call __truncsfbf2
; CHECK-NEXT: fmv.s fs0, fa0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index 1baa2a14cf57c..dde4f4c8c5a10 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -4845,8 +4845,8 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i8_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a5, v0
-; RV64ZVE32F-NEXT: andi a3, a5, 1
+; RV64ZVE32F-NEXT: vmv.x.s a6, v0
+; RV64ZVE32F-NEXT: andi a3, a6, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB50_5
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
@@ -4854,22 +4854,22 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: bnez a4, .LBB50_6
; RV64ZVE32F-NEXT: .LBB50_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: bnez a6, .LBB50_7
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: bnez a5, .LBB50_7
; RV64ZVE32F-NEXT: .LBB50_3:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: ld a5, 16(a2)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: bnez a7, .LBB50_8
; RV64ZVE32F-NEXT: .LBB50_4:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
; RV64ZVE32F-NEXT: j .LBB50_9
; RV64ZVE32F-NEXT: .LBB50_5:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB50_2
; RV64ZVE32F-NEXT: .LBB50_6: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
@@ -4879,17 +4879,17 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB50_3
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: beqz a5, .LBB50_3
; RV64ZVE32F-NEXT: .LBB50_7: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a6, v9
-; RV64ZVE32F-NEXT: zext.b a6, a6
-; RV64ZVE32F-NEXT: slli a6, a6, 3
-; RV64ZVE32F-NEXT: add a6, a1, a6
-; RV64ZVE32F-NEXT: ld a6, 0(a6)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: vmv.x.s a5, v9
+; RV64ZVE32F-NEXT: zext.b a5, a5
+; RV64ZVE32F-NEXT: slli a5, a5, 3
+; RV64ZVE32F-NEXT: add a5, a1, a5
+; RV64ZVE32F-NEXT: ld a5, 0(a5)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: beqz a7, .LBB50_4
; RV64ZVE32F-NEXT: .LBB50_8: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
@@ -4902,7 +4902,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: .LBB50_9: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi t0, a5, 16
+; RV64ZVE32F-NEXT: andi t0, a6, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB50_14
; RV64ZVE32F-NEXT: # %bb.10: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s t0, v8
@@ -4910,22 +4910,22 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: bnez t1, .LBB50_15
; RV64ZVE32F-NEXT: .LBB50_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: bnez t2, .LBB50_16
; RV64ZVE32F-NEXT: .LBB50_12:
; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB50_17
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: bnez a6, .LBB50_17
; RV64ZVE32F-NEXT: .LBB50_13:
; RV64ZVE32F-NEXT: ld a1, 56(a2)
; RV64ZVE32F-NEXT: j .LBB50_18
; RV64ZVE32F-NEXT: .LBB50_14:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB50_11
; RV64ZVE32F-NEXT: .LBB50_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
@@ -4935,7 +4935,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: beqz t2, .LBB50_12
; RV64ZVE32F-NEXT: .LBB50_16: # %cond.load16
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
@@ -4945,8 +4945,8 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB50_13
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: beqz a6, .LBB50_13
; RV64ZVE32F-NEXT: .LBB50_17: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
@@ -4958,7 +4958,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: .LBB50_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a6, 16(a0)
+; RV64ZVE32F-NEXT: sd a5, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -5136,8 +5136,8 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-LABEL: mgather_baseidx_v8i16_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a5, v0
-; RV64ZVE32F-NEXT: andi a3, a5, 1
+; RV64ZVE32F-NEXT: vmv.x.s a6, v0
+; RV64ZVE32F-NEXT: andi a3, a6, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB51_5
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -5145,22 +5145,22 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: bnez a4, .LBB51_6
; RV64ZVE32F-NEXT: .LBB51_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: bnez a6, .LBB51_7
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: bnez a5, .LBB51_7
; RV64ZVE32F-NEXT: .LBB51_3:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: ld a5, 16(a2)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: bnez a7, .LBB51_8
; RV64ZVE32F-NEXT: .LBB51_4:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
; RV64ZVE32F-NEXT: j .LBB51_9
; RV64ZVE32F-NEXT: .LBB51_5:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB51_2
; RV64ZVE32F-NEXT: .LBB51_6: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5169,16 +5169,16 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB51_3
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: beqz a5, .LBB51_3
; RV64ZVE32F-NEXT: .LBB51_7: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a6, v9
-; RV64ZVE32F-NEXT: slli a6, a6, 3
-; RV64ZVE32F-NEXT: add a6, a1, a6
-; RV64ZVE32F-NEXT: ld a6, 0(a6)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: vmv.x.s a5, v9
+; RV64ZVE32F-NEXT: slli a5, a5, 3
+; RV64ZVE32F-NEXT: add a5, a1, a5
+; RV64ZVE32F-NEXT: ld a5, 0(a5)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: beqz a7, .LBB51_4
; RV64ZVE32F-NEXT: .LBB51_8: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5190,29 +5190,29 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: .LBB51_9: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi t0, a5, 16
+; RV64ZVE32F-NEXT: andi t0, a6, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB51_14
; RV64ZVE32F-NEXT: # %bb.10: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s t0, v8
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: bnez t1, .LBB51_15
; RV64ZVE32F-NEXT: .LBB51_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: bnez t2, .LBB51_16
; RV64ZVE32F-NEXT: .LBB51_12:
; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB51_17
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: bnez a6, .LBB51_17
; RV64ZVE32F-NEXT: .LBB51_13:
; RV64ZVE32F-NEXT: ld a1, 56(a2)
; RV64ZVE32F-NEXT: j .LBB51_18
; RV64ZVE32F-NEXT: .LBB51_14:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB51_11
; RV64ZVE32F-NEXT: .LBB51_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5221,7 +5221,7 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: beqz t2, .LBB51_12
; RV64ZVE32F-NEXT: .LBB51_16: # %cond.load16
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
@@ -5230,8 +5230,8 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB51_13
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: beqz a6, .LBB51_13
; RV64ZVE32F-NEXT: .LBB51_17: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
@@ -5242,7 +5242,7 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: .LBB51_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a6, 16(a0)
+; RV64ZVE32F-NEXT: sd a5, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -5419,8 +5419,8 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i16_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a5, v0
-; RV64ZVE32F-NEXT: andi a3, a5, 1
+; RV64ZVE32F-NEXT: vmv.x.s a6, v0
+; RV64ZVE32F-NEXT: andi a3, a6, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB52_5
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -5428,22 +5428,22 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: bnez a4, .LBB52_6
; RV64ZVE32F-NEXT: .LBB52_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: bnez a6, .LBB52_7
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: bnez a5, .LBB52_7
; RV64ZVE32F-NEXT: .LBB52_3:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: ld a5, 16(a2)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: bnez a7, .LBB52_8
; RV64ZVE32F-NEXT: .LBB52_4:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
; RV64ZVE32F-NEXT: j .LBB52_9
; RV64ZVE32F-NEXT: .LBB52_5:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB52_2
; RV64ZVE32F-NEXT: .LBB52_6: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5452,16 +5452,16 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB52_3
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: beqz a5, .LBB52_3
; RV64ZVE32F-NEXT: .LBB52_7: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a6, v9
-; RV64ZVE32F-NEXT: slli a6, a6, 3
-; RV64ZVE32F-NEXT: add a6, a1, a6
-; RV64ZVE32F-NEXT: ld a6, 0(a6)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: vmv.x.s a5, v9
+; RV64ZVE32F-NEXT: slli a5, a5, 3
+; RV64ZVE32F-NEXT: add a5, a1, a5
+; RV64ZVE32F-NEXT: ld a5, 0(a5)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: beqz a7, .LBB52_4
; RV64ZVE32F-NEXT: .LBB52_8: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5473,29 +5473,29 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: .LBB52_9: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi t0, a5, 16
+; RV64ZVE32F-NEXT: andi t0, a6, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB52_14
; RV64ZVE32F-NEXT: # %bb.10: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s t0, v8
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: bnez t1, .LBB52_15
; RV64ZVE32F-NEXT: .LBB52_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: bnez t2, .LBB52_16
; RV64ZVE32F-NEXT: .LBB52_12:
; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB52_17
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: bnez a6, .LBB52_17
; RV64ZVE32F-NEXT: .LBB52_13:
; RV64ZVE32F-NEXT: ld a1, 56(a2)
; RV64ZVE32F-NEXT: j .LBB52_18
; RV64ZVE32F-NEXT: .LBB52_14:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB52_11
; RV64ZVE32F-NEXT: .LBB52_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5504,7 +5504,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: beqz t2, .LBB52_12
; RV64ZVE32F-NEXT: .LBB52_16: # %cond.load16
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
@@ -5513,8 +5513,8 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB52_13
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: beqz a6, .LBB52_13
; RV64ZVE32F-NEXT: .LBB52_17: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
@@ -5525,7 +5525,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: .LBB52_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a6, 16(a0)
+; RV64ZVE32F-NEXT: sd a5, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -5704,8 +5704,8 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i16_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a5, v0
-; RV64ZVE32F-NEXT: andi a3, a5, 1
+; RV64ZVE32F-NEXT: vmv.x.s a6, v0
+; RV64ZVE32F-NEXT: andi a3, a6, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB53_5
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -5714,22 +5714,22 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli a3, a3, 45
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: bnez a4, .LBB53_6
; RV64ZVE32F-NEXT: .LBB53_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: bnez a6, .LBB53_7
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: bnez a5, .LBB53_7
; RV64ZVE32F-NEXT: .LBB53_3:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: ld a5, 16(a2)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: bnez a7, .LBB53_8
; RV64ZVE32F-NEXT: .LBB53_4:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
; RV64ZVE32F-NEXT: j .LBB53_9
; RV64ZVE32F-NEXT: .LBB53_5:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB53_2
; RV64ZVE32F-NEXT: .LBB53_6: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5739,17 +5739,17 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli a4, a4, 45
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB53_3
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: beqz a5, .LBB53_3
; RV64ZVE32F-NEXT: .LBB53_7: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a6, v9
-; RV64ZVE32F-NEXT: slli a6, a6, 48
-; RV64ZVE32F-NEXT: srli a6, a6, 45
-; RV64ZVE32F-NEXT: add a6, a1, a6
-; RV64ZVE32F-NEXT: ld a6, 0(a6)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: vmv.x.s a5, v9
+; RV64ZVE32F-NEXT: slli a5, a5, 48
+; RV64ZVE32F-NEXT: srli a5, a5, 45
+; RV64ZVE32F-NEXT: add a5, a1, a5
+; RV64ZVE32F-NEXT: ld a5, 0(a5)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: beqz a7, .LBB53_4
; RV64ZVE32F-NEXT: .LBB53_8: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5762,7 +5762,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: .LBB53_9: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi t0, a5, 16
+; RV64ZVE32F-NEXT: andi t0, a6, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB53_14
; RV64ZVE32F-NEXT: # %bb.10: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s t0, v8
@@ -5770,22 +5770,22 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli t0, t0, 45
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: bnez t1, .LBB53_15
; RV64ZVE32F-NEXT: .LBB53_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: bnez t2, .LBB53_16
; RV64ZVE32F-NEXT: .LBB53_12:
; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB53_17
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: bnez a6, .LBB53_17
; RV64ZVE32F-NEXT: .LBB53_13:
; RV64ZVE32F-NEXT: ld a1, 56(a2)
; RV64ZVE32F-NEXT: j .LBB53_18
; RV64ZVE32F-NEXT: .LBB53_14:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB53_11
; RV64ZVE32F-NEXT: .LBB53_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5795,7 +5795,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli t1, t1, 45
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: beqz t2, .LBB53_12
; RV64ZVE32F-NEXT: .LBB53_16: # %cond.load16
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
@@ -5805,8 +5805,8 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli t2, t2, 45
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB53_13
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: beqz a6, .LBB53_13
; RV64ZVE32F-NEXT: .LBB53_17: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
@@ -5818,7 +5818,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: .LBB53_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a6, 16(a0)
+; RV64ZVE32F-NEXT: sd a5, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -5993,8 +5993,8 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-LABEL: mgather_baseidx_v8i32_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a5, v0
-; RV64ZVE32F-NEXT: andi a3, a5, 1
+; RV64ZVE32F-NEXT: vmv.x.s a6, v0
+; RV64ZVE32F-NEXT: andi a3, a6, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB54_4
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
@@ -6002,18 +6002,18 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: bnez a4, .LBB54_5
; RV64ZVE32F-NEXT: .LBB54_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: bnez a6, .LBB54_6
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: bnez a5, .LBB54_6
; RV64ZVE32F-NEXT: .LBB54_3:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
+; RV64ZVE32F-NEXT: ld a5, 16(a2)
; RV64ZVE32F-NEXT: j .LBB54_7
; RV64ZVE32F-NEXT: .LBB54_4:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB54_2
; RV64ZVE32F-NEXT: .LBB54_5: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6022,19 +6022,19 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB54_3
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: beqz a5, .LBB54_3
; RV64ZVE32F-NEXT: .LBB54_6: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a6, v10
-; RV64ZVE32F-NEXT: slli a6, a6, 3
-; RV64ZVE32F-NEXT: add a6, a1, a6
-; RV64ZVE32F-NEXT: ld a6, 0(a6)
+; RV64ZVE32F-NEXT: vmv.x.s a5, v10
+; RV64ZVE32F-NEXT: slli a5, a5, 3
+; RV64ZVE32F-NEXT: add a5, a1, a5
+; RV64ZVE32F-NEXT: ld a5, 0(a5)
; RV64ZVE32F-NEXT: .LBB54_7: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: beqz a7, .LBB54_13
; RV64ZVE32F-NEXT: # %bb.8: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6043,26 +6043,26 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: andi t0, a5, 16
+; RV64ZVE32F-NEXT: andi t0, a6, 16
; RV64ZVE32F-NEXT: bnez t0, .LBB54_14
; RV64ZVE32F-NEXT: .LBB54_9:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: bnez t1, .LBB54_15
; RV64ZVE32F-NEXT: .LBB54_10:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: bnez t2, .LBB54_16
; RV64ZVE32F-NEXT: .LBB54_11:
; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB54_17
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: bnez a6, .LBB54_17
; RV64ZVE32F-NEXT: .LBB54_12:
; RV64ZVE32F-NEXT: ld a1, 56(a2)
; RV64ZVE32F-NEXT: j .LBB54_18
; RV64ZVE32F-NEXT: .LBB54_13:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: andi t0, a5, 16
+; RV64ZVE32F-NEXT: andi t0, a6, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB54_9
; RV64ZVE32F-NEXT: .LBB54_14: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6070,7 +6070,7 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB54_10
; RV64ZVE32F-NEXT: .LBB54_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6079,7 +6079,7 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: beqz t2, .LBB54_11
; RV64ZVE32F-NEXT: .LBB54_16: # %cond.load16
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
@@ -6088,8 +6088,8 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB54_12
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: beqz a6, .LBB54_12
; RV64ZVE32F-NEXT: .LBB54_17: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
@@ -6100,7 +6100,7 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: .LBB54_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a6, 16(a0)
+; RV64ZVE32F-NEXT: sd a5, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -6274,8 +6274,8 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i32_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a5, v0
-; RV64ZVE32F-NEXT: andi a3, a5, 1
+; RV64ZVE32F-NEXT: vmv.x.s a6, v0
+; RV64ZVE32F-NEXT: andi a3, a6, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB55_4
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
@@ -6283,18 +6283,18 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: bnez a4, .LBB55_5
; RV64ZVE32F-NEXT: .LBB55_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: bnez a6, .LBB55_6
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: bnez a5, .LBB55_6
; RV64ZVE32F-NEXT: .LBB55_3:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
+; RV64ZVE32F-NEXT: ld a5, 16(a2)
; RV64ZVE32F-NEXT: j .LBB55_7
; RV64ZVE32F-NEXT: .LBB55_4:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB55_2
; RV64ZVE32F-NEXT: .LBB55_5: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6303,19 +6303,19 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB55_3
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: beqz a5, .LBB55_3
; RV64ZVE32F-NEXT: .LBB55_6: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a6, v10
-; RV64ZVE32F-NEXT: slli a6, a6, 3
-; RV64ZVE32F-NEXT: add a6, a1, a6
-; RV64ZVE32F-NEXT: ld a6, 0(a6)
+; RV64ZVE32F-NEXT: vmv.x.s a5, v10
+; RV64ZVE32F-NEXT: slli a5, a5, 3
+; RV64ZVE32F-NEXT: add a5, a1, a5
+; RV64ZVE32F-NEXT: ld a5, 0(a5)
; RV64ZVE32F-NEXT: .LBB55_7: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: beqz a7, .LBB55_13
; RV64ZVE32F-NEXT: # %bb.8: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6324,26 +6324,26 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: andi t0, a5, 16
+; RV64ZVE32F-NEXT: andi t0, a6, 16
; RV64ZVE32F-NEXT: bnez t0, .LBB55_14
; RV64ZVE32F-NEXT: .LBB55_9:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: bnez t1, .LBB55_15
; RV64ZVE32F-NEXT: .LBB55_10:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: bnez t2, .LBB55_16
; RV64ZVE32F-NEXT: .LBB55_11:
; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB55_17
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: bnez a6, .LBB55_17
; RV64ZVE32F-NEXT: .LBB55_12:
; RV64ZVE32F-NEXT: ld a1, 56(a2)
; RV64ZVE32F-NEXT: j .LBB55_18
; RV64ZVE32F-NEXT: .LBB55_13:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: andi t0, a5, 16
+; RV64ZVE32F-NEXT: andi t0, a6, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB55_9
; RV64ZVE32F-NEXT: .LBB55_14: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6351,7 +6351,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB55_10
; RV64ZVE32F-NEXT: .LBB55_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6360,7 +6360,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: beqz t2, .LBB55_11
; RV64ZVE32F-NEXT: .LBB55_16: # %cond.load16
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
@@ -6369,8 +6369,8 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB55_12
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: beqz a6, .LBB55_12
; RV64ZVE32F-NEXT: .LBB55_17: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
@@ -6381,7 +6381,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: .LBB55_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a6, 16(a0)
+; RV64ZVE32F-NEXT: sd a5, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -6556,8 +6556,8 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i32_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a5, v0
-; RV64ZVE32F-NEXT: andi a3, a5, 1
+; RV64ZVE32F-NEXT: vmv.x.s a6, v0
+; RV64ZVE32F-NEXT: andi a3, a6, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB56_4
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
@@ -6566,18 +6566,18 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: srli a3, a3, 29
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: bnez a4, .LBB56_5
; RV64ZVE32F-NEXT: .LBB56_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: bnez a6, .LBB56_6
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: bnez a5, .LBB56_6
; RV64ZVE32F-NEXT: .LBB56_3:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
+; RV64ZVE32F-NEXT: ld a5, 16(a2)
; RV64ZVE32F-NEXT: j .LBB56_7
; RV64ZVE32F-NEXT: .LBB56_4:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB56_2
; RV64ZVE32F-NEXT: .LBB56_5: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6587,20 +6587,20 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: srli a4, a4, 29
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB56_3
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: beqz a5, .LBB56_3
; RV64ZVE32F-NEXT: .LBB56_6: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a6, v10
-; RV64ZVE32F-NEXT: slli a6, a6, 32
-; RV64ZVE32F-NEXT: srli a6, a6, 29
-; RV64ZVE32F-NEXT: add a6, a1, a6
-; RV64ZVE32F-NEXT: ld a6, 0(a6)
+; RV64ZVE32F-NEXT: vmv.x.s a5, v10
+; RV64ZVE32F-NEXT: slli a5, a5, 32
+; RV64ZVE32F-NEXT: srli a5, a5, 29
+; RV64ZVE32F-NEXT: add a5, a1, a5
+; RV64ZVE32F-NEXT: ld a5, 0(a5)
; RV64ZVE32F-NEXT: .LBB56_7: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
-; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: andi a7, a6, 8
; RV64ZVE32F-NEXT: beqz a7, .LBB56_13
; RV64ZVE32F-NEXT: # %bb.8: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6610,26 +6610,26 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: srli a7, a7, 29
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: andi t0, a5, 16
+; RV64ZVE32F-NEXT: andi t0, a6, 16
; RV64ZVE32F-NEXT: bnez t0, .LBB56_14
; RV64ZVE32F-NEXT: .LBB56_9:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: bnez t1, .LBB56_15
; RV64ZVE32F-NEXT: .LBB56_10:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: bnez t2, .LBB56_16
; RV64ZVE32F-NEXT: .LBB56_11:
; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB56_17
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: bnez a6, .LBB56_17
; RV64ZVE32F-NEXT: .LBB56_12:
; RV64ZVE32F-NEXT: ld a1, 56(a2)
; RV64ZVE32F-NEXT: j .LBB56_18
; RV64ZVE32F-NEXT: .LBB56_13:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: andi t0, a5, 16
+; RV64ZVE32F-NEXT: andi t0, a6, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB56_9
; RV64ZVE32F-NEXT: .LBB56_14: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6638,7 +6638,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: srli t0, t0, 29
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
+; RV64ZVE32F-NEXT: andi t1, a6, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB56_10
; RV64ZVE32F-NEXT: .LBB56_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6648,7 +6648,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: srli t1, t1, 29
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: andi t2, a6, 64
; RV64ZVE32F-NEXT: beqz t2, .LBB56_11
; RV64ZVE32F-NEXT: .LBB56_16: # %cond.load16
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
@@ -6658,8 +6658,8 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: srli t2, t2, 29
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB56_12
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: beqz a6, .LBB56_12
; RV64ZVE32F-NEXT: .LBB56_17: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
@@ -6671,7 +6671,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: .LBB56_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a6, 16(a0)
+; RV64ZVE32F-NEXT: sd a5, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -6706,53 +6706,53 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32ZVE32F-LABEL: mgather_baseidx_v8i64:
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV32ZVE32F-NEXT: vmv.x.s a6, v0
+; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: lw a4, 0(a2)
; RV32ZVE32F-NEXT: lw a5, 8(a2)
-; RV32ZVE32F-NEXT: lw a7, 16(a2)
-; RV32ZVE32F-NEXT: lw t0, 24(a2)
+; RV32ZVE32F-NEXT: lw a6, 16(a2)
+; RV32ZVE32F-NEXT: lw a7, 24(a2)
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v8, a4
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a5
+; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a6
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a7
-; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t0
; RV32ZVE32F-NEXT: lw a4, 32(a2)
; RV32ZVE32F-NEXT: lw a5, 40(a2)
-; RV32ZVE32F-NEXT: lw a7, 48(a2)
+; RV32ZVE32F-NEXT: lw a6, 48(a2)
; RV32ZVE32F-NEXT: lw a2, 56(a2)
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a4
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a5
-; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a7
+; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a6
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a2
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT: andi a1, a6, 1
+; RV32ZVE32F-NEXT: andi a1, t0, 1
; RV32ZVE32F-NEXT: beqz a1, .LBB57_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: lw a1, 0(a2)
; RV32ZVE32F-NEXT: lw a2, 4(a2)
-; RV32ZVE32F-NEXT: andi a4, a6, 2
+; RV32ZVE32F-NEXT: andi a4, t0, 2
; RV32ZVE32F-NEXT: bnez a4, .LBB57_8
; RV32ZVE32F-NEXT: .LBB57_2:
; RV32ZVE32F-NEXT: lw a4, 8(a3)
; RV32ZVE32F-NEXT: lw a5, 12(a3)
-; RV32ZVE32F-NEXT: andi a7, a6, 4
-; RV32ZVE32F-NEXT: bnez a7, .LBB57_9
+; RV32ZVE32F-NEXT: andi a6, t0, 4
+; RV32ZVE32F-NEXT: bnez a6, .LBB57_9
; RV32ZVE32F-NEXT: .LBB57_3:
-; RV32ZVE32F-NEXT: lw a7, 16(a3)
-; RV32ZVE32F-NEXT: lw t0, 20(a3)
-; RV32ZVE32F-NEXT: andi t1, a6, 8
+; RV32ZVE32F-NEXT: lw a6, 16(a3)
+; RV32ZVE32F-NEXT: lw a7, 20(a3)
+; RV32ZVE32F-NEXT: andi t1, t0, 8
; RV32ZVE32F-NEXT: bnez t1, .LBB57_10
; RV32ZVE32F-NEXT: .LBB57_4:
; RV32ZVE32F-NEXT: lw t1, 24(a3)
; RV32ZVE32F-NEXT: lw t2, 28(a3)
-; RV32ZVE32F-NEXT: andi t3, a6, 16
+; RV32ZVE32F-NEXT: andi t3, t0, 16
; RV32ZVE32F-NEXT: bnez t3, .LBB57_11
; RV32ZVE32F-NEXT: .LBB57_5:
; RV32ZVE32F-NEXT: lw t3, 32(a3)
; RV32ZVE32F-NEXT: lw t4, 36(a3)
-; RV32ZVE32F-NEXT: andi t5, a6, 32
+; RV32ZVE32F-NEXT: andi t5, t0, 32
; RV32ZVE32F-NEXT: bnez t5, .LBB57_12
; RV32ZVE32F-NEXT: .LBB57_6:
; RV32ZVE32F-NEXT: lw t5, 40(a3)
@@ -6761,7 +6761,7 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32ZVE32F-NEXT: .LBB57_7:
; RV32ZVE32F-NEXT: lw a1, 0(a3)
; RV32ZVE32F-NEXT: lw a2, 4(a3)
-; RV32ZVE32F-NEXT: andi a4, a6, 2
+; RV32ZVE32F-NEXT: andi a4, t0, 2
; RV32ZVE32F-NEXT: beqz a4, .LBB57_2
; RV32ZVE32F-NEXT: .LBB57_8: # %cond.load1
; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6769,15 +6769,15 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32ZVE32F-NEXT: vmv.x.s a5, v10
; RV32ZVE32F-NEXT: lw a4, 0(a5)
; RV32ZVE32F-NEXT: lw a5, 4(a5)
-; RV32ZVE32F-NEXT: andi a7, a6, 4
-; RV32ZVE32F-NEXT: beqz a7, .LBB57_3
+; RV32ZVE32F-NEXT: andi a6, t0, 4
+; RV32ZVE32F-NEXT: beqz a6, .LBB57_3
; RV32ZVE32F-NEXT: .LBB57_9: # %cond.load4
; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV32ZVE32F-NEXT: vmv.x.s t0, v10
-; RV32ZVE32F-NEXT: lw a7, 0(t0)
-; RV32ZVE32F-NEXT: lw t0, 4(t0)
-; RV32ZVE32F-NEXT: andi t1, a6, 8
+; RV32ZVE32F-NEXT: vmv.x.s a7, v10
+; RV32ZVE32F-NEXT: lw a6, 0(a7)
+; RV32ZVE32F-NEXT: lw a7, 4(a7)
+; RV32ZVE32F-NEXT: andi t1, t0, 8
; RV32ZVE32F-NEXT: beqz t1, .LBB57_4
; RV32ZVE32F-NEXT: .LBB57_10: # %cond.load7
; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -6785,7 +6785,7 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32ZVE32F-NEXT: vmv.x.s t2, v10
; RV32ZVE32F-NEXT: lw t1, 0(t2)
; RV32ZVE32F-NEXT: lw t2, 4(t2)
-; RV32ZVE32F-NEXT: andi t3, a6, 16
+; RV32ZVE32F-NEXT: andi t3, t0, 16
; RV32ZVE32F-NEXT: beqz t3, .LBB57_5
; RV32ZVE32F-NEXT: .LBB57_11: # %cond.load10
; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
@@ -6793,7 +6793,7 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32ZVE32F-NEXT: vmv.x.s t4, v10
; RV32ZVE32F-NEXT: lw t3, 0(t4)
; RV32ZVE32F-NEXT: lw t4, 4(t4)
-; RV32ZVE32F-NEXT: andi t5, a6, 32
+; RV32ZVE32F-NEXT: andi t5, t0, 32
; RV32ZVE32F-NEXT: beqz t5, .LBB57_6
; RV32ZVE32F-NEXT: .LBB57_12: # %cond.load13
; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
@@ -6808,7 +6808,7 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32ZVE32F-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
-; RV32ZVE32F-NEXT: andi s0, a6, 64
+; RV32ZVE32F-NEXT: andi s0, t0, 64
; RV32ZVE32F-NEXT: beqz s0, .LBB57_16
; RV32ZVE32F-NEXT: # %bb.14: # %cond.load16
; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
@@ -6816,30 +6816,30 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32ZVE32F-NEXT: vmv.x.s s1, v10
; RV32ZVE32F-NEXT: lw s0, 0(s1)
; RV32ZVE32F-NEXT: lw s1, 4(s1)
-; RV32ZVE32F-NEXT: andi a6, a6, -128
-; RV32ZVE32F-NEXT: bnez a6, .LBB57_17
+; RV32ZVE32F-NEXT: andi t0, t0, -128
+; RV32ZVE32F-NEXT: bnez t0, .LBB57_17
; RV32ZVE32F-NEXT: .LBB57_15:
-; RV32ZVE32F-NEXT: lw a6, 56(a3)
+; RV32ZVE32F-NEXT: lw t0, 56(a3)
; RV32ZVE32F-NEXT: lw a3, 60(a3)
; RV32ZVE32F-NEXT: j .LBB57_18
; RV32ZVE32F-NEXT: .LBB57_16:
; RV32ZVE32F-NEXT: lw s0, 48(a3)
; RV32ZVE32F-NEXT: lw s1, 52(a3)
-; RV32ZVE32F-NEXT: andi a6, a6, -128
-; RV32ZVE32F-NEXT: beqz a6, .LBB57_15
+; RV32ZVE32F-NEXT: andi t0, t0, -128
+; RV32ZVE32F-NEXT: beqz t0, .LBB57_15
; RV32ZVE32F-NEXT: .LBB57_17: # %cond.load19
; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 7
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
-; RV32ZVE32F-NEXT: lw a6, 0(a3)
+; RV32ZVE32F-NEXT: lw t0, 0(a3)
; RV32ZVE32F-NEXT: lw a3, 4(a3)
; RV32ZVE32F-NEXT: .LBB57_18: # %else20
; RV32ZVE32F-NEXT: sw a1, 0(a0)
; RV32ZVE32F-NEXT: sw a2, 4(a0)
; RV32ZVE32F-NEXT: sw a4, 8(a0)
; RV32ZVE32F-NEXT: sw a5, 12(a0)
-; RV32ZVE32F-NEXT: sw a7, 16(a0)
-; RV32ZVE32F-NEXT: sw t0, 20(a0)
+; RV32ZVE32F-NEXT: sw a6, 16(a0)
+; RV32ZVE32F-NEXT: sw a7, 20(a0)
; RV32ZVE32F-NEXT: sw t1, 24(a0)
; RV32ZVE32F-NEXT: sw t2, 28(a0)
; RV32ZVE32F-NEXT: sw t3, 32(a0)
@@ -6848,7 +6848,7 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32ZVE32F-NEXT: sw t6, 44(a0)
; RV32ZVE32F-NEXT: sw s0, 48(a0)
; RV32ZVE32F-NEXT: sw s1, 52(a0)
-; RV32ZVE32F-NEXT: sw a6, 56(a0)
+; RV32ZVE32F-NEXT: sw t0, 56(a0)
; RV32ZVE32F-NEXT: sw a3, 60(a0)
; RV32ZVE32F-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
index f84c207c3becb..30648f371c28f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
@@ -257,47 +257,47 @@ define <4 x i32> @ustest_f32i32(<4 x float> %x) {
; CHECK-NOV-LABEL: ustest_f32i32:
; CHECK-NOV: # %bb.0: # %entry
; CHECK-NOV-NEXT: fcvt.l.s a3, fa1, rtz
-; CHECK-NOV-NEXT: fcvt.l.s a2, fa0, rtz
+; CHECK-NOV-NEXT: fcvt.l.s a1, fa0, rtz
; CHECK-NOV-NEXT: fcvt.l.s a4, fa2, rtz
-; CHECK-NOV-NEXT: fcvt.l.s a1, fa3, rtz
+; CHECK-NOV-NEXT: fcvt.l.s a2, fa3, rtz
; CHECK-NOV-NEXT: li a5, -1
-; CHECK-NOV-NEXT: sgtz a6, a2
+; CHECK-NOV-NEXT: sgtz a6, a1
; CHECK-NOV-NEXT: sgtz a7, a3
; CHECK-NOV-NEXT: sgtz t0, a4
; CHECK-NOV-NEXT: neg a6, a6
-; CHECK-NOV-NEXT: and a2, a6, a2
-; CHECK-NOV-NEXT: sgtz a6, a1
+; CHECK-NOV-NEXT: and a1, a6, a1
+; CHECK-NOV-NEXT: sgtz a6, a2
; CHECK-NOV-NEXT: neg t1, a7
; CHECK-NOV-NEXT: srli a5, a5, 32
; CHECK-NOV-NEXT: neg a7, t0
; CHECK-NOV-NEXT: and a3, t1, a3
-; CHECK-NOV-NEXT: bltu a2, a5, .LBB5_2
+; CHECK-NOV-NEXT: bltu a1, a5, .LBB5_2
; CHECK-NOV-NEXT: # %bb.1: # %entry
-; CHECK-NOV-NEXT: mv a2, a5
+; CHECK-NOV-NEXT: mv a1, a5
; CHECK-NOV-NEXT: .LBB5_2: # %entry
; CHECK-NOV-NEXT: neg a6, a6
; CHECK-NOV-NEXT: and a4, a7, a4
; CHECK-NOV-NEXT: bgeu a3, a5, .LBB5_7
; CHECK-NOV-NEXT: # %bb.3: # %entry
-; CHECK-NOV-NEXT: and a1, a6, a1
+; CHECK-NOV-NEXT: and a2, a6, a2
; CHECK-NOV-NEXT: bgeu a4, a5, .LBB5_8
; CHECK-NOV-NEXT: .LBB5_4: # %entry
-; CHECK-NOV-NEXT: bltu a1, a5, .LBB5_6
+; CHECK-NOV-NEXT: bltu a2, a5, .LBB5_6
; CHECK-NOV-NEXT: .LBB5_5: # %entry
-; CHECK-NOV-NEXT: mv a1, a5
+; CHECK-NOV-NEXT: mv a2, a5
; CHECK-NOV-NEXT: .LBB5_6: # %entry
-; CHECK-NOV-NEXT: sw a2, 0(a0)
+; CHECK-NOV-NEXT: sw a1, 0(a0)
; CHECK-NOV-NEXT: sw a3, 4(a0)
; CHECK-NOV-NEXT: sw a4, 8(a0)
-; CHECK-NOV-NEXT: sw a1, 12(a0)
+; CHECK-NOV-NEXT: sw a2, 12(a0)
; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB5_7: # %entry
; CHECK-NOV-NEXT: mv a3, a5
-; CHECK-NOV-NEXT: and a1, a6, a1
+; CHECK-NOV-NEXT: and a2, a6, a2
; CHECK-NOV-NEXT: bltu a4, a5, .LBB5_4
; CHECK-NOV-NEXT: .LBB5_8: # %entry
; CHECK-NOV-NEXT: mv a4, a5
-; CHECK-NOV-NEXT: bgeu a1, a5, .LBB5_5
+; CHECK-NOV-NEXT: bgeu a2, a5, .LBB5_5
; CHECK-NOV-NEXT: j .LBB5_6
;
; CHECK-V-LABEL: ustest_f32i32:
@@ -1146,47 +1146,47 @@ define <4 x i16> @ustest_f32i16(<4 x float> %x) {
; CHECK-NOV-LABEL: ustest_f32i16:
; CHECK-NOV: # %bb.0: # %entry
; CHECK-NOV-NEXT: fcvt.w.s a3, fa1, rtz
-; CHECK-NOV-NEXT: fcvt.w.s a2, fa0, rtz
+; CHECK-NOV-NEXT: fcvt.w.s a1, fa0, rtz
; CHECK-NOV-NEXT: fcvt.w.s a4, fa2, rtz
-; CHECK-NOV-NEXT: fcvt.w.s a1, fa3, rtz
+; CHECK-NOV-NEXT: fcvt.w.s a2, fa3, rtz
; CHECK-NOV-NEXT: lui a5, 16
-; CHECK-NOV-NEXT: sgtz a6, a2
+; CHECK-NOV-NEXT: sgtz a6, a1
; CHECK-NOV-NEXT: sgtz a7, a3
; CHECK-NOV-NEXT: sgtz t0, a4
; CHECK-NOV-NEXT: neg a6, a6
-; CHECK-NOV-NEXT: and a2, a6, a2
-; CHECK-NOV-NEXT: sgtz a6, a1
+; CHECK-NOV-NEXT: and a1, a6, a1
+; CHECK-NOV-NEXT: sgtz a6, a2
; CHECK-NOV-NEXT: neg t1, a7
; CHECK-NOV-NEXT: addi a5, a5, -1
; CHECK-NOV-NEXT: neg a7, t0
; CHECK-NOV-NEXT: and a3, t1, a3
-; CHECK-NOV-NEXT: bltu a2, a5, .LBB14_2
+; CHECK-NOV-NEXT: bltu a1, a5, .LBB14_2
; CHECK-NOV-NEXT: # %bb.1: # %entry
-; CHECK-NOV-NEXT: mv a2, a5
+; CHECK-NOV-NEXT: mv a1, a5
; CHECK-NOV-NEXT: .LBB14_2: # %entry
; CHECK-NOV-NEXT: neg a6, a6
; CHECK-NOV-NEXT: and a4, a7, a4
; CHECK-NOV-NEXT: bgeu a3, a5, .LBB14_7
; CHECK-NOV-NEXT: # %bb.3: # %entry
-; CHECK-NOV-NEXT: and a1, a6, a1
+; CHECK-NOV-NEXT: and a2, a6, a2
; CHECK-NOV-NEXT: bgeu a4, a5, .LBB14_8
; CHECK-NOV-NEXT: .LBB14_4: # %entry
-; CHECK-NOV-NEXT: bltu a1, a5, .LBB14_6
+; CHECK-NOV-NEXT: bltu a2, a5, .LBB14_6
; CHECK-NOV-NEXT: .LBB14_5: # %entry
-; CHECK-NOV-NEXT: mv a1, a5
+; CHECK-NOV-NEXT: mv a2, a5
; CHECK-NOV-NEXT: .LBB14_6: # %entry
-; CHECK-NOV-NEXT: sh a2, 0(a0)
+; CHECK-NOV-NEXT: sh a1, 0(a0)
; CHECK-NOV-NEXT: sh a3, 2(a0)
; CHECK-NOV-NEXT: sh a4, 4(a0)
-; CHECK-NOV-NEXT: sh a1, 6(a0)
+; CHECK-NOV-NEXT: sh a2, 6(a0)
; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB14_7: # %entry
; CHECK-NOV-NEXT: mv a3, a5
-; CHECK-NOV-NEXT: and a1, a6, a1
+; CHECK-NOV-NEXT: and a2, a6, a2
; CHECK-NOV-NEXT: bltu a4, a5, .LBB14_4
; CHECK-NOV-NEXT: .LBB14_8: # %entry
; CHECK-NOV-NEXT: mv a4, a5
-; CHECK-NOV-NEXT: bgeu a1, a5, .LBB14_5
+; CHECK-NOV-NEXT: bgeu a2, a5, .LBB14_5
; CHECK-NOV-NEXT: j .LBB14_6
;
; CHECK-V-LABEL: ustest_f32i16:
@@ -1663,31 +1663,31 @@ define <8 x i16> @utest_f16i16(<8 x half> %x) {
; CHECK-NOV-NEXT: fmv.w.x fa0, s5
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fcvt.lu.s a0, fa0, rtz
-; CHECK-NOV-NEXT: lui a3, 16
-; CHECK-NOV-NEXT: addi a3, a3, -1
-; CHECK-NOV-NEXT: bgeu a0, a3, .LBB16_10
+; CHECK-NOV-NEXT: lui a2, 16
+; CHECK-NOV-NEXT: addi a2, a2, -1
+; CHECK-NOV-NEXT: bgeu a0, a2, .LBB16_10
; CHECK-NOV-NEXT: # %bb.1: # %entry
; CHECK-NOV-NEXT: fcvt.lu.s a1, fs5, rtz
-; CHECK-NOV-NEXT: bgeu s1, a3, .LBB16_11
+; CHECK-NOV-NEXT: bgeu s1, a2, .LBB16_11
; CHECK-NOV-NEXT: .LBB16_2: # %entry
-; CHECK-NOV-NEXT: fcvt.lu.s a2, fs4, rtz
-; CHECK-NOV-NEXT: bgeu a1, a3, .LBB16_12
+; CHECK-NOV-NEXT: fcvt.lu.s a3, fs4, rtz
+; CHECK-NOV-NEXT: bgeu a1, a2, .LBB16_12
; CHECK-NOV-NEXT: .LBB16_3: # %entry
; CHECK-NOV-NEXT: fcvt.lu.s a4, fs3, rtz
-; CHECK-NOV-NEXT: bgeu a2, a3, .LBB16_13
+; CHECK-NOV-NEXT: bgeu a3, a2, .LBB16_13
; CHECK-NOV-NEXT: .LBB16_4: # %entry
; CHECK-NOV-NEXT: fcvt.lu.s a5, fs2, rtz
-; CHECK-NOV-NEXT: bgeu a4, a3, .LBB16_14
+; CHECK-NOV-NEXT: bgeu a4, a2, .LBB16_14
; CHECK-NOV-NEXT: .LBB16_5: # %entry
; CHECK-NOV-NEXT: fcvt.lu.s a6, fs1, rtz
-; CHECK-NOV-NEXT: bgeu a5, a3, .LBB16_15
+; CHECK-NOV-NEXT: bgeu a5, a2, .LBB16_15
; CHECK-NOV-NEXT: .LBB16_6: # %entry
; CHECK-NOV-NEXT: fcvt.lu.s a7, fs0, rtz
-; CHECK-NOV-NEXT: bgeu a6, a3, .LBB16_16
+; CHECK-NOV-NEXT: bgeu a6, a2, .LBB16_16
; CHECK-NOV-NEXT: .LBB16_7: # %entry
-; CHECK-NOV-NEXT: bltu a7, a3, .LBB16_9
+; CHECK-NOV-NEXT: bltu a7, a2, .LBB16_9
; CHECK-NOV-NEXT: .LBB16_8: # %entry
-; CHECK-NOV-NEXT: mv a7, a3
+; CHECK-NOV-NEXT: mv a7, a2
; CHECK-NOV-NEXT: .LBB16_9: # %entry
; CHECK-NOV-NEXT: sh a4, 8(s0)
; CHECK-NOV-NEXT: sh a5, 10(s0)
@@ -1696,7 +1696,7 @@ define <8 x i16> @utest_f16i16(<8 x half> %x) {
; CHECK-NOV-NEXT: sh a0, 0(s0)
; CHECK-NOV-NEXT: sh s1, 2(s0)
; CHECK-NOV-NEXT: sh a1, 4(s0)
-; CHECK-NOV-NEXT: sh a2, 6(s0)
+; CHECK-NOV-NEXT: sh a3, 6(s0)
; CHECK-NOV-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; CHECK-NOV-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; CHECK-NOV-NEXT: ld s1, 104(sp) # 8-byte Folded Reload
@@ -1734,32 +1734,32 @@ define <8 x i16> @utest_f16i16(<8 x half> %x) {
; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB16_10: # %entry
; CHECK-NOV-NEXT: .cfi_restore_state
-; CHECK-NOV-NEXT: mv a0, a3
+; CHECK-NOV-NEXT: mv a0, a2
; CHECK-NOV-NEXT: fcvt.lu.s a1, fs5, rtz
-; CHECK-NOV-NEXT: bltu s1, a3, .LBB16_2
+; CHECK-NOV-NEXT: bltu s1, a2, .LBB16_2
; CHECK-NOV-NEXT: .LBB16_11: # %entry
-; CHECK-NOV-NEXT: mv s1, a3
-; CHECK-NOV-NEXT: fcvt.lu.s a2, fs4, rtz
-; CHECK-NOV-NEXT: bltu a1, a3, .LBB16_3
+; CHECK-NOV-NEXT: mv s1, a2
+; CHECK-NOV-NEXT: fcvt.lu.s a3, fs4, rtz
+; CHECK-NOV-NEXT: bltu a1, a2, .LBB16_3
; CHECK-NOV-NEXT: .LBB16_12: # %entry
-; CHECK-NOV-NEXT: mv a1, a3
+; CHECK-NOV-NEXT: mv a1, a2
; CHECK-NOV-NEXT: fcvt.lu.s a4, fs3, rtz
-; CHECK-NOV-NEXT: bltu a2, a3, .LBB16_4
+; CHECK-NOV-NEXT: bltu a3, a2, .LBB16_4
; CHECK-NOV-NEXT: .LBB16_13: # %entry
-; CHECK-NOV-NEXT: mv a2, a3
+; CHECK-NOV-NEXT: mv a3, a2
; CHECK-NOV-NEXT: fcvt.lu.s a5, fs2, rtz
-; CHECK-NOV-NEXT: bltu a4, a3, .LBB16_5
+; CHECK-NOV-NEXT: bltu a4, a2, .LBB16_5
; CHECK-NOV-NEXT: .LBB16_14: # %entry
-; CHECK-NOV-NEXT: mv a4, a3
+; CHECK-NOV-NEXT: mv a4, a2
; CHECK-NOV-NEXT: fcvt.lu.s a6, fs1, rtz
-; CHECK-NOV-NEXT: bltu a5, a3, .LBB16_6
+; CHECK-NOV-NEXT: bltu a5, a2, .LBB16_6
; CHECK-NOV-NEXT: .LBB16_15: # %entry
-; CHECK-NOV-NEXT: mv a5, a3
+; CHECK-NOV-NEXT: mv a5, a2
; CHECK-NOV-NEXT: fcvt.lu.s a7, fs0, rtz
-; CHECK-NOV-NEXT: bltu a6, a3, .LBB16_7
+; CHECK-NOV-NEXT: bltu a6, a2, .LBB16_7
; CHECK-NOV-NEXT: .LBB16_16: # %entry
-; CHECK-NOV-NEXT: mv a6, a3
-; CHECK-NOV-NEXT: bgeu a7, a3, .LBB16_8
+; CHECK-NOV-NEXT: mv a6, a2
+; CHECK-NOV-NEXT: bgeu a7, a2, .LBB16_8
; CHECK-NOV-NEXT: j .LBB16_9
;
; CHECK-V-LABEL: utest_f16i16:
@@ -3801,47 +3801,47 @@ define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
; CHECK-NOV-LABEL: ustest_f32i32_mm:
; CHECK-NOV: # %bb.0: # %entry
; CHECK-NOV-NEXT: fcvt.l.s a1, fa1, rtz
-; CHECK-NOV-NEXT: fcvt.l.s a3, fa0, rtz
-; CHECK-NOV-NEXT: fcvt.l.s a4, fa2, rtz
-; CHECK-NOV-NEXT: fcvt.l.s a2, fa3, rtz
-; CHECK-NOV-NEXT: sgtz a5, a1
+; CHECK-NOV-NEXT: fcvt.l.s a2, fa0, rtz
+; CHECK-NOV-NEXT: fcvt.l.s a5, fa2, rtz
+; CHECK-NOV-NEXT: fcvt.l.s a3, fa3, rtz
+; CHECK-NOV-NEXT: sgtz a4, a1
; CHECK-NOV-NEXT: li a6, -1
-; CHECK-NOV-NEXT: neg a5, a5
-; CHECK-NOV-NEXT: sgtz a7, a3
-; CHECK-NOV-NEXT: and a1, a5, a1
-; CHECK-NOV-NEXT: sgtz t0, a4
-; CHECK-NOV-NEXT: neg a5, a7
-; CHECK-NOV-NEXT: and a3, a5, a3
-; CHECK-NOV-NEXT: srli a5, a6, 32
-; CHECK-NOV-NEXT: sgtz a6, a2
+; CHECK-NOV-NEXT: neg a4, a4
+; CHECK-NOV-NEXT: sgtz a7, a2
+; CHECK-NOV-NEXT: and a1, a4, a1
+; CHECK-NOV-NEXT: sgtz t0, a5
+; CHECK-NOV-NEXT: neg a4, a7
+; CHECK-NOV-NEXT: and a2, a4, a2
+; CHECK-NOV-NEXT: srli a4, a6, 32
+; CHECK-NOV-NEXT: sgtz a6, a3
; CHECK-NOV-NEXT: neg a7, t0
-; CHECK-NOV-NEXT: blt a3, a5, .LBB32_2
+; CHECK-NOV-NEXT: blt a2, a4, .LBB32_2
; CHECK-NOV-NEXT: # %bb.1: # %entry
-; CHECK-NOV-NEXT: mv a3, a5
+; CHECK-NOV-NEXT: mv a2, a4
; CHECK-NOV-NEXT: .LBB32_2: # %entry
; CHECK-NOV-NEXT: neg a6, a6
-; CHECK-NOV-NEXT: and a4, a7, a4
-; CHECK-NOV-NEXT: bge a1, a5, .LBB32_7
+; CHECK-NOV-NEXT: and a5, a7, a5
+; CHECK-NOV-NEXT: bge a1, a4, .LBB32_7
; CHECK-NOV-NEXT: # %bb.3: # %entry
-; CHECK-NOV-NEXT: and a2, a6, a2
-; CHECK-NOV-NEXT: bge a4, a5, .LBB32_8
+; CHECK-NOV-NEXT: and a3, a6, a3
+; CHECK-NOV-NEXT: bge a5, a4, .LBB32_8
; CHECK-NOV-NEXT: .LBB32_4: # %entry
-; CHECK-NOV-NEXT: blt a2, a5, .LBB32_6
+; CHECK-NOV-NEXT: blt a3, a4, .LBB32_6
; CHECK-NOV-NEXT: .LBB32_5: # %entry
-; CHECK-NOV-NEXT: mv a2, a5
+; CHECK-NOV-NEXT: mv a3, a4
; CHECK-NOV-NEXT: .LBB32_6: # %entry
-; CHECK-NOV-NEXT: sw a3, 0(a0)
+; CHECK-NOV-NEXT: sw a2, 0(a0)
; CHECK-NOV-NEXT: sw a1, 4(a0)
-; CHECK-NOV-NEXT: sw a4, 8(a0)
-; CHECK-NOV-NEXT: sw a2, 12(a0)
+; CHECK-NOV-NEXT: sw a5, 8(a0)
+; CHECK-NOV-NEXT: sw a3, 12(a0)
; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB32_7: # %entry
-; CHECK-NOV-NEXT: mv a1, a5
-; CHECK-NOV-NEXT: and a2, a6, a2
-; CHECK-NOV-NEXT: blt a4, a5, .LBB32_4
+; CHECK-NOV-NEXT: mv a1, a4
+; CHECK-NOV-NEXT: and a3, a6, a3
+; CHECK-NOV-NEXT: blt a5, a4, .LBB32_4
; CHECK-NOV-NEXT: .LBB32_8: # %entry
-; CHECK-NOV-NEXT: mv a4, a5
-; CHECK-NOV-NEXT: bge a2, a5, .LBB32_5
+; CHECK-NOV-NEXT: mv a5, a4
+; CHECK-NOV-NEXT: bge a3, a4, .LBB32_5
; CHECK-NOV-NEXT: j .LBB32_6
;
; CHECK-V-LABEL: ustest_f32i32_mm:
@@ -4675,47 +4675,47 @@ define <4 x i16> @ustest_f32i16_mm(<4 x float> %x) {
; CHECK-NOV-LABEL: ustest_f32i16_mm:
; CHECK-NOV: # %bb.0: # %entry
; CHECK-NOV-NEXT: fcvt.w.s a1, fa1, rtz
-; CHECK-NOV-NEXT: fcvt.w.s a3, fa0, rtz
-; CHECK-NOV-NEXT: fcvt.w.s a4, fa2, rtz
-; CHECK-NOV-NEXT: fcvt.w.s a2, fa3, rtz
-; CHECK-NOV-NEXT: sgtz a5, a1
+; CHECK-NOV-NEXT: fcvt.w.s a2, fa0, rtz
+; CHECK-NOV-NEXT: fcvt.w.s a5, fa2, rtz
+; CHECK-NOV-NEXT: fcvt.w.s a3, fa3, rtz
+; CHECK-NOV-NEXT: sgtz a4, a1
; CHECK-NOV-NEXT: lui a6, 16
-; CHECK-NOV-NEXT: neg a5, a5
-; CHECK-NOV-NEXT: sgtz a7, a3
-; CHECK-NOV-NEXT: and a1, a5, a1
-; CHECK-NOV-NEXT: sgtz t0, a4
-; CHECK-NOV-NEXT: neg a5, a7
-; CHECK-NOV-NEXT: and a3, a5, a3
-; CHECK-NOV-NEXT: addi a5, a6, -1
-; CHECK-NOV-NEXT: sgtz a6, a2
+; CHECK-NOV-NEXT: neg a4, a4
+; CHECK-NOV-NEXT: sgtz a7, a2
+; CHECK-NOV-NEXT: and a1, a4, a1
+; CHECK-NOV-NEXT: sgtz t0, a5
+; CHECK-NOV-NEXT: neg a4, a7
+; CHECK-NOV-NEXT: and a2, a4, a2
+; CHECK-NOV-NEXT: addi a4, a6, -1
+; CHECK-NOV-NEXT: sgtz a6, a3
; CHECK-NOV-NEXT: neg a7, t0
-; CHECK-NOV-NEXT: blt a3, a5, .LBB41_2
+; CHECK-NOV-NEXT: blt a2, a4, .LBB41_2
; CHECK-NOV-NEXT: # %bb.1: # %entry
-; CHECK-NOV-NEXT: mv a3, a5
+; CHECK-NOV-NEXT: mv a2, a4
; CHECK-NOV-NEXT: .LBB41_2: # %entry
; CHECK-NOV-NEXT: neg a6, a6
-; CHECK-NOV-NEXT: and a4, a7, a4
-; CHECK-NOV-NEXT: bge a1, a5, .LBB41_7
+; CHECK-NOV-NEXT: and a5, a7, a5
+; CHECK-NOV-NEXT: bge a1, a4, .LBB41_7
; CHECK-NOV-NEXT: # %bb.3: # %entry
-; CHECK-NOV-NEXT: and a2, a6, a2
-; CHECK-NOV-NEXT: bge a4, a5, .LBB41_8
+; CHECK-NOV-NEXT: and a3, a6, a3
+; CHECK-NOV-NEXT: bge a5, a4, .LBB41_8
; CHECK-NOV-NEXT: .LBB41_4: # %entry
-; CHECK-NOV-NEXT: blt a2, a5, .LBB41_6
+; CHECK-NOV-NEXT: blt a3, a4, .LBB41_6
; CHECK-NOV-NEXT: .LBB41_5: # %entry
-; CHECK-NOV-NEXT: mv a2, a5
+; CHECK-NOV-NEXT: mv a3, a4
; CHECK-NOV-NEXT: .LBB41_6: # %entry
-; CHECK-NOV-NEXT: sh a3, 0(a0)
+; CHECK-NOV-NEXT: sh a2, 0(a0)
; CHECK-NOV-NEXT: sh a1, 2(a0)
-; CHECK-NOV-NEXT: sh a4, 4(a0)
-; CHECK-NOV-NEXT: sh a2, 6(a0)
+; CHECK-NOV-NEXT: sh a5, 4(a0)
+; CHECK-NOV-NEXT: sh a3, 6(a0)
; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB41_7: # %entry
-; CHECK-NOV-NEXT: mv a1, a5
-; CHECK-NOV-NEXT: and a2, a6, a2
-; CHECK-NOV-NEXT: blt a4, a5, .LBB41_4
+; CHECK-NOV-NEXT: mv a1, a4
+; CHECK-NOV-NEXT: and a3, a6, a3
+; CHECK-NOV-NEXT: blt a5, a4, .LBB41_4
; CHECK-NOV-NEXT: .LBB41_8: # %entry
-; CHECK-NOV-NEXT: mv a4, a5
-; CHECK-NOV-NEXT: bge a2, a5, .LBB41_5
+; CHECK-NOV-NEXT: mv a5, a4
+; CHECK-NOV-NEXT: bge a3, a4, .LBB41_5
; CHECK-NOV-NEXT: j .LBB41_6
;
; CHECK-V-LABEL: ustest_f32i16_mm:
@@ -5188,31 +5188,31 @@ define <8 x i16> @utest_f16i16_mm(<8 x half> %x) {
; CHECK-NOV-NEXT: fmv.w.x fa0, s5
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fcvt.lu.s a0, fa0, rtz
-; CHECK-NOV-NEXT: lui a3, 16
-; CHECK-NOV-NEXT: addi a3, a3, -1
-; CHECK-NOV-NEXT: bgeu a0, a3, .LBB43_10
+; CHECK-NOV-NEXT: lui a2, 16
+; CHECK-NOV-NEXT: addi a2, a2, -1
+; CHECK-NOV-NEXT: bgeu a0, a2, .LBB43_10
; CHECK-NOV-NEXT: # %bb.1: # %entry
; CHECK-NOV-NEXT: fcvt.lu.s a1, fs5, rtz
-; CHECK-NOV-NEXT: bgeu s1, a3, .LBB43_11
+; CHECK-NOV-NEXT: bgeu s1, a2, .LBB43_11
; CHECK-NOV-NEXT: .LBB43_2: # %entry
-; CHECK-NOV-NEXT: fcvt.lu.s a2, fs4, rtz
-; CHECK-NOV-NEXT: bgeu a1, a3, .LBB43_12
+; CHECK-NOV-NEXT: fcvt.lu.s a3, fs4, rtz
+; CHECK-NOV-NEXT: bgeu a1, a2, .LBB43_12
; CHECK-NOV-NEXT: .LBB43_3: # %entry
; CHECK-NOV-NEXT: fcvt.lu.s a4, fs3, rtz
-; CHECK-NOV-NEXT: bgeu a2, a3, .LBB43_13
+; CHECK-NOV-NEXT: bgeu a3, a2, .LBB43_13
; CHECK-NOV-NEXT: .LBB43_4: # %entry
; CHECK-NOV-NEXT: fcvt.lu.s a5, fs2, rtz
-; CHECK-NOV-NEXT: bgeu a4, a3, .LBB43_14
+; CHECK-NOV-NEXT: bgeu a4, a2, .LBB43_14
; CHECK-NOV-NEXT: .LBB43_5: # %entry
; CHECK-NOV-NEXT: fcvt.lu.s a6, fs1, rtz
-; CHECK-NOV-NEXT: bgeu a5, a3, .LBB43_15
+; CHECK-NOV-NEXT: bgeu a5, a2, .LBB43_15
; CHECK-NOV-NEXT: .LBB43_6: # %entry
; CHECK-NOV-NEXT: fcvt.lu.s a7, fs0, rtz
-; CHECK-NOV-NEXT: bgeu a6, a3, .LBB43_16
+; CHECK-NOV-NEXT: bgeu a6, a2, .LBB43_16
; CHECK-NOV-NEXT: .LBB43_7: # %entry
-; CHECK-NOV-NEXT: bltu a7, a3, .LBB43_9
+; CHECK-NOV-NEXT: bltu a7, a2, .LBB43_9
; CHECK-NOV-NEXT: .LBB43_8: # %entry
-; CHECK-NOV-NEXT: mv a7, a3
+; CHECK-NOV-NEXT: mv a7, a2
; CHECK-NOV-NEXT: .LBB43_9: # %entry
; CHECK-NOV-NEXT: sh a4, 8(s0)
; CHECK-NOV-NEXT: sh a5, 10(s0)
@@ -5221,7 +5221,7 @@ define <8 x i16> @utest_f16i16_mm(<8 x half> %x) {
; CHECK-NOV-NEXT: sh a0, 0(s0)
; CHECK-NOV-NEXT: sh s1, 2(s0)
; CHECK-NOV-NEXT: sh a1, 4(s0)
-; CHECK-NOV-NEXT: sh a2, 6(s0)
+; CHECK-NOV-NEXT: sh a3, 6(s0)
; CHECK-NOV-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; CHECK-NOV-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; CHECK-NOV-NEXT: ld s1, 104(sp) # 8-byte Folded Reload
@@ -5259,32 +5259,32 @@ define <8 x i16> @utest_f16i16_mm(<8 x half> %x) {
; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB43_10: # %entry
; CHECK-NOV-NEXT: .cfi_restore_state
-; CHECK-NOV-NEXT: mv a0, a3
+; CHECK-NOV-NEXT: mv a0, a2
; CHECK-NOV-NEXT: fcvt.lu.s a1, fs5, rtz
-; CHECK-NOV-NEXT: bltu s1, a3, .LBB43_2
+; CHECK-NOV-NEXT: bltu s1, a2, .LBB43_2
; CHECK-NOV-NEXT: .LBB43_11: # %entry
-; CHECK-NOV-NEXT: mv s1, a3
-; CHECK-NOV-NEXT: fcvt.lu.s a2, fs4, rtz
-; CHECK-NOV-NEXT: bltu a1, a3, .LBB43_3
+; CHECK-NOV-NEXT: mv s1, a2
+; CHECK-NOV-NEXT: fcvt.lu.s a3, fs4, rtz
+; CHECK-NOV-NEXT: bltu a1, a2, .LBB43_3
; CHECK-NOV-NEXT: .LBB43_12: # %entry
-; CHECK-NOV-NEXT: mv a1, a3
+; CHECK-NOV-NEXT: mv a1, a2
; CHECK-NOV-NEXT: fcvt.lu.s a4, fs3, rtz
-; CHECK-NOV-NEXT: bltu a2, a3, .LBB43_4
+; CHECK-NOV-NEXT: bltu a3, a2, .LBB43_4
; CHECK-NOV-NEXT: .LBB43_13: # %entry
-; CHECK-NOV-NEXT: mv a2, a3
+; CHECK-NOV-NEXT: mv a3, a2
; CHECK-NOV-NEXT: fcvt.lu.s a5, fs2, rtz
-; CHECK-NOV-NEXT: bltu a4, a3, .LBB43_5
+; CHECK-NOV-NEXT: bltu a4, a2, .LBB43_5
; CHECK-NOV-NEXT: .LBB43_14: # %entry
-; CHECK-NOV-NEXT: mv a4, a3
+; CHECK-NOV-NEXT: mv a4, a2
; CHECK-NOV-NEXT: fcvt.lu.s a6, fs1, rtz
-; CHECK-NOV-NEXT: bltu a5, a3, .LBB43_6
+; CHECK-NOV-NEXT: bltu a5, a2, .LBB43_6
; CHECK-NOV-NEXT: .LBB43_15: # %entry
-; CHECK-NOV-NEXT: mv a5, a3
+; CHECK-NOV-NEXT: mv a5, a2
; CHECK-NOV-NEXT: fcvt.lu.s a7, fs0, rtz
-; CHECK-NOV-NEXT: bltu a6, a3, .LBB43_7
+; CHECK-NOV-NEXT: bltu a6, a2, .LBB43_7
; CHECK-NOV-NEXT: .LBB43_16: # %entry
-; CHECK-NOV-NEXT: mv a6, a3
-; CHECK-NOV-NEXT: bgeu a7, a3, .LBB43_8
+; CHECK-NOV-NEXT: mv a6, a2
+; CHECK-NOV-NEXT: bgeu a7, a2, .LBB43_8
; CHECK-NOV-NEXT: j .LBB43_9
;
; CHECK-V-LABEL: utest_f16i16_mm:
diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
index 4b4d4dd0fa4d1..c66e22b724c97 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
@@ -1457,19 +1457,19 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_fmul_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fmul_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: bgeu a2, a3, .LBB26_2
+; CHECK-NEXT: li a1, 1024
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: bgeu a1, a3, .LBB26_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB26_5
; CHECK-NEXT: .LBB26_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB26_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1477,12 +1477,12 @@ define void @sink_splat_fmul_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB26_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB26_7
; CHECK-NEXT: .LBB26_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -1547,19 +1547,19 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_fdiv_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fdiv_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: bgeu a2, a3, .LBB27_2
+; CHECK-NEXT: li a1, 1024
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: bgeu a1, a3, .LBB27_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB27_5
; CHECK-NEXT: .LBB27_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB27_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1567,12 +1567,12 @@ define void @sink_splat_fdiv_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB27_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB27_7
; CHECK-NEXT: .LBB27_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -1637,19 +1637,19 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_frdiv_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_frdiv_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: bgeu a2, a3, .LBB28_2
+; CHECK-NEXT: li a1, 1024
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: bgeu a1, a3, .LBB28_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB28_5
; CHECK-NEXT: .LBB28_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB28_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1657,12 +1657,12 @@ define void @sink_splat_frdiv_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: vfrdiv.vf v8, v8, fa0
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB28_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB28_7
; CHECK-NEXT: .LBB28_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -1727,19 +1727,19 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fadd_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: bgeu a2, a3, .LBB29_2
+; CHECK-NEXT: li a1, 1024
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: bgeu a1, a3, .LBB29_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB29_5
; CHECK-NEXT: .LBB29_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB29_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1747,12 +1747,12 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB29_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB29_7
; CHECK-NEXT: .LBB29_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -1817,19 +1817,19 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_fsub_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fsub_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: bgeu a2, a3, .LBB30_2
+; CHECK-NEXT: li a1, 1024
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: bgeu a1, a3, .LBB30_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB30_5
; CHECK-NEXT: .LBB30_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB30_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1837,12 +1837,12 @@ define void @sink_splat_fsub_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB30_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB30_7
; CHECK-NEXT: .LBB30_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -1907,19 +1907,19 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_frsub_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_frsub_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: bgeu a2, a3, .LBB31_2
+; CHECK-NEXT: li a1, 1024
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: bgeu a1, a3, .LBB31_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB31_5
; CHECK-NEXT: .LBB31_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB31_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1927,12 +1927,12 @@ define void @sink_splat_frsub_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: vfrsub.vf v8, v8, fa0
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB31_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB31_7
; CHECK-NEXT: .LBB31_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -2073,20 +2073,20 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_fma_scalable(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, float %x) {
; CHECK-LABEL: sink_splat_fma_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a4, a2, 2
-; CHECK-NEXT: li a3, 1024
-; CHECK-NEXT: bgeu a3, a4, .LBB34_2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: srli a4, a3, 2
+; CHECK-NEXT: li a2, 1024
+; CHECK-NEXT: bgeu a2, a4, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a3, 0
+; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB34_5
; CHECK-NEXT: .LBB34_2: # %vector.ph
-; CHECK-NEXT: addi a3, a4, -1
-; CHECK-NEXT: andi a5, a3, 1024
-; CHECK-NEXT: xori a3, a5, 1024
+; CHECK-NEXT: addi a2, a4, -1
+; CHECK-NEXT: andi a5, a2, 1024
+; CHECK-NEXT: xori a2, a5, 1024
; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: mv a7, a1
-; CHECK-NEXT: mv t0, a3
+; CHECK-NEXT: mv t0, a2
; CHECK-NEXT: vsetvli t1, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB34_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -2095,13 +2095,13 @@ define void @sink_splat_fma_scalable(ptr noalias nocapture %a, ptr noalias nocap
; CHECK-NEXT: vfmacc.vf v9, fa0, v8
; CHECK-NEXT: sub t0, t0, a4
; CHECK-NEXT: vs1r.v v9, (a6)
-; CHECK-NEXT: add a7, a7, a2
-; CHECK-NEXT: add a6, a6, a2
+; CHECK-NEXT: add a7, a7, a3
+; CHECK-NEXT: add a6, a6, a3
; CHECK-NEXT: bnez t0, .LBB34_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a5, .LBB34_7
; CHECK-NEXT: .LBB34_5: # %for.body.preheader
-; CHECK-NEXT: slli a2, a3, 2
+; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: lui a3, 1
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: add a2, a1, a2
@@ -2173,20 +2173,20 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_fma_commute_scalable(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, float %x) {
; CHECK-LABEL: sink_splat_fma_commute_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a4, a2, 2
-; CHECK-NEXT: li a3, 1024
-; CHECK-NEXT: bgeu a3, a4, .LBB35_2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: srli a4, a3, 2
+; CHECK-NEXT: li a2, 1024
+; CHECK-NEXT: bgeu a2, a4, .LBB35_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a3, 0
+; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB35_5
; CHECK-NEXT: .LBB35_2: # %vector.ph
-; CHECK-NEXT: addi a3, a4, -1
-; CHECK-NEXT: andi a5, a3, 1024
-; CHECK-NEXT: xori a3, a5, 1024
+; CHECK-NEXT: addi a2, a4, -1
+; CHECK-NEXT: andi a5, a2, 1024
+; CHECK-NEXT: xori a2, a5, 1024
; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: mv a7, a1
-; CHECK-NEXT: mv t0, a3
+; CHECK-NEXT: mv t0, a2
; CHECK-NEXT: vsetvli t1, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB35_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -2195,13 +2195,13 @@ define void @sink_splat_fma_commute_scalable(ptr noalias nocapture %a, ptr noali
; CHECK-NEXT: vfmacc.vf v9, fa0, v8
; CHECK-NEXT: sub t0, t0, a4
; CHECK-NEXT: vs1r.v v9, (a6)
-; CHECK-NEXT: add a7, a7, a2
-; CHECK-NEXT: add a6, a6, a2
+; CHECK-NEXT: add a7, a7, a3
+; CHECK-NEXT: add a6, a6, a3
; CHECK-NEXT: bnez t0, .LBB35_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a5, .LBB35_7
; CHECK-NEXT: .LBB35_5: # %for.body.preheader
-; CHECK-NEXT: slli a2, a3, 2
+; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: lui a3, 1
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: add a2, a1, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll b/llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
index 65def512bc473..0bd98ae0a642c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
@@ -480,16 +480,16 @@ define i8 @pr187458(<vscale x 64 x i8> %0, <vscale x 64 x i1> %mask) {
; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vx v0, v0, a3
; RV32-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV32-NEXT: vcpop.m a2, v0
-; RV32-NEXT: slli a1, a0, 1
-; RV32-NEXT: bnez a2, .LBB13_2
+; RV32-NEXT: vcpop.m a1, v0
+; RV32-NEXT: slli a2, a0, 1
+; RV32-NEXT: bnez a1, .LBB13_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vmerge.vvm v24, v8, v24, v0
; RV32-NEXT: vredmaxu.vs v24, v24, v24
-; RV32-NEXT: vmv.x.s a2, v24
+; RV32-NEXT: vmv.x.s a1, v24
; RV32-NEXT: j .LBB13_3
; RV32-NEXT: .LBB13_2:
; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -497,8 +497,8 @@ define i8 @pr187458(<vscale x 64 x i8> %0, <vscale x 64 x i1> %mask) {
; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vmerge.vvm v24, v16, v24, v0
; RV32-NEXT: vredmaxu.vs v24, v24, v24
-; RV32-NEXT: vmv.x.s a2, v24
-; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vmv.x.s a1, v24
+; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: .LBB13_3: # %entry
; RV32-NEXT: srli a4, a0, 1
; RV32-NEXT: vsetvli a5, zero, e8, m1, ta, ma
@@ -514,7 +514,7 @@ define i8 @pr187458(<vscale x 64 x i8> %0, <vscale x 64 x i1> %mask) {
; RV32-NEXT: vid.v v16
; RV32-NEXT: vmerge.vvm v16, v8, v16, v0
; RV32-NEXT: vredmaxu.vs v16, v16, v16
-; RV32-NEXT: vmv.x.s a1, v16
+; RV32-NEXT: vmv.x.s a2, v16
; RV32-NEXT: j .LBB13_6
; RV32-NEXT: .LBB13_5:
; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -522,19 +522,19 @@ define i8 @pr187458(<vscale x 64 x i8> %0, <vscale x 64 x i1> %mask) {
; RV32-NEXT: vmerge.vvm v16, v8, v16, v0
; RV32-NEXT: vredmaxu.vs v16, v16, v16
; RV32-NEXT: vmv.x.s a3, v16
-; RV32-NEXT: add a1, a3, a1
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: .LBB13_6: # %entry
; RV32-NEXT: vsetvli a3, zero, e8, m4, ta, ma
; RV32-NEXT: vcpop.m a3, v6
; RV32-NEXT: beqz a3, .LBB13_8
; RV32-NEXT: # %bb.7:
; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: add a2, a1, a0
+; RV32-NEXT: add a1, a2, a0
; RV32-NEXT: .LBB13_8: # %entry
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; RV32-NEXT: vslidedown.vx v8, v8, a2
+; RV32-NEXT: vslidedown.vx v8, v8, a1
; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-NEXT: vcpop.m a0, v7
; RV32-NEXT: vmv.x.s a1, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpload.ll b/llvm/test/CodeGen/RISCV/rvv/vpload.ll
index 7c4acbe74ce3c..1503db34dce8d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpload.ll
@@ -488,45 +488,45 @@ define <vscale x 16 x double> @vpload_nxv17f64(ptr %ptr, ptr %out, <vscale x 17
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a5, a3, 1
-; CHECK-NEXT: mv a4, a2
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a5, a4, 1
+; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: bltu a2, a5, .LBB45_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a4, a5
+; CHECK-NEXT: mv a3, a5
; CHECK-NEXT: .LBB45_2:
-; CHECK-NEXT: sub a6, a4, a3
-; CHECK-NEXT: srli a7, a3, 3
+; CHECK-NEXT: sub a6, a3, a4
+; CHECK-NEXT: srli a7, a4, 3
; CHECK-NEXT: sub a5, a2, a5
-; CHECK-NEXT: sltu t0, a4, a6
+; CHECK-NEXT: sltu t0, a3, a6
; CHECK-NEXT: vsetvli t1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a7
; CHECK-NEXT: sltu a2, a2, a5
; CHECK-NEXT: addi t0, t0, -1
; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: slli a7, a3, 3
+; CHECK-NEXT: slli a7, a4, 3
; CHECK-NEXT: and a2, a2, a5
; CHECK-NEXT: and a6, t0, a6
; CHECK-NEXT: add a5, a0, a7
-; CHECK-NEXT: bltu a2, a3, .LBB45_4
+; CHECK-NEXT: bltu a2, a4, .LBB45_4
; CHECK-NEXT: # %bb.3:
-; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: mv a2, a4
; CHECK-NEXT: .LBB45_4:
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a5), v0.t
-; CHECK-NEXT: srli a5, a3, 2
+; CHECK-NEXT: srli a5, a4, 2
; CHECK-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a5
-; CHECK-NEXT: slli a5, a3, 4
+; CHECK-NEXT: slli a5, a4, 4
; CHECK-NEXT: add a5, a0, a5
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a5), v0.t
-; CHECK-NEXT: bltu a4, a3, .LBB45_6
+; CHECK-NEXT: bltu a3, a4, .LBB45_6
; CHECK-NEXT: # %bb.5:
-; CHECK-NEXT: mv a4, a3
+; CHECK-NEXT: mv a3, a4
; CHECK-NEXT: .LBB45_6:
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0), v0.t
; CHECK-NEXT: vs1r.v v24, (a1)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/smulh.ll b/llvm/test/CodeGen/RISCV/smulh.ll
index 642162bad17af..48d84223cffe6 100644
--- a/llvm/test/CodeGen/RISCV/smulh.ll
+++ b/llvm/test/CodeGen/RISCV/smulh.ll
@@ -4474,21 +4474,21 @@ define <2 x i128> @smulh_v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; RV32M-NEXT: .LBB15_2:
; RV32M-NEXT: mulhu t5, a3, t2
; RV32M-NEXT: mul s0, a4, t2
-; RV32M-NEXT: mulhu s1, a4, t2
+; RV32M-NEXT: mulhu s2, a4, t2
; RV32M-NEXT: mul s4, a3, t1
; RV32M-NEXT: mulhu s5, a3, t1
; RV32M-NEXT: mul s6, a4, t1
; RV32M-NEXT: add t5, s0, t5
-; RV32M-NEXT: srai s2, t1, 31
+; RV32M-NEXT: srai s1, t1, 31
; RV32M-NEXT: sltu s0, t5, s0
; RV32M-NEXT: mulhu s7, a4, t1
-; RV32M-NEXT: add s0, s1, s0
-; RV32M-NEXT: mul s1, s2, a3
+; RV32M-NEXT: add s0, s2, s0
+; RV32M-NEXT: mul s2, s1, a3
; RV32M-NEXT: add t5, s4, t5
-; RV32M-NEXT: mul s8, s2, a4
+; RV32M-NEXT: mul s8, s1, a4
; RV32M-NEXT: sltu a4, t5, s4
; RV32M-NEXT: add s5, s5, a4
-; RV32M-NEXT: mulhu s4, s2, a3
+; RV32M-NEXT: mulhu s4, s1, a3
; RV32M-NEXT: add a4, a6, t6
; RV32M-NEXT: mul t6, a3, t2
; RV32M-NEXT: sltu s9, a4, a6
@@ -4496,26 +4496,26 @@ define <2 x i128> @smulh_v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; RV32M-NEXT: sltu a3, s5, s0
; RV32M-NEXT: add s5, s6, s5
; RV32M-NEXT: add s7, s7, a3
-; RV32M-NEXT: add a3, s5, s1
+; RV32M-NEXT: add a3, s5, s2
; RV32M-NEXT: sltu a6, s5, s6
; RV32M-NEXT: sltu s0, a3, s5
; RV32M-NEXT: add a6, s7, a6
; RV32M-NEXT: add s4, s4, s8
-; RV32M-NEXT: add s1, s4, s1
+; RV32M-NEXT: add s2, s4, s2
; RV32M-NEXT: add a5, t6, a5
; RV32M-NEXT: add t4, t5, t4
; RV32M-NEXT: sltu a5, a5, t6
-; RV32M-NEXT: add s1, a6, s1
+; RV32M-NEXT: add s2, a6, s2
; RV32M-NEXT: add a6, t4, a5
; RV32M-NEXT: add s3, s3, s9
-; RV32M-NEXT: add s8, s1, s0
+; RV32M-NEXT: add s8, s2, s0
; RV32M-NEXT: beq a6, t5, .LBB15_4
; RV32M-NEXT: # %bb.3:
; RV32M-NEXT: sltu a5, a6, t5
; RV32M-NEXT: .LBB15_4:
; RV32M-NEXT: mulhu s9, t0, t2
; RV32M-NEXT: mul s5, a7, t2
-; RV32M-NEXT: mul s7, t0, t1
+; RV32M-NEXT: mul s6, t0, t1
; RV32M-NEXT: mul t4, t0, t2
; RV32M-NEXT: add a5, a3, a5
; RV32M-NEXT: sltu a3, a5, a3
@@ -4525,7 +4525,7 @@ define <2 x i128> @smulh_v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; RV32M-NEXT: sltu s4, a3, a4
; RV32M-NEXT: add a6, a6, s4
; RV32M-NEXT: add s9, s5, s9
-; RV32M-NEXT: add s10, s7, s9
+; RV32M-NEXT: add s10, s6, s9
; RV32M-NEXT: add a3, t4, a3
; RV32M-NEXT: add a4, s10, a6
; RV32M-NEXT: sw a3, 4(sp) # 4-byte Folded Spill
@@ -4537,7 +4537,7 @@ define <2 x i128> @smulh_v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; RV32M-NEXT: .LBB15_6:
; RV32M-NEXT: sw a4, 0(sp) # 4-byte Folded Spill
; RV32M-NEXT: lw s0, 16(a2)
-; RV32M-NEXT: lw s1, 20(a2)
+; RV32M-NEXT: lw s2, 20(a2)
; RV32M-NEXT: lw t4, 16(a1)
; RV32M-NEXT: lw t5, 20(a1)
; RV32M-NEXT: lw a5, 24(a1)
@@ -4550,141 +4550,141 @@ define <2 x i128> @smulh_v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; RV32M-NEXT: mulhu ra, t0, t1
; RV32M-NEXT: mul a3, a7, t1
; RV32M-NEXT: mul a4, t2, t3
-; RV32M-NEXT: mul s6, s2, t0
+; RV32M-NEXT: mul s7, s1, t0
; RV32M-NEXT: lw a6, 24(a2)
; RV32M-NEXT: lw a2, 28(a2)
; RV32M-NEXT: srai s3, s3, 31
; RV32M-NEXT: srai s8, s8, 31
; RV32M-NEXT: sltu s5, s9, s5
-; RV32M-NEXT: sltu s7, s10, s7
+; RV32M-NEXT: sltu s6, s10, s6
; RV32M-NEXT: mulhu s9, t2, t3
; RV32M-NEXT: add s5, s11, s5
-; RV32M-NEXT: add s7, ra, s7
+; RV32M-NEXT: add s6, ra, s6
; RV32M-NEXT: add s8, s3, s8
-; RV32M-NEXT: add s7, s5, s7
-; RV32M-NEXT: add s10, s6, a4
-; RV32M-NEXT: add s11, a3, s7
+; RV32M-NEXT: add s6, s5, s6
+; RV32M-NEXT: add s10, s7, a4
+; RV32M-NEXT: add s11, a3, s6
; RV32M-NEXT: add s4, s8, s4
; RV32M-NEXT: add t2, s11, s10
; RV32M-NEXT: sltu s3, s8, s3
; RV32M-NEXT: mul ra, t1, t3
; RV32M-NEXT: add t3, s8, s3
; RV32M-NEXT: sltu s3, s4, s8
-; RV32M-NEXT: mul s8, s2, a7
-; RV32M-NEXT: mulhu t6, s2, t0
+; RV32M-NEXT: mul s8, s1, a7
+; RV32M-NEXT: mulhu t6, s1, t0
; RV32M-NEXT: add t0, t2, s4
; RV32M-NEXT: add t3, t3, s3
-; RV32M-NEXT: sltu s2, t2, s11
+; RV32M-NEXT: sltu s1, t2, s11
; RV32M-NEXT: mulhu a7, a7, t1
; RV32M-NEXT: sltu a3, s11, a3
; RV32M-NEXT: add a4, s9, a4
-; RV32M-NEXT: sltu t1, s7, s5
+; RV32M-NEXT: sltu t1, s6, s5
; RV32M-NEXT: add a4, a4, ra
; RV32M-NEXT: mulhu s3, a5, s0
; RV32M-NEXT: mul s4, a1, s0
; RV32M-NEXT: add t6, t6, s8
-; RV32M-NEXT: mul s5, a5, s1
-; RV32M-NEXT: add t6, t6, s6
-; RV32M-NEXT: mulhu s7, a1, s0
+; RV32M-NEXT: mul s5, a5, s2
+; RV32M-NEXT: add t6, t6, s7
+; RV32M-NEXT: mulhu s6, a1, s0
; RV32M-NEXT: add a7, a7, t1
; RV32M-NEXT: add a4, t6, a4
-; RV32M-NEXT: sltu t1, s10, s6
-; RV32M-NEXT: mulhu t6, a5, s1
+; RV32M-NEXT: sltu t1, s10, s7
+; RV32M-NEXT: mulhu t6, a5, s2
; RV32M-NEXT: add a3, a7, a3
; RV32M-NEXT: add a4, a4, t1
; RV32M-NEXT: add s3, s4, s3
-; RV32M-NEXT: mul s6, a1, s1
+; RV32M-NEXT: mul s7, a1, s2
; RV32M-NEXT: sltu a7, s3, s4
; RV32M-NEXT: add s4, s5, s3
-; RV32M-NEXT: add s7, s7, a7
+; RV32M-NEXT: add s6, s6, a7
; RV32M-NEXT: sltu t1, s4, s5
; RV32M-NEXT: srai a7, a1, 31
-; RV32M-NEXT: mulhu s3, a1, s1
+; RV32M-NEXT: mulhu s3, a1, s2
; RV32M-NEXT: add t6, t6, t1
; RV32M-NEXT: mul s5, s0, a7
; RV32M-NEXT: add t1, a3, a4
-; RV32M-NEXT: add t6, s7, t6
-; RV32M-NEXT: add a3, s6, t6
+; RV32M-NEXT: add t6, s6, t6
+; RV32M-NEXT: add a3, s7, t6
; RV32M-NEXT: mulhu a4, s0, a7
; RV32M-NEXT: mulhu s8, t4, s0
; RV32M-NEXT: mul s9, t5, s0
-; RV32M-NEXT: sltu s6, a3, s6
-; RV32M-NEXT: sltu t6, t6, s7
+; RV32M-NEXT: sltu s7, a3, s7
+; RV32M-NEXT: sltu t6, t6, s6
; RV32M-NEXT: add t6, s3, t6
-; RV32M-NEXT: mul s7, t4, s1
+; RV32M-NEXT: mul s6, t4, s2
; RV32M-NEXT: add s3, a3, s5
-; RV32M-NEXT: add t6, t6, s6
-; RV32M-NEXT: mulhu s6, t5, s0
-; RV32M-NEXT: mulhu s10, t4, s1
+; RV32M-NEXT: add t6, t6, s7
+; RV32M-NEXT: mulhu s7, t5, s0
+; RV32M-NEXT: mulhu s10, t4, s2
; RV32M-NEXT: add a4, a4, s5
-; RV32M-NEXT: mul s5, s1, a7
+; RV32M-NEXT: mul s5, s2, a7
; RV32M-NEXT: add s8, s9, s8
-; RV32M-NEXT: mul s11, t5, s1
+; RV32M-NEXT: mul s11, t5, s2
; RV32M-NEXT: sltu s9, s8, s9
-; RV32M-NEXT: mulhu s1, t5, s1
-; RV32M-NEXT: add s8, s7, s8
+; RV32M-NEXT: mulhu s2, t5, s2
+; RV32M-NEXT: add s8, s6, s8
; RV32M-NEXT: mul s0, a5, s0
; RV32M-NEXT: sltu a3, s3, a3
-; RV32M-NEXT: sltu s7, s8, s7
-; RV32M-NEXT: add s6, s6, s9
-; RV32M-NEXT: add s7, s10, s7
+; RV32M-NEXT: sltu s6, s8, s6
+; RV32M-NEXT: add s7, s7, s9
+; RV32M-NEXT: add s6, s10, s6
; RV32M-NEXT: add a4, a4, s5
-; RV32M-NEXT: add s7, s6, s7
-; RV32M-NEXT: add s5, s11, s7
-; RV32M-NEXT: sltu s6, s7, s6
+; RV32M-NEXT: add s6, s7, s6
+; RV32M-NEXT: add s5, s11, s6
+; RV32M-NEXT: sltu s6, s6, s7
; RV32M-NEXT: sltu s7, s5, s11
-; RV32M-NEXT: add s1, s1, s6
-; RV32M-NEXT: add s1, s1, s7
-; RV32M-NEXT: add s5, s0, s5
-; RV32M-NEXT: add s1, s4, s1
-; RV32M-NEXT: sltu s7, s5, s0
+; RV32M-NEXT: add s2, s2, s6
+; RV32M-NEXT: add s7, s2, s7
+; RV32M-NEXT: add s2, s0, s5
+; RV32M-NEXT: add s5, s4, s7
+; RV32M-NEXT: sltu s6, s2, s0
; RV32M-NEXT: add a4, t6, a4
-; RV32M-NEXT: add s6, s1, s7
-; RV32M-NEXT: add s0, s2, t3
+; RV32M-NEXT: add s5, s5, s6
+; RV32M-NEXT: add s0, s1, t3
; RV32M-NEXT: add t3, a4, a3
-; RV32M-NEXT: beq s6, s4, .LBB15_10
+; RV32M-NEXT: beq s5, s4, .LBB15_10
; RV32M-NEXT: # %bb.9:
-; RV32M-NEXT: sltu s7, s6, s4
+; RV32M-NEXT: sltu s6, s5, s4
; RV32M-NEXT: .LBB15_10:
; RV32M-NEXT: mulhu a3, t4, a6
; RV32M-NEXT: mul a4, t5, a6
-; RV32M-NEXT: mulhu s2, t5, a6
-; RV32M-NEXT: mul s8, t4, a2
+; RV32M-NEXT: mulhu s4, t5, a6
+; RV32M-NEXT: mul s7, t4, a2
; RV32M-NEXT: add t6, t0, a0
; RV32M-NEXT: add s0, t1, s0
; RV32M-NEXT: sltu s1, t0, t2
; RV32M-NEXT: mulhu a0, t4, a2
-; RV32M-NEXT: mul s9, t5, a2
+; RV32M-NEXT: mul s8, t5, a2
; RV32M-NEXT: add a3, a4, a3
; RV32M-NEXT: srai t1, a2, 31
; RV32M-NEXT: sltu a4, a3, a4
-; RV32M-NEXT: mulhu s10, t5, a2
-; RV32M-NEXT: add a4, s2, a4
-; RV32M-NEXT: mul s2, t1, t4
-; RV32M-NEXT: add s4, s8, a3
+; RV32M-NEXT: mulhu s9, t5, a2
+; RV32M-NEXT: add a4, s4, a4
+; RV32M-NEXT: mul s10, t1, t4
+; RV32M-NEXT: add s4, s7, a3
; RV32M-NEXT: mul a3, t1, t5
-; RV32M-NEXT: sltu t2, s4, s8
+; RV32M-NEXT: sltu t2, s4, s7
; RV32M-NEXT: add a0, a0, t2
; RV32M-NEXT: mulhu t5, t1, t4
-; RV32M-NEXT: add t2, s3, s7
-; RV32M-NEXT: mul s7, t4, a6
-; RV32M-NEXT: sltu s8, t2, s3
+; RV32M-NEXT: add t2, s3, s6
+; RV32M-NEXT: mul s6, t4, a6
+; RV32M-NEXT: sltu s7, t2, s3
; RV32M-NEXT: add a0, a4, a0
; RV32M-NEXT: sltu a4, a0, a4
-; RV32M-NEXT: add a0, s9, a0
-; RV32M-NEXT: add a4, s10, a4
-; RV32M-NEXT: add t4, a0, s2
-; RV32M-NEXT: sltu s3, a0, s9
+; RV32M-NEXT: add a0, s8, a0
+; RV32M-NEXT: add a4, s9, a4
+; RV32M-NEXT: add t4, a0, s10
+; RV32M-NEXT: sltu s3, a0, s8
; RV32M-NEXT: sltu a0, t4, a0
; RV32M-NEXT: add a4, a4, s3
; RV32M-NEXT: add a3, t5, a3
-; RV32M-NEXT: add a3, a3, s2
-; RV32M-NEXT: add s5, s7, s5
-; RV32M-NEXT: add s3, s4, s6
-; RV32M-NEXT: sltu t5, s5, s7
+; RV32M-NEXT: add a3, a3, s10
+; RV32M-NEXT: add s2, s6, s2
+; RV32M-NEXT: add s3, s4, s5
+; RV32M-NEXT: sltu t5, s2, s6
; RV32M-NEXT: add a3, a4, a3
; RV32M-NEXT: add s3, s3, t5
-; RV32M-NEXT: add s2, t3, s8
+; RV32M-NEXT: add s2, t3, s7
; RV32M-NEXT: add s5, a3, a0
; RV32M-NEXT: beq s3, s4, .LBB15_12
; RV32M-NEXT: # %bb.11:
diff --git a/llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll b/llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll
index 5a0a590a23561..7fcf571d4a23d 100644
--- a/llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll
+++ b/llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll
@@ -267,17 +267,17 @@ define double @select_f64_fcmp(double %a, double %b, double %c, double %d) nounw
; RV32ZFINX_NOZICOND-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32ZFINX_NOZICOND-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32ZFINX_NOZICOND-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32ZFINX_NOZICOND-NEXT: mv s1, a7
+; RV32ZFINX_NOZICOND-NEXT: mv s2, a7
; RV32ZFINX_NOZICOND-NEXT: mv s3, a6
; RV32ZFINX_NOZICOND-NEXT: mv s0, a5
-; RV32ZFINX_NOZICOND-NEXT: mv s2, a4
+; RV32ZFINX_NOZICOND-NEXT: mv s1, a4
; RV32ZFINX_NOZICOND-NEXT: call __gtdf2
; RV32ZFINX_NOZICOND-NEXT: bgtz a0, .LBB2_2
; RV32ZFINX_NOZICOND-NEXT: # %bb.1: # %entry
-; RV32ZFINX_NOZICOND-NEXT: mv s2, s3
-; RV32ZFINX_NOZICOND-NEXT: mv s0, s1
+; RV32ZFINX_NOZICOND-NEXT: mv s1, s3
+; RV32ZFINX_NOZICOND-NEXT: mv s0, s2
; RV32ZFINX_NOZICOND-NEXT: .LBB2_2: # %entry
-; RV32ZFINX_NOZICOND-NEXT: mv a0, s2
+; RV32ZFINX_NOZICOND-NEXT: mv a0, s1
; RV32ZFINX_NOZICOND-NEXT: mv a1, s0
; RV32ZFINX_NOZICOND-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32ZFINX_NOZICOND-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
index 40e90d6bdd6af..67d390fdf192b 100644
--- a/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
+++ b/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
@@ -11,13 +11,13 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
; SPARC-NEXT: mov %i2, %g4
; SPARC-NEXT: umul %i2, %i5, %i2
; SPARC-NEXT: rd %y, %l7
-; SPARC-NEXT: ld [%fp+92], %l4
+; SPARC-NEXT: ld [%fp+92], %l5
; SPARC-NEXT: umul %i4, %i3, %i3
; SPARC-NEXT: rd %y, %o1
; SPARC-NEXT: ld [%fp+96], %g3
; SPARC-NEXT: umul %i5, %g2, %l3
; SPARC-NEXT: rd %y, %o0
-; SPARC-NEXT: umul %l4, %i1, %l2
+; SPARC-NEXT: umul %l5, %i1, %l2
; SPARC-NEXT: rd %y, %l1
; SPARC-NEXT: add %i3, %i2, %i2
; SPARC-NEXT: umul %i0, %g3, %i3
@@ -32,20 +32,20 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
; SPARC-NEXT: rd %y, %i2
; SPARC-NEXT: addxcc %l2, %o2, %o4
; SPARC-NEXT: umul %g4, %g3, %g3
-; SPARC-NEXT: rd %y, %l5
+; SPARC-NEXT: rd %y, %l4
; SPARC-NEXT: addcc %g3, %i2, %i2
-; SPARC-NEXT: addxcc %l5, 0, %g3
-; SPARC-NEXT: umul %g2, %l4, %g2
-; SPARC-NEXT: rd %y, %l5
+; SPARC-NEXT: addxcc %l4, 0, %g3
+; SPARC-NEXT: umul %g2, %l5, %g2
+; SPARC-NEXT: rd %y, %l4
; SPARC-NEXT: addcc %g2, %i2, %i2
-; SPARC-NEXT: addxcc %l5, 0, %g2
+; SPARC-NEXT: addxcc %l4, 0, %g2
; SPARC-NEXT: addcc %g3, %g2, %g2
; SPARC-NEXT: addxcc %g0, 0, %g3
-; SPARC-NEXT: umul %g4, %l4, %l5
+; SPARC-NEXT: umul %g4, %l5, %l4
; SPARC-NEXT: rd %y, %o3
-; SPARC-NEXT: addcc %l5, %g2, %l5
+; SPARC-NEXT: addcc %l4, %g2, %l4
; SPARC-NEXT: addxcc %o3, %g3, %o3
-; SPARC-NEXT: addcc %l5, %l3, %g2
+; SPARC-NEXT: addcc %l4, %l3, %g2
; SPARC-NEXT: addxcc %o3, %o4, %g3
; SPARC-NEXT: mov 1, %l3
; SPARC-NEXT: cmp %g3, %o3
@@ -54,17 +54,17 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
; SPARC-NEXT: ! %bb.1: ! %start
; SPARC-NEXT: mov %g0, %o4
; SPARC-NEXT: .LBB0_2: ! %start
-; SPARC-NEXT: cmp %g2, %l5
+; SPARC-NEXT: cmp %g2, %l4
; SPARC-NEXT: bcs .LBB0_4
-; SPARC-NEXT: mov %l3, %l5
+; SPARC-NEXT: mov %l3, %l4
; SPARC-NEXT: ! %bb.3: ! %start
-; SPARC-NEXT: mov %g0, %l5
+; SPARC-NEXT: mov %g0, %l4
; SPARC-NEXT: .LBB0_4: ! %start
; SPARC-NEXT: cmp %g3, %o3
; SPARC-NEXT: be .LBB0_6
; SPARC-NEXT: nop
; SPARC-NEXT: ! %bb.5: ! %start
-; SPARC-NEXT: mov %o4, %l5
+; SPARC-NEXT: mov %o4, %l4
; SPARC-NEXT: .LBB0_6: ! %start
; SPARC-NEXT: cmp %g4, 0
; SPARC-NEXT: bne .LBB0_8
@@ -96,11 +96,11 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
; SPARC-NEXT: ! %bb.15: ! %start
; SPARC-NEXT: mov %g0, %g4
; SPARC-NEXT: .LBB0_16: ! %start
-; SPARC-NEXT: cmp %l4, 0
+; SPARC-NEXT: cmp %l5, 0
; SPARC-NEXT: bne .LBB0_18
-; SPARC-NEXT: mov %l3, %l4
+; SPARC-NEXT: mov %l3, %l5
; SPARC-NEXT: ! %bb.17: ! %start
-; SPARC-NEXT: mov %g0, %l4
+; SPARC-NEXT: mov %g0, %l5
; SPARC-NEXT: .LBB0_18: ! %start
; SPARC-NEXT: cmp %i0, 0
; SPARC-NEXT: bne .LBB0_20
@@ -116,13 +116,13 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
; SPARC-NEXT: .LBB0_22: ! %start
; SPARC-NEXT: and %o4, %o3, %o2
; SPARC-NEXT: cmp %l1, 0
-; SPARC-NEXT: and %o0, %l4, %o0
+; SPARC-NEXT: and %o0, %l5, %o0
; SPARC-NEXT: bne .LBB0_24
; SPARC-NEXT: mov %l3, %l1
; SPARC-NEXT: ! %bb.23: ! %start
; SPARC-NEXT: mov %g0, %l1
; SPARC-NEXT: .LBB0_24: ! %start
-; SPARC-NEXT: or %o2, %o1, %l4
+; SPARC-NEXT: or %o2, %o1, %l5
; SPARC-NEXT: cmp %l2, %l0
; SPARC-NEXT: or %o0, %l6, %l6
; SPARC-NEXT: bcs .LBB0_26
@@ -130,7 +130,7 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
; SPARC-NEXT: ! %bb.25: ! %start
; SPARC-NEXT: mov %g0, %l0
; SPARC-NEXT: .LBB0_26: ! %start
-; SPARC-NEXT: or %l4, %l7, %l2
+; SPARC-NEXT: or %l5, %l7, %l2
; SPARC-NEXT: orcc %i5, %i4, %g0
; SPARC-NEXT: or %l6, %l1, %l1
; SPARC-NEXT: bne .LBB0_28
@@ -148,7 +148,7 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
; SPARC-NEXT: and %l3, %i4, %i1
; SPARC-NEXT: or %i1, %i0, %i0
; SPARC-NEXT: or %i0, %i5, %i0
-; SPARC-NEXT: or %i0, %l5, %i0
+; SPARC-NEXT: or %i0, %l4, %i0
; SPARC-NEXT: and %i0, 1, %i4
; SPARC-NEXT: mov %g3, %i0
; SPARC-NEXT: ret
diff --git a/llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll b/llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll
index 66b5d76fd9871..f30a4ef9088bc 100644
--- a/llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll
@@ -49,7 +49,7 @@ define void @fun0(ptr %Src, ptr %Dst) {
; CHECK-NEXT: ldgr %f10, %r0
; CHECK-NEXT: lgh %r0, 2(%r2)
; CHECK-NEXT: sllg %r0, %r0, 48
-; CHECK-NEXT: ldgr %f9, %r0
+; CHECK-NEXT: ldgr %f8, %r0
; CHECK-NEXT: lgh %r0, 0(%r2)
; CHECK-NEXT: sllg %r0, %r0, 48
; CHECK-NEXT: ldgr %f12, %r0
@@ -64,7 +64,7 @@ define void @fun0(ptr %Src, ptr %Dst) {
; CHECK-NEXT: ldgr %f13, %r0
; CHECK-NEXT: lgh %r0, 18(%r2)
; CHECK-NEXT: sllg %r0, %r0, 48
-; CHECK-NEXT: ldgr %f8, %r0
+; CHECK-NEXT: ldgr %f9, %r0
; CHECK-NEXT: lgh %r0, 16(%r2)
; CHECK-NEXT: lgh %r8, 10(%r2)
; CHECK-NEXT: lgh %r6, 8(%r2)
@@ -90,15 +90,15 @@ define void @fun0(ptr %Src, ptr %Dst) {
; CHECK-NEXT: brasl %r14, __truncsfhf2 at PLT
; CHECK-NEXT: # kill: def $f0h killed $f0h def $f0d
; CHECK-NEXT: std %f0, 176(%r15) # 8-byte Spill
-; CHECK-NEXT: ler %f0, %f8
-; CHECK-NEXT: brasl %r14, __extendhfsf2 at PLT
-; CHECK-NEXT: ler %f8, %f0
; CHECK-NEXT: ler %f0, %f9
; CHECK-NEXT: brasl %r14, __extendhfsf2 at PLT
-; CHECK-NEXT: cebr %f0, %f8
+; CHECK-NEXT: ler %f9, %f0
+; CHECK-NEXT: ler %f0, %f8
+; CHECK-NEXT: brasl %r14, __extendhfsf2 at PLT
+; CHECK-NEXT: cebr %f0, %f9
; CHECK-NEXT: je .LBB0_4
; CHECK-NEXT: # %bb.3:
-; CHECK-NEXT: ler %f0, %f8
+; CHECK-NEXT: ler %f0, %f9
; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: sllg %r11, %r8, 48
; CHECK-NEXT: sllg %r8, %r7, 48
diff --git a/llvm/test/CodeGen/Thumb/scmp.ll b/llvm/test/CodeGen/Thumb/scmp.ll
index c0024492b3a6d..e934222cded2e 100644
--- a/llvm/test/CodeGen/Thumb/scmp.ll
+++ b/llvm/test/CodeGen/Thumb/scmp.ll
@@ -184,44 +184,48 @@ define i8 @scmp_8_128(i128 %x, i128 %y) nounwind {
; THUMB1: @ %bb.0:
; THUMB1-NEXT: .save {r4, r5, r6, r7, lr}
; THUMB1-NEXT: push {r4, r5, r6, r7, lr}
-; THUMB1-NEXT: .pad #20
-; THUMB1-NEXT: sub sp, #20
-; THUMB1-NEXT: str r3, [sp, #16] @ 4-byte Spill
-; THUMB1-NEXT: movs r3, #1
-; THUMB1-NEXT: str r3, [sp] @ 4-byte Spill
-; THUMB1-NEXT: movs r3, #0
-; THUMB1-NEXT: str r3, [sp, #12] @ 4-byte Spill
-; THUMB1-NEXT: ldr r6, [sp, #52]
-; THUMB1-NEXT: add r7, sp, #40
-; THUMB1-NEXT: ldm r7, {r3, r5, r7}
-; THUMB1-NEXT: subs r4, r0, r3
-; THUMB1-NEXT: str r1, [sp, #4] @ 4-byte Spill
+; THUMB1-NEXT: .pad #28
+; THUMB1-NEXT: sub sp, #28
+; THUMB1-NEXT: mov r6, r2
+; THUMB1-NEXT: movs r2, #1
+; THUMB1-NEXT: str r2, [sp] @ 4-byte Spill
+; THUMB1-NEXT: movs r2, #0
+; THUMB1-NEXT: str r2, [sp, #20] @ 4-byte Spill
+; THUMB1-NEXT: ldr r2, [sp, #60]
+; THUMB1-NEXT: add r7, sp, #48
+; THUMB1-NEXT: ldm r7, {r4, r5, r7}
+; THUMB1-NEXT: str r0, [sp, #8] @ 4-byte Spill
+; THUMB1-NEXT: str r4, [sp, #4] @ 4-byte Spill
+; THUMB1-NEXT: subs r4, r0, r4
+; THUMB1-NEXT: str r1, [sp, #12] @ 4-byte Spill
; THUMB1-NEXT: mov r4, r1
-; THUMB1-NEXT: ldr r1, [sp] @ 4-byte Reload
; THUMB1-NEXT: sbcs r4, r5
-; THUMB1-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; THUMB1-NEXT: mov r4, r2
-; THUMB1-NEXT: sbcs r4, r7
-; THUMB1-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
-; THUMB1-NEXT: sbcs r4, r6
-; THUMB1-NEXT: mov r2, r1
+; THUMB1-NEXT: str r6, [sp, #16] @ 4-byte Spill
+; THUMB1-NEXT: sbcs r6, r7
+; THUMB1-NEXT: str r3, [sp, #24] @ 4-byte Spill
+; THUMB1-NEXT: mov r4, r3
+; THUMB1-NEXT: ldr r3, [sp] @ 4-byte Reload
+; THUMB1-NEXT: sbcs r4, r2
+; THUMB1-NEXT: mov r1, r3
; THUMB1-NEXT: blt .LBB4_2
; THUMB1-NEXT: @ %bb.1:
-; THUMB1-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
+; THUMB1-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; THUMB1-NEXT: .LBB4_2:
-; THUMB1-NEXT: subs r0, r3, r0
-; THUMB1-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
-; THUMB1-NEXT: sbcs r5, r0
; THUMB1-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
-; THUMB1-NEXT: sbcs r7, r0
+; THUMB1-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; THUMB1-NEXT: subs r0, r4, r0
+; THUMB1-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
+; THUMB1-NEXT: sbcs r5, r0
; THUMB1-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
-; THUMB1-NEXT: sbcs r6, r0
+; THUMB1-NEXT: sbcs r7, r0
+; THUMB1-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
+; THUMB1-NEXT: sbcs r2, r0
; THUMB1-NEXT: blt .LBB4_4
; THUMB1-NEXT: @ %bb.3:
-; THUMB1-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; THUMB1-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
; THUMB1-NEXT: .LBB4_4:
-; THUMB1-NEXT: subs r0, r1, r2
-; THUMB1-NEXT: add sp, #20
+; THUMB1-NEXT: subs r0, r3, r1
+; THUMB1-NEXT: add sp, #28
; THUMB1-NEXT: pop {r4, r5, r6, r7, pc}
;
; THUMB2-LABEL: scmp_8_128:
diff --git a/llvm/test/CodeGen/Thumb/ucmp.ll b/llvm/test/CodeGen/Thumb/ucmp.ll
index 5d0f57e2a9d72..aadec79b8582b 100644
--- a/llvm/test/CodeGen/Thumb/ucmp.ll
+++ b/llvm/test/CodeGen/Thumb/ucmp.ll
@@ -151,44 +151,48 @@ define i8 @ucmp_8_128(i128 %x, i128 %y) nounwind {
; THUMB1: @ %bb.0:
; THUMB1-NEXT: .save {r4, r5, r6, r7, lr}
; THUMB1-NEXT: push {r4, r5, r6, r7, lr}
-; THUMB1-NEXT: .pad #20
-; THUMB1-NEXT: sub sp, #20
-; THUMB1-NEXT: str r3, [sp, #16] @ 4-byte Spill
-; THUMB1-NEXT: movs r3, #1
-; THUMB1-NEXT: str r3, [sp] @ 4-byte Spill
-; THUMB1-NEXT: movs r3, #0
-; THUMB1-NEXT: str r3, [sp, #12] @ 4-byte Spill
-; THUMB1-NEXT: ldr r6, [sp, #52]
-; THUMB1-NEXT: add r7, sp, #40
-; THUMB1-NEXT: ldm r7, {r3, r5, r7}
-; THUMB1-NEXT: subs r4, r0, r3
-; THUMB1-NEXT: str r1, [sp, #4] @ 4-byte Spill
+; THUMB1-NEXT: .pad #28
+; THUMB1-NEXT: sub sp, #28
+; THUMB1-NEXT: mov r6, r2
+; THUMB1-NEXT: movs r2, #1
+; THUMB1-NEXT: str r2, [sp] @ 4-byte Spill
+; THUMB1-NEXT: movs r2, #0
+; THUMB1-NEXT: str r2, [sp, #20] @ 4-byte Spill
+; THUMB1-NEXT: ldr r2, [sp, #60]
+; THUMB1-NEXT: add r7, sp, #48
+; THUMB1-NEXT: ldm r7, {r4, r5, r7}
+; THUMB1-NEXT: str r0, [sp, #8] @ 4-byte Spill
+; THUMB1-NEXT: str r4, [sp, #4] @ 4-byte Spill
+; THUMB1-NEXT: subs r4, r0, r4
+; THUMB1-NEXT: str r1, [sp, #12] @ 4-byte Spill
; THUMB1-NEXT: mov r4, r1
-; THUMB1-NEXT: ldr r1, [sp] @ 4-byte Reload
; THUMB1-NEXT: sbcs r4, r5
-; THUMB1-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; THUMB1-NEXT: mov r4, r2
-; THUMB1-NEXT: sbcs r4, r7
-; THUMB1-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
-; THUMB1-NEXT: sbcs r4, r6
-; THUMB1-NEXT: mov r2, r1
+; THUMB1-NEXT: str r6, [sp, #16] @ 4-byte Spill
+; THUMB1-NEXT: sbcs r6, r7
+; THUMB1-NEXT: str r3, [sp, #24] @ 4-byte Spill
+; THUMB1-NEXT: mov r4, r3
+; THUMB1-NEXT: ldr r3, [sp] @ 4-byte Reload
+; THUMB1-NEXT: sbcs r4, r2
+; THUMB1-NEXT: mov r1, r3
; THUMB1-NEXT: blo .LBB4_2
; THUMB1-NEXT: @ %bb.1:
-; THUMB1-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
+; THUMB1-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; THUMB1-NEXT: .LBB4_2:
-; THUMB1-NEXT: subs r0, r3, r0
-; THUMB1-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
-; THUMB1-NEXT: sbcs r5, r0
; THUMB1-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
-; THUMB1-NEXT: sbcs r7, r0
+; THUMB1-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; THUMB1-NEXT: subs r0, r4, r0
+; THUMB1-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
+; THUMB1-NEXT: sbcs r5, r0
; THUMB1-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
-; THUMB1-NEXT: sbcs r6, r0
+; THUMB1-NEXT: sbcs r7, r0
+; THUMB1-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
+; THUMB1-NEXT: sbcs r2, r0
; THUMB1-NEXT: blo .LBB4_4
; THUMB1-NEXT: @ %bb.3:
-; THUMB1-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; THUMB1-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
; THUMB1-NEXT: .LBB4_4:
-; THUMB1-NEXT: subs r0, r1, r2
-; THUMB1-NEXT: add sp, #20
+; THUMB1-NEXT: subs r0, r3, r1
+; THUMB1-NEXT: add sp, #28
; THUMB1-NEXT: pop {r4, r5, r6, r7, pc}
;
; THUMB2-LABEL: ucmp_8_128:
diff --git a/llvm/test/CodeGen/Thumb/umul_fix_sat.ll b/llvm/test/CodeGen/Thumb/umul_fix_sat.ll
index f24fe933e5ad4..24888669c1f5e 100644
--- a/llvm/test/CodeGen/Thumb/umul_fix_sat.ll
+++ b/llvm/test/CodeGen/Thumb/umul_fix_sat.ll
@@ -196,22 +196,25 @@ define i64 @func5(i64 %x, i64 %y) {
; ARM-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; ARM-NEXT: mov r3, r5
; ARM-NEXT: bl __aeabi_lmul
+; ARM-NEXT: mov r2, r0
; ARM-NEXT: adds r3, r1, r6
-; ARM-NEXT: mov r2, r5
-; ARM-NEXT: adcs r2, r5
-; ARM-NEXT: orrs r2, r4
+; ARM-NEXT: mov r0, r5
+; ARM-NEXT: adcs r0, r5
+; ARM-NEXT: orrs r0, r4
; ARM-NEXT: mvns r1, r5
-; ARM-NEXT: cmp r2, #0
-; ARM-NEXT: mov r2, r1
-; ARM-NEXT: bne .LBB4_2
+; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: mov r0, r1
+; ARM-NEXT: beq .LBB4_3
; ARM-NEXT: @ %bb.1:
-; ARM-NEXT: mov r2, r0
+; ARM-NEXT: beq .LBB4_4
; ARM-NEXT: .LBB4_2:
-; ARM-NEXT: bne .LBB4_4
-; ARM-NEXT: @ %bb.3:
-; ARM-NEXT: mov r1, r3
-; ARM-NEXT: .LBB4_4:
+; ARM-NEXT: add sp, #12
+; ARM-NEXT: pop {r4, r5, r6, r7, pc}
+; ARM-NEXT: .LBB4_3:
; ARM-NEXT: mov r0, r2
+; ARM-NEXT: bne .LBB4_2
+; ARM-NEXT: .LBB4_4:
+; ARM-NEXT: mov r1, r3
; ARM-NEXT: add sp, #12
; ARM-NEXT: pop {r4, r5, r6, r7, pc}
%tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 0)
@@ -249,14 +252,14 @@ define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {
; ARM-NEXT: .pad #12
; ARM-NEXT: sub sp, #12
; ARM-NEXT: str r3, [sp, #8] @ 4-byte Spill
-; ARM-NEXT: mov r7, r2
+; ARM-NEXT: mov r6, r2
; ARM-NEXT: mov r5, r1
; ARM-NEXT: ldr r2, [sp, #32]
-; ARM-NEXT: movs r6, #0
-; ARM-NEXT: mov r1, r6
-; ARM-NEXT: mov r3, r6
+; ARM-NEXT: movs r7, #0
+; ARM-NEXT: mov r1, r7
+; ARM-NEXT: mov r3, r7
; ARM-NEXT: bl __aeabi_lmul
-; ARM-NEXT: mvns r4, r6
+; ARM-NEXT: mvns r4, r7
; ARM-NEXT: cmp r1, #0
; ARM-NEXT: mov r1, r4
; ARM-NEXT: bhi .LBB6_2
@@ -266,8 +269,8 @@ define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {
; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
; ARM-NEXT: ldr r2, [sp, #36]
; ARM-NEXT: mov r0, r5
-; ARM-NEXT: mov r1, r6
-; ARM-NEXT: mov r3, r6
+; ARM-NEXT: mov r1, r7
+; ARM-NEXT: mov r3, r7
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: cmp r1, #0
; ARM-NEXT: mov r5, r4
@@ -276,20 +279,20 @@ define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {
; ARM-NEXT: mov r5, r0
; ARM-NEXT: .LBB6_4:
; ARM-NEXT: ldr r2, [sp, #40]
-; ARM-NEXT: mov r0, r7
-; ARM-NEXT: mov r1, r6
-; ARM-NEXT: mov r3, r6
+; ARM-NEXT: mov r0, r6
+; ARM-NEXT: mov r1, r7
+; ARM-NEXT: mov r3, r7
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: cmp r1, #0
-; ARM-NEXT: mov r7, r4
+; ARM-NEXT: mov r6, r4
; ARM-NEXT: bhi .LBB6_6
; ARM-NEXT: @ %bb.5:
-; ARM-NEXT: mov r7, r0
+; ARM-NEXT: mov r6, r0
; ARM-NEXT: .LBB6_6:
; ARM-NEXT: ldr r2, [sp, #44]
; ARM-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
-; ARM-NEXT: mov r1, r6
-; ARM-NEXT: mov r3, r6
+; ARM-NEXT: mov r1, r7
+; ARM-NEXT: mov r3, r7
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: cmp r1, #0
; ARM-NEXT: bhi .LBB6_8
@@ -298,7 +301,7 @@ define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {
; ARM-NEXT: .LBB6_8:
; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; ARM-NEXT: mov r1, r5
-; ARM-NEXT: mov r2, r7
+; ARM-NEXT: mov r2, r6
; ARM-NEXT: mov r3, r4
; ARM-NEXT: add sp, #12
; ARM-NEXT: pop {r4, r5, r6, r7, pc}
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
index 696938c27b0f5..8fadc4750fc0e 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
@@ -13,7 +13,7 @@ define dso_local i32 @vpsel_mul_reduce_add(ptr noalias nocapture readonly %a, pt
; CHECK-NEXT: add.w r12, r3, #3
; CHECK-NEXT: mov.w lr, #1
; CHECK-NEXT: bic r12, r12, #3
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: sub.w r12, r12, #4
; CHECK-NEXT: add.w lr, lr, r12, lsr #2
; CHECK-NEXT: mov.w r12, #0
@@ -21,23 +21,23 @@ define dso_local i32 @vpsel_mul_reduce_add(ptr noalias nocapture readonly %a, pt
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: and r4, r12, #15
; CHECK-NEXT: vctp.32 r3
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrwt.u32 q1, [r2], #16
+; CHECK-NEXT: vldrwt.u32 q0, [r2], #16
; CHECK-NEXT: vldrwt.u32 q2, [r1], #16
; CHECK-NEXT: vdup.32 q3, r4
; CHECK-NEXT: add.w r12, r12, #4
; CHECK-NEXT: vpt.i32 eq, q3, zr
-; CHECK-NEXT: vmovt q1, q2
+; CHECK-NEXT: vmovt q0, q2
; CHECK-NEXT: vctp.32 r3
; CHECK-NEXT: vpst
; CHECK-NEXT: vldrwt.u32 q2, [r0], #16
; CHECK-NEXT: subs r3, #4
-; CHECK-NEXT: vmul.i32 q1, q1, q2
-; CHECK-NEXT: vadd.i32 q1, q1, q0
+; CHECK-NEXT: vmul.i32 q0, q0, q2
+; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: le lr, .LBB0_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: pop {r4, pc}
entry:
@@ -90,7 +90,7 @@ define dso_local i32 @vpsel_mul_reduce_add_2(ptr noalias nocapture readonly %a,
; CHECK-NEXT: beq .LBB1_4
; CHECK-NEXT: @ %bb.1: @ %vector.ph
; CHECK-NEXT: add.w r4, r12, #3
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: bic r4, r4, #3
; CHECK-NEXT: sub.w lr, r4, #4
; CHECK-NEXT: movs r4, #1
@@ -100,24 +100,24 @@ define dso_local i32 @vpsel_mul_reduce_add_2(ptr noalias nocapture readonly %a,
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.32 r12
; CHECK-NEXT: and r5, r4, #15
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vpsttt
-; CHECK-NEXT: vldrwt.u32 q1, [r1], #16
+; CHECK-NEXT: vldrwt.u32 q0, [r1], #16
; CHECK-NEXT: vldrwt.u32 q2, [r3], #16
; CHECK-NEXT: vldrwt.u32 q3, [r2], #16
; CHECK-NEXT: vdup.32 q4, r5
; CHECK-NEXT: adds r4, #4
; CHECK-NEXT: vpt.i32 eq, q4, zr
-; CHECK-NEXT: vsubt.i32 q1, q3, q2
+; CHECK-NEXT: vsubt.i32 q0, q3, q2
; CHECK-NEXT: vctp.32 r12
; CHECK-NEXT: vpst
; CHECK-NEXT: vldrwt.u32 q2, [r0], #16
; CHECK-NEXT: sub.w r12, r12, #4
-; CHECK-NEXT: vmul.i32 q1, q1, q2
-; CHECK-NEXT: vadd.i32 q1, q1, q0
+; CHECK-NEXT: vmul.i32 q0, q0, q2
+; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: le lr, .LBB1_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r7, pc}
@@ -181,35 +181,35 @@ define dso_local i32 @and_mul_reduce_add(ptr noalias nocapture readonly %a, ptr
; CHECK-NEXT: add.w lr, r12, #3
; CHECK-NEXT: movs r4, #1
; CHECK-NEXT: bic lr, lr, #3
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: sub.w lr, lr, #4
; CHECK-NEXT: add.w r4, r4, lr, lsr #2
; CHECK-NEXT: dls lr, r4
; CHECK-NEXT: .LBB2_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.32 r12
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrwt.u32 q1, [r1], #16
+; CHECK-NEXT: vldrwt.u32 q0, [r1], #16
; CHECK-NEXT: vldrwt.u32 q2, [r0], #16
; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill
; CHECK-NEXT: sub.w r12, r12, #4
-; CHECK-NEXT: vsub.i32 q1, q2, q1
+; CHECK-NEXT: vsub.i32 q0, q2, q0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vcmpt.i32 eq, q1, zr
+; CHECK-NEXT: vcmpt.i32 eq, q0, zr
; CHECK-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: vpst
-; CHECK-NEXT: vldrwt.u32 q1, [r3], #16
+; CHECK-NEXT: vldrwt.u32 q0, [r3], #16
; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: vpst
; CHECK-NEXT: vldrwt.u32 q2, [r2], #16
-; CHECK-NEXT: vmul.i32 q1, q2, q1
-; CHECK-NEXT: vadd.i32 q1, q1, q0
+; CHECK-NEXT: vmul.i32 q0, q2, q0
+; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: le lr, .LBB2_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: add sp, #8
; CHECK-NEXT: pop {r4, pc}
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
index 5159306fb23d0..b953988b35c06 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
@@ -68,7 +68,7 @@ define dso_local arm_aapcs_vfpcc signext i16 @one_loop_add_add_v8i16(ptr nocaptu
; CHECK-NEXT: .LBB1_1: @ %vector.ph
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: adds r3, r2, #7
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: bic r3, r3, #7
; CHECK-NEXT: sub.w r12, r3, #8
; CHECK-NEXT: movs r3, #1
@@ -77,16 +77,16 @@ define dso_local arm_aapcs_vfpcc signext i16 @one_loop_add_add_v8i16(ptr nocaptu
; CHECK-NEXT: .LBB1_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.16 r2
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrbt.u16 q1, [r0], #8
+; CHECK-NEXT: vldrbt.u16 q0, [r0], #8
; CHECK-NEXT: vldrbt.u16 q2, [r1], #8
; CHECK-NEXT: subs r2, #8
-; CHECK-NEXT: vadd.i16 q1, q0, q1
-; CHECK-NEXT: vadd.i16 q1, q1, q2
+; CHECK-NEXT: vadd.i16 q0, q1, q0
+; CHECK-NEXT: vadd.i16 q0, q0, q2
; CHECK-NEXT: le lr, .LBB1_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: pop.w {r7, lr}
; CHECK-NEXT: sxth r0, r0
@@ -139,7 +139,7 @@ define dso_local arm_aapcs_vfpcc zeroext i8 @one_loop_sub_add_v16i8(ptr nocaptur
; CHECK-NEXT: .LBB2_1: @ %vector.ph
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: add.w r3, r2, #15
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: bic r3, r3, #15
; CHECK-NEXT: sub.w r12, r3, #16
; CHECK-NEXT: movs r3, #1
@@ -148,16 +148,16 @@ define dso_local arm_aapcs_vfpcc zeroext i8 @one_loop_sub_add_v16i8(ptr nocaptur
; CHECK-NEXT: .LBB2_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.8 r2
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrbt.u8 q1, [r1], #16
+; CHECK-NEXT: vldrbt.u8 q0, [r1], #16
; CHECK-NEXT: vldrbt.u8 q2, [r0], #16
; CHECK-NEXT: subs r2, #16
-; CHECK-NEXT: vsub.i8 q1, q2, q1
-; CHECK-NEXT: vadd.i8 q1, q1, q0
+; CHECK-NEXT: vsub.i8 q0, q2, q0
+; CHECK-NEXT: vadd.i8 q0, q0, q1
; CHECK-NEXT: le lr, .LBB2_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u8 r0, q0
; CHECK-NEXT: pop.w {r7, lr}
; CHECK-NEXT: uxtb r0, r0
@@ -208,7 +208,7 @@ define dso_local arm_aapcs_vfpcc signext i16 @one_loop_sub_add_v8i16(ptr nocaptu
; CHECK-NEXT: .LBB3_1: @ %vector.ph
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: adds r3, r2, #7
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: bic r3, r3, #7
; CHECK-NEXT: sub.w r12, r3, #8
; CHECK-NEXT: movs r3, #1
@@ -217,16 +217,16 @@ define dso_local arm_aapcs_vfpcc signext i16 @one_loop_sub_add_v8i16(ptr nocaptu
; CHECK-NEXT: .LBB3_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.16 r2
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrbt.u16 q1, [r0], #8
+; CHECK-NEXT: vldrbt.u16 q0, [r0], #8
; CHECK-NEXT: vldrbt.u16 q2, [r1], #8
; CHECK-NEXT: subs r2, #8
-; CHECK-NEXT: vsub.i16 q1, q2, q1
-; CHECK-NEXT: vadd.i16 q1, q1, q0
+; CHECK-NEXT: vsub.i16 q0, q2, q0
+; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: le lr, .LBB3_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: pop.w {r7, lr}
; CHECK-NEXT: sxth r0, r0
@@ -279,7 +279,7 @@ define dso_local arm_aapcs_vfpcc zeroext i8 @one_loop_mul_add_v16i8(ptr nocaptur
; CHECK-NEXT: .LBB4_1: @ %vector.ph
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: add.w r3, r2, #15
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: bic r3, r3, #15
; CHECK-NEXT: sub.w r12, r3, #16
; CHECK-NEXT: movs r3, #1
@@ -288,16 +288,16 @@ define dso_local arm_aapcs_vfpcc zeroext i8 @one_loop_mul_add_v16i8(ptr nocaptur
; CHECK-NEXT: .LBB4_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.8 r2
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrbt.u8 q1, [r0], #16
+; CHECK-NEXT: vldrbt.u8 q0, [r0], #16
; CHECK-NEXT: vldrbt.u8 q2, [r1], #16
; CHECK-NEXT: subs r2, #16
-; CHECK-NEXT: vmul.i8 q1, q2, q1
-; CHECK-NEXT: vadd.i8 q1, q1, q0
+; CHECK-NEXT: vmul.i8 q0, q2, q0
+; CHECK-NEXT: vadd.i8 q0, q0, q1
; CHECK-NEXT: le lr, .LBB4_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u8 r0, q0
; CHECK-NEXT: pop.w {r7, lr}
; CHECK-NEXT: uxtb r0, r0
@@ -348,7 +348,7 @@ define dso_local arm_aapcs_vfpcc signext i16 @one_loop_mul_add_v8i16(ptr nocaptu
; CHECK-NEXT: .LBB5_1: @ %vector.ph
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: adds r3, r2, #7
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: bic r3, r3, #7
; CHECK-NEXT: sub.w r12, r3, #8
; CHECK-NEXT: movs r3, #1
@@ -357,16 +357,16 @@ define dso_local arm_aapcs_vfpcc signext i16 @one_loop_mul_add_v8i16(ptr nocaptu
; CHECK-NEXT: .LBB5_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.16 r2
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrbt.u16 q1, [r0], #8
+; CHECK-NEXT: vldrbt.u16 q0, [r0], #8
; CHECK-NEXT: vldrbt.u16 q2, [r1], #8
; CHECK-NEXT: subs r2, #8
-; CHECK-NEXT: vmul.i16 q1, q2, q1
-; CHECK-NEXT: vadd.i16 q1, q1, q0
+; CHECK-NEXT: vmul.i16 q0, q2, q0
+; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: le lr, .LBB5_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: pop.w {r7, lr}
; CHECK-NEXT: sxth r0, r0
@@ -418,7 +418,7 @@ define dso_local arm_aapcs_vfpcc i32 @two_loops_mul_add_v4i32(ptr nocapture read
; CHECK-NEXT: .LBB6_1: @ %vector.ph
; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: adds r3, r2, #3
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: bic r3, r3, #3
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: subs r7, r3, #4
@@ -430,16 +430,16 @@ define dso_local arm_aapcs_vfpcc i32 @two_loops_mul_add_v4i32(ptr nocapture read
; CHECK-NEXT: .LBB6_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.32 r3
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrbt.u32 q1, [r4], #4
+; CHECK-NEXT: vldrbt.u32 q0, [r4], #4
; CHECK-NEXT: vldrbt.u32 q2, [r5], #4
; CHECK-NEXT: subs r3, #4
-; CHECK-NEXT: vmul.i32 q1, q2, q1
-; CHECK-NEXT: vadd.i32 q1, q1, q0
+; CHECK-NEXT: vmul.i32 q0, q2, q0
+; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: le lr, .LBB6_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u32 r12, q0
; CHECK-NEXT: cbz r2, .LBB6_7
; CHECK-NEXT: @ %bb.4: @ %vector.ph47
@@ -543,9 +543,9 @@ define dso_local arm_aapcs_vfpcc void @two_reductions_mul_add_v8i16(ptr nocaptur
; CHECK-NEXT: adds r3, r2, #7
; CHECK-NEXT: movs r4, #1
; CHECK-NEXT: bic r3, r3, #7
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: subs r3, #8
-; CHECK-NEXT: vmov.i32 q3, #0x0
+; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: add.w r12, r4, r3, lsr #3
; CHECK-NEXT: mov r3, r0
; CHECK-NEXT: mov r4, r1
@@ -553,21 +553,21 @@ define dso_local arm_aapcs_vfpcc void @two_reductions_mul_add_v8i16(ptr nocaptur
; CHECK-NEXT: .LBB7_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.16 r2
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrbt.u16 q1, [r3], #8
+; CHECK-NEXT: vldrbt.u16 q0, [r3], #8
; CHECK-NEXT: vldrbt.u16 q4, [r4], #8
-; CHECK-NEXT: vmov q2, q3
+; CHECK-NEXT: vmov q3, q1
; CHECK-NEXT: subs r2, #8
-; CHECK-NEXT: vsub.i16 q3, q4, q1
-; CHECK-NEXT: vmul.i16 q1, q4, q1
-; CHECK-NEXT: vadd.i16 q3, q3, q2
-; CHECK-NEXT: vadd.i16 q1, q1, q0
+; CHECK-NEXT: vsub.i16 q1, q4, q0
+; CHECK-NEXT: vmul.i16 q0, q4, q0
+; CHECK-NEXT: vadd.i16 q1, q1, q3
+; CHECK-NEXT: vadd.i16 q0, q0, q2
; CHECK-NEXT: le lr, .LBB7_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
-; CHECK-NEXT: vpsel q2, q3, q2
-; CHECK-NEXT: vpsel q0, q1, q0
-; CHECK-NEXT: vaddv.u16 r4, q2
+; CHECK-NEXT: vpsel q1, q1, q3
+; CHECK-NEXT: vpsel q0, q0, q2
+; CHECK-NEXT: vaddv.u16 r4, q1
; CHECK-NEXT: vaddv.u16 r2, q0
; CHECK-NEXT: b .LBB7_5
; CHECK-NEXT: .LBB7_4:
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
index 1769c5d2fd385..a3eae51b0c3c2 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
@@ -52,7 +52,7 @@ define dso_local void @varying_outer_2d_reduction(ptr nocapture readonly %Input,
; ENABLED-NEXT: movs r7, #1
; ENABLED-NEXT: subs r0, #4
; ENABLED-NEXT: sub.w r4, r2, r12
-; ENABLED-NEXT: vmov.i32 q1, #0x0
+; ENABLED-NEXT: vmov.i32 q0, #0x0
; ENABLED-NEXT: add.w r6, r7, r0, lsr #2
; ENABLED-NEXT: adds r0, r2, #3
; ENABLED-NEXT: sub.w r0, r0, r12
@@ -66,20 +66,20 @@ define dso_local void @varying_outer_2d_reduction(ptr nocapture readonly %Input,
; ENABLED-NEXT: @ Parent Loop BB0_4 Depth=1
; ENABLED-NEXT: @ => This Inner Loop Header: Depth=2
; ENABLED-NEXT: vctp.32 r4
-; ENABLED-NEXT: vmov q0, q1
+; ENABLED-NEXT: vmov q1, q0
; ENABLED-NEXT: vpstt
-; ENABLED-NEXT: vldrht.s32 q1, [r0], #8
+; ENABLED-NEXT: vldrht.s32 q0, [r0], #8
; ENABLED-NEXT: vldrht.s32 q2, [r7], #8
; ENABLED-NEXT: mov lr, r6
; ENABLED-NEXT: subs r6, #1
-; ENABLED-NEXT: vmul.i32 q1, q2, q1
+; ENABLED-NEXT: vmul.i32 q0, q2, q0
; ENABLED-NEXT: subs r4, #4
-; ENABLED-NEXT: vshl.s32 q1, r5
-; ENABLED-NEXT: vadd.i32 q1, q1, q0
+; ENABLED-NEXT: vshl.s32 q0, r5
+; ENABLED-NEXT: vadd.i32 q0, q0, q1
; ENABLED-NEXT: le lr, .LBB0_6
; ENABLED-NEXT: @ %bb.7: @ %middle.block
; ENABLED-NEXT: @ in Loop: Header=BB0_4 Depth=1
-; ENABLED-NEXT: vpsel q0, q1, q0
+; ENABLED-NEXT: vpsel q0, q0, q1
; ENABLED-NEXT: vaddv.u32 r0, q0
; ENABLED-NEXT: b .LBB0_3
; ENABLED-NEXT: .LBB0_8:
@@ -123,7 +123,7 @@ define dso_local void @varying_outer_2d_reduction(ptr nocapture readonly %Input,
; NOREDUCTIONS-NEXT: movs r7, #1
; NOREDUCTIONS-NEXT: subs r0, #4
; NOREDUCTIONS-NEXT: sub.w r4, r2, r12
-; NOREDUCTIONS-NEXT: vmov.i32 q1, #0x0
+; NOREDUCTIONS-NEXT: vmov.i32 q0, #0x0
; NOREDUCTIONS-NEXT: add.w r6, r7, r0, lsr #2
; NOREDUCTIONS-NEXT: adds r0, r2, #3
; NOREDUCTIONS-NEXT: sub.w r0, r0, r12
@@ -137,20 +137,20 @@ define dso_local void @varying_outer_2d_reduction(ptr nocapture readonly %Input,
; NOREDUCTIONS-NEXT: @ Parent Loop BB0_4 Depth=1
; NOREDUCTIONS-NEXT: @ => This Inner Loop Header: Depth=2
; NOREDUCTIONS-NEXT: vctp.32 r4
-; NOREDUCTIONS-NEXT: vmov q0, q1
+; NOREDUCTIONS-NEXT: vmov q1, q0
; NOREDUCTIONS-NEXT: vpstt
-; NOREDUCTIONS-NEXT: vldrht.s32 q1, [r0], #8
+; NOREDUCTIONS-NEXT: vldrht.s32 q0, [r0], #8
; NOREDUCTIONS-NEXT: vldrht.s32 q2, [r7], #8
; NOREDUCTIONS-NEXT: mov lr, r6
; NOREDUCTIONS-NEXT: subs r6, #1
-; NOREDUCTIONS-NEXT: vmul.i32 q1, q2, q1
+; NOREDUCTIONS-NEXT: vmul.i32 q0, q2, q0
; NOREDUCTIONS-NEXT: subs r4, #4
-; NOREDUCTIONS-NEXT: vshl.s32 q1, r5
-; NOREDUCTIONS-NEXT: vadd.i32 q1, q1, q0
+; NOREDUCTIONS-NEXT: vshl.s32 q0, r5
+; NOREDUCTIONS-NEXT: vadd.i32 q0, q0, q1
; NOREDUCTIONS-NEXT: le lr, .LBB0_6
; NOREDUCTIONS-NEXT: @ %bb.7: @ %middle.block
; NOREDUCTIONS-NEXT: @ in Loop: Header=BB0_4 Depth=1
-; NOREDUCTIONS-NEXT: vpsel q0, q1, q0
+; NOREDUCTIONS-NEXT: vpsel q0, q0, q1
; NOREDUCTIONS-NEXT: vaddv.u32 r0, q0
; NOREDUCTIONS-NEXT: b .LBB0_3
; NOREDUCTIONS-NEXT: .LBB0_8:
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
index 0f1420068ab29..01c546ed25897 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
@@ -11,7 +11,7 @@ define dso_local i32 @mul_reduce_add(ptr noalias nocapture readonly %a, ptr noal
; CHECK-NEXT: .LBB0_1: @ %vector.ph
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: adds r3, r2, #3
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: bic r3, r3, #3
; CHECK-NEXT: sub.w r12, r3, #4
; CHECK-NEXT: movs r3, #1
@@ -20,16 +20,16 @@ define dso_local i32 @mul_reduce_add(ptr noalias nocapture readonly %a, ptr noal
; CHECK-NEXT: .LBB0_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.32 r2
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrwt.u32 q1, [r0], #16
+; CHECK-NEXT: vldrwt.u32 q0, [r0], #16
; CHECK-NEXT: vldrwt.u32 q2, [r1], #16
; CHECK-NEXT: subs r2, #4
-; CHECK-NEXT: vmul.i32 q1, q2, q1
-; CHECK-NEXT: vadd.i32 q1, q1, q0
+; CHECK-NEXT: vmul.i32 q0, q2, q0
+; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: le lr, .LBB0_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
-; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: pop {r7, pc}
entry:
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
index 68cceb324cb3a..18fcd7da59820 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
@@ -165,39 +165,35 @@ define dso_local i32 @b(ptr %c, i32 %d, i32 %e, ptr %n) "frame-pointer"="all" {
; CHECK-NEXT: sub sp, #12
; CHECK-NEXT: wls lr, r1, .LBB2_3
; CHECK-NEXT: @ %bb.1: @ %while.body.preheader
-; CHECK-NEXT: mvn r10, #1
-; CHECK-NEXT: @ implicit-def: $r1
-; CHECK-NEXT: @ implicit-def: $r12
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: mov r9, r3
+; CHECK-NEXT: mvn r1, #1
+; CHECK-NEXT: @ implicit-def: $r9
+; CHECK-NEXT: @ implicit-def: $r4
+; CHECK-NEXT: mov r10, r0
+; CHECK-NEXT: mov r12, r3
; CHECK-NEXT: str r2, [sp] @ 4-byte Spill
; CHECK-NEXT: .LBB2_2: @ %while.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: strd r3, r4, [sp, #4] @ 8-byte Folded Spill
-; CHECK-NEXT: asr.w r5, r12, #31
-; CHECK-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT: ldr r4, [r2, #4]!
-; CHECK-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT: muls r4, r3, r4
-; CHECK-NEXT: adds.w r6, r12, r4
-; CHECK-NEXT: adc.w r5, r5, r4, asr #31
-; CHECK-NEXT: adds.w r6, r6, #-2147483648
-; CHECK-NEXT: adc r12, r5, #0
-; CHECK-NEXT: ldrd r2, r5, [r10]
-; CHECK-NEXT: smull r5, r6, r5, r1
-; CHECK-NEXT: asr.w r4, r12, #31
-; CHECK-NEXT: muls r2, r1, r2
-; CHECK-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: subs.w r5, r12, r5
+; CHECK-NEXT: ldr r2, [r10, #4]!
+; CHECK-NEXT: asrs r5, r4, #31
+; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: muls r2, r3, r2
+; CHECK-NEXT: adds r4, r4, r2
+; CHECK-NEXT: adc.w r2, r5, r2, asr #31
+; CHECK-NEXT: ldrd r6, r5, [r1]
+; CHECK-NEXT: str r6, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: smull r5, r6, r5, r9
+; CHECK-NEXT: adds.w r4, r4, #-2147483648
+; CHECK-NEXT: adc r2, r2, #0
+; CHECK-NEXT: asrs r4, r2, #31
+; CHECK-NEXT: subs r5, r2, r5
; CHECK-NEXT: sbcs r4, r6
; CHECK-NEXT: adds.w r6, r5, #-2147483648
; CHECK-NEXT: adc r5, r4, #0
; CHECK-NEXT: ldr r4, [r0]
-; CHECK-NEXT: adds r2, #2
; CHECK-NEXT: muls r4, r3, r4
; CHECK-NEXT: adds.w r8, r4, #-2147483648
; CHECK-NEXT: asr.w r3, r4, #31
-; CHECK-NEXT: ldr r4, [r9, #4]!
+; CHECK-NEXT: ldr r4, [r12, #4]!
; CHECK-NEXT: adc r3, r3, #0
; CHECK-NEXT: muls r0, r4, r0
; CHECK-NEXT: add.w r0, r0, #-2147483648
@@ -206,28 +202,31 @@ define dso_local i32 @b(ptr %c, i32 %d, i32 %e, ptr %n) "frame-pointer"="all" {
; CHECK-NEXT: lsll r0, r3, #30
; CHECK-NEXT: asr.w r11, r3, #31
; CHECK-NEXT: mov r0, r3
+; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: lsll r0, r11, r4
; CHECK-NEXT: lsrl r0, r11, #2
-; CHECK-NEXT: lsll r0, r11, r2
+; CHECK-NEXT: mul r3, r3, r9
+; CHECK-NEXT: adds r3, #2
+; CHECK-NEXT: lsll r0, r11, r3
; CHECK-NEXT: add.w r0, r0, #-2147483648
; CHECK-NEXT: asrl r6, r5, r0
; CHECK-NEXT: movs r0, #2
; CHECK-NEXT: lsrl r6, r5, #2
; CHECK-NEXT: str r6, [r0]
-; CHECK-NEXT: ldr r0, [r10], #-4
-; CHECK-NEXT: mls r0, r0, r4, r12
-; CHECK-NEXT: ldr r4, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT: adds.w r12, r0, #-2147483648
+; CHECK-NEXT: mov r9, r6
+; CHECK-NEXT: ldr r0, [r1], #-4
+; CHECK-NEXT: mls r0, r0, r4, r2
+; CHECK-NEXT: adds.w r4, r0, #-2147483648
; CHECK-NEXT: asr.w r2, r0, #31
; CHECK-NEXT: adc r3, r2, #0
+; CHECK-NEXT: lsrl r4, r3, #2
; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
-; CHECK-NEXT: lsrl r12, r3, #2
-; CHECK-NEXT: rsb.w r0, r12, #0
-; CHECK-NEXT: mov r3, r9
+; CHECK-NEXT: ldr r3, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: rsbs r0, r4, #0
; CHECK-NEXT: str r0, [r2]
-; CHECK-NEXT: str r0, [r1]
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: str r0, [r3]
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r3, r12
; CHECK-NEXT: le lr, .LBB2_2
; CHECK-NEXT: .LBB2_3: @ %while.end
; CHECK-NEXT: add sp, #12
diff --git a/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll b/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
index 50299d3abd305..bb46fb48dbe34 100644
--- a/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
+++ b/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
@@ -45,21 +45,21 @@ define i64 @loopif(ptr nocapture readonly %x, i32 %y, i32 %n) {
; CHECK-NEXT: dls lr, r2
; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: movs r3, #0
+; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB1_2: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldr r2, [r12], #4
-; CHECK-NEXT: smlal r0, r3, r2, r1
+; CHECK-NEXT: ldr r3, [r12], #4
+; CHECK-NEXT: smlal r0, r2, r3, r1
; CHECK-NEXT: le lr, .LBB1_2
; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
-; CHECK-NEXT: mov r1, r3
+; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: mov r1, r3
+; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: pop {r7, pc}
entry:
%cmp7 = icmp sgt i32 %n, 0
diff --git a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
index a9043476b0549..9b9e2364a48d5 100644
--- a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
@@ -1002,22 +1002,22 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: lsrs.w r12, r3, #2
; CHECK-NEXT: beq.w .LBB16_12
; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph
-; CHECK-NEXT: ldrh r4, [r0]
+; CHECK-NEXT: ldrh r3, [r0]
; CHECK-NEXT: movs r1, #1
-; CHECK-NEXT: ldrd r5, r3, [r0, #4]
-; CHECK-NEXT: sub.w r0, r4, #8
+; CHECK-NEXT: ldrd r5, r10, [r0, #4]
+; CHECK-NEXT: sub.w r0, r3, #8
; CHECK-NEXT: add.w r7, r0, r0, lsr #29
; CHECK-NEXT: and r0, r0, #7
; CHECK-NEXT: asrs r6, r7, #3
; CHECK-NEXT: cmp r6, #1
; CHECK-NEXT: it gt
; CHECK-NEXT: asrgt r1, r7, #3
-; CHECK-NEXT: add.w r7, r5, r4, lsl #1
+; CHECK-NEXT: add.w r7, r5, r3, lsl #1
; CHECK-NEXT: str r1, [sp] @ 4-byte Spill
; CHECK-NEXT: subs r1, r7, #2
-; CHECK-NEXT: rsbs r7, r4, #0
-; CHECK-NEXT: str r4, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT: str r7, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: rsbs r3, r3, #0
+; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: b .LBB16_6
; CHECK-NEXT: .LBB16_3: @ %while.end.loopexit
@@ -1042,37 +1042,37 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: @ =>This Loop Header: Depth=1
; CHECK-NEXT: @ Child Loop BB16_8 Depth 2
; CHECK-NEXT: @ Child Loop BB16_11 Depth 2
-; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
-; CHECK-NEXT: ldrh.w lr, [r3, #14]
-; CHECK-NEXT: vldrw.u32 q0, [r0], #8
-; CHECK-NEXT: ldrh.w r10, [r3, #12]
-; CHECK-NEXT: ldrh r7, [r3, #10]
-; CHECK-NEXT: ldrh r4, [r3, #8]
-; CHECK-NEXT: ldrh r6, [r3, #6]
-; CHECK-NEXT: ldrh.w r9, [r3, #4]
-; CHECK-NEXT: ldrh.w r11, [r3, #2]
-; CHECK-NEXT: ldrh.w r8, [r3]
+; CHECK-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: ldrh.w lr, [r10, #14]
+; CHECK-NEXT: vldrw.u32 q0, [r3], #8
+; CHECK-NEXT: ldrh.w r0, [r10, #12]
+; CHECK-NEXT: ldrh.w r7, [r10, #10]
+; CHECK-NEXT: ldrh.w r4, [r10, #8]
+; CHECK-NEXT: ldrh.w r6, [r10, #6]
+; CHECK-NEXT: ldrh.w r9, [r10, #4]
+; CHECK-NEXT: ldrh.w r11, [r10, #2]
+; CHECK-NEXT: ldrh.w r8, [r10]
; CHECK-NEXT: vstrb.8 q0, [r1], #8
; CHECK-NEXT: vldrw.u32 q0, [r5]
-; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
-; CHECK-NEXT: adds r0, r5, #2
-; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: str r3, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: adds r3, r5, #2
+; CHECK-NEXT: vldrw.u32 q1, [r3]
; CHECK-NEXT: vmul.f16 q0, q0, r8
-; CHECK-NEXT: adds r0, r5, #6
+; CHECK-NEXT: adds r3, r5, #6
; CHECK-NEXT: vfma.f16 q0, q1, r11
; CHECK-NEXT: vldrw.u32 q1, [r5, #4]
; CHECK-NEXT: vfma.f16 q0, q1, r9
-; CHECK-NEXT: vldrw.u32 q1, [r0]
-; CHECK-NEXT: add.w r0, r5, #10
+; CHECK-NEXT: vldrw.u32 q1, [r3]
+; CHECK-NEXT: add.w r3, r5, #10
; CHECK-NEXT: vfma.f16 q0, q1, r6
; CHECK-NEXT: vldrw.u32 q1, [r5, #8]
; CHECK-NEXT: add.w r6, r5, #16
; CHECK-NEXT: vfma.f16 q0, q1, r4
-; CHECK-NEXT: vldrw.u32 q1, [r0]
-; CHECK-NEXT: add.w r0, r5, #14
+; CHECK-NEXT: vldrw.u32 q1, [r3]
; CHECK-NEXT: vfma.f16 q0, q1, r7
; CHECK-NEXT: vldrw.u32 q1, [r5, #12]
-; CHECK-NEXT: vfma.f16 q0, q1, r10
+; CHECK-NEXT: vfma.f16 q0, q1, r0
+; CHECK-NEXT: add.w r0, r5, #14
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: vfma.f16 q0, q1, lr
@@ -1081,32 +1081,32 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: @ %bb.7: @ %for.body.preheader
; CHECK-NEXT: @ in Loop: Header=BB16_6 Depth=1
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
-; CHECK-NEXT: add.w r5, r3, #16
+; CHECK-NEXT: add.w r5, r10, #16
; CHECK-NEXT: dls lr, r0
; CHECK-NEXT: .LBB16_8: @ %for.body
; CHECK-NEXT: @ Parent Loop BB16_6 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-NEXT: ldrh r0, [r5], #16
; CHECK-NEXT: vldrw.u32 q1, [r6]
-; CHECK-NEXT: adds r4, r6, #2
+; CHECK-NEXT: adds r3, r6, #2
; CHECK-NEXT: vfma.f16 q0, q1, r0
-; CHECK-NEXT: vldrw.u32 q1, [r4]
+; CHECK-NEXT: vldrw.u32 q1, [r3]
; CHECK-NEXT: ldrh r0, [r5, #-14]
-; CHECK-NEXT: adds r4, r6, #6
+; CHECK-NEXT: adds r3, r6, #6
; CHECK-NEXT: vfma.f16 q0, q1, r0
; CHECK-NEXT: ldrh r0, [r5, #-12]
; CHECK-NEXT: vldrw.u32 q1, [r6, #4]
; CHECK-NEXT: vfma.f16 q0, q1, r0
-; CHECK-NEXT: vldrw.u32 q1, [r4]
+; CHECK-NEXT: vldrw.u32 q1, [r3]
; CHECK-NEXT: ldrh r0, [r5, #-10]
-; CHECK-NEXT: add.w r4, r6, #10
+; CHECK-NEXT: add.w r3, r6, #10
; CHECK-NEXT: vfma.f16 q0, q1, r0
; CHECK-NEXT: ldrh r0, [r5, #-8]
; CHECK-NEXT: vldrw.u32 q1, [r6, #8]
; CHECK-NEXT: vfma.f16 q0, q1, r0
-; CHECK-NEXT: vldrw.u32 q1, [r4]
+; CHECK-NEXT: vldrw.u32 q1, [r3]
; CHECK-NEXT: ldrh r0, [r5, #-6]
-; CHECK-NEXT: ldrh r4, [r5, #-2]
+; CHECK-NEXT: ldrh r3, [r5, #-2]
; CHECK-NEXT: vfma.f16 q0, q1, r0
; CHECK-NEXT: ldrh r0, [r5, #-4]
; CHECK-NEXT: vldrw.u32 q1, [r6, #12]
@@ -1114,11 +1114,11 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: add.w r0, r6, #14
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: adds r6, #16
-; CHECK-NEXT: vfma.f16 q0, q1, r4
+; CHECK-NEXT: vfma.f16 q0, q1, r3
; CHECK-NEXT: le lr, .LBB16_8
; CHECK-NEXT: b .LBB16_4
; CHECK-NEXT: .LBB16_9: @ in Loop: Header=BB16_6 Depth=1
-; CHECK-NEXT: add.w r5, r3, #16
+; CHECK-NEXT: add.w r5, r10, #16
; CHECK-NEXT: b .LBB16_4
; CHECK-NEXT: .LBB16_10: @ %while.body76.preheader
; CHECK-NEXT: @ in Loop: Header=BB16_6 Depth=1
@@ -1126,9 +1126,9 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
; CHECK-NEXT: .LBB16_11: @ %while.body76
; CHECK-NEXT: @ Parent Loop BB16_6 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
-; CHECK-NEXT: ldrh r4, [r5], #2
+; CHECK-NEXT: ldrh r3, [r5], #2
; CHECK-NEXT: vldrh.u16 q1, [r0], #2
-; CHECK-NEXT: vfma.f16 q0, q1, r4
+; CHECK-NEXT: vfma.f16 q0, q1, r3
; CHECK-NEXT: le lr, .LBB16_11
; CHECK-NEXT: b .LBB16_3
; CHECK-NEXT: .LBB16_12: @ %if.end
diff --git a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
index b6657d607ce6d..ea290775b58f9 100644
--- a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
@@ -1573,125 +1573,132 @@ define arm_aapcs_vfpcc void @arm_biquad_cascade_df1_f32(ptr nocapture readonly %
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
-; CHECK-NEXT: ldm.w r0, {r7, r9, r11}
-; CHECK-NEXT: and r0, r3, #3
-; CHECK-NEXT: @ implicit-def: $r5
-; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT: lsrs r0, r3, #2
-; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: b .LBB19_3
-; CHECK-NEXT: .LBB19_1: @ in Loop: Header=BB19_3 Depth=1
-; CHECK-NEXT: mov r8, r3
-; CHECK-NEXT: mov r3, r12
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: mov r12, r10
+; CHECK-NEXT: ldrd r7, r9, [r0]
+; CHECK-NEXT: and r6, r3, #3
+; CHECK-NEXT: ldr r0, [r0, #8]
+; CHECK-NEXT: lsrs r3, r3, #2
+; CHECK-NEXT: @ implicit-def: $r10
+; CHECK-NEXT: str r6, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
+; CHECK-NEXT: str r2, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: b .LBB19_4
+; CHECK-NEXT: .LBB19_1: @ in Loop: Header=BB19_4 Depth=1
+; CHECK-NEXT: mov r2, r3
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: mov r5, r11
+; CHECK-NEXT: mov r8, r12
; CHECK-NEXT: .LBB19_2: @ %if.end69
-; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
+; CHECK-NEXT: @ in Loop: Header=BB19_4 Depth=1
; CHECK-NEXT: ldr r7, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: add.w r11, r11, #128
-; CHECK-NEXT: strd r8, r0, [r9]
-; CHECK-NEXT: mov r1, r2
-; CHECK-NEXT: strd r3, r12, [r9, #8]
-; CHECK-NEXT: add.w r9, r9, #16
+; CHECK-NEXT: .LBB19_3: @ %if.end69
+; CHECK-NEXT: @ in Loop: Header=BB19_4 Depth=1
+; CHECK-NEXT: strd r2, r5, [r9]
+; CHECK-NEXT: adds r0, #128
+; CHECK-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: subs r7, #1
-; CHECK-NEXT: beq.w .LBB19_13
-; CHECK-NEXT: .LBB19_3: @ %do.body
+; CHECK-NEXT: strd r3, r8, [r9, #8]
+; CHECK-NEXT: add.w r9, r9, #16
+; CHECK-NEXT: mov r1, r2
+; CHECK-NEXT: beq.w .LBB19_14
+; CHECK-NEXT: .LBB19_4: @ %do.body
; CHECK-NEXT: @ =>This Loop Header: Depth=1
-; CHECK-NEXT: @ Child Loop BB19_5 Depth 2
-; CHECK-NEXT: ldr.w r10, [r9, #12]
+; CHECK-NEXT: @ Child Loop BB19_6 Depth 2
+; CHECK-NEXT: ldrd r3, r11, [r9]
; CHECK-NEXT: mov r6, r2
-; CHECK-NEXT: ldm.w r9, {r3, r4, r12}
-; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: ldrd r8, r12, [r9, #8]
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
; CHECK-NEXT: str r7, [sp, #12] @ 4-byte Spill
-; CHECK-NEXT: wls lr, r0, .LBB19_6
-; CHECK-NEXT: @ %bb.4: @ %while.body.lr.ph
-; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
-; CHECK-NEXT: mov r6, r2
-; CHECK-NEXT: .LBB19_5: @ %while.body
-; CHECK-NEXT: @ Parent Loop BB19_3 Depth=1
+; CHECK-NEXT: wls lr, r2, .LBB19_7
+; CHECK-NEXT: @ %bb.5: @ %while.body.lr.ph
+; CHECK-NEXT: @ in Loop: Header=BB19_4 Depth=1
+; CHECK-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: .LBB19_6: @ %while.body
+; CHECK-NEXT: @ Parent Loop BB19_4 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-NEXT: mov r5, r3
-; CHECK-NEXT: mov r8, r4
-; CHECK-NEXT: ldrd r4, r3, [r1, #8]
-; CHECK-NEXT: vldrw.u32 q2, [r11]
-; CHECK-NEXT: vldrw.u32 q6, [r11, #16]
-; CHECK-NEXT: ldrd r0, r7, [r1]
+; CHECK-NEXT: ldr r3, [r1, #12]
+; CHECK-NEXT: vldrw.u32 q2, [r0]
+; CHECK-NEXT: vldrw.u32 q6, [r0, #16]
+; CHECK-NEXT: mov r4, r11
+; CHECK-NEXT: ldm.w r1, {r2, r7, r11}
; CHECK-NEXT: vmul.f32 q2, q2, r3
-; CHECK-NEXT: vldrw.u32 q7, [r11, #32]
-; CHECK-NEXT: vfma.f32 q2, q6, r4
-; CHECK-NEXT: vldrw.u32 q4, [r11, #48]
+; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
+; CHECK-NEXT: vfma.f32 q2, q6, r11
+; CHECK-NEXT: vldrw.u32 q4, [r0, #48]
; CHECK-NEXT: vfma.f32 q2, q7, r7
-; CHECK-NEXT: vldrw.u32 q5, [r11, #64]
-; CHECK-NEXT: vfma.f32 q2, q4, r0
-; CHECK-NEXT: vldrw.u32 q3, [r11, #80]
+; CHECK-NEXT: vldrw.u32 q5, [r0, #64]
+; CHECK-NEXT: vfma.f32 q2, q4, r2
+; CHECK-NEXT: vldrw.u32 q3, [r0, #80]
; CHECK-NEXT: vfma.f32 q2, q5, r5
-; CHECK-NEXT: vldrw.u32 q1, [r11, #96]
-; CHECK-NEXT: vfma.f32 q2, q3, r8
-; CHECK-NEXT: vldrw.u32 q0, [r11, #112]
-; CHECK-NEXT: vfma.f32 q2, q1, r12
+; CHECK-NEXT: vldrw.u32 q1, [r0, #96]
+; CHECK-NEXT: vfma.f32 q2, q3, r4
+; CHECK-NEXT: vldrw.u32 q0, [r0, #112]
+; CHECK-NEXT: vfma.f32 q2, q1, r8
; CHECK-NEXT: adds r1, #16
-; CHECK-NEXT: vfma.f32 q2, q0, r10
-; CHECK-NEXT: mov r5, r3
-; CHECK-NEXT: vmov r10, r12, d5
+; CHECK-NEXT: vfma.f32 q2, q0, r12
+; CHECK-NEXT: mov r10, r3
+; CHECK-NEXT: vmov r12, r8, d5
; CHECK-NEXT: vstrb.8 q2, [r6], #16
-; CHECK-NEXT: le lr, .LBB19_5
-; CHECK-NEXT: .LBB19_6: @ %while.end
-; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
-; CHECK-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: le lr, .LBB19_6
+; CHECK-NEXT: .LBB19_7: @ %while.end
+; CHECK-NEXT: @ in Loop: Header=BB19_4 Depth=1
+; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: beq .LBB19_1
-; CHECK-NEXT: @ %bb.7: @ %if.then
-; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
-; CHECK-NEXT: ldrd lr, r0, [r1]
-; CHECK-NEXT: vldrw.u32 q0, [r11]
-; CHECK-NEXT: ldrd r8, r1, [r1, #8]
-; CHECK-NEXT: vldrw.u32 q6, [r11, #16]
-; CHECK-NEXT: vldrw.u32 q7, [r11, #32]
-; CHECK-NEXT: vldrw.u32 q4, [r11, #48]
+; CHECK-NEXT: @ %bb.8: @ %if.then
+; CHECK-NEXT: @ in Loop: Header=BB19_4 Depth=1
+; CHECK-NEXT: ldrd lr, r5, [r1]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: ldrd r2, r1, [r1, #8]
+; CHECK-NEXT: vldrw.u32 q6, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
+; CHECK-NEXT: vldrw.u32 q4, [r0, #48]
; CHECK-NEXT: vmul.f32 q0, q0, r1
-; CHECK-NEXT: vldrw.u32 q5, [r11, #64]
-; CHECK-NEXT: vfma.f32 q0, q6, r8
-; CHECK-NEXT: vldrw.u32 q3, [r11, #80]
-; CHECK-NEXT: vfma.f32 q0, q7, r0
-; CHECK-NEXT: vldrw.u32 q2, [r11, #96]
+; CHECK-NEXT: vldrw.u32 q5, [r0, #64]
+; CHECK-NEXT: vfma.f32 q0, q6, r2
+; CHECK-NEXT: vldrw.u32 q3, [r0, #80]
+; CHECK-NEXT: vfma.f32 q0, q7, r5
+; CHECK-NEXT: vldrw.u32 q2, [r0, #96]
; CHECK-NEXT: vfma.f32 q0, q4, lr
-; CHECK-NEXT: vldrw.u32 q1, [r11, #112]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #112]
; CHECK-NEXT: vfma.f32 q0, q5, r3
; CHECK-NEXT: cmp r7, #1
-; CHECK-NEXT: vfma.f32 q0, q3, r4
-; CHECK-NEXT: vfma.f32 q0, q2, r12
-; CHECK-NEXT: vfma.f32 q0, q1, r10
+; CHECK-NEXT: vfma.f32 q0, q3, r11
+; CHECK-NEXT: vfma.f32 q0, q2, r8
+; CHECK-NEXT: vfma.f32 q0, q1, r12
; CHECK-NEXT: vmov r4, s0
-; CHECK-NEXT: bne .LBB19_9
-; CHECK-NEXT: @ %bb.8: @ %if.then58
-; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
+; CHECK-NEXT: bne .LBB19_10
+; CHECK-NEXT: @ %bb.9: @ %if.then58
+; CHECK-NEXT: @ in Loop: Header=BB19_4 Depth=1
+; CHECK-NEXT: mov r5, r10
; CHECK-NEXT: str r4, [r6]
-; CHECK-NEXT: mov r8, lr
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r2, lr
; CHECK-NEXT: mov r3, r4
-; CHECK-NEXT: b .LBB19_12
-; CHECK-NEXT: .LBB19_9: @ %if.else
-; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
-; CHECK-NEXT: vmov r12, s1
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: b .LBB19_2
+; CHECK-NEXT: .LBB19_10: @ %if.else
+; CHECK-NEXT: @ in Loop: Header=BB19_4 Depth=1
+; CHECK-NEXT: vmov r8, s1
; CHECK-NEXT: cmp r7, #2
+; CHECK-NEXT: ldr r7, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: vstr s1, [r6, #4]
; CHECK-NEXT: str r4, [r6]
-; CHECK-NEXT: bne .LBB19_11
-; CHECK-NEXT: @ %bb.10: @ in Loop: Header=BB19_3 Depth=1
-; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r3, r12
-; CHECK-NEXT: mov r0, lr
-; CHECK-NEXT: mov r12, r4
-; CHECK-NEXT: b .LBB19_12
-; CHECK-NEXT: .LBB19_11: @ %if.else64
-; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
+; CHECK-NEXT: bne .LBB19_12
+; CHECK-NEXT: @ %bb.11: @ in Loop: Header=BB19_4 Depth=1
+; CHECK-NEXT: mov r2, r5
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: mov r5, lr
+; CHECK-NEXT: mov r8, r4
+; CHECK-NEXT: b .LBB19_13
+; CHECK-NEXT: .LBB19_12: @ %if.else64
+; CHECK-NEXT: @ in Loop: Header=BB19_4 Depth=1
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: vstr s2, [r6, #8]
-; CHECK-NEXT: .LBB19_12: @ %if.end69
-; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: b .LBB19_2
-; CHECK-NEXT: .LBB19_13: @ %do.end
+; CHECK-NEXT: .LBB19_13: @ %if.end69
+; CHECK-NEXT: @ in Loop: Header=BB19_4 Depth=1
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: b .LBB19_3
+; CHECK-NEXT: .LBB19_14: @ %do.end
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: add sp, #4
diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-increment.ll b/llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
index c43f76ea10444..d490452461a2b 100644
--- a/llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
@@ -610,30 +610,32 @@ define arm_aapcs_vfpcc void @gather_inc_v8i16_simple(ptr noalias nocapture reado
; CHECK-NEXT: .pad #28
; CHECK-NEXT: sub sp, #28
; CHECK-NEXT: cmp r2, #1
-; CHECK-NEXT: strd r1, r2, [sp, #4] @ 8-byte Folded Spill
+; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: blt .LBB14_5
; CHECK-NEXT: @ %bb.1: @ %vector.ph.preheader
-; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: bic r1, r2, #7
+; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: sub.w r3, r1, #8
; CHECK-NEXT: movs r6, #1
+; CHECK-NEXT: mov r11, r2
; CHECK-NEXT: add r2, sp, #12
-; CHECK-NEXT: mov.w r9, #8
-; CHECK-NEXT: bic r1, r1, #7
-; CHECK-NEXT: str r1, [sp] @ 4-byte Spill
-; CHECK-NEXT: sub.w r3, r1, #8
-; CHECK-NEXT: add.w r8, r6, r3, lsr #3
+; CHECK-NEXT: add.w r1, r6, r3, lsr #3
; CHECK-NEXT: adr r3, .LCPI14_0
; CHECK-NEXT: vldrw.u32 q0, [r3]
+; CHECK-NEXT: mov.w r9, #8
+; CHECK-NEXT: str r1, [sp] @ 4-byte Spill
; CHECK-NEXT: .LBB14_2: @ %vector.ph
; CHECK-NEXT: @ =>This Loop Header: Depth=1
; CHECK-NEXT: @ Child Loop BB14_3 Depth 2
-; CHECK-NEXT: dls lr, r8
+; CHECK-NEXT: ldr r1, [sp] @ 4-byte Reload
; CHECK-NEXT: vmov q1, q0
-; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: dls lr, r1
+; CHECK-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: .LBB14_3: @ %vector.body
; CHECK-NEXT: @ Parent Loop BB14_2 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-NEXT: vstrw.32 q1, [r2]
-; CHECK-NEXT: mov r12, r2
+; CHECK-NEXT: mov r8, r2
; CHECK-NEXT: vldrh.s32 q2, [r2, #8]
; CHECK-NEXT: vadd.i16 q1, q1, r9
; CHECK-NEXT: vshl.i32 q2, q2, #1
@@ -649,15 +651,15 @@ define arm_aapcs_vfpcc void @gather_inc_v8i16_simple(ptr noalias nocapture reado
; CHECK-NEXT: ldrh r5, [r5]
; CHECK-NEXT: ldrh.w r2, [r10]
; CHECK-NEXT: ldrh.w r10, [r3]
-; CHECK-NEXT: vmov r3, r11, d4
+; CHECK-NEXT: vmov r3, r12, d4
; CHECK-NEXT: ldrh r1, [r1]
; CHECK-NEXT: ldrh r3, [r3]
-; CHECK-NEXT: ldrh.w r11, [r11]
+; CHECK-NEXT: ldrh.w r12, [r12]
; CHECK-NEXT: vmov.16 q2[0], r3
-; CHECK-NEXT: vmov.16 q2[1], r11
+; CHECK-NEXT: vmov.16 q2[1], r12
; CHECK-NEXT: vmov.16 q2[2], r1
; CHECK-NEXT: vmov.16 q2[3], r2
-; CHECK-NEXT: mov r2, r12
+; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: vmov.16 q2[4], r10
; CHECK-NEXT: vmov.16 q2[5], r4
; CHECK-NEXT: vmov.16 q2[6], r7
@@ -666,9 +668,8 @@ define arm_aapcs_vfpcc void @gather_inc_v8i16_simple(ptr noalias nocapture reado
; CHECK-NEXT: le lr, .LBB14_3
; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: @ in Loop: Header=BB14_2 Depth=1
-; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload
-; CHECK-NEXT: cmp r3, r1
+; CHECK-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: cmp r1, r11
; CHECK-NEXT: bne .LBB14_2
; CHECK-NEXT: .LBB14_5: @ %for.cond.cleanup
; CHECK-NEXT: add sp, #28
@@ -942,8 +943,8 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: .pad #240
-; CHECK-NEXT: sub sp, #240
+; CHECK-NEXT: .pad #256
+; CHECK-NEXT: sub sp, #256
; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: str r1, [sp, #56] @ 4-byte Spill
; CHECK-NEXT: blt.w .LBB16_5
@@ -965,9 +966,9 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: ldr.w r10, [sp, #56] @ 4-byte Reload
; CHECK-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: adr r1, .LCPI16_9
-; CHECK-NEXT: vldrw.u32 q5, [r1]
+; CHECK-NEXT: vldrw.u32 q3, [r1]
; CHECK-NEXT: adr r1, .LCPI16_5
-; CHECK-NEXT: vldrw.u32 q4, [r1]
+; CHECK-NEXT: vldrw.u32 q5, [r1]
; CHECK-NEXT: adr r1, .LCPI16_6
; CHECK-NEXT: vldrw.u32 q2, [r1]
; CHECK-NEXT: adr r1, .LCPI16_3
@@ -975,36 +976,42 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: adr r1, .LCPI16_4
; CHECK-NEXT: vldrw.u32 q6, [r1]
; CHECK-NEXT: adr r1, .LCPI16_2
-; CHECK-NEXT: vstrw.32 q0, [sp, #144] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q0, [sp, #192] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: adr r1, .LCPI16_10
; CHECK-NEXT: bic r12, r2, #7
-; CHECK-NEXT: vstrw.32 q0, [sp, #208] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q0, [sp, #224] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: adr r1, .LCPI16_11
; CHECK-NEXT: str.w r12, [sp, #60] @ 4-byte Spill
-; CHECK-NEXT: vstrw.32 q0, [sp, #224] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q0, [sp, #240] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q0, [r1]
+; CHECK-NEXT: vstrw.32 q0, [sp, #208] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
-; CHECK-NEXT: vldrw.u32 q7, [r1]
; CHECK-NEXT: vstrw.32 q0, [sp, #160] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
-; CHECK-NEXT: vstrw.32 q0, [sp, #128] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q0, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
-; CHECK-NEXT: vstrw.32 q0, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q0, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: .LBB16_3: @ %vector.body
; CHECK-NEXT: @ Parent Loop BB16_2 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
-; CHECK-NEXT: vstrw.32 q1, [sp, #192] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q1, [sp, #176] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q6, [sp, #96] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q0, [sp, #176] @ 16-byte Reload
+; CHECK-NEXT: vmov q6, q5
+; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vadd.i32 q3, q2, r0
-; CHECK-NEXT: vldrw.u32 q0, [sp, #192] @ 16-byte Reload
-; CHECK-NEXT: vmov r2, r8, d6
-; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill
-; CHECK-NEXT: vstrw.32 q6, [sp, #176] @ 16-byte Spill
; CHECK-NEXT: vadd.i32 q1, q0, r0
-; CHECK-NEXT: vadd.i32 q0, q7, r0
+; CHECK-NEXT: vmov r2, r8, d6
; CHECK-NEXT: vmov r7, r6, d3
-; CHECK-NEXT: vstrw.32 q4, [sp, #64] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q0, [sp, #208] @ 16-byte Reload
+; CHECK-NEXT: vstrw.32 q2, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q6, [sp, #64] @ 16-byte Spill
+; CHECK-NEXT: vadd.i32 q0, q0, r0
+; CHECK-NEXT: vldrw.u32 q7, [sp, #160] @ 16-byte Reload
; CHECK-NEXT: vmov r1, r5, d1
+; CHECK-NEXT: vldrw.u32 q4, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q5, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: subs.w r12, r12, #16
; CHECK-NEXT: ldrb r4, [r6]
@@ -1019,7 +1026,7 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: ldrb r7, [r5]
; CHECK-NEXT: vmov.8 q0[2], r1
; CHECK-NEXT: vmov r1, r2, d2
-; CHECK-NEXT: vldrw.u32 q1, [sp, #208] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q1, [sp, #224] @ 16-byte Reload
; CHECK-NEXT: vmov.8 q0[3], r7
; CHECK-NEXT: vadd.i32 q2, q1, r0
; CHECK-NEXT: ldrb r1, [r1]
@@ -1034,12 +1041,12 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: vmov.8 q1[5], r3
; CHECK-NEXT: ldrb.w r9, [r1]
; CHECK-NEXT: vmov r1, lr, d5
-; CHECK-NEXT: vldrw.u32 q2, [sp, #224] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q2, [sp, #240] @ 16-byte Reload
; CHECK-NEXT: vadd.i32 q2, q2, r0
; CHECK-NEXT: ldrb.w r11, [r1]
; CHECK-NEXT: vmov r1, r2, d7
-; CHECK-NEXT: vldrw.u32 q3, [sp, #144] @ 16-byte Reload
-; CHECK-NEXT: vmov q6, q3
+; CHECK-NEXT: vmov q3, q6
+; CHECK-NEXT: vldrw.u32 q6, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: ldrb r1, [r1]
; CHECK-NEXT: ldrb r2, [r2]
; CHECK-NEXT: vmov.8 q1[6], r1
@@ -1052,7 +1059,7 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: vadd.i32 q2, q5, r0
; CHECK-NEXT: vmov.8 q0[5], r3
; CHECK-NEXT: vmov r3, r4, d4
-; CHECK-NEXT: vldrw.u32 q5, [sp, #112] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q5, [sp, #208] @ 16-byte Reload
; CHECK-NEXT: ldrb r1, [r1]
; CHECK-NEXT: ldrb r2, [r2]
; CHECK-NEXT: vmov.8 q0[6], r1
@@ -1061,7 +1068,7 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: ldrb r2, [r4]
; CHECK-NEXT: vmov.8 q0[8], r1
; CHECK-NEXT: vmov r1, r8, d5
-; CHECK-NEXT: vadd.i32 q2, q4, r0
+; CHECK-NEXT: vadd.i32 q2, q3, r0
; CHECK-NEXT: vmov.8 q0[9], r9
; CHECK-NEXT: vmov r4, r5, d4
; CHECK-NEXT: ldrb.w r7, [lr]
@@ -1069,9 +1076,8 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: ldrb r3, [r3]
; CHECK-NEXT: vmov.8 q0[11], r7
; CHECK-NEXT: vmov r7, r6, d5
-; CHECK-NEXT: vldrw.u32 q2, [sp, #176] @ 16-byte Reload
-; CHECK-NEXT: vldrw.u32 q4, [sp, #128] @ 16-byte Reload
-; CHECK-NEXT: vadd.i32 q2, q2, r0
+; CHECK-NEXT: vadd.i32 q2, q6, r0
+; CHECK-NEXT: vldrw.u32 q3, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: ldrb r1, [r1]
; CHECK-NEXT: ldrb r4, [r4]
; CHECK-NEXT: ldrb r5, [r5]
@@ -1090,22 +1096,22 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: ldrb r1, [r2]
; CHECK-NEXT: vmov.8 q0[13], r1
; CHECK-NEXT: vmov r1, r2, d5
-; CHECK-NEXT: vadd.i32 q2, q3, r0
-; CHECK-NEXT: vldrw.u32 q3, [sp, #160] @ 16-byte Reload
; CHECK-NEXT: ldrb r1, [r1]
; CHECK-NEXT: vmov.8 q0[14], r1
; CHECK-NEXT: ldrb r1, [r2]
; CHECK-NEXT: vmov.8 q0[15], r1
; CHECK-NEXT: ldrb.w r1, [r8]
; CHECK-NEXT: vmov.8 q1[15], r1
-; CHECK-NEXT: vmov r1, r2, d4
; CHECK-NEXT: vadd.i8 q0, q1, q0
+; CHECK-NEXT: vldrw.u32 q1, [sp, #192] @ 16-byte Reload
+; CHECK-NEXT: vadd.i32 q2, q1, r0
+; CHECK-NEXT: vmov r1, r2, d4
; CHECK-NEXT: ldrb r1, [r1]
; CHECK-NEXT: ldrb r2, [r2]
; CHECK-NEXT: vmov.8 q1[0], r1
; CHECK-NEXT: vmov.8 q1[1], r2
; CHECK-NEXT: vmov r1, r2, d5
-; CHECK-NEXT: vadd.i32 q2, q3, r0
+; CHECK-NEXT: vadd.i32 q2, q7, r0
; CHECK-NEXT: ldrb r1, [r1]
; CHECK-NEXT: vmov.8 q1[2], r1
; CHECK-NEXT: ldrb r1, [r2]
@@ -1116,7 +1122,7 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: ldrb r1, [r2]
; CHECK-NEXT: vmov.8 q1[5], r1
; CHECK-NEXT: vmov r1, r2, d5
-; CHECK-NEXT: vadd.i32 q2, q4, r0
+; CHECK-NEXT: vadd.i32 q2, q3, r0
; CHECK-NEXT: ldrb r1, [r1]
; CHECK-NEXT: vmov.8 q1[6], r1
; CHECK-NEXT: ldrb r1, [r2]
@@ -1127,7 +1133,7 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: ldrb r1, [r2]
; CHECK-NEXT: vmov.8 q1[9], r1
; CHECK-NEXT: vmov r1, r2, d5
-; CHECK-NEXT: vadd.i32 q2, q5, r0
+; CHECK-NEXT: vadd.i32 q2, q4, r0
; CHECK-NEXT: ldrb r1, [r1]
; CHECK-NEXT: vmov.8 q1[10], r1
; CHECK-NEXT: ldrb r1, [r2]
@@ -1138,38 +1144,39 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: ldrb r1, [r2]
; CHECK-NEXT: vmov.8 q1[13], r1
; CHECK-NEXT: vmov r1, r2, d5
-; CHECK-NEXT: vldrw.u32 q2, [sp, #96] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q2, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: ldrb r1, [r1]
; CHECK-NEXT: vmov.8 q1[14], r1
; CHECK-NEXT: ldrb r1, [r2]
; CHECK-NEXT: vmov.8 q1[15], r1
; CHECK-NEXT: vadd.i8 q0, q0, q1
-; CHECK-NEXT: vldrw.u32 q1, [sp, #192] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q1, [sp, #176] @ 16-byte Reload
; CHECK-NEXT: vstrb.8 q0, [r10], #16
; CHECK-NEXT: vmov.i32 q0, #0x30
-; CHECK-NEXT: vadd.i32 q6, q6, q0
-; CHECK-NEXT: vadd.i32 q3, q3, q0
-; CHECK-NEXT: vstrw.32 q6, [sp, #144] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q6, [sp, #224] @ 16-byte Reload
-; CHECK-NEXT: vadd.i32 q4, q4, q0
; CHECK-NEXT: vadd.i32 q5, q5, q0
-; CHECK-NEXT: vadd.i32 q6, q6, q0
-; CHECK-NEXT: vstrw.32 q3, [sp, #160] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q3, [sp, #208] @ 16-byte Reload
-; CHECK-NEXT: vstrw.32 q6, [sp, #224] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q6, [sp, #176] @ 16-byte Reload
-; CHECK-NEXT: vstrw.32 q4, [sp, #128] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q4, [sp, #64] @ 16-byte Reload
-; CHECK-NEXT: vstrw.32 q5, [sp, #112] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q5, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vadd.i32 q3, q3, q0
+; CHECK-NEXT: vstrw.32 q5, [sp, #208] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q5, [sp, #192] @ 16-byte Reload
+; CHECK-NEXT: vstrw.32 q3, [sp, #144] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q3, [sp, #80] @ 16-byte Reload
+; CHECK-NEXT: vadd.i32 q5, q5, q0
; CHECK-NEXT: vadd.i32 q7, q7, q0
+; CHECK-NEXT: vstrw.32 q5, [sp, #192] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q5, [sp, #240] @ 16-byte Reload
+; CHECK-NEXT: vadd.i32 q4, q4, q0
; CHECK-NEXT: vadd.i32 q1, q1, q0
+; CHECK-NEXT: vadd.i32 q5, q5, q0
; CHECK-NEXT: vadd.i32 q2, q2, q0
-; CHECK-NEXT: vadd.i32 q4, q4, q0
+; CHECK-NEXT: vstrw.32 q5, [sp, #240] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q5, [sp, #224] @ 16-byte Reload
; CHECK-NEXT: vadd.i32 q6, q6, q0
+; CHECK-NEXT: vadd.i32 q3, q3, q0
+; CHECK-NEXT: vadd.i32 q5, q5, q0
+; CHECK-NEXT: vstrw.32 q7, [sp, #160] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q5, [sp, #224] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q5, [sp, #64] @ 16-byte Reload
+; CHECK-NEXT: vstrw.32 q4, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vadd.i32 q5, q5, q0
-; CHECK-NEXT: vstrw.32 q3, [sp, #208] @ 16-byte Spill
; CHECK-NEXT: bne.w .LBB16_3
; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: @ in Loop: Header=BB16_2 Depth=1
@@ -1178,7 +1185,7 @@ define arm_aapcs_vfpcc void @gather_inc_v16i8_complex(ptr noalias nocapture read
; CHECK-NEXT: cmp r1, r2
; CHECK-NEXT: bne.w .LBB16_2
; CHECK-NEXT: .LBB16_5: @ %for.cond.cleanup
-; CHECK-NEXT: add sp, #240
+; CHECK-NEXT: add sp, #256
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
diff --git a/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll b/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
index 67910e40e7705..ba1c46796f75a 100644
--- a/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
@@ -149,7 +149,7 @@ define void @foo_sext_v2i64_v2i32(ptr %dest, ptr %mask, ptr %src) {
; CHECK-BE-NEXT: rsbs.w r3, lr, #0
; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: sbcs.w r3, r1, lr, asr #31
-; CHECK-BE-NEXT: vmov q0[3], q0[1], r12, lr
+; CHECK-BE-NEXT: vmov q1[3], q1[1], r12, lr
; CHECK-BE-NEXT: csetm lr, lt
; CHECK-BE-NEXT: rsbs.w r3, r12, #0
; CHECK-BE-NEXT: @ implicit-def: $q2
@@ -161,33 +161,33 @@ define void @foo_sext_v2i64_v2i32(ptr %dest, ptr %mask, ptr %src) {
; CHECK-BE-NEXT: bpl .LBB5_2
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
; CHECK-BE-NEXT: ldr r3, [r2]
-; CHECK-BE-NEXT: vmov.32 q1[1], r3
-; CHECK-BE-NEXT: vrev64.32 q2, q1
+; CHECK-BE-NEXT: vmov.32 q0[1], r3
+; CHECK-BE-NEXT: vrev64.32 q2, q0
; CHECK-BE-NEXT: .LBB5_2: @ %else
-; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vrev64.32 q0, q1
; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB5_4
; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1
; CHECK-BE-NEXT: ldr r1, [r2, #4]
-; CHECK-BE-NEXT: vrev64.32 q0, q2
-; CHECK-BE-NEXT: vmov.32 q0[3], r1
-; CHECK-BE-NEXT: vrev64.32 q2, q0
-; CHECK-BE-NEXT: .LBB5_4: @ %else2
-; CHECK-BE-NEXT: vrev64.32 q0, q2
+; CHECK-BE-NEXT: vrev64.32 q1, q2
+; CHECK-BE-NEXT: vmov.32 q1[3], r1
; CHECK-BE-NEXT: vrev64.32 q2, q1
-; CHECK-BE-NEXT: vmov r2, s3
+; CHECK-BE-NEXT: .LBB5_4: @ %else2
+; CHECK-BE-NEXT: vrev64.32 q1, q2
; CHECK-BE-NEXT: movs r1, #0
-; CHECK-BE-NEXT: vmov r3, s1
-; CHECK-BE-NEXT: vmov r4, s11
+; CHECK-BE-NEXT: vmov r2, s7
+; CHECK-BE-NEXT: vmov r3, s5
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmov r4, s7
; CHECK-BE-NEXT: asr.w r12, r2, #31
; CHECK-BE-NEXT: asr.w lr, r3, #31
; CHECK-BE-NEXT: rsbs r5, r4, #0
-; CHECK-BE-NEXT: vmov q1[2], q1[0], lr, r12
+; CHECK-BE-NEXT: vmov q2[2], q2[0], lr, r12
; CHECK-BE-NEXT: sbcs.w r4, r1, r4, asr #31
-; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, r2
-; CHECK-BE-NEXT: vmov r3, s9
+; CHECK-BE-NEXT: vmov q2[3], q2[1], r3, r2
+; CHECK-BE-NEXT: vmov r3, s5
; CHECK-BE-NEXT: csetm r2, lt
-; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: vrev64.32 q0, q2
; CHECK-BE-NEXT: rsbs r5, r3, #0
; CHECK-BE-NEXT: sbcs.w r3, r1, r3, asr #31
; CHECK-BE-NEXT: bfi r1, r2, #0, #1
@@ -219,9 +219,9 @@ define void @foo_sext_v2i64_v2i32_unaligned(ptr %dest, ptr %mask, ptr %src) {
; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: ldrd r12, lr, [r1]
; CHECK-LE-NEXT: movs r1, #0
-; CHECK-LE-NEXT: @ implicit-def: $q0
+; CHECK-LE-NEXT: @ implicit-def: $q1
; CHECK-LE-NEXT: rsbs.w r3, r12, #0
-; CHECK-LE-NEXT: vmov q1[2], q1[0], r12, lr
+; CHECK-LE-NEXT: vmov q0[2], q0[0], r12, lr
; CHECK-LE-NEXT: sbcs.w r3, r1, r12, asr #31
; CHECK-LE-NEXT: csetm r3, lt
; CHECK-LE-NEXT: rsbs.w r4, lr, #0
@@ -232,23 +232,23 @@ define void @foo_sext_v2i64_v2i32_unaligned(ptr %dest, ptr %mask, ptr %src) {
; CHECK-LE-NEXT: lsls r3, r1, #31
; CHECK-LE-NEXT: itt ne
; CHECK-LE-NEXT: ldrne r3, [r2]
-; CHECK-LE-NEXT: vmovne.32 q0[0], r3
+; CHECK-LE-NEXT: vmovne.32 q1[0], r3
; CHECK-LE-NEXT: lsls r1, r1, #30
; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: ldrmi r1, [r2, #4]
-; CHECK-LE-NEXT: vmovmi.32 q0[2], r1
-; CHECK-LE-NEXT: vmov r2, s2
+; CHECK-LE-NEXT: vmovmi.32 q1[2], r1
+; CHECK-LE-NEXT: vmov r2, s6
; CHECK-LE-NEXT: movs r1, #0
-; CHECK-LE-NEXT: vmov r3, s4
-; CHECK-LE-NEXT: vmov r4, s0
-; CHECK-LE-NEXT: vmov q0[2], q0[0], r4, r2
+; CHECK-LE-NEXT: vmov r3, s0
+; CHECK-LE-NEXT: vmov r4, s4
+; CHECK-LE-NEXT: vmov q1[2], q1[0], r4, r2
; CHECK-LE-NEXT: rsbs r5, r3, #0
; CHECK-LE-NEXT: asr.w r12, r2, #31
; CHECK-LE-NEXT: sbcs.w r2, r1, r3, asr #31
-; CHECK-LE-NEXT: vmov r3, s6
+; CHECK-LE-NEXT: vmov r3, s2
; CHECK-LE-NEXT: csetm r2, lt
; CHECK-LE-NEXT: asr.w lr, r4, #31
-; CHECK-LE-NEXT: vmov q0[3], q0[1], lr, r12
+; CHECK-LE-NEXT: vmov q1[3], q1[1], lr, r12
; CHECK-LE-NEXT: rsbs r5, r3, #0
; CHECK-LE-NEXT: sbcs.w r3, r1, r3, asr #31
; CHECK-LE-NEXT: bfi r1, r2, #0, #1
@@ -256,11 +256,11 @@ define void @foo_sext_v2i64_v2i32_unaligned(ptr %dest, ptr %mask, ptr %src) {
; CHECK-LE-NEXT: bfi r1, r2, #1, #1
; CHECK-LE-NEXT: lsls r2, r1, #31
; CHECK-LE-NEXT: itt ne
-; CHECK-LE-NEXT: vmovne r2, r3, d0
+; CHECK-LE-NEXT: vmovne r2, r3, d2
; CHECK-LE-NEXT: strdne r2, r3, [r0]
; CHECK-LE-NEXT: lsls r1, r1, #30
; CHECK-LE-NEXT: itt mi
-; CHECK-LE-NEXT: vmovmi r1, r2, d1
+; CHECK-LE-NEXT: vmovmi r1, r2, d3
; CHECK-LE-NEXT: strdmi r1, r2, [r0, #8]
; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: pop {r4, r5, r7, pc}
@@ -275,7 +275,7 @@ define void @foo_sext_v2i64_v2i32_unaligned(ptr %dest, ptr %mask, ptr %src) {
; CHECK-BE-NEXT: rsbs.w r3, lr, #0
; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: sbcs.w r3, r1, lr, asr #31
-; CHECK-BE-NEXT: vmov q0[3], q0[1], r12, lr
+; CHECK-BE-NEXT: vmov q1[3], q1[1], r12, lr
; CHECK-BE-NEXT: csetm lr, lt
; CHECK-BE-NEXT: rsbs.w r3, r12, #0
; CHECK-BE-NEXT: @ implicit-def: $q2
@@ -287,33 +287,33 @@ define void @foo_sext_v2i64_v2i32_unaligned(ptr %dest, ptr %mask, ptr %src) {
; CHECK-BE-NEXT: bpl .LBB6_2
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
; CHECK-BE-NEXT: ldr r3, [r2]
-; CHECK-BE-NEXT: vmov.32 q1[1], r3
-; CHECK-BE-NEXT: vrev64.32 q2, q1
+; CHECK-BE-NEXT: vmov.32 q0[1], r3
+; CHECK-BE-NEXT: vrev64.32 q2, q0
; CHECK-BE-NEXT: .LBB6_2: @ %else
-; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vrev64.32 q0, q1
; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB6_4
; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1
; CHECK-BE-NEXT: ldr r1, [r2, #4]
-; CHECK-BE-NEXT: vrev64.32 q0, q2
-; CHECK-BE-NEXT: vmov.32 q0[3], r1
-; CHECK-BE-NEXT: vrev64.32 q2, q0
-; CHECK-BE-NEXT: .LBB6_4: @ %else2
-; CHECK-BE-NEXT: vrev64.32 q0, q2
+; CHECK-BE-NEXT: vrev64.32 q1, q2
+; CHECK-BE-NEXT: vmov.32 q1[3], r1
; CHECK-BE-NEXT: vrev64.32 q2, q1
-; CHECK-BE-NEXT: vmov r2, s3
+; CHECK-BE-NEXT: .LBB6_4: @ %else2
+; CHECK-BE-NEXT: vrev64.32 q1, q2
; CHECK-BE-NEXT: movs r1, #0
-; CHECK-BE-NEXT: vmov r3, s1
-; CHECK-BE-NEXT: vmov r4, s11
+; CHECK-BE-NEXT: vmov r2, s7
+; CHECK-BE-NEXT: vmov r3, s5
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmov r4, s7
; CHECK-BE-NEXT: asr.w r12, r2, #31
; CHECK-BE-NEXT: asr.w lr, r3, #31
; CHECK-BE-NEXT: rsbs r5, r4, #0
-; CHECK-BE-NEXT: vmov q1[2], q1[0], lr, r12
+; CHECK-BE-NEXT: vmov q2[2], q2[0], lr, r12
; CHECK-BE-NEXT: sbcs.w r4, r1, r4, asr #31
-; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, r2
-; CHECK-BE-NEXT: vmov r3, s9
+; CHECK-BE-NEXT: vmov q2[3], q2[1], r3, r2
+; CHECK-BE-NEXT: vmov r3, s5
; CHECK-BE-NEXT: csetm r2, lt
-; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: vrev64.32 q0, q2
; CHECK-BE-NEXT: rsbs r5, r3, #0
; CHECK-BE-NEXT: sbcs.w r3, r1, r3, asr #31
; CHECK-BE-NEXT: bfi r1, r2, #0, #1
diff --git a/llvm/test/CodeGen/Thumb2/mve-phireg.ll b/llvm/test/CodeGen/Thumb2/mve-phireg.ll
index 00a998cba6426..9fa2777d9847a 100644
--- a/llvm/test/CodeGen/Thumb2/mve-phireg.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-phireg.ll
@@ -142,7 +142,7 @@ define dso_local i32 @e() #0 {
; CHECK-NEXT: .pad #392
; CHECK-NEXT: sub sp, #392
; CHECK-NEXT: movw r7, :lower16:.L_MergedGlobals
-; CHECK-NEXT: vldr s15, .LCPI1_1
+; CHECK-NEXT: vldr s19, .LCPI1_1
; CHECK-NEXT: movt r7, :upper16:.L_MergedGlobals
; CHECK-NEXT: movw r2, :lower16:e
; CHECK-NEXT: mov r4, r7
@@ -150,26 +150,26 @@ define dso_local i32 @e() #0 {
; CHECK-NEXT: ldr r6, [r4, #8]!
; CHECK-NEXT: movt r2, :upper16:e
; CHECK-NEXT: ldr r0, [r3, #4]!
-; CHECK-NEXT: vmov r5, s15
+; CHECK-NEXT: vmov r5, s19
; CHECK-NEXT: vmov q0[2], q0[0], r4, r4
-; CHECK-NEXT: vldr s12, .LCPI1_0
-; CHECK-NEXT: vmov s13, r3
+; CHECK-NEXT: vldr s16, .LCPI1_0
+; CHECK-NEXT: vmov s17, r3
; CHECK-NEXT: vmov q0[3], q0[1], r5, r2
; CHECK-NEXT: vdup.32 q7, r3
; CHECK-NEXT: vmov q6[2], q6[0], r3, r5
; CHECK-NEXT: vstrw.32 q0, [sp, #76]
; CHECK-NEXT: vmov q0, q7
; CHECK-NEXT: vmov q6[3], q6[1], r3, r2
-; CHECK-NEXT: vmov q4, q7
+; CHECK-NEXT: vmov q3, q7
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: vmov.32 q7[1], r2
; CHECK-NEXT: vmov s21, r2
; CHECK-NEXT: movs r1, #64
-; CHECK-NEXT: vmov.f32 s20, s12
+; CHECK-NEXT: vmov.f32 s20, s16
; CHECK-NEXT: str r0, [sp, #24]
-; CHECK-NEXT: vmov.f32 s22, s13
+; CHECK-NEXT: vmov.f32 s22, s17
; CHECK-NEXT: str r6, [r0]
-; CHECK-NEXT: vmov.f32 s23, s15
+; CHECK-NEXT: vmov.f32 s23, s19
; CHECK-NEXT: str r0, [r0]
; CHECK-NEXT: vstrw.32 q5, [r0]
; CHECK-NEXT: vstrw.32 q7, [r0]
@@ -180,12 +180,12 @@ define dso_local i32 @e() #0 {
; CHECK-NEXT: vmov q2[2], q2[0], r3, r3
; CHECK-NEXT: mov.w r12, #4
; CHECK-NEXT: vmov q1[3], q1[1], r2, r4
-; CHECK-NEXT: vmov.f32 s14, s13
+; CHECK-NEXT: vmov.f32 s18, s17
; CHECK-NEXT: vmov q2[3], q2[1], r4, r5
-; CHECK-NEXT: vmov.32 q4[0], r8
+; CHECK-NEXT: vmov.32 q3[0], r8
; CHECK-NEXT: @ implicit-def: $r2
; CHECK-NEXT: str.w r8, [sp, #28]
-; CHECK-NEXT: vstrw.32 q3, [sp, #44]
+; CHECK-NEXT: vstrw.32 q4, [sp, #44]
; CHECK-NEXT: strh.w r12, [sp, #390]
; CHECK-NEXT: wlstp.8 lr, r1, .LBB1_2
; CHECK-NEXT: .LBB1_1: @ =>This Inner Loop Header: Depth=1
@@ -195,7 +195,7 @@ define dso_local i32 @e() #0 {
; CHECK-NEXT: .LBB1_2: @ %entry
; CHECK-NEXT: vstrw.32 q1, [r0]
; CHECK-NEXT: str.w r8, [r7]
-; CHECK-NEXT: vstrw.32 q4, [r0]
+; CHECK-NEXT: vstrw.32 q3, [r0]
; CHECK-NEXT: vstrw.32 q2, [r0]
; CHECK-NEXT: str.w r12, [sp, #308]
; CHECK-NEXT: .LBB1_3: @ %for.cond
diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll b/llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
index 2587a0bb6e00b..abfd99aba59d8 100644
--- a/llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
@@ -402,8 +402,8 @@ define void @DCT_mve4(ptr nocapture readonly %S, ptr nocapture readonly %pIn, pt
; CHECK-NEXT: movs r6, #1
; CHECK-NEXT: ldr r1, [r0]
; CHECK-NEXT: add.w r0, r2, r2, lsl #1
-; CHECK-NEXT: add.w r12, r1, r2, lsl #2
-; CHECK-NEXT: add.w r8, r1, r2, lsl #3
+; CHECK-NEXT: add.w r8, r1, r2, lsl #2
+; CHECK-NEXT: add.w r12, r1, r2, lsl #3
; CHECK-NEXT: add.w r10, r1, r2, lsl #4
; CHECK-NEXT: add.w r9, r1, r0, lsl #2
; CHECK-NEXT: adds r0, r2, #3
@@ -419,8 +419,8 @@ define void @DCT_mve4(ptr nocapture readonly %S, ptr nocapture readonly %pIn, pt
; CHECK-NEXT: @ Child Loop BB3_3 Depth 2
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: vmov.i32 q0, #0x0
-; CHECK-NEXT: mov r3, r12
-; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: mov r5, r9
; CHECK-NEXT: mov r4, r10
; CHECK-NEXT: vmov.i32 q1, #0x0
@@ -468,8 +468,8 @@ define void @DCT_mve4(ptr nocapture readonly %S, ptr nocapture readonly %pIn, pt
; CHECK-NEXT: add.w r0, r1, r0, lsl #2
; CHECK-NEXT: vstr s0, [r0]
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
-; CHECK-NEXT: add r12, r0
; CHECK-NEXT: add r8, r0
+; CHECK-NEXT: add r12, r0
; CHECK-NEXT: add r9, r0
; CHECK-NEXT: add r10, r0
; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
@@ -1332,44 +1332,45 @@ define void @DCT_mve8(ptr nocapture readonly %S, ptr nocapture readonly %pIn, pt
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q6, q1, q0
; CHECK-NEXT: vldrwt.u32 q1, [r5]
-; CHECK-NEXT: vstrw.32 q6, [sp, #16] @ 16-byte Spill
-; CHECK-NEXT: vmov q6, q5
-; CHECK-NEXT: vpst
+; CHECK-NEXT: adds r5, r7, r6
+; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q7, q1, q0
+; CHECK-NEXT: vldrwt.u32 q1, [r7]
+; CHECK-NEXT: vstrw.32 q7, [sp, #16] @ 16-byte Spill
+; CHECK-NEXT: vmov q7, q6
+; CHECK-NEXT: vmov q6, q5
; CHECK-NEXT: vmov q5, q4
; CHECK-NEXT: vmov q4, q3
; CHECK-NEXT: vmov q3, q2
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vldrwt.u32 q1, [r7]
; CHECK-NEXT: vldrw.u32 q2, [sp, #32] @ 16-byte Reload
-; CHECK-NEXT: adds r5, r7, r6
+; CHECK-NEXT: adds r7, r5, r6
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q2, q1, q0
; CHECK-NEXT: vldrwt.u32 q1, [r5]
; CHECK-NEXT: vstrw.32 q2, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [sp, #48] @ 16-byte Reload
-; CHECK-NEXT: adds r7, r5, r6
+; CHECK-NEXT: adds r5, r7, r6
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q2, q1, q0
; CHECK-NEXT: vldrwt.u32 q1, [r7]
-; CHECK-NEXT: adds r5, r7, r6
; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov q2, q3
-; CHECK-NEXT: vmov q3, q4
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q2, q1, q0
; CHECK-NEXT: vldrwt.u32 q1, [r5]
-; CHECK-NEXT: vmov q4, q5
; CHECK-NEXT: adds r7, r5, r6
+; CHECK-NEXT: vmov q3, q4
+; CHECK-NEXT: vmov q4, q5
+; CHECK-NEXT: vmov q5, q6
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q4, q1, q0
; CHECK-NEXT: vldrwt.u32 q1, [r7]
-; CHECK-NEXT: vmov q5, q6
; CHECK-NEXT: adds r5, r7, r6
+; CHECK-NEXT: vmov q6, q7
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q5, q1, q0
; CHECK-NEXT: vldrwt.u32 q1, [r5]
-; CHECK-NEXT: vldrw.u32 q6, [sp, #16] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q7, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vpst
; CHECK-NEXT: vfmat.f32 q3, q1, q0
; CHECK-NEXT: le lr, .LBB7_3
diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll b/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
index f3495eb937891..de48b86d48c76 100644
--- a/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
@@ -566,20 +566,20 @@ if.end: ; preds = %for.cond.cleanup23,
define i32 @arm_nn_mat_mul_core_4x_s8(i32 %row_elements, i32 %offset, ptr %row_base, ptr %col_base, ptr nocapture readnone %sum_col, ptr nocapture %output) {
; CHECK-LABEL: arm_nn_mat_mul_core_4x_s8:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r10, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r10, lr}
-; CHECK-NEXT: ldr.w r12, [sp, #32]
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: ldr.w r9, [sp, #36]
; CHECK-NEXT: cmp r0, #1
; CHECK-NEXT: blt .LBB4_3
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
-; CHECK-NEXT: add.w r5, r2, r1, lsl #1
+; CHECK-NEXT: adds r4, r2, r1
; CHECK-NEXT: mov.w r8, #0
-; CHECK-NEXT: movs r4, #0
+; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: mov.w r10, #0
-; CHECK-NEXT: movs r6, #0
-; CHECK-NEXT: adds r7, r2, r1
+; CHECK-NEXT: add.w r5, r2, r1, lsl #1
; CHECK-NEXT: add.w r1, r1, r1, lsl #1
; CHECK-NEXT: add r1, r2
+; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: dlstp.8 lr, r0
; CHECK-NEXT: .LBB4_2: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
@@ -587,8 +587,8 @@ define i32 @arm_nn_mat_mul_core_4x_s8(i32 %row_elements, i32 %offset, ptr %row_b
; CHECK-NEXT: vldrb.u8 q1, [r1], #16
; CHECK-NEXT: vmlava.s8 r10, q1, q0
; CHECK-NEXT: vldrb.u8 q1, [r5], #16
-; CHECK-NEXT: vmlava.s8 r4, q1, q0
-; CHECK-NEXT: vldrb.u8 q1, [r7], #16
+; CHECK-NEXT: vmlava.s8 r12, q1, q0
+; CHECK-NEXT: vldrb.u8 q1, [r4], #16
; CHECK-NEXT: vmlava.s8 r6, q1, q0
; CHECK-NEXT: vldrb.u8 q1, [r2], #16
; CHECK-NEXT: vmlava.s8 r8, q1, q0
@@ -596,14 +596,14 @@ define i32 @arm_nn_mat_mul_core_4x_s8(i32 %row_elements, i32 %offset, ptr %row_b
; CHECK-NEXT: b .LBB4_4
; CHECK-NEXT: .LBB4_3:
; CHECK-NEXT: mov.w r10, #0
-; CHECK-NEXT: movs r4, #0
+; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: mov.w r8, #0
; CHECK-NEXT: .LBB4_4: @ %for.cond.cleanup
; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: strd r8, r6, [r12]
-; CHECK-NEXT: strd r4, r10, [r12, #8]
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r10, pc}
+; CHECK-NEXT: strd r8, r6, [r9]
+; CHECK-NEXT: strd r12, r10, [r9, #8]
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
entry:
%add = add nsw i32 %row_elements, 15
%div = sdiv i32 %add, 16
@@ -1059,68 +1059,69 @@ define arm_aapcs_vfpcc void @_Z37_arm_radix4_butterfly_inverse_f32_mvePK21arm_cf
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: .pad #40
-; CHECK-NEXT: sub sp, #40
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, #48
; CHECK-NEXT: cmp r2, #8
-; CHECK-NEXT: vstr s0, [sp] @ 4-byte Spill
-; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
-; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: vstr s0, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: str r2, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: blo .LBB7_9
; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: mov.w r11, #0
-; CHECK-NEXT: mov.w r12, #1
-; CHECK-NEXT: str r2, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: movs r3, #1
+; CHECK-NEXT: str r2, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: lsrs r1, r2, #2
; CHECK-NEXT: b .LBB7_3
; CHECK-NEXT: .LBB7_2: @ in Loop: Header=BB7_3 Depth=1
-; CHECK-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: add.w r11, r11, #1
-; CHECK-NEXT: lsl.w r12, r12, #2
+; CHECK-NEXT: lsls r3, r3, #2
; CHECK-NEXT: cmp r2, #7
; CHECK-NEXT: asr.w r1, r2, #2
; CHECK-NEXT: ble .LBB7_9
; CHECK-NEXT: .LBB7_3: @ =>This Loop Header: Depth=1
; CHECK-NEXT: @ Child Loop BB7_6 Depth 2
; CHECK-NEXT: @ Child Loop BB7_7 Depth 3
-; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT: cmp.w r12, #1
-; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: str r1, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: cmp r3, #1
+; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: lsr.w r2, r1, #2
-; CHECK-NEXT: str r2, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: str r2, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: blt .LBB7_2
; CHECK-NEXT: @ %bb.4: @ in Loop: Header=BB7_3 Depth=1
; CHECK-NEXT: lsrs r2, r1, #3
-; CHECK-NEXT: str r2, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: str r2, [sp, #32] @ 4-byte Spill
; CHECK-NEXT: beq .LBB7_2
; CHECK-NEXT: @ %bb.5: @ %.preheader
; CHECK-NEXT: @ in Loop: Header=BB7_3 Depth=1
-; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: lsls r1, r1, #1
-; CHECK-NEXT: movs r4, #0
-; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: mov.w r12, #0
+; CHECK-NEXT: str r1, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: lsl.w r10, r2, #1
; CHECK-NEXT: .LBB7_6: @ Parent Loop BB7_3 Depth=1
; CHECK-NEXT: @ => This Loop Header: Depth=2
; CHECK-NEXT: @ Child Loop BB7_7 Depth 3
-; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
-; CHECK-NEXT: ldrd lr, r2, [r0, #16]
-; CHECK-NEXT: ldrd r3, r8, [r0, #24]
-; CHECK-NEXT: muls r1, r4, r1
-; CHECK-NEXT: ldr.w r2, [r2, r11, lsl #2]
-; CHECK-NEXT: ldrd r7, r5, [r0, #32]
+; CHECK-NEXT: add.w r7, r0, #16
+; CHECK-NEXT: ldr r4, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: ldr r5, [r0, #36]
+; CHECK-NEXT: ldm r7, {r1, r2, r3, r6, r7}
; CHECK-NEXT: ldr.w r3, [r3, r11, lsl #2]
-; CHECK-NEXT: ldr.w r6, [lr, r11, lsl #2]
-; CHECK-NEXT: add.w r7, r7, r2, lsl #2
-; CHECK-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: mul r4, r4, r12
+; CHECK-NEXT: ldr.w r1, [r1, r11, lsl #2]
+; CHECK-NEXT: ldr.w r2, [r2, r11, lsl #2]
; CHECK-NEXT: add.w r5, r5, r3, lsl #2
-; CHECK-NEXT: add.w r1, r2, r1, lsl #2
-; CHECK-NEXT: add.w r3, r8, r6, lsl #2
-; CHECK-NEXT: ldr r6, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: add.w r3, r6, r1, lsl #2
+; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: ldr r6, [sp, #32] @ 4-byte Reload
+; CHECK-NEXT: add.w r7, r7, r2, lsl #2
+; CHECK-NEXT: add.w r1, r1, r4, lsl #2
; CHECK-NEXT: add.w r2, r1, r10, lsl #2
+; CHECK-NEXT: dls lr, r6
; CHECK-NEXT: add.w r8, r2, r10, lsl #2
; CHECK-NEXT: add.w r9, r8, r10, lsl #2
-; CHECK-NEXT: dls lr, r6
; CHECK-NEXT: .LBB7_7: @ Parent Loop BB7_3 Depth=1
; CHECK-NEXT: @ Parent Loop BB7_6 Depth=2
; CHECK-NEXT: @ => This Inner Loop Header: Depth=3
@@ -1151,21 +1152,22 @@ define arm_aapcs_vfpcc void @_Z37_arm_radix4_butterfly_inverse_f32_mvePK21arm_cf
; CHECK-NEXT: vstrb.8 q2, [r9], #16
; CHECK-NEXT: le lr, .LBB7_7
; CHECK-NEXT: @ %bb.8: @ in Loop: Header=BB7_6 Depth=2
-; CHECK-NEXT: adds r4, #1
-; CHECK-NEXT: cmp r4, r12
+; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: add.w r12, r12, #1
+; CHECK-NEXT: cmp r12, r3
; CHECK-NEXT: bne .LBB7_6
; CHECK-NEXT: b .LBB7_2
; CHECK-NEXT: .LBB7_9:
; CHECK-NEXT: adr r1, .LCPI7_0
-; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: vldrw.u32 q1, [r1]
-; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: vadd.i32 q1, q1, r1
; CHECK-NEXT: lsrs r0, r0, #3
; CHECK-NEXT: vldrw.u32 q2, [q1, #64]!
; CHECK-NEXT: wls lr, r0, .LBB7_12
; CHECK-NEXT: @ %bb.10:
-; CHECK-NEXT: vldr s0, [sp] @ 4-byte Reload
+; CHECK-NEXT: vldr s0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vldrw.u32 q0, [q1, #16]
; CHECK-NEXT: .LBB7_11: @ =>This Inner Loop Header: Depth=1
@@ -1179,7 +1181,7 @@ define arm_aapcs_vfpcc void @_Z37_arm_radix4_butterfly_inverse_f32_mvePK21arm_cf
; CHECK-NEXT: vsub.f32 q2, q0, q3
; CHECK-NEXT: vmul.f32 q7, q7, r0
; CHECK-NEXT: vadd.f32 q3, q0, q3
-; CHECK-NEXT: vstrw.32 q7, [sp, #24] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vcadd.f32 q7, q6, q5, #90
; CHECK-NEXT: vmul.f32 q4, q2, r0
; CHECK-NEXT: vldrw.u32 q2, [q1, #64]!
@@ -1189,11 +1191,11 @@ define arm_aapcs_vfpcc void @_Z37_arm_radix4_butterfly_inverse_f32_mvePK21arm_cf
; CHECK-NEXT: vstrw.32 q3, [q1, #-64]
; CHECK-NEXT: vstrw.32 q4, [q1, #-56]
; CHECK-NEXT: vstrw.32 q5, [q1, #-48]
-; CHECK-NEXT: vldrw.u32 q3, [sp, #24] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q3, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q3, [q1, #-40]
; CHECK-NEXT: le lr, .LBB7_11
; CHECK-NEXT: .LBB7_12:
-; CHECK-NEXT: add sp, #40
+; CHECK-NEXT: add sp, #48
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
diff --git a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
index 40d534a0ebfc5..02105fd6be974 100644
--- a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
@@ -11,96 +11,91 @@ define arm_aapcs_vfpcc void @ssatmul_s_q31(ptr nocapture readonly %pSrcA, ptr no
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: beq.w .LBB0_8
; CHECK-NEXT: @ %bb.1: @ %entry
-; CHECK-NEXT: mov r5, r2
; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: bne .LBB0_3
; CHECK-NEXT: @ %bb.2:
-; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: movs r7, #0
; CHECK-NEXT: mov r12, r0
-; CHECK-NEXT: mov r11, r1
-; CHECK-NEXT: mov r10, r5
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: mov r11, r2
; CHECK-NEXT: b .LBB0_6
; CHECK-NEXT: .LBB0_3: @ %vector.ph
-; CHECK-NEXT: bic r2, r3, #1
+; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: bic r3, r3, #1
+; CHECK-NEXT: subs r7, r3, #2
; CHECK-NEXT: adr r4, .LCPI0_0
-; CHECK-NEXT: subs r7, r2, #2
; CHECK-NEXT: movs r6, #1
; CHECK-NEXT: vldrw.u32 q0, [r4]
; CHECK-NEXT: adr r4, .LCPI0_1
-; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: add.w lr, r6, r7, lsr #1
-; CHECK-NEXT: str r2, [sp] @ 4-byte Spill
-; CHECK-NEXT: add.w r10, r5, r2, lsl #2
-; CHECK-NEXT: add.w r11, r1, r2, lsl #2
-; CHECK-NEXT: add.w r12, r0, r2, lsl #2
+; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
+; CHECK-NEXT: add.w r11, r2, r3, lsl #2
+; CHECK-NEXT: add.w r10, r1, r3, lsl #2
+; CHECK-NEXT: add.w r12, r0, r3, lsl #2
; CHECK-NEXT: vldrw.u32 q1, [r4]
; CHECK-NEXT: .LBB0_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldrd r4, r2, [r0], #8
-; CHECK-NEXT: mov.w r3, #-1
+; CHECK-NEXT: ldrd r4, r5, [r0], #8
+; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: ldrd r7, r8, [r1], #8
; CHECK-NEXT: smull r4, r7, r7, r4
; CHECK-NEXT: asrl r4, r7, #31
; CHECK-NEXT: rsbs.w r9, r4, #-2147483648
-; CHECK-NEXT: sbcs r3, r7
-; CHECK-NEXT: mov r9, r5
+; CHECK-NEXT: mov.w r9, #-1
+; CHECK-NEXT: sbcs.w r3, r9, r7
; CHECK-NEXT: csetm r3, lt
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: bfi r5, r3, #0, #8
-; CHECK-NEXT: smull r2, r3, r8, r2
-; CHECK-NEXT: asrl r2, r3, #31
-; CHECK-NEXT: rsbs.w r6, r2, #-2147483648
-; CHECK-NEXT: vmov q2[2], q2[0], r4, r2
-; CHECK-NEXT: mov.w r6, #-1
+; CHECK-NEXT: bfi r6, r3, #0, #8
+; CHECK-NEXT: smull r8, r3, r8, r5
+; CHECK-NEXT: asrl r8, r3, #31
+; CHECK-NEXT: rsbs.w r5, r8, #-2147483648
+; CHECK-NEXT: vmov q2[2], q2[0], r4, r8
+; CHECK-NEXT: sbcs.w r5, r9, r3
; CHECK-NEXT: vmov q2[3], q2[1], r7, r3
-; CHECK-NEXT: sbcs r6, r3
-; CHECK-NEXT: csetm r6, lt
-; CHECK-NEXT: bfi r5, r6, #8, #8
+; CHECK-NEXT: csetm r5, lt
+; CHECK-NEXT: bfi r6, r5, #8, #8
+; CHECK-NEXT: vmsr p0, r6
; CHECK-NEXT: mvn r6, #-2147483648
-; CHECK-NEXT: vmsr p0, r5
-; CHECK-NEXT: mov r5, r9
; CHECK-NEXT: vpsel q2, q2, q0
-; CHECK-NEXT: vmov r2, r3, d4
-; CHECK-NEXT: subs r2, r2, r6
-; CHECK-NEXT: sbcs r2, r3, #0
-; CHECK-NEXT: mov.w r3, #0
-; CHECK-NEXT: csetm r2, lt
-; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, r4, d5
-; CHECK-NEXT: subs r2, r2, r6
-; CHECK-NEXT: sbcs r2, r4, #0
-; CHECK-NEXT: csetm r2, lt
-; CHECK-NEXT: bfi r3, r2, #8, #8
-; CHECK-NEXT: vmsr p0, r3
+; CHECK-NEXT: vmov r3, r4, d4
+; CHECK-NEXT: subs r3, r3, r6
+; CHECK-NEXT: sbcs r3, r4, #0
+; CHECK-NEXT: mov.w r4, #0
+; CHECK-NEXT: csetm r3, lt
+; CHECK-NEXT: bfi r4, r3, #0, #8
+; CHECK-NEXT: vmov r3, r5, d5
+; CHECK-NEXT: subs r3, r3, r6
+; CHECK-NEXT: sbcs r3, r5, #0
+; CHECK-NEXT: csetm r3, lt
+; CHECK-NEXT: bfi r4, r3, #8, #8
+; CHECK-NEXT: vmsr p0, r4
; CHECK-NEXT: vpsel q2, q2, q1
-; CHECK-NEXT: vmov r2, s10
-; CHECK-NEXT: vmov r3, s8
-; CHECK-NEXT: strd r3, r2, [r5]
-; CHECK-NEXT: add.w r5, r9, #8
+; CHECK-NEXT: vmov r3, s10
+; CHECK-NEXT: vmov r4, s8
+; CHECK-NEXT: strd r4, r3, [r2], #8
; CHECK-NEXT: le lr, .LBB0_4
; CHECK-NEXT: @ %bb.5: @ %middle.block
-; CHECK-NEXT: ldrd r2, r3, [sp] @ 8-byte Folded Reload
-; CHECK-NEXT: cmp r2, r3
+; CHECK-NEXT: ldrd r7, r3, [sp] @ 8-byte Folded Reload
+; CHECK-NEXT: cmp r7, r3
; CHECK-NEXT: beq .LBB0_8
; CHECK-NEXT: .LBB0_6: @ %for.body.preheader
-; CHECK-NEXT: sub.w lr, r3, r2
+; CHECK-NEXT: sub.w lr, r3, r7
; CHECK-NEXT: mov.w r0, #-1
; CHECK-NEXT: mov.w r1, #-2147483648
-; CHECK-NEXT: mvn r3, #-2147483648
+; CHECK-NEXT: mvn r2, #-2147483648
; CHECK-NEXT: .LBB0_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldr r2, [r12], #4
-; CHECK-NEXT: ldr r4, [r11], #4
-; CHECK-NEXT: smull r2, r5, r4, r2
-; CHECK-NEXT: asrl r2, r5, #31
-; CHECK-NEXT: subs r4, r1, r2
-; CHECK-NEXT: sbcs.w r4, r0, r5
-; CHECK-NEXT: csel r2, r2, r1, lt
-; CHECK-NEXT: csel r4, r5, r0, lt
-; CHECK-NEXT: subs r5, r2, r3
-; CHECK-NEXT: sbcs r4, r4, #0
-; CHECK-NEXT: csel r2, r2, r3, lt
-; CHECK-NEXT: str r2, [r10], #4
+; CHECK-NEXT: ldr r3, [r12], #4
+; CHECK-NEXT: ldr r4, [r10], #4
+; CHECK-NEXT: smull r4, r3, r4, r3
+; CHECK-NEXT: asrl r4, r3, #31
+; CHECK-NEXT: subs r5, r1, r4
+; CHECK-NEXT: sbcs.w r5, r0, r3
+; CHECK-NEXT: csel r4, r4, r1, lt
+; CHECK-NEXT: csel r3, r3, r0, lt
+; CHECK-NEXT: subs r5, r4, r2
+; CHECK-NEXT: sbcs r3, r3, #0
+; CHECK-NEXT: csel r3, r4, r2, lt
+; CHECK-NEXT: str r3, [r11], #4
; CHECK-NEXT: le lr, .LBB0_7
; CHECK-NEXT: .LBB0_8: @ %for.cond.cleanup
; CHECK-NEXT: add sp, #8
diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
index c7661a1f430c6..cf49b2e383799 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
@@ -2282,22 +2282,23 @@ define i64 @add4i64(ptr noalias nocapture readonly %x, i32 %n) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
-; CHECK-NEXT: cbz r1, .LBB29_3
+; CHECK-NEXT: cbz r1, .LBB29_4
; CHECK-NEXT: @ %bb.1: @ %vector.ph
-; CHECK-NEXT: movs r2, #0
-; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: mov r2, r0
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: mov r3, r0
; CHECK-NEXT: dlstp.32 lr, r1
; CHECK-NEXT: .LBB29_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vldrw.u32 q0, [r0], #16
-; CHECK-NEXT: vaddlva.s32 r2, r3, q0
+; CHECK-NEXT: vldrw.u32 q0, [r2], #16
+; CHECK-NEXT: vaddlva.s32 r0, r3, q0
; CHECK-NEXT: letp lr, .LBB29_2
-; CHECK-NEXT: b .LBB29_4
-; CHECK-NEXT: .LBB29_3:
-; CHECK-NEXT: movs r2, #0
-; CHECK-NEXT: mov r3, r2
-; CHECK-NEXT: .LBB29_4: @ %for.cond.cleanup
-; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-NEXT: mov r1, r3
+; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: .LBB29_4:
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: mov r3, r0
; CHECK-NEXT: mov r1, r3
; CHECK-NEXT: pop {r7, pc}
entry:
@@ -2332,27 +2333,28 @@ for.cond.cleanup: ; preds = %vector.body, %entry
define i64 @mla4i64(ptr noalias nocapture readonly %x, ptr noalias nocapture readonly %y, i32 %n) {
; CHECK-LABEL: mla4i64:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r7, lr}
-; CHECK-NEXT: push {r7, lr}
-; CHECK-NEXT: cbz r2, .LBB30_3
+; CHECK-NEXT: .save {r5, lr}
+; CHECK-NEXT: push {r5, lr}
+; CHECK-NEXT: cbz r2, .LBB30_4
; CHECK-NEXT: @ %bb.1: @ %vector.ph
-; CHECK-NEXT: mov.w r12, #0
-; CHECK-NEXT: mov r3, r12
+; CHECK-NEXT: mov r3, r0
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: dlstp.32 lr, r2
; CHECK-NEXT: .LBB30_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vldrw.u32 q0, [r0], #16
+; CHECK-NEXT: vldrw.u32 q0, [r3], #16
; CHECK-NEXT: vldrw.u32 q1, [r1], #16
-; CHECK-NEXT: vmlalva.s32 r12, r3, q1, q0
+; CHECK-NEXT: vmlalva.s32 r0, r5, q1, q0
; CHECK-NEXT: letp lr, .LBB30_2
-; CHECK-NEXT: b .LBB30_4
-; CHECK-NEXT: .LBB30_3:
-; CHECK-NEXT: mov.w r12, #0
-; CHECK-NEXT: mov r3, r12
-; CHECK-NEXT: .LBB30_4: @ %for.cond.cleanup
-; CHECK-NEXT: mov r0, r12
-; CHECK-NEXT: mov r1, r3
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: pop {r5, pc}
+; CHECK-NEXT: .LBB30_4:
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: pop {r5, pc}
entry:
%cmp9.not = icmp eq i32 %n, 0
br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
@@ -2390,27 +2392,28 @@ for.cond.cleanup: ; preds = %vector.body, %entry
define i64 @mla8i64(ptr noalias nocapture readonly %x, ptr noalias nocapture readonly %y, i32 %n) {
; CHECK-LABEL: mla8i64:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r7, lr}
-; CHECK-NEXT: push {r7, lr}
-; CHECK-NEXT: cbz r2, .LBB31_3
+; CHECK-NEXT: .save {r5, lr}
+; CHECK-NEXT: push {r5, lr}
+; CHECK-NEXT: cbz r2, .LBB31_4
; CHECK-NEXT: @ %bb.1: @ %vector.ph
-; CHECK-NEXT: mov.w r12, #0
-; CHECK-NEXT: mov r3, r12
+; CHECK-NEXT: mov r3, r0
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: dlstp.16 lr, r2
; CHECK-NEXT: .LBB31_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vldrh.u16 q0, [r0], #16
+; CHECK-NEXT: vldrh.u16 q0, [r3], #16
; CHECK-NEXT: vldrh.u16 q1, [r1], #16
-; CHECK-NEXT: vmlalva.s16 r12, r3, q1, q0
+; CHECK-NEXT: vmlalva.s16 r0, r5, q1, q0
; CHECK-NEXT: letp lr, .LBB31_2
-; CHECK-NEXT: b .LBB31_4
-; CHECK-NEXT: .LBB31_3:
-; CHECK-NEXT: mov.w r12, #0
-; CHECK-NEXT: mov r3, r12
-; CHECK-NEXT: .LBB31_4: @ %for.cond.cleanup
-; CHECK-NEXT: mov r0, r12
-; CHECK-NEXT: mov r1, r3
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: pop {r5, pc}
+; CHECK-NEXT: .LBB31_4:
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: pop {r5, pc}
entry:
%cmp9.not = icmp eq i32 %n, 0
br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
diff --git a/llvm/test/CodeGen/VE/Scalar/atomic.ll b/llvm/test/CodeGen/VE/Scalar/atomic.ll
index af849596cbad6..6f5e826889d56 100644
--- a/llvm/test/CodeGen/VE/Scalar/atomic.ll
+++ b/llvm/test/CodeGen/VE/Scalar/atomic.ll
@@ -121,16 +121,16 @@ define signext i8 @test_atomic_fetch_xor_1() {
; CHECK-NEXT: fencem 3
; CHECK-NEXT: lea %s0, c at lo
; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s1, c at hi(, %s0)
-; CHECK-NEXT: ldl.zx %s0, (, %s1)
+; CHECK-NEXT: lea.sl %s0, c at hi(, %s0)
+; CHECK-NEXT: ldl.zx %s1, (, %s0)
; CHECK-NEXT: .LBB4_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: or %s2, 0, %s0
-; CHECK-NEXT: xor %s0, 1, %s2
-; CHECK-NEXT: cas.w %s0, (%s1), %s2
-; CHECK-NEXT: brne.w %s0, %s2, .LBB4_1
+; CHECK-NEXT: or %s2, 0, %s1
+; CHECK-NEXT: xor %s1, 1, %s2
+; CHECK-NEXT: cas.w %s1, (%s0), %s2
+; CHECK-NEXT: brne.w %s1, %s2, .LBB4_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
-; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sll %s0, %s1, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: fencem 3
; CHECK-NEXT: b.l.t (, %s10)
@@ -147,22 +147,22 @@ define signext i16 @test_atomic_fetch_nand_2() {
; CHECK-NEXT: lea %s0, s at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, s at hi(, %s0)
-; CHECK-NEXT: ldl.zx %s2, (, %s0)
+; CHECK-NEXT: ldl.zx %s3, (, %s0)
; CHECK-NEXT: lea %s1, 65534
-; CHECK-NEXT: lea %s3, -65536
-; CHECK-NEXT: and %s3, %s3, (32)0
+; CHECK-NEXT: lea %s2, -65536
+; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: .LBB5_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: or %s4, 0, %s2
-; CHECK-NEXT: xor %s2, -1, %s4
-; CHECK-NEXT: or %s2, %s2, %s1
-; CHECK-NEXT: and %s2, %s2, (48)0
-; CHECK-NEXT: and %s5, %s4, %s3
-; CHECK-NEXT: or %s2, %s5, %s2
-; CHECK-NEXT: cas.w %s2, (%s0), %s4
-; CHECK-NEXT: brne.w %s2, %s4, .LBB5_1
+; CHECK-NEXT: or %s4, 0, %s3
+; CHECK-NEXT: xor %s3, -1, %s4
+; CHECK-NEXT: or %s3, %s3, %s1
+; CHECK-NEXT: and %s3, %s3, (48)0
+; CHECK-NEXT: and %s5, %s4, %s2
+; CHECK-NEXT: or %s3, %s5, %s3
+; CHECK-NEXT: cas.w %s3, (%s0), %s4
+; CHECK-NEXT: brne.w %s3, %s4, .LBB5_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
-; CHECK-NEXT: sll %s0, %s2, 48
+; CHECK-NEXT: sll %s0, %s3, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: fencem 3
; CHECK-NEXT: b.l.t (, %s10)
@@ -178,16 +178,16 @@ define signext i32 @test_atomic_fetch_max_4() {
; CHECK-NEXT: fencem 3
; CHECK-NEXT: lea %s0, i at lo
; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s1, i at hi(, %s0)
-; CHECK-NEXT: ldl.zx %s0, (, %s1)
+; CHECK-NEXT: lea.sl %s0, i at hi(, %s0)
+; CHECK-NEXT: ldl.zx %s1, (, %s0)
; CHECK-NEXT: .LBB6_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: or %s2, 0, %s0
-; CHECK-NEXT: maxs.w.sx %s0, 1, %s0
-; CHECK-NEXT: cas.w %s0, (%s1), %s2
-; CHECK-NEXT: brne.w %s0, %s2, .LBB6_1
+; CHECK-NEXT: or %s2, 0, %s1
+; CHECK-NEXT: maxs.w.sx %s1, 1, %s1
+; CHECK-NEXT: cas.w %s1, (%s0), %s2
+; CHECK-NEXT: brne.w %s1, %s2, .LBB6_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: fencem 3
; CHECK-NEXT: b.l.t (, %s10)
entry:
@@ -202,16 +202,16 @@ define signext i32 @test_atomic_fetch_min_4() {
; CHECK-NEXT: fencem 3
; CHECK-NEXT: lea %s0, i at lo
; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s1, i at hi(, %s0)
-; CHECK-NEXT: ldl.zx %s0, (, %s1)
+; CHECK-NEXT: lea.sl %s0, i at hi(, %s0)
+; CHECK-NEXT: ldl.zx %s1, (, %s0)
; CHECK-NEXT: .LBB7_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: or %s2, 0, %s0
-; CHECK-NEXT: mins.w.sx %s0, 1, %s0
-; CHECK-NEXT: cas.w %s0, (%s1), %s2
-; CHECK-NEXT: brne.w %s0, %s2, .LBB7_1
+; CHECK-NEXT: or %s2, 0, %s1
+; CHECK-NEXT: mins.w.sx %s1, 1, %s1
+; CHECK-NEXT: cas.w %s1, (%s0), %s2
+; CHECK-NEXT: brne.w %s1, %s2, .LBB7_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: fencem 3
; CHECK-NEXT: b.l.t (, %s10)
entry:
diff --git a/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll b/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
index 65c291ab5a748..5901b9b8300fa 100644
--- a/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
+++ b/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
@@ -13,15 +13,15 @@ define fastcc void @mp_sqrt(i32 %n, i32 %radix, ptr %in, ptr %out, ptr %tmp1, pt
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: movb $1, %al
+; CHECK-NEXT: movb $1, %cl
; CHECK-NEXT: movl $1, %esi
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %bb.i5
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: addl %esi, %esi
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: testb $1, %cl
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %mp_unexp_mp2d.exit.i
; CHECK-NEXT: je .LBB0_3
@@ -29,7 +29,7 @@ define fastcc void @mp_sqrt(i32 %n, i32 %radix, ptr %in, ptr %out, ptr %tmp1, pt
; CHECK-NEXT: jne .LBB0_3
; CHECK-NEXT: # %bb.6: # %cond_next36.i
; CHECK-NEXT: movl $0, 0
-; CHECK-NEXT: movzbl %cl, %ebp
+; CHECK-NEXT: movzbl %al, %ebp
; CHECK-NEXT: andl $1, %ebp
; CHECK-NEXT: xorpd %xmm0, %xmm0
; CHECK-NEXT: xorl %eax, %eax
diff --git a/llvm/test/CodeGen/X86/apx/push2-pop2.ll b/llvm/test/CodeGen/X86/apx/push2-pop2.ll
index 45438a4f84c04..9525d1b83cfae 100644
--- a/llvm/test/CodeGen/X86/apx/push2-pop2.ll
+++ b/llvm/test/CodeGen/X86/apx/push2-pop2.ll
@@ -267,107 +267,109 @@ declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias
define void @lea_in_epilog(i1 %arg, ptr %arg1, ptr %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i64 %arg8, i64 %arg9, i64 %arg10) nounwind {
; CHECK-LABEL: lea_in_epilog:
; CHECK: # %bb.0: # %bb
-; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: je .LBB6_5
-; CHECK-NEXT: # %bb.1: # %bb13
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: push2 %r14, %r15
; CHECK-NEXT: push2 %r12, %r13
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $24, %rsp
+; CHECK-NEXT: movl %edi, %r14d
+; CHECK-NEXT: testb $1, %r14b
+; CHECK-NEXT: je .LBB6_5
+; CHECK-NEXT: # %bb.1: # %bb13
; CHECK-NEXT: movq %r9, %r13
; CHECK-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: addq {{[0-9]+}}(%rsp), %r13
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r14
-; CHECK-NEXT: addq %r13, %r14
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r15
-; CHECK-NEXT: addq %r13, %r15
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rbx
; CHECK-NEXT: addq %r13, %rbx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r15
+; CHECK-NEXT: addq %r13, %r15
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; CHECK-NEXT: addq %r13, %rdx
; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: xorl %r12d, %r12d
-; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB6_2: # %bb15
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: incq %r12
; CHECK-NEXT: movl $432, %edx # imm = 0x1B0
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: movq %r15, %rsi
; CHECK-NEXT: callq memcpy at PLT
-; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edi # 4-byte Reload
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
-; CHECK-NEXT: addq %rax, %r14
-; CHECK-NEXT: addq %rax, %r15
; CHECK-NEXT: addq %rax, %rbx
+; CHECK-NEXT: addq %rax, %r15
+; CHECK-NEXT: addq %rax, %rdx
; CHECK-NEXT: addq %rax, %r13
; CHECK-NEXT: addq $8, %rbp
-; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: testb $1, %r14b
; CHECK-NEXT: je .LBB6_2
; CHECK-NEXT: # %bb.3: # %bb11
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsp
-; CHECK-NEXT: popq %rbx
-; CHECK-NEXT: pop2 %r13, %r12
-; CHECK-NEXT: pop2 %r15, %r14
-; CHECK-NEXT: popq %rbp
; CHECK-NEXT: jne .LBB6_5
; CHECK-NEXT: # %bb.4: # %bb12
; CHECK-NEXT: movq $0, (%rax)
; CHECK-NEXT: .LBB6_5: # %bb14
+; CHECK-NEXT: addq $24, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: pop2 %r13, %r12
+; CHECK-NEXT: pop2 %r15, %r14
+; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq
;
-; PPX-NO-NF-LABEL: lea_in_epilog:
-; PPX-NO-NF: # %bb.0: # %bb
-; PPX-NO-NF-NEXT: testb $1, %dil
-; PPX-NO-NF-NEXT: je .LBB6_5
-; PPX-NO-NF-NEXT: # %bb.1: # %bb13
-; PPX-NO-NF-NEXT: pushp %rbp
-; PPX-NO-NF-NEXT: push2p %r14, %r15
-; PPX-NO-NF-NEXT: push2p %r12, %r13
-; PPX-NO-NF-NEXT: pushp %rbx
-; PPX-NO-NF-NEXT: subq $24, %rsp
-; PPX-NO-NF-NEXT: movq %r9, %r13
-; PPX-NO-NF-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; PPX-NO-NF-NEXT: addq {{[0-9]+}}(%rsp), %r13
-; PPX-NO-NF-NEXT: movq {{[0-9]+}}(%rsp), %r14
-; PPX-NO-NF-NEXT: addq %r13, %r14
-; PPX-NO-NF-NEXT: movq {{[0-9]+}}(%rsp), %r15
-; PPX-NO-NF-NEXT: addq %r13, %r15
-; PPX-NO-NF-NEXT: movq {{[0-9]+}}(%rsp), %rbx
-; PPX-NO-NF-NEXT: addq %r13, %rbx
-; PPX-NO-NF-NEXT: xorl %ebp, %ebp
-; PPX-NO-NF-NEXT: xorl %r12d, %r12d
-; PPX-NO-NF-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
-; PPX-NO-NF-NEXT: .p2align 4
-; PPX-NO-NF-NEXT: .LBB6_2: # %bb15
-; PPX-NO-NF-NEXT: # =>This Inner Loop Header: Depth=1
-; PPX-NO-NF-NEXT: incq %r12
-; PPX-NO-NF-NEXT: movl $432, %edx # imm = 0x1B0
-; PPX-NO-NF-NEXT: xorl %edi, %edi
-; PPX-NO-NF-NEXT: movq %r15, %rsi
-; PPX-NO-NF-NEXT: callq memcpy at PLT
-; PPX-NO-NF-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edi # 4-byte Reload
-; PPX-NO-NF-NEXT: movq {{[0-9]+}}(%rsp), %rax
-; PPX-NO-NF-NEXT: addq %rax, %r14
-; PPX-NO-NF-NEXT: addq %rax, %r15
-; PPX-NO-NF-NEXT: addq %rax, %rbx
-; PPX-NO-NF-NEXT: addq %rax, %r13
-; PPX-NO-NF-NEXT: addq $8, %rbp
-; PPX-NO-NF-NEXT: testb $1, %dil
-; PPX-NO-NF-NEXT: je .LBB6_2
-; PPX-NO-NF-NEXT: # %bb.3: # %bb11
-; PPX-NO-NF-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; PPX-NO-NF-NEXT: leaq {{[0-9]+}}(%rsp), %rsp
-; PPX-NO-NF-NEXT: popp %rbx
-; PPX-NO-NF-NEXT: pop2p %r13, %r12
-; PPX-NO-NF-NEXT: pop2p %r15, %r14
-; PPX-NO-NF-NEXT: popp %rbp
-; PPX-NO-NF-NEXT: jne .LBB6_5
-; PPX-NO-NF-NEXT: # %bb.4: # %bb12
-; PPX-NO-NF-NEXT: movq $0, (%rax)
-; PPX-NO-NF-NEXT: .LBB6_5: # %bb14
-; PPX-NO-NF-NEXT: retq
+; PPX-LABEL: lea_in_epilog:
+; PPX: # %bb.0: # %bb
+; PPX-NEXT: pushp %rbp
+; PPX-NEXT: push2p %r14, %r15
+; PPX-NEXT: push2p %r12, %r13
+; PPX-NEXT: pushp %rbx
+; PPX-NEXT: subq $24, %rsp
+; PPX-NEXT: movl %edi, %r14d
+; PPX-NEXT: testb $1, %r14b
+; PPX-NEXT: je .LBB6_5
+; PPX-NEXT: # %bb.1: # %bb13
+; PPX-NEXT: movq %r9, %r13
+; PPX-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; PPX-NEXT: addq {{[0-9]+}}(%rsp), %r13
+; PPX-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; PPX-NEXT: addq %r13, %rbx
+; PPX-NEXT: movq {{[0-9]+}}(%rsp), %r15
+; PPX-NEXT: addq %r13, %r15
+; PPX-NEXT: movq {{[0-9]+}}(%rsp), %rdx
+; PPX-NEXT: addq %r13, %rdx
+; PPX-NEXT: xorl %ebp, %ebp
+; PPX-NEXT: xorl %r12d, %r12d
+; PPX-NEXT: .p2align 4
+; PPX-NEXT: .LBB6_2: # %bb15
+; PPX-NEXT: # =>This Inner Loop Header: Depth=1
+; PPX-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; PPX-NEXT: incq %r12
+; PPX-NEXT: movl $432, %edx # imm = 0x1B0
+; PPX-NEXT: xorl %edi, %edi
+; PPX-NEXT: movq %r15, %rsi
+; PPX-NEXT: callq memcpy at PLT
+; PPX-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
+; PPX-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; PPX-NEXT: addq %rax, %rbx
+; PPX-NEXT: addq %rax, %r15
+; PPX-NEXT: addq %rax, %rdx
+; PPX-NEXT: addq %rax, %r13
+; PPX-NEXT: addq $8, %rbp
+; PPX-NEXT: testb $1, %r14b
+; PPX-NEXT: je .LBB6_2
+; PPX-NEXT: # %bb.3: # %bb11
+; PPX-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; PPX-NEXT: jne .LBB6_5
+; PPX-NEXT: # %bb.4: # %bb12
+; PPX-NEXT: movq $0, (%rax)
+; PPX-NEXT: .LBB6_5: # %bb14
+; PPX-NEXT: addq $24, %rsp
+; PPX-NEXT: popp %rbx
+; PPX-NEXT: pop2p %r13, %r12
+; PPX-NEXT: pop2p %r15, %r14
+; PPX-NEXT: popp %rbp
+; PPX-NEXT: retq
;
; FRAME-LABEL: lea_in_epilog:
; FRAME: # %bb.0: # %bb
@@ -423,58 +425,6 @@ define void @lea_in_epilog(i1 %arg, ptr %arg1, ptr %arg2, i64 %arg3, i64 %arg4,
; FRAME-NEXT: movq $0, (%rax)
; FRAME-NEXT: .LBB6_5: # %bb14
; FRAME-NEXT: retq
-;
-; PPX-NF-LABEL: lea_in_epilog:
-; PPX-NF: # %bb.0: # %bb
-; PPX-NF-NEXT: testb $1, %dil
-; PPX-NF-NEXT: je .LBB6_5
-; PPX-NF-NEXT: # %bb.1: # %bb13
-; PPX-NF-NEXT: pushp %rbp
-; PPX-NF-NEXT: push2p %r14, %r15
-; PPX-NF-NEXT: push2p %r12, %r13
-; PPX-NF-NEXT: pushp %rbx
-; PPX-NF-NEXT: subq $24, %rsp
-; PPX-NF-NEXT: movq %r9, %r13
-; PPX-NF-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; PPX-NF-NEXT: addq {{[0-9]+}}(%rsp), %r13
-; PPX-NF-NEXT: movq {{[0-9]+}}(%rsp), %r14
-; PPX-NF-NEXT: addq %r13, %r14
-; PPX-NF-NEXT: movq {{[0-9]+}}(%rsp), %r15
-; PPX-NF-NEXT: addq %r13, %r15
-; PPX-NF-NEXT: movq {{[0-9]+}}(%rsp), %rbx
-; PPX-NF-NEXT: addq %r13, %rbx
-; PPX-NF-NEXT: xorl %ebp, %ebp
-; PPX-NF-NEXT: xorl %r12d, %r12d
-; PPX-NF-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
-; PPX-NF-NEXT: .p2align 4
-; PPX-NF-NEXT: .LBB6_2: # %bb15
-; PPX-NF-NEXT: # =>This Inner Loop Header: Depth=1
-; PPX-NF-NEXT: incq %r12
-; PPX-NF-NEXT: movl $432, %edx # imm = 0x1B0
-; PPX-NF-NEXT: xorl %edi, %edi
-; PPX-NF-NEXT: movq %r15, %rsi
-; PPX-NF-NEXT: callq memcpy at PLT
-; PPX-NF-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edi # 4-byte Reload
-; PPX-NF-NEXT: movq {{[0-9]+}}(%rsp), %rax
-; PPX-NF-NEXT: addq %rax, %r14
-; PPX-NF-NEXT: addq %rax, %r15
-; PPX-NF-NEXT: addq %rax, %rbx
-; PPX-NF-NEXT: addq %rax, %r13
-; PPX-NF-NEXT: addq $8, %rbp
-; PPX-NF-NEXT: testb $1, %dil
-; PPX-NF-NEXT: je .LBB6_2
-; PPX-NF-NEXT: # %bb.3: # %bb11
-; PPX-NF-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; PPX-NF-NEXT: {nf} addq $24, %rsp
-; PPX-NF-NEXT: popp %rbx
-; PPX-NF-NEXT: pop2p %r13, %r12
-; PPX-NF-NEXT: pop2p %r15, %r14
-; PPX-NF-NEXT: popp %rbp
-; PPX-NF-NEXT: jne .LBB6_5
-; PPX-NF-NEXT: # %bb.4: # %bb12
-; PPX-NF-NEXT: movq $0, (%rax)
-; PPX-NF-NEXT: .LBB6_5: # %bb14
-; PPX-NF-NEXT: retq
bb:
br i1 %arg, label %bb13, label %bb14
@@ -508,3 +458,6 @@ bb15:
call void @llvm.memcpy.p0.p0.i64(ptr null, ptr %getelementptr21, i64 0, i1 false)
br i1 %arg, label %bb11, label %bb15
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; PPX-NF: {{.*}}
+; PPX-NO-NF: {{.*}}
diff --git a/llvm/test/CodeGen/X86/atom-fixup-lea2.ll b/llvm/test/CodeGen/X86/atom-fixup-lea2.ll
index 20519a9974542..adea9e1386a90 100644
--- a/llvm/test/CodeGen/X86/atom-fixup-lea2.ll
+++ b/llvm/test/CodeGen/X86/atom-fixup-lea2.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
; CHECK:%bb.5
-; CHECK-NEXT:addl
+; CHECK-NEXT:leal
; CHECK-NEXT:leal
; CHECK-NEXT:leal
; CHECK-NEXT:movl
diff --git a/llvm/test/CodeGen/X86/block-placement.ll b/llvm/test/CodeGen/X86/block-placement.ll
index df682a5eb6f56..856e4987e8e69 100644
--- a/llvm/test/CodeGen/X86/block-placement.ll
+++ b/llvm/test/CodeGen/X86/block-placement.ll
@@ -608,8 +608,8 @@ define void @test_unnatural_cfg_backwards_inner_loop(i1 %arg) {
;
; CHECK-LABEL: test_unnatural_cfg_backwards_inner_loop
; CHECK: %entry
-; CHECK: %loop2b
; CHECK: %loop3
+; CHECK: %loop2b
entry:
br i1 %arg, label %loop2a, label %body
diff --git a/llvm/test/CodeGen/X86/branchfolding-debugloc.ll b/llvm/test/CodeGen/X86/branchfolding-debugloc.ll
index cfcc2af16e3fc..35e7b3533dcae 100644
--- a/llvm/test/CodeGen/X86/branchfolding-debugloc.ll
+++ b/llvm/test/CodeGen/X86/branchfolding-debugloc.ll
@@ -22,7 +22,7 @@
; CHECK: .loc 1 6 3
; CHECK-NEXT: je [[BB:.LBB[^ ]+]]
; CHECK: [[BB]]:
-; CHECK: xorl %ebp, %ebp
+; CHECK: xorl %ebx, %ebx
; CHECK-NEXT: .LBB{{.*}} # %for.end
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/CodeGen/X86/bsf.ll b/llvm/test/CodeGen/X86/bsf.ll
index f780f0172647f..b1a29c13a3d7a 100644
--- a/llvm/test/CodeGen/X86/bsf.ll
+++ b/llvm/test/CodeGen/X86/bsf.ll
@@ -266,65 +266,65 @@ define i128 @cmov_bsf128(i128 %x, i128 %y) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $16, %esp
-; X86-NEXT: movl 32(%ebp), %ecx
-; X86-NEXT: movl 24(%ebp), %edx
+; X86-NEXT: movl 32(%ebp), %edx
+; X86-NEXT: movl 24(%ebp), %esi
; X86-NEXT: movl 28(%ebp), %edi
; X86-NEXT: movl %edi, %eax
; X86-NEXT: orl 36(%ebp), %eax
-; X86-NEXT: movl %edx, %esi
-; X86-NEXT: orl %ecx, %esi
-; X86-NEXT: orl %eax, %esi
+; X86-NEXT: movl %esi, %ecx
+; X86-NEXT: orl %edx, %ecx
+; X86-NEXT: orl %eax, %ecx
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: je .LBB8_1
; X86-NEXT: # %bb.2: # %cond.false
-; X86-NEXT: testl %edx, %edx
+; X86-NEXT: testl %esi, %esi
; X86-NEXT: jne .LBB8_3
; X86-NEXT: # %bb.4: # %cond.false
; X86-NEXT: rep bsfl %edi, %ebx
; X86-NEXT: addl $32, %ebx
-; X86-NEXT: testl %ecx, %ecx
+; X86-NEXT: testl %edx, %edx
; X86-NEXT: je .LBB8_7
; X86-NEXT: .LBB8_6:
-; X86-NEXT: rep bsfl %ecx, %esi
+; X86-NEXT: rep bsfl %edx, %ecx
; X86-NEXT: jmp .LBB8_8
; X86-NEXT: .LBB8_1:
; X86-NEXT: movl $128, %ebx
; X86-NEXT: jmp .LBB8_11
; X86-NEXT: .LBB8_3:
-; X86-NEXT: rep bsfl %edx, %ebx
-; X86-NEXT: testl %ecx, %ecx
+; X86-NEXT: rep bsfl %esi, %ebx
+; X86-NEXT: testl %edx, %edx
; X86-NEXT: jne .LBB8_6
; X86-NEXT: .LBB8_7: # %cond.false
-; X86-NEXT: rep bsfl 36(%ebp), %esi
-; X86-NEXT: addl $32, %esi
+; X86-NEXT: rep bsfl 36(%ebp), %ecx
+; X86-NEXT: addl $32, %ecx
; X86-NEXT: .LBB8_8: # %cond.false
-; X86-NEXT: movl %edx, %ecx
-; X86-NEXT: orl %edi, %ecx
+; X86-NEXT: movl %esi, %edx
+; X86-NEXT: orl %edi, %edx
; X86-NEXT: jne .LBB8_10
; X86-NEXT: # %bb.9: # %cond.false
-; X86-NEXT: addl $64, %esi
-; X86-NEXT: movl %esi, %ebx
+; X86-NEXT: addl $64, %ecx
+; X86-NEXT: movl %ecx, %ebx
; X86-NEXT: .LBB8_10: # %cond.false
-; X86-NEXT: movl 32(%ebp), %ecx
+; X86-NEXT: movl 32(%ebp), %edx
; X86-NEXT: .LBB8_11: # %cond.end
-; X86-NEXT: orl %ecx, %edx
+; X86-NEXT: orl %edx, %esi
; X86-NEXT: orl 36(%ebp), %edi
-; X86-NEXT: orl %edx, %edi
+; X86-NEXT: orl %esi, %edi
; X86-NEXT: je .LBB8_12
; X86-NEXT: # %bb.13: # %cond.end
-; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: xorl %esi, %esi
+; X86-NEXT: xorl %edi, %edi
; X86-NEXT: jmp .LBB8_14
; X86-NEXT: .LBB8_12:
-; X86-NEXT: movl 52(%ebp), %esi
-; X86-NEXT: movl 48(%ebp), %edx
-; X86-NEXT: movl 44(%ebp), %ecx
+; X86-NEXT: movl 52(%ebp), %edi
+; X86-NEXT: movl 48(%ebp), %esi
+; X86-NEXT: movl 44(%ebp), %edx
; X86-NEXT: movl 40(%ebp), %ebx
; X86-NEXT: .LBB8_14: # %cond.end
-; X86-NEXT: movl %esi, 12(%eax)
-; X86-NEXT: movl %edx, 8(%eax)
-; X86-NEXT: movl %ecx, 4(%eax)
+; X86-NEXT: movl %edi, 12(%eax)
+; X86-NEXT: movl %esi, 8(%eax)
+; X86-NEXT: movl %edx, 4(%eax)
; X86-NEXT: movl %ebx, (%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
@@ -367,27 +367,27 @@ define i128 @cmov_bsf128_undef(i128 %x, i128 %y) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $16, %esp
-; X86-NEXT: movl 36(%ebp), %esi
-; X86-NEXT: movl 32(%ebp), %edi
+; X86-NEXT: movl 36(%ebp), %edi
+; X86-NEXT: movl 32(%ebp), %ebx
; X86-NEXT: movl 28(%ebp), %ecx
; X86-NEXT: movl 24(%ebp), %edx
; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %edx, %ebx
-; X86-NEXT: orl %edi, %ebx
-; X86-NEXT: orl %eax, %ebx
+; X86-NEXT: orl %edi, %eax
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: orl %ebx, %esi
+; X86-NEXT: orl %eax, %esi
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: je .LBB9_11
; X86-NEXT: # %bb.1: # %select.true.sink
; X86-NEXT: testl %edx, %edx
; X86-NEXT: jne .LBB9_2
; X86-NEXT: # %bb.3: # %select.true.sink
-; X86-NEXT: rep bsfl %ecx, %ebx
-; X86-NEXT: addl $32, %ebx
-; X86-NEXT: testl %edi, %edi
+; X86-NEXT: rep bsfl %ecx, %esi
+; X86-NEXT: addl $32, %esi
+; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: je .LBB9_6
; X86-NEXT: .LBB9_5:
-; X86-NEXT: rep bsfl %edi, %esi
+; X86-NEXT: rep bsfl %ebx, %edi
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: je .LBB9_8
; X86-NEXT: jmp .LBB9_9
@@ -402,19 +402,19 @@ define i128 @cmov_bsf128_undef(i128 %x, i128 %y) nounwind {
; X86-NEXT: movl %ecx, 12(%eax)
; X86-NEXT: jmp .LBB9_10
; X86-NEXT: .LBB9_2:
-; X86-NEXT: rep bsfl %edx, %ebx
-; X86-NEXT: testl %edi, %edi
+; X86-NEXT: rep bsfl %edx, %esi
+; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: jne .LBB9_5
; X86-NEXT: .LBB9_6: # %select.true.sink
-; X86-NEXT: rep bsfl %esi, %esi
-; X86-NEXT: addl $32, %esi
+; X86-NEXT: rep bsfl %edi, %edi
+; X86-NEXT: addl $32, %edi
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: jne .LBB9_9
; X86-NEXT: .LBB9_8: # %select.true.sink
-; X86-NEXT: addl $64, %esi
-; X86-NEXT: movl %esi, %ebx
+; X86-NEXT: addl $64, %edi
+; X86-NEXT: movl %edi, %esi
; X86-NEXT: .LBB9_9: # %select.true.sink
-; X86-NEXT: movl %ebx, (%eax)
+; X86-NEXT: movl %esi, (%eax)
; X86-NEXT: movl $0, 12(%eax)
; X86-NEXT: movl $0, 8(%eax)
; X86-NEXT: movl $0, 4(%eax)
diff --git a/llvm/test/CodeGen/X86/bsr.ll b/llvm/test/CodeGen/X86/bsr.ll
index affacc5ee6487..e2e38e39bef45 100644
--- a/llvm/test/CodeGen/X86/bsr.ll
+++ b/llvm/test/CodeGen/X86/bsr.ll
@@ -295,14 +295,14 @@ define i128 @cmov_bsr128(i128 %x, i128 %y) nounwind {
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $16, %esp
; X86-NEXT: movl 32(%ebp), %ebx
-; X86-NEXT: movl 24(%ebp), %ecx
+; X86-NEXT: movl 24(%ebp), %edx
; X86-NEXT: movl 36(%ebp), %esi
; X86-NEXT: movl 28(%ebp), %edi
; X86-NEXT: movl %edi, %eax
; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %ecx, %edx
-; X86-NEXT: orl %ebx, %edx
-; X86-NEXT: orl %eax, %edx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: orl %ebx, %ecx
+; X86-NEXT: orl %eax, %ecx
; X86-NEXT: je .LBB8_1
; X86-NEXT: # %bb.2: # %cond.false
; X86-NEXT: testl %esi, %esi
@@ -315,8 +315,8 @@ define i128 @cmov_bsr128(i128 %x, i128 %y) nounwind {
; X86-NEXT: testl %edi, %edi
; X86-NEXT: je .LBB8_7
; X86-NEXT: .LBB8_6:
-; X86-NEXT: bsrl %edi, %edx
-; X86-NEXT: xorl $31, %edx
+; X86-NEXT: bsrl %edi, %ecx
+; X86-NEXT: xorl $31, %ecx
; X86-NEXT: orl %eax, %ebx
; X86-NEXT: je .LBB8_9
; X86-NEXT: jmp .LBB8_10
@@ -331,37 +331,37 @@ define i128 @cmov_bsr128(i128 %x, i128 %y) nounwind {
; X86-NEXT: testl %edi, %edi
; X86-NEXT: jne .LBB8_6
; X86-NEXT: .LBB8_7: # %cond.false
-; X86-NEXT: bsrl %ecx, %edx
-; X86-NEXT: xorl $31, %edx
-; X86-NEXT: orl $32, %edx
+; X86-NEXT: bsrl %edx, %ecx
+; X86-NEXT: xorl $31, %ecx
+; X86-NEXT: orl $32, %ecx
; X86-NEXT: orl %eax, %ebx
; X86-NEXT: jne .LBB8_10
; X86-NEXT: .LBB8_9: # %cond.false
-; X86-NEXT: orl $64, %edx
-; X86-NEXT: movl %edx, %esi
+; X86-NEXT: orl $64, %ecx
+; X86-NEXT: movl %ecx, %esi
; X86-NEXT: .LBB8_10: # %cond.false
; X86-NEXT: movl 32(%ebp), %ebx
; X86-NEXT: .LBB8_11: # %cond.end
-; X86-NEXT: orl %ebx, %ecx
+; X86-NEXT: orl %ebx, %edx
; X86-NEXT: orl %eax, %edi
-; X86-NEXT: orl %ecx, %edi
+; X86-NEXT: orl %edx, %edi
; X86-NEXT: je .LBB8_12
; X86-NEXT: # %bb.13: # %cond.end
; X86-NEXT: xorl $127, %esi
-; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: xorl %edi, %edi
; X86-NEXT: jmp .LBB8_14
; X86-NEXT: .LBB8_12:
; X86-NEXT: movl 52(%ebp), %edi
-; X86-NEXT: movl 48(%ebp), %edx
-; X86-NEXT: movl 44(%ebp), %ecx
+; X86-NEXT: movl 48(%ebp), %ecx
+; X86-NEXT: movl 44(%ebp), %edx
; X86-NEXT: movl 40(%ebp), %esi
; X86-NEXT: .LBB8_14: # %cond.end
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl %edi, 12(%eax)
-; X86-NEXT: movl %edx, 8(%eax)
-; X86-NEXT: movl %ecx, 4(%eax)
+; X86-NEXT: movl %ecx, 8(%eax)
+; X86-NEXT: movl %edx, 4(%eax)
; X86-NEXT: movl %esi, (%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
diff --git a/llvm/test/CodeGen/X86/call-rv-marker.ll b/llvm/test/CodeGen/X86/call-rv-marker.ll
index 6ce7430b52c71..8d363bc451c63 100644
--- a/llvm/test/CodeGen/X86/call-rv-marker.ll
+++ b/llvm/test/CodeGen/X86/call-rv-marker.ll
@@ -117,14 +117,11 @@ lpad: ; preds = %entry
define void @rv_marker_4() personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: rv_marker_4
-; CHECK: pushq %r14
+; CHECK: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: pushq %rbx
-; CHECK-NEXT: .cfi_def_cfa_offset 24
-; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: .cfi_offset %rbx, -24
-; CHECK-NEXT: .cfi_offset %r14, -16
+; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: Ltmp3:
; CHECK-NEXT: callq _foo1
; CHECK-NEXT: movq %rax, %rdi
diff --git a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
index f90e05203fce5..3d389523dffb3 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
@@ -17,7 +17,7 @@ define dso_local void @n(ptr %o, i32 %p, i32 %u) nounwind {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movl %edx, %ebp
-; CHECK-NEXT: movl %esi, %r15d
+; CHECK-NEXT: movl %esi, %r12d
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: callq c
; CHECK-NEXT: movl %eax, %r14d
@@ -26,13 +26,12 @@ define dso_local void @n(ptr %o, i32 %p, i32 %u) nounwind {
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jne .LBB0_9
; CHECK-NEXT: # %bb.1: # %if.end
-; CHECK-NEXT: movl %r15d, %eax
; CHECK-NEXT: cmpl $0, e(%rip)
; CHECK-NEXT: # implicit-def: $r15d
; CHECK-NEXT: # implicit-def: $r13d
; CHECK-NEXT: je .LBB0_4
; CHECK-NEXT: # %bb.2: # %if.then4
-; CHECK-NEXT: movslq %eax, %rdi
+; CHECK-NEXT: movslq %r12d, %rdi
; CHECK-NEXT: callq m
; CHECK-NEXT: # implicit-def: $r15d
; CHECK-NEXT: # implicit-def: $r12d
diff --git a/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir b/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir
index e53747d7b8bed..d1a7887fd732c 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir
+++ b/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir
@@ -36,12 +36,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY killed [[COPY]].sub_8bit
; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32r0_]], %subreg.sub_32bit
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY killed [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.loop (inlineasm-br-indirect-target):
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY killed [[COPY2]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY2]]
; CHECK-NEXT: TEST8ri [[COPY1]], 1, implicit-def $eflags
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = IMPLICIT_DEF
; CHECK-NEXT: JCC_1 %bb.1, 4, implicit killed $eflags
diff --git a/llvm/test/CodeGen/X86/callbr-asm-kill.mir b/llvm/test/CodeGen/X86/callbr-asm-kill.mir
index ce895a38f5831..11aec09468a1b 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-kill.mir
+++ b/llvm/test/CodeGen/X86/callbr-asm-kill.mir
@@ -57,19 +57,19 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY killed $rsi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY killed $rdi
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY killed [[COPY1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY1]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.loop (ir-block-address-taken %ir-block.loop, inlineasm-br-indirect-target):
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY killed [[COPY2]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY2]]
; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.mem)
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-NEXT: $rdi = COPY killed [[COPY3]]
; CHECK-NEXT: CALL64pcrel32 target-flags(x86-plt) @foo, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[MOV64rm]]
- ; CHECK-NEXT: INLINEASM_BR &"", sideeffect mayload attdialect, mem:m, killed [[MOV64rm]], 1, $noreg, 0, $noreg, imm, blockaddress(@test1, %ir-block.loop)
+ ; CHECK-NEXT: INLINEASM_BR &"", sideeffect mayload attdialect, mem:m, [[MOV64rm]], 1, $noreg, 0, $noreg, imm, blockaddress(@test1, %ir-block.loop)
; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.end:
diff --git a/llvm/test/CodeGen/X86/coalescer-copy-from-erasable-implicit-def.ll b/llvm/test/CodeGen/X86/coalescer-copy-from-erasable-implicit-def.ll
index 7b92777cf54c3..ede878b3c40fa 100644
--- a/llvm/test/CodeGen/X86/coalescer-copy-from-erasable-implicit-def.ll
+++ b/llvm/test/CodeGen/X86/coalescer-copy-from-erasable-implicit-def.ll
@@ -20,10 +20,10 @@ define <16 x i32> @f1() {
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_3: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: # implicit-def: $xmm1
-; CHECK-NEXT: # implicit-def: $xmm1
-; CHECK-NEXT: # implicit-def: $xmm1
-; CHECK-NEXT: xorps %xmm1, %xmm1
-; CHECK-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; CHECK-NEXT: # implicit-def: $xmm2
+; CHECK-NEXT: # implicit-def: $xmm3
+; CHECK-NEXT: xorps %xmm4, %xmm4
+; CHECK-NEXT: movss {{.*#+}} xmm0 = xmm4[0],xmm0[1,2,3]
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_3
diff --git a/llvm/test/CodeGen/X86/codegen-prepare-addrmode-tls.ll b/llvm/test/CodeGen/X86/codegen-prepare-addrmode-tls.ll
index 0ca1da26fa89c..fb2f3a7c5350a 100644
--- a/llvm/test/CodeGen/X86/codegen-prepare-addrmode-tls.ll
+++ b/llvm/test/CodeGen/X86/codegen-prepare-addrmode-tls.ll
@@ -156,19 +156,19 @@ define i32 @func_nonlocal_tls(i32 %arg0, i64 %arg1) nounwind {
; TLSDESC-NEXT: pushq %rbx
; TLSDESC-NEXT: leaq foo_nonlocal at tlsdesc(%rip), %rax
; TLSDESC-NEXT: callq *foo_nonlocal at tlscall(%rax)
+; TLSDESC-NEXT: movq %rax, %rcx
; TLSDESC-NEXT: movl %fs:(%rax), %ebp
; TLSDESC-NEXT: testl %edi, %edi
-; TLSDESC-NEXT: movl %ebp, %ecx
+; TLSDESC-NEXT: movl %ebp, %eax
; TLSDESC-NEXT: jne .LBB1_2
; TLSDESC-NEXT: # %bb.1: # %if.then
; TLSDESC-NEXT: movq %rsi, %rbx
-; TLSDESC-NEXT: addq %fs:0, %rax
-; TLSDESC-NEXT: movq %rax, %r14
+; TLSDESC-NEXT: addq %fs:0, %rcx
+; TLSDESC-NEXT: movq %rcx, %r14
; TLSDESC-NEXT: callq effect at PLT
-; TLSDESC-NEXT: movl 168(%r14,%rbx,4), %ecx
+; TLSDESC-NEXT: movl 168(%r14,%rbx,4), %eax
; TLSDESC-NEXT: .LBB1_2: # %if.end
-; TLSDESC-NEXT: addl %ebp, %ecx
-; TLSDESC-NEXT: movl %ecx, %eax
+; TLSDESC-NEXT: addl %ebp, %eax
; TLSDESC-NEXT: popq %rbx
; TLSDESC-NEXT: popq %r14
; TLSDESC-NEXT: popq %rbp
diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
index 080dc54677e6e..0c899c3ff12b6 100644
--- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
+++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
@@ -175,23 +175,23 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: movl 52(%ebp), %ecx
; X86-NEXT: movl %ecx, %edx
; X86-NEXT: sarl $31, %edx
-; X86-NEXT: movl %ecx, %ebx
-; X86-NEXT: xorl %edx, %ebx
+; X86-NEXT: movl %ecx, %edi
+; X86-NEXT: xorl %edx, %edi
; X86-NEXT: movl 48(%ebp), %esi
; X86-NEXT: xorl %edx, %esi
-; X86-NEXT: movl 44(%ebp), %eax
+; X86-NEXT: movl 44(%ebp), %ebx
+; X86-NEXT: xorl %edx, %ebx
+; X86-NEXT: movl 40(%ebp), %eax
; X86-NEXT: xorl %edx, %eax
-; X86-NEXT: movl 40(%ebp), %edi
-; X86-NEXT: xorl %edx, %edi
-; X86-NEXT: subl %edx, %edi
-; X86-NEXT: sbbl %edx, %eax
+; X86-NEXT: subl %edx, %eax
+; X86-NEXT: sbbl %edx, %ebx
; X86-NEXT: sbbl %edx, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sbbl %edx, %ebx
-; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: orl %ebx, %ecx
-; X86-NEXT: movl %edi, %edx
+; X86-NEXT: sbbl %edx, %edi
+; X86-NEXT: movl %ebx, %ecx
+; X86-NEXT: orl %edi, %ecx
+; X86-NEXT: movl %eax, %edx
; X86-NEXT: orl %esi, %edx
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: sete %dl
@@ -203,61 +203,61 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: sete %cl
; X86-NEXT: orb %dl, %cl
; X86-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
-; X86-NEXT: bsrl %ebx, %esi
+; X86-NEXT: bsrl %edi, %esi
; X86-NEXT: xorl $31, %esi
-; X86-NEXT: bsrl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: bsrl %ecx, %edx
; X86-NEXT: xorl $31, %edx
; X86-NEXT: orl $32, %edx
-; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: testl %edi, %edi
; X86-NEXT: cmovnel %esi, %edx
-; X86-NEXT: bsrl %eax, %esi
+; X86-NEXT: bsrl %ebx, %esi
; X86-NEXT: xorl $31, %esi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: bsrl %edi, %ecx
-; X86-NEXT: xorl $31, %ecx
-; X86-NEXT: orl $32, %ecx
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: testl %eax, %eax
-; X86-NEXT: cmovnel %esi, %ecx
-; X86-NEXT: orl $64, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: bsrl %eax, %eax
+; X86-NEXT: xorl $31, %eax
+; X86-NEXT: orl $32, %eax
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %ebx, %esi
-; X86-NEXT: cmovnel %edx, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: bsrl %eax, %esi
+; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: cmovnel %esi, %eax
+; X86-NEXT: orl $64, %eax
+; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %edi, %esi
+; X86-NEXT: cmovnel %edx, %eax
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; X86-NEXT: bsrl %ebx, %esi
; X86-NEXT: xorl $31, %esi
; X86-NEXT: bsrl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: xorl $31, %edx
; X86-NEXT: orl $32, %edx
-; X86-NEXT: testl %eax, %eax
+; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: cmovnel %esi, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X86-NEXT: bsrl %ebx, %edi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: bsrl %ecx, %edi
; X86-NEXT: xorl $31, %edi
; X86-NEXT: bsrl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload
; X86-NEXT: xorl $31, %esi
; X86-NEXT: orl $32, %esi
-; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: cmovnel %edi, %esi
; X86-NEXT: orl $64, %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: orl %eax, %edi
+; X86-NEXT: orl %ebx, %edi
; X86-NEXT: cmovnel %edx, %esi
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: xorl %ebx, %ebx
+; X86-NEXT: xorl %edi, %edi
; X86-NEXT: subl %esi, %eax
; X86-NEXT: movl $0, %edx
; X86-NEXT: sbbl %edx, %edx
+; X86-NEXT: movl $0, %ebx
+; X86-NEXT: sbbl %ebx, %ebx
; X86-NEXT: movl $0, %esi
; X86-NEXT: sbbl %esi, %esi
-; X86-NEXT: movl $0, %edi
-; X86-NEXT: sbbl %edi, %edi
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jne .LBB4_1
; X86-NEXT: # %bb.2: # %select.false.sink
; X86-NEXT: movl $127, %ecx
@@ -265,34 +265,32 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %edx, %ecx
; X86-NEXT: movl $0, %ecx
-; X86-NEXT: sbbl %esi, %ecx
+; X86-NEXT: sbbl %ebx, %ecx
; X86-NEXT: movl $0, %ecx
-; X86-NEXT: sbbl %edi, %ecx
+; X86-NEXT: sbbl %esi, %ecx
; X86-NEXT: setb %cl
; X86-NEXT: .LBB4_3: # %select.end
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: xorl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: testb %cl, %cl
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: cmovnel %ebx, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %edi
+; X86-NEXT: cmovnel %edi, %eax
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: cmovnel %edi, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: cmovnel %edi, %ebx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: cmovnel %edi, %esi
; X86-NEXT: cmovel {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
-; X86-NEXT: jne .LBB4_4
-; X86-NEXT: # %bb.10: # %select.end
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: xorl $127, %eax
-; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
+; X86-NEXT: jne .LBB4_9
+; X86-NEXT: # %bb.4: # %select.end
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: xorl $127, %esi
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
-; X86-NEXT: orl %eax, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: je .LBB4_11
-; X86-NEXT: # %bb.8: # %udiv-bb1
+; X86-NEXT: orl %esi, %ecx
+; X86-NEXT: je .LBB4_9
+; X86-NEXT: # %bb.5: # %udiv-bb1
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
@@ -300,10 +298,10 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: movl %edi, {{[0-9]+}}(%esp)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: xorb $127, %cl
@@ -312,51 +310,52 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: andb $12, %al
; X86-NEXT: negb %al
; X86-NEXT: movsbl %al, %eax
-; X86-NEXT: movl 152(%esp,%eax), %edx
-; X86-NEXT: movl 156(%esp,%eax), %esi
-; X86-NEXT: shldl %cl, %edx, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 144(%esp,%eax), %esi
-; X86-NEXT: movl 148(%esp,%eax), %eax
-; X86-NEXT: shldl %cl, %eax, %edx
+; X86-NEXT: movl 152(%esp,%eax), %edi
+; X86-NEXT: movl 156(%esp,%eax), %edx
+; X86-NEXT: shldl %cl, %edi, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl %cl, %esi, %eax
+; X86-NEXT: movl 144(%esp,%eax), %edx
+; X86-NEXT: movl 148(%esp,%eax), %eax
+; X86-NEXT: shldl %cl, %eax, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl %cl, %edx, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shll %cl, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shll %cl, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl $1, %ebx
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: jb .LBB4_9
-; X86-NEXT: # %bb.5: # %udiv-preheader
-; X86-NEXT: movl %ebx, %ecx
+; X86-NEXT: jb .LBB4_10
+; X86-NEXT: # %bb.6: # %udiv-preheader
; X86-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %edi, {{[0-9]+}}(%esp)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: movl %ecx, %eax
; X86-NEXT: shrb $3, %al
; X86-NEXT: andb $12, %al
; X86-NEXT: movzbl %al, %eax
; X86-NEXT: movl 108(%esp,%eax), %ebx
-; X86-NEXT: movl 104(%esp,%eax), %edx
-; X86-NEXT: movl %edx, %esi
-; X86-NEXT: shrdl %cl, %ebx, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 96(%esp,%eax), %esi
-; X86-NEXT: movl 100(%esp,%eax), %edi
-; X86-NEXT: movl %edi, %eax
-; X86-NEXT: shrdl %cl, %edx, %eax
+; X86-NEXT: movl 104(%esp,%eax), %edi
+; X86-NEXT: movl %edi, %edx
+; X86-NEXT: shrdl %cl, %ebx, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 96(%esp,%eax), %edx
+; X86-NEXT: movl 100(%esp,%eax), %esi
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: shrdl %cl, %edi, %eax
+; X86-NEXT: movl %eax, %edi
; X86-NEXT: shrl %cl, %ebx
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: # kill: def $cl killed $cl killed $ecx
-; X86-NEXT: shrdl %cl, %edi, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrdl %cl, %esi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: addl $-1, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
@@ -370,129 +369,129 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: adcl $-1, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .p2align 4
-; X86-NEXT: .LBB4_6: # %udiv-do-while
+; X86-NEXT: .LBB4_7: # %udiv-do-while
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edx, %ebx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: shldl $1, %esi, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %eax, %esi
-; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shldl $1, %eax, %esi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X86-NEXT: shldl $1, %ebx, %eax
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: shldl $1, %edi, %esi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: shldl $1, %ecx, %eax
+; X86-NEXT: shldl $1, %edx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %ebx
+; X86-NEXT: shldl $1, %edi, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; X86-NEXT: orl %ebx, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: orl %edx, %ebx
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl $1, %ecx, %edi
-; X86-NEXT: orl %edx, %edi
+; X86-NEXT: shldl $1, %edx, %edi
+; X86-NEXT: orl %ebx, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %ecx
-; X86-NEXT: orl %edx, %ecx
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %edi, %edx
+; X86-NEXT: orl %ebx, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl %edi, %edi
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: cmpl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %esi, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: cmpl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: sbbl %edx, %ecx
-; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %edi
+; X86-NEXT: sbbl %eax, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: sbbl %esi, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: movl %edx, %edi
; X86-NEXT: andl $1, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %ecx, %edi
+; X86-NEXT: movl %edx, %edi
; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %ecx, %ebx
+; X86-NEXT: movl %edx, %ebx
; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
-; X86-NEXT: movl %ecx, %edi
+; X86-NEXT: movl %edx, %edi
; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
-; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
+; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: subl %ecx, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sbbl %edi, %esi
-; X86-NEXT: movl %esi, %eax
-; X86-NEXT: sbbl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: movl %edx, %ebx
-; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
+; X86-NEXT: subl %edx, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: sbbl %edi, %eax
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: sbbl %ebx, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
; X86-NEXT: addl $-1, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: adcl $-1, %esi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: adcl $-1, %edi
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edi, %ecx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %esi, %edx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl $-1, %eax
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %eax, %esi
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: orl %ecx, %edx
+; X86-NEXT: orl %esi, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: jne .LBB4_7
+; X86-NEXT: .LBB4_8: # %udiv-loop-exit
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; X86-NEXT: shldl $1, %ebx, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: shldl $1, %eax, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: jne .LBB4_6
-; X86-NEXT: .LBB4_7: # %udiv-loop-exit
+; X86-NEXT: shldl $1, %ecx, %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shldl $1, %esi, %eax
-; X86-NEXT: shldl $1, %ecx, %esi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edx, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: leal (%edi,%edx,2), %ebx
+; X86-NEXT: leal (%esi,%ecx,2), %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edx, %edi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl %eax, %edi
-; X86-NEXT: .LBB4_11: # %udiv-end
+; X86-NEXT: .LBB4_9: # %udiv-end
; X86-NEXT: xorl %edx, %edi
-; X86-NEXT: xorl %edx, %esi
-; X86-NEXT: xorl %edx, %ecx
; X86-NEXT: xorl %edx, %ebx
-; X86-NEXT: subl %edx, %ebx
-; X86-NEXT: sbbl %edx, %ecx
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sbbl %edx, %esi
+; X86-NEXT: xorl %edx, %eax
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: xorl %edx, %esi
+; X86-NEXT: subl %edx, %esi
+; X86-NEXT: sbbl %edx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sbbl %edx, %ebx
; X86-NEXT: sbbl %edx, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 56(%ebp), %eax
-; X86-NEXT: movl %ebx, (%eax)
-; X86-NEXT: movl %ecx, 4(%eax)
-; X86-NEXT: movl %esi, 8(%eax)
-; X86-NEXT: movl %edi, 12(%eax)
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: movl 40(%ebp), %ecx
-; X86-NEXT: mull %ecx
-; X86-NEXT: movl %edx, %edi
+; X86-NEXT: movl 56(%ebp), %ecx
+; X86-NEXT: movl %esi, (%ecx)
+; X86-NEXT: movl %eax, 4(%ecx)
+; X86-NEXT: movl %ebx, 8(%ecx)
+; X86-NEXT: movl %edi, 12(%ecx)
+; X86-NEXT: movl 40(%ebp), %edi
+; X86-NEXT: mull %edi
+; X86-NEXT: movl %edx, %ecx
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %ebx, %eax
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: mull %ecx
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: mull %edi
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edx, %ecx
-; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
-; X86-NEXT: adcl $0, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %ebx, %eax
-; X86-NEXT: movl %esi, %edi
+; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: adcl $0, %ecx
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: movl %ebx, %edi
; X86-NEXT: movl 44(%ebp), %esi
; X86-NEXT: mull %esi
-; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
+; X86-NEXT: adcl %ecx, %edx
; X86-NEXT: movl %edx, %ecx
; X86-NEXT: setb %bl
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
@@ -546,13 +545,10 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: .LBB4_1:
; X86-NEXT: movb $1, %cl
; X86-NEXT: jmp .LBB4_3
-; X86-NEXT: .LBB4_9:
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: .LBB4_10:
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: jmp .LBB4_7
-; X86-NEXT: .LBB4_4:
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: jmp .LBB4_11
+; X86-NEXT: jmp .LBB4_8
;
; X64-LABEL: scalar_i128:
; X64: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
index b418d95238597..322054382ffcd 100644
--- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
+++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
@@ -183,12 +183,12 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: xorl $31, %ebx
; X86-NEXT: orl $32, %ebx
; X86-NEXT: testl %edi, %edi
+; X86-NEXT: movl 36(%ebp), %edi
; X86-NEXT: cmovnel %edx, %ebx
; X86-NEXT: orl $64, %ebx
; X86-NEXT: movl %eax, %edx
; X86-NEXT: orl %esi, %edx
; X86-NEXT: cmovnel %ecx, %ebx
-; X86-NEXT: movl 36(%ebp), %edi
; X86-NEXT: bsrl %edi, %edx
; X86-NEXT: xorl $31, %edx
; X86-NEXT: bsrl 32(%ebp), %ecx
@@ -221,7 +221,6 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jne .LBB4_1
; X86-NEXT: # %bb.2: # %select.false.sink
; X86-NEXT: movl $127, %eax
@@ -234,37 +233,38 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: sbbl %edi, %eax
; X86-NEXT: setb %al
; X86-NEXT: .LBB4_3: # %select.end
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: testb %al, %al
; X86-NEXT: movl 28(%ebp), %edx
; X86-NEXT: cmovnel %ecx, %edx
; X86-NEXT: movl 24(%ebp), %eax
; X86-NEXT: cmovnel %ecx, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 32(%ebp), %ebx
-; X86-NEXT: cmovnel %ecx, %ebx
-; X86-NEXT: movl 36(%ebp), %esi
-; X86-NEXT: movl %esi, %eax
-; X86-NEXT: cmovnel %ecx, %eax
-; X86-NEXT: movl %eax, %edi
+; X86-NEXT: movl 32(%ebp), %esi
+; X86-NEXT: cmovnel %ecx, %esi
+; X86-NEXT: movl 36(%ebp), %edi
+; X86-NEXT: cmovnel %ecx, %edi
; X86-NEXT: jne .LBB4_9
; X86-NEXT: # %bb.4: # %select.end
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: xorl $127, %eax
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl %ecx, %ebx
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: orl %eax, %ecx
-; X86-NEXT: movl 28(%ebp), %eax
+; X86-NEXT: movl 36(%ebp), %ecx
; X86-NEXT: je .LBB4_9
; X86-NEXT: # %bb.5: # %udiv-bb1
; X86-NEXT: movl 24(%ebp), %edi
; X86-NEXT: movl %edi, {{[0-9]+}}(%esp)
; X86-NEXT: xorps %xmm0, %xmm0
; X86-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: movl 28(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 32(%ebp), %edi
-; X86-NEXT: movl %edi, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
+; X86-NEXT: movl 32(%ebp), %edx
+; X86-NEXT: movl %edx, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, %ecx
; X86-NEXT: xorb $127, %cl
@@ -274,19 +274,20 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: negb %al
; X86-NEXT: movsbl %al, %eax
; X86-NEXT: movl 136(%esp,%eax), %esi
-; X86-NEXT: movl 140(%esp,%eax), %ebx
-; X86-NEXT: shldl %cl, %esi, %ebx
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 128(%esp,%eax), %ebx
+; X86-NEXT: movl 140(%esp,%eax), %edi
+; X86-NEXT: shldl %cl, %esi, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 128(%esp,%eax), %edi
; X86-NEXT: movl 132(%esp,%eax), %eax
; X86-NEXT: shldl %cl, %eax, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl %cl, %ebx, %eax
+; X86-NEXT: shldl %cl, %edi, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shll %cl, %ebx
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shll %cl, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl $1, %edx
-; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: adcl $0, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jb .LBB4_10
@@ -296,23 +297,25 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 28(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %edi, {{[0-9]+}}(%esp)
+; X86-NEXT: movl 32(%ebp), %eax
+; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 36(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %edx, %eax
+; X86-NEXT: movl %edx, %ebx
+; X86-NEXT: movl %ebx, %eax
; X86-NEXT: shrb $3, %al
; X86-NEXT: andb $12, %al
; X86-NEXT: movzbl %al, %eax
; X86-NEXT: movl 92(%esp,%eax), %esi
-; X86-NEXT: movl 88(%esp,%eax), %ebx
-; X86-NEXT: movl %ebx, %edi
-; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: movl 88(%esp,%eax), %edx
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: shrdl %cl, %esi, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 80(%esp,%eax), %edi
; X86-NEXT: movl 84(%esp,%eax), %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shrdl %cl, %ebx, %eax
+; X86-NEXT: shrdl %cl, %edx, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: shrl %cl, %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
@@ -331,7 +334,6 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: adcl $-1, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl %edx, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
@@ -410,86 +412,92 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind {
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: jne .LBB4_7
; X86-NEXT: .LBB4_8: # %udiv-loop-exit
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X86-NEXT: shldl $1, %ebx, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: shldl $1, %eax, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edx, %ebx
+; X86-NEXT: shldl $1, %edx, %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: shldl $1, %esi, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: leal (%edi,%esi,2), %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %eax, %esi
; X86-NEXT: movl %ecx, %edi
; X86-NEXT: .LBB4_9: # %udiv-end
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 56(%ebp), %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl %ecx, (%eax)
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %esi, %ebx
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edx, 4(%eax)
; X86-NEXT: movl %ebx, 8(%eax)
; X86-NEXT: movl %edi, 12(%eax)
+; X86-NEXT: movl %edi, %ebx
; X86-NEXT: movl 48(%ebp), %eax
-; X86-NEXT: movl %edi, %esi
-; X86-NEXT: movl %eax, %edi
-; X86-NEXT: imull %edx, %edi
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: mull %ecx
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: imull %edx, %ecx
+; X86-NEXT: mull %esi
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: addl %edi, %edx
+; X86-NEXT: addl %ecx, %edx
; X86-NEXT: movl 52(%ebp), %edi
-; X86-NEXT: imull %ecx, %edi
+; X86-NEXT: imull %esi, %edi
; X86-NEXT: addl %edx, %edi
; X86-NEXT: movl 40(%ebp), %eax
-; X86-NEXT: mull %ebx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: mull %esi
; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: imull 40(%ebp), %esi
-; X86-NEXT: addl %edx, %esi
+; X86-NEXT: imull 40(%ebp), %ebx
+; X86-NEXT: addl %edx, %ebx
; X86-NEXT: movl 44(%ebp), %eax
-; X86-NEXT: imull %eax, %ebx
-; X86-NEXT: addl %esi, %ebx
+; X86-NEXT: imull %eax, %esi
+; X86-NEXT: addl %ebx, %esi
; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: adcl %edi, %ebx
+; X86-NEXT: adcl %edi, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: movl %edi, %eax
; X86-NEXT: movl 40(%ebp), %ecx
; X86-NEXT: mull %ecx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edx, %esi
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: movl %esi, %eax
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; X86-NEXT: movl %ebx, %eax
; X86-NEXT: mull %ecx
; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
+; X86-NEXT: addl %esi, %ecx
; X86-NEXT: adcl $0, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edx, %esi
; X86-NEXT: movl %edi, %eax
; X86-NEXT: mull 44(%ebp)
; X86-NEXT: movl %edx, %edi
; X86-NEXT: addl %ecx, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
+; X86-NEXT: adcl %esi, %edi
; X86-NEXT: setb %cl
-; X86-NEXT: movl %esi, %eax
+; X86-NEXT: movl %ebx, %eax
; X86-NEXT: mull 44(%ebp)
; X86-NEXT: addl %edi, %eax
; X86-NEXT: movzbl %cl, %ecx
; X86-NEXT: adcl %ecx, %edx
; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
-; X86-NEXT: adcl %ebx, %edx
+; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: movl 24(%ebp), %edi
; X86-NEXT: subl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
-; X86-NEXT: movl 28(%ebp), %ebx
-; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
+; X86-NEXT: movl 28(%ebp), %esi
+; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload
; X86-NEXT: movl 32(%ebp), %ecx
; X86-NEXT: sbbl %eax, %ecx
-; X86-NEXT: movl 36(%ebp), %esi
-; X86-NEXT: sbbl %edx, %esi
+; X86-NEXT: movl 36(%ebp), %ebx
+; X86-NEXT: sbbl %edx, %ebx
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl %edi, (%eax)
-; X86-NEXT: movl %ebx, 4(%eax)
+; X86-NEXT: movl %esi, 4(%eax)
; X86-NEXT: movl %ecx, 8(%eax)
-; X86-NEXT: movl %esi, 12(%eax)
+; X86-NEXT: movl %ebx, 12(%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/extract-bits.ll b/llvm/test/CodeGen/X86/extract-bits.ll
index 90e075bfabf0a..71159bb8dc2b6 100644
--- a/llvm/test/CodeGen/X86/extract-bits.ll
+++ b/llvm/test/CodeGen/X86/extract-bits.ll
@@ -3621,24 +3621,24 @@ define i32 @bextr64_32_b0(i64 %val, i64 %numskipbits, i8 %numlowbits) nounwind {
; X86-BMI2-LABEL: bextr64_32_b0:
; X86-BMI2: # %bb.0:
; X86-BMI2-NEXT: pushl %esi
-; X86-BMI2-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-BMI2-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-BMI2-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
-; X86-BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-BMI2-NEXT: shrdl %cl, %esi, %edx
+; X86-BMI2-NEXT: shrdl %cl, %esi, %eax
; X86-BMI2-NEXT: testb $32, %cl
; X86-BMI2-NEXT: je .LBB31_2
; X86-BMI2-NEXT: # %bb.1:
-; X86-BMI2-NEXT: shrxl %ecx, %esi, %edx
+; X86-BMI2-NEXT: shrxl %ecx, %esi, %eax
; X86-BMI2-NEXT: .LBB31_2:
; X86-BMI2-NEXT: xorl %ecx, %ecx
-; X86-BMI2-NEXT: testb $32, %al
+; X86-BMI2-NEXT: testb $32, %dl
; X86-BMI2-NEXT: jne .LBB31_4
; X86-BMI2-NEXT: # %bb.3:
; X86-BMI2-NEXT: movl $-1, %ecx
-; X86-BMI2-NEXT: shlxl %eax, %ecx, %ecx
+; X86-BMI2-NEXT: shlxl %edx, %ecx, %ecx
; X86-BMI2-NEXT: .LBB31_4:
-; X86-BMI2-NEXT: andnl %edx, %ecx, %eax
+; X86-BMI2-NEXT: andnl %eax, %ecx, %eax
; X86-BMI2-NEXT: popl %esi
; X86-BMI2-NEXT: retl
;
@@ -3949,24 +3949,24 @@ define i32 @bextr64_32_b3(i64 %val, i64 %numskipbits, i8 %numlowbits) nounwind {
; X86-BMI2-LABEL: bextr64_32_b3:
; X86-BMI2: # %bb.0:
; X86-BMI2-NEXT: pushl %esi
-; X86-BMI2-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-BMI2-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-BMI2-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
-; X86-BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-BMI2-NEXT: shrdl %cl, %esi, %edx
+; X86-BMI2-NEXT: shrdl %cl, %esi, %eax
; X86-BMI2-NEXT: testb $32, %cl
; X86-BMI2-NEXT: je .LBB34_2
; X86-BMI2-NEXT: # %bb.1:
-; X86-BMI2-NEXT: shrxl %ecx, %esi, %edx
+; X86-BMI2-NEXT: shrxl %ecx, %esi, %eax
; X86-BMI2-NEXT: .LBB34_2:
; X86-BMI2-NEXT: xorl %ecx, %ecx
-; X86-BMI2-NEXT: testb $32, %al
+; X86-BMI2-NEXT: testb $32, %dl
; X86-BMI2-NEXT: jne .LBB34_4
; X86-BMI2-NEXT: # %bb.3:
; X86-BMI2-NEXT: movl $-1, %ecx
-; X86-BMI2-NEXT: shlxl %eax, %ecx, %ecx
+; X86-BMI2-NEXT: shlxl %edx, %ecx, %ecx
; X86-BMI2-NEXT: .LBB34_4:
-; X86-BMI2-NEXT: andnl %edx, %ecx, %eax
+; X86-BMI2-NEXT: andnl %eax, %ecx, %eax
; X86-BMI2-NEXT: popl %esi
; X86-BMI2-NEXT: retl
;
diff --git a/llvm/test/CodeGen/X86/extract-lowbits.ll b/llvm/test/CodeGen/X86/extract-lowbits.ll
index aff5ac7437a29..cfeab10ac3c88 100644
--- a/llvm/test/CodeGen/X86/extract-lowbits.ll
+++ b/llvm/test/CodeGen/X86/extract-lowbits.ll
@@ -1865,15 +1865,15 @@ define i32 @bzhi64_32_b0(i64 %val, i8 %numlowbits) nounwind {
;
; X86-BMI2-LABEL: bzhi64_32_b0:
; X86-BMI2: # %bb.0:
-; X86-BMI2-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X86-BMI2-NEXT: xorl %ecx, %ecx
-; X86-BMI2-NEXT: testb $32, %al
+; X86-BMI2-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
+; X86-BMI2-NEXT: xorl %eax, %eax
+; X86-BMI2-NEXT: testb $32, %cl
; X86-BMI2-NEXT: jne .LBB26_2
; X86-BMI2-NEXT: # %bb.1:
-; X86-BMI2-NEXT: movl $-1, %ecx
-; X86-BMI2-NEXT: shlxl %eax, %ecx, %ecx
+; X86-BMI2-NEXT: movl $-1, %eax
+; X86-BMI2-NEXT: shlxl %ecx, %eax, %eax
; X86-BMI2-NEXT: .LBB26_2:
-; X86-BMI2-NEXT: andnl {{[0-9]+}}(%esp), %ecx, %eax
+; X86-BMI2-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
; X86-BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bzhi64_32_b0:
@@ -2045,15 +2045,15 @@ define i32 @bzhi64_32_b3(i64 %val, i8 %numlowbits) nounwind {
;
; X86-BMI2-LABEL: bzhi64_32_b3:
; X86-BMI2: # %bb.0:
-; X86-BMI2-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X86-BMI2-NEXT: xorl %ecx, %ecx
-; X86-BMI2-NEXT: testb $32, %al
+; X86-BMI2-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
+; X86-BMI2-NEXT: xorl %eax, %eax
+; X86-BMI2-NEXT: testb $32, %cl
; X86-BMI2-NEXT: jne .LBB29_2
; X86-BMI2-NEXT: # %bb.1:
-; X86-BMI2-NEXT: movl $-1, %ecx
-; X86-BMI2-NEXT: shlxl %eax, %ecx, %ecx
+; X86-BMI2-NEXT: movl $-1, %eax
+; X86-BMI2-NEXT: shlxl %ecx, %eax, %eax
; X86-BMI2-NEXT: .LBB29_2:
-; X86-BMI2-NEXT: andnl {{[0-9]+}}(%esp), %ecx, %eax
+; X86-BMI2-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
; X86-BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bzhi64_32_b3:
@@ -3497,26 +3497,26 @@ define i64 @bzhi64_d0(i64 %val, i64 %numlowbits) nounwind {
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
-; X86-NOBMI-NEXT: movl %edx, %esi
-; X86-NOBMI-NEXT: shll %cl, %esi
+; X86-NOBMI-NEXT: movl %edx, %edi
+; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: shldl %cl, %edx, %eax
; X86-NOBMI-NEXT: testb $32, %cl
-; X86-NOBMI-NEXT: movl %esi, %edi
+; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: jne .LBB48_2
; X86-NOBMI-NEXT: # %bb.1:
-; X86-NOBMI-NEXT: movl %eax, %edi
+; X86-NOBMI-NEXT: movl %eax, %esi
; X86-NOBMI-NEXT: .LBB48_2:
-; X86-NOBMI-NEXT: movl %edi, %eax
+; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: xorl %ebx, %ebx
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl $0, %edx
; X86-NOBMI-NEXT: jne .LBB48_4
; X86-NOBMI-NEXT: # %bb.3:
-; X86-NOBMI-NEXT: movl %esi, %ebx
+; X86-NOBMI-NEXT: movl %edi, %ebx
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: .LBB48_4:
-; X86-NOBMI-NEXT: shrdl %cl, %edi, %ebx
+; X86-NOBMI-NEXT: shrdl %cl, %esi, %ebx
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: jne .LBB48_6
; X86-NOBMI-NEXT: # %bb.5:
@@ -3536,26 +3536,26 @@ define i64 @bzhi64_d0(i64 %val, i64 %numlowbits) nounwind {
; X86-BMI1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1-NEXT: movb $64, %cl
; X86-BMI1-NEXT: subb {{[0-9]+}}(%esp), %cl
-; X86-BMI1-NEXT: movl %edx, %esi
-; X86-BMI1-NEXT: shll %cl, %esi
+; X86-BMI1-NEXT: movl %edx, %edi
+; X86-BMI1-NEXT: shll %cl, %edi
; X86-BMI1-NEXT: shldl %cl, %edx, %eax
; X86-BMI1-NEXT: testb $32, %cl
-; X86-BMI1-NEXT: movl %esi, %edi
+; X86-BMI1-NEXT: movl %edi, %esi
; X86-BMI1-NEXT: jne .LBB48_2
; X86-BMI1-NEXT: # %bb.1:
-; X86-BMI1-NEXT: movl %eax, %edi
+; X86-BMI1-NEXT: movl %eax, %esi
; X86-BMI1-NEXT: .LBB48_2:
-; X86-BMI1-NEXT: movl %edi, %eax
+; X86-BMI1-NEXT: movl %esi, %eax
; X86-BMI1-NEXT: shrl %cl, %eax
; X86-BMI1-NEXT: xorl %ebx, %ebx
; X86-BMI1-NEXT: testb $32, %cl
; X86-BMI1-NEXT: movl $0, %edx
; X86-BMI1-NEXT: jne .LBB48_4
; X86-BMI1-NEXT: # %bb.3:
-; X86-BMI1-NEXT: movl %esi, %ebx
+; X86-BMI1-NEXT: movl %edi, %ebx
; X86-BMI1-NEXT: movl %eax, %edx
; X86-BMI1-NEXT: .LBB48_4:
-; X86-BMI1-NEXT: shrdl %cl, %edi, %ebx
+; X86-BMI1-NEXT: shrdl %cl, %esi, %ebx
; X86-BMI1-NEXT: testb $32, %cl
; X86-BMI1-NEXT: jne .LBB48_6
; X86-BMI1-NEXT: # %bb.5:
@@ -3634,26 +3634,26 @@ define i64 @bzhi64_d1_indexzext(i64 %val, i8 %numlowbits) nounwind {
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
-; X86-NOBMI-NEXT: movl %edx, %esi
-; X86-NOBMI-NEXT: shll %cl, %esi
+; X86-NOBMI-NEXT: movl %edx, %edi
+; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: shldl %cl, %edx, %eax
; X86-NOBMI-NEXT: testb $32, %cl
-; X86-NOBMI-NEXT: movl %esi, %edi
+; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: jne .LBB49_2
; X86-NOBMI-NEXT: # %bb.1:
-; X86-NOBMI-NEXT: movl %eax, %edi
+; X86-NOBMI-NEXT: movl %eax, %esi
; X86-NOBMI-NEXT: .LBB49_2:
-; X86-NOBMI-NEXT: movl %edi, %eax
+; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: xorl %ebx, %ebx
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl $0, %edx
; X86-NOBMI-NEXT: jne .LBB49_4
; X86-NOBMI-NEXT: # %bb.3:
-; X86-NOBMI-NEXT: movl %esi, %ebx
+; X86-NOBMI-NEXT: movl %edi, %ebx
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: .LBB49_4:
-; X86-NOBMI-NEXT: shrdl %cl, %edi, %ebx
+; X86-NOBMI-NEXT: shrdl %cl, %esi, %ebx
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: jne .LBB49_6
; X86-NOBMI-NEXT: # %bb.5:
@@ -3673,26 +3673,26 @@ define i64 @bzhi64_d1_indexzext(i64 %val, i8 %numlowbits) nounwind {
; X86-BMI1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1-NEXT: movb $64, %cl
; X86-BMI1-NEXT: subb {{[0-9]+}}(%esp), %cl
-; X86-BMI1-NEXT: movl %edx, %esi
-; X86-BMI1-NEXT: shll %cl, %esi
+; X86-BMI1-NEXT: movl %edx, %edi
+; X86-BMI1-NEXT: shll %cl, %edi
; X86-BMI1-NEXT: shldl %cl, %edx, %eax
; X86-BMI1-NEXT: testb $32, %cl
-; X86-BMI1-NEXT: movl %esi, %edi
+; X86-BMI1-NEXT: movl %edi, %esi
; X86-BMI1-NEXT: jne .LBB49_2
; X86-BMI1-NEXT: # %bb.1:
-; X86-BMI1-NEXT: movl %eax, %edi
+; X86-BMI1-NEXT: movl %eax, %esi
; X86-BMI1-NEXT: .LBB49_2:
-; X86-BMI1-NEXT: movl %edi, %eax
+; X86-BMI1-NEXT: movl %esi, %eax
; X86-BMI1-NEXT: shrl %cl, %eax
; X86-BMI1-NEXT: xorl %ebx, %ebx
; X86-BMI1-NEXT: testb $32, %cl
; X86-BMI1-NEXT: movl $0, %edx
; X86-BMI1-NEXT: jne .LBB49_4
; X86-BMI1-NEXT: # %bb.3:
-; X86-BMI1-NEXT: movl %esi, %ebx
+; X86-BMI1-NEXT: movl %edi, %ebx
; X86-BMI1-NEXT: movl %eax, %edx
; X86-BMI1-NEXT: .LBB49_4:
-; X86-BMI1-NEXT: shrdl %cl, %edi, %ebx
+; X86-BMI1-NEXT: shrdl %cl, %esi, %ebx
; X86-BMI1-NEXT: testb $32, %cl
; X86-BMI1-NEXT: jne .LBB49_6
; X86-BMI1-NEXT: # %bb.5:
@@ -3775,26 +3775,26 @@ define i64 @bzhi64_d2_load(ptr %w, i64 %numlowbits) nounwind {
; X86-NOBMI-NEXT: movl 4(%eax), %eax
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
-; X86-NOBMI-NEXT: movl %edx, %esi
-; X86-NOBMI-NEXT: shll %cl, %esi
+; X86-NOBMI-NEXT: movl %edx, %edi
+; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: shldl %cl, %edx, %eax
; X86-NOBMI-NEXT: testb $32, %cl
-; X86-NOBMI-NEXT: movl %esi, %edi
+; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: jne .LBB50_2
; X86-NOBMI-NEXT: # %bb.1:
-; X86-NOBMI-NEXT: movl %eax, %edi
+; X86-NOBMI-NEXT: movl %eax, %esi
; X86-NOBMI-NEXT: .LBB50_2:
-; X86-NOBMI-NEXT: movl %edi, %eax
+; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: xorl %ebx, %ebx
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl $0, %edx
; X86-NOBMI-NEXT: jne .LBB50_4
; X86-NOBMI-NEXT: # %bb.3:
-; X86-NOBMI-NEXT: movl %esi, %ebx
+; X86-NOBMI-NEXT: movl %edi, %ebx
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: .LBB50_4:
-; X86-NOBMI-NEXT: shrdl %cl, %edi, %ebx
+; X86-NOBMI-NEXT: shrdl %cl, %esi, %ebx
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: jne .LBB50_6
; X86-NOBMI-NEXT: # %bb.5:
@@ -3815,26 +3815,26 @@ define i64 @bzhi64_d2_load(ptr %w, i64 %numlowbits) nounwind {
; X86-BMI1-NEXT: movl 4(%eax), %eax
; X86-BMI1-NEXT: movb $64, %cl
; X86-BMI1-NEXT: subb {{[0-9]+}}(%esp), %cl
-; X86-BMI1-NEXT: movl %edx, %esi
-; X86-BMI1-NEXT: shll %cl, %esi
+; X86-BMI1-NEXT: movl %edx, %edi
+; X86-BMI1-NEXT: shll %cl, %edi
; X86-BMI1-NEXT: shldl %cl, %edx, %eax
; X86-BMI1-NEXT: testb $32, %cl
-; X86-BMI1-NEXT: movl %esi, %edi
+; X86-BMI1-NEXT: movl %edi, %esi
; X86-BMI1-NEXT: jne .LBB50_2
; X86-BMI1-NEXT: # %bb.1:
-; X86-BMI1-NEXT: movl %eax, %edi
+; X86-BMI1-NEXT: movl %eax, %esi
; X86-BMI1-NEXT: .LBB50_2:
-; X86-BMI1-NEXT: movl %edi, %eax
+; X86-BMI1-NEXT: movl %esi, %eax
; X86-BMI1-NEXT: shrl %cl, %eax
; X86-BMI1-NEXT: xorl %ebx, %ebx
; X86-BMI1-NEXT: testb $32, %cl
; X86-BMI1-NEXT: movl $0, %edx
; X86-BMI1-NEXT: jne .LBB50_4
; X86-BMI1-NEXT: # %bb.3:
-; X86-BMI1-NEXT: movl %esi, %ebx
+; X86-BMI1-NEXT: movl %edi, %ebx
; X86-BMI1-NEXT: movl %eax, %edx
; X86-BMI1-NEXT: .LBB50_4:
-; X86-BMI1-NEXT: shrdl %cl, %edi, %ebx
+; X86-BMI1-NEXT: shrdl %cl, %esi, %ebx
; X86-BMI1-NEXT: testb $32, %cl
; X86-BMI1-NEXT: jne .LBB50_6
; X86-BMI1-NEXT: # %bb.5:
@@ -3916,26 +3916,26 @@ define i64 @bzhi64_d3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {
; X86-NOBMI-NEXT: movl 4(%eax), %eax
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
-; X86-NOBMI-NEXT: movl %edx, %esi
-; X86-NOBMI-NEXT: shll %cl, %esi
+; X86-NOBMI-NEXT: movl %edx, %edi
+; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: shldl %cl, %edx, %eax
; X86-NOBMI-NEXT: testb $32, %cl
-; X86-NOBMI-NEXT: movl %esi, %edi
+; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: jne .LBB51_2
; X86-NOBMI-NEXT: # %bb.1:
-; X86-NOBMI-NEXT: movl %eax, %edi
+; X86-NOBMI-NEXT: movl %eax, %esi
; X86-NOBMI-NEXT: .LBB51_2:
-; X86-NOBMI-NEXT: movl %edi, %eax
+; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: xorl %ebx, %ebx
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl $0, %edx
; X86-NOBMI-NEXT: jne .LBB51_4
; X86-NOBMI-NEXT: # %bb.3:
-; X86-NOBMI-NEXT: movl %esi, %ebx
+; X86-NOBMI-NEXT: movl %edi, %ebx
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: .LBB51_4:
-; X86-NOBMI-NEXT: shrdl %cl, %edi, %ebx
+; X86-NOBMI-NEXT: shrdl %cl, %esi, %ebx
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: jne .LBB51_6
; X86-NOBMI-NEXT: # %bb.5:
@@ -3956,26 +3956,26 @@ define i64 @bzhi64_d3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {
; X86-BMI1-NEXT: movl 4(%eax), %eax
; X86-BMI1-NEXT: movb $64, %cl
; X86-BMI1-NEXT: subb {{[0-9]+}}(%esp), %cl
-; X86-BMI1-NEXT: movl %edx, %esi
-; X86-BMI1-NEXT: shll %cl, %esi
+; X86-BMI1-NEXT: movl %edx, %edi
+; X86-BMI1-NEXT: shll %cl, %edi
; X86-BMI1-NEXT: shldl %cl, %edx, %eax
; X86-BMI1-NEXT: testb $32, %cl
-; X86-BMI1-NEXT: movl %esi, %edi
+; X86-BMI1-NEXT: movl %edi, %esi
; X86-BMI1-NEXT: jne .LBB51_2
; X86-BMI1-NEXT: # %bb.1:
-; X86-BMI1-NEXT: movl %eax, %edi
+; X86-BMI1-NEXT: movl %eax, %esi
; X86-BMI1-NEXT: .LBB51_2:
-; X86-BMI1-NEXT: movl %edi, %eax
+; X86-BMI1-NEXT: movl %esi, %eax
; X86-BMI1-NEXT: shrl %cl, %eax
; X86-BMI1-NEXT: xorl %ebx, %ebx
; X86-BMI1-NEXT: testb $32, %cl
; X86-BMI1-NEXT: movl $0, %edx
; X86-BMI1-NEXT: jne .LBB51_4
; X86-BMI1-NEXT: # %bb.3:
-; X86-BMI1-NEXT: movl %esi, %ebx
+; X86-BMI1-NEXT: movl %edi, %ebx
; X86-BMI1-NEXT: movl %eax, %edx
; X86-BMI1-NEXT: .LBB51_4:
-; X86-BMI1-NEXT: shrdl %cl, %edi, %ebx
+; X86-BMI1-NEXT: shrdl %cl, %esi, %ebx
; X86-BMI1-NEXT: testb $32, %cl
; X86-BMI1-NEXT: jne .LBB51_6
; X86-BMI1-NEXT: # %bb.5:
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics.ll b/llvm/test/CodeGen/X86/fp-intrinsics.ll
index fd459be0d0ec1..f80ad43fbb8c8 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics.ll
@@ -1423,14 +1423,14 @@ define i64 @f20u64(double %x) #0 {
;
; AVX1-LABEL: f20u64:
; AVX1: # %bb.0: # %entry
-; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm1, %xmm0
-; AVX1-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vmovsd {{.*#+}} xmm2 = [9.2233720368547758E+18,0.0E+0]
+; AVX1-NEXT: vcomisd %xmm2, %xmm0
+; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: jb .LBB25_2
; AVX1-NEXT: # %bb.1: # %entry
-; AVX1-NEXT: vmovapd %xmm1, %xmm2
+; AVX1-NEXT: vmovapd %xmm2, %xmm1
; AVX1-NEXT: .LBB25_2: # %entry
-; AVX1-NEXT: vsubsd %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vcvttsd2si %xmm0, %rcx
; AVX1-NEXT: setae %al
; AVX1-NEXT: movzbl %al, %eax
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll
index 0498f9b7f9a3d..4056af1ec9366 100644
--- a/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll
@@ -369,14 +369,14 @@ define i64 @fptoui_f16toi64(half %x) #0 {
; F16C-NEXT: movzwl %ax, %eax
; F16C-NEXT: vmovd %eax, %xmm0
; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
-; F16C-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
-; F16C-NEXT: vcomiss %xmm1, %xmm0
-; F16C-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; F16C-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; F16C-NEXT: vcomiss %xmm2, %xmm0
+; F16C-NEXT: vxorps %xmm1, %xmm1, %xmm1
; F16C-NEXT: jb .LBB9_2
; F16C-NEXT: # %bb.1:
-; F16C-NEXT: vmovaps %xmm1, %xmm2
+; F16C-NEXT: vmovaps %xmm2, %xmm1
; F16C-NEXT: .LBB9_2:
-; F16C-NEXT: vsubss %xmm2, %xmm0, %xmm0
+; F16C-NEXT: vsubss %xmm1, %xmm0, %xmm0
; F16C-NEXT: vcvttss2si %xmm0, %rcx
; F16C-NEXT: setae %al
; F16C-NEXT: movzbl %al, %eax
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll
index ecdc507a882c3..7c281645f1768 100644
--- a/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll
@@ -620,14 +620,14 @@ define i64 @fptoui_f32toi64(float %x) #0 {
;
; AVX1-X64-LABEL: fptoui_f32toi64:
; AVX1-X64: # %bb.0:
-; AVX1-X64-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-X64-NEXT: vcomiss %xmm1, %xmm0
-; AVX1-X64-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; AVX1-X64-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; AVX1-X64-NEXT: vcomiss %xmm2, %xmm0
+; AVX1-X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-X64-NEXT: jb .LBB9_2
; AVX1-X64-NEXT: # %bb.1:
-; AVX1-X64-NEXT: vmovaps %xmm1, %xmm2
+; AVX1-X64-NEXT: vmovaps %xmm2, %xmm1
; AVX1-X64-NEXT: .LBB9_2:
-; AVX1-X64-NEXT: vsubss %xmm2, %xmm0, %xmm0
+; AVX1-X64-NEXT: vsubss %xmm1, %xmm0, %xmm0
; AVX1-X64-NEXT: vcvttss2si %xmm0, %rcx
; AVX1-X64-NEXT: setae %al
; AVX1-X64-NEXT: movzbl %al, %eax
@@ -1260,14 +1260,14 @@ define i64 @fptoui_f64toi64(double %x) #0 {
;
; AVX1-X64-LABEL: fptoui_f64toi64:
; AVX1-X64: # %bb.0:
-; AVX1-X64-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
-; AVX1-X64-NEXT: vcomisd %xmm1, %xmm0
-; AVX1-X64-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; AVX1-X64-NEXT: vmovsd {{.*#+}} xmm2 = [9.2233720368547758E+18,0.0E+0]
+; AVX1-X64-NEXT: vcomisd %xmm2, %xmm0
+; AVX1-X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-X64-NEXT: jb .LBB18_2
; AVX1-X64-NEXT: # %bb.1:
-; AVX1-X64-NEXT: vmovapd %xmm1, %xmm2
+; AVX1-X64-NEXT: vmovapd %xmm2, %xmm1
; AVX1-X64-NEXT: .LBB18_2:
-; AVX1-X64-NEXT: vsubsd %xmm2, %xmm0, %xmm0
+; AVX1-X64-NEXT: vsubsd %xmm1, %xmm0, %xmm0
; AVX1-X64-NEXT: vcvttsd2si %xmm0, %rcx
; AVX1-X64-NEXT: setae %al
; AVX1-X64-NEXT: movzbl %al, %eax
diff --git a/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll b/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
index d074eaf7323d4..5f3fdc35e2cea 100644
--- a/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
@@ -676,7 +676,7 @@ define i100 @test_unsigned_i100_f32(float %f) nounwind {
; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixunssfti
; X86-X87-NEXT: subl $4, %esp
-; X86-X87-NEXT: xorl %esi, %esi
+; X86-X87-NEXT: xorl %edi, %edi
; X86-X87-NEXT: movb %bh, %ah
; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %eax
@@ -684,16 +684,16 @@ define i100 @test_unsigned_i100_f32(float %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: .LBB8_2:
-; X86-X87-NEXT: movl $0, %edi
+; X86-X87-NEXT: movl $0, %esi
; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jb .LBB8_4
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
-; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB8_4:
; X86-X87-NEXT: jb .LBB8_6
; X86-X87-NEXT: # %bb.5:
-; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB8_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -706,20 +706,20 @@ define i100 @test_unsigned_i100_f32(float %f) nounwind {
; X86-X87-NEXT: movl $15, %eax
; X86-X87-NEXT: ja .LBB8_8
; X86-X87-NEXT: # %bb.7:
-; X86-X87-NEXT: movl %esi, %eax
+; X86-X87-NEXT: movl %edi, %eax
; X86-X87-NEXT: .LBB8_8:
-; X86-X87-NEXT: movl $-1, %esi
+; X86-X87-NEXT: movl $-1, %edi
; X86-X87-NEXT: movl $-1, %ebp
; X86-X87-NEXT: movl $-1, %edx
; X86-X87-NEXT: ja .LBB8_10
; X86-X87-NEXT: # %bb.9:
-; X86-X87-NEXT: movl %ebx, %esi
-; X86-X87-NEXT: movl %edi, %ebp
+; X86-X87-NEXT: movl %ebx, %edi
+; X86-X87-NEXT: movl %esi, %ebp
; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-X87-NEXT: .LBB8_10:
; X86-X87-NEXT: movl %edx, 8(%ecx)
; X86-X87-NEXT: movl %ebp, 4(%ecx)
-; X86-X87-NEXT: movl %esi, (%ecx)
+; X86-X87-NEXT: movl %edi, (%ecx)
; X86-X87-NEXT: andl $15, %eax
; X86-X87-NEXT: movb %al, 12(%ecx)
; X86-X87-NEXT: movl %ecx, %eax
@@ -1588,7 +1588,7 @@ define i100 @test_unsigned_i100_f64(double %f) nounwind {
; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixunsdfti
; X86-X87-NEXT: subl $4, %esp
-; X86-X87-NEXT: xorl %esi, %esi
+; X86-X87-NEXT: xorl %edi, %edi
; X86-X87-NEXT: movb %bh, %ah
; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %eax
@@ -1596,16 +1596,16 @@ define i100 @test_unsigned_i100_f64(double %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: .LBB18_2:
-; X86-X87-NEXT: movl $0, %edi
+; X86-X87-NEXT: movl $0, %esi
; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jb .LBB18_4
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
-; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB18_4:
; X86-X87-NEXT: jb .LBB18_6
; X86-X87-NEXT: # %bb.5:
-; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB18_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -1618,20 +1618,20 @@ define i100 @test_unsigned_i100_f64(double %f) nounwind {
; X86-X87-NEXT: movl $15, %eax
; X86-X87-NEXT: ja .LBB18_8
; X86-X87-NEXT: # %bb.7:
-; X86-X87-NEXT: movl %esi, %eax
+; X86-X87-NEXT: movl %edi, %eax
; X86-X87-NEXT: .LBB18_8:
-; X86-X87-NEXT: movl $-1, %esi
+; X86-X87-NEXT: movl $-1, %edi
; X86-X87-NEXT: movl $-1, %ebp
; X86-X87-NEXT: movl $-1, %edx
; X86-X87-NEXT: ja .LBB18_10
; X86-X87-NEXT: # %bb.9:
-; X86-X87-NEXT: movl %ebx, %esi
-; X86-X87-NEXT: movl %edi, %ebp
+; X86-X87-NEXT: movl %ebx, %edi
+; X86-X87-NEXT: movl %esi, %ebp
; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-X87-NEXT: .LBB18_10:
; X86-X87-NEXT: movl %edx, 8(%ecx)
; X86-X87-NEXT: movl %ebp, 4(%ecx)
-; X86-X87-NEXT: movl %esi, (%ecx)
+; X86-X87-NEXT: movl %edi, (%ecx)
; X86-X87-NEXT: andl $15, %eax
; X86-X87-NEXT: movb %al, 12(%ecx)
; X86-X87-NEXT: movl %ecx, %eax
@@ -2627,7 +2627,7 @@ define i100 @test_unsigned_i100_f16(half %f) nounwind {
; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixunssfti
; X86-X87-NEXT: subl $4, %esp
-; X86-X87-NEXT: xorl %esi, %esi
+; X86-X87-NEXT: xorl %edi, %edi
; X86-X87-NEXT: movb %bh, %ah
; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %eax
@@ -2635,16 +2635,16 @@ define i100 @test_unsigned_i100_f16(half %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: .LBB28_2:
-; X86-X87-NEXT: movl $0, %edi
+; X86-X87-NEXT: movl $0, %esi
; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jb .LBB28_4
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
-; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB28_4:
; X86-X87-NEXT: jb .LBB28_6
; X86-X87-NEXT: # %bb.5:
-; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB28_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -2657,20 +2657,20 @@ define i100 @test_unsigned_i100_f16(half %f) nounwind {
; X86-X87-NEXT: movl $15, %eax
; X86-X87-NEXT: ja .LBB28_8
; X86-X87-NEXT: # %bb.7:
-; X86-X87-NEXT: movl %esi, %eax
+; X86-X87-NEXT: movl %edi, %eax
; X86-X87-NEXT: .LBB28_8:
-; X86-X87-NEXT: movl $-1, %esi
+; X86-X87-NEXT: movl $-1, %edi
; X86-X87-NEXT: movl $-1, %ebp
; X86-X87-NEXT: movl $-1, %edx
; X86-X87-NEXT: ja .LBB28_10
; X86-X87-NEXT: # %bb.9:
-; X86-X87-NEXT: movl %ebx, %esi
-; X86-X87-NEXT: movl %edi, %ebp
+; X86-X87-NEXT: movl %ebx, %edi
+; X86-X87-NEXT: movl %esi, %ebp
; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-X87-NEXT: .LBB28_10:
; X86-X87-NEXT: movl %edx, 8(%ecx)
; X86-X87-NEXT: movl %ebp, 4(%ecx)
-; X86-X87-NEXT: movl %esi, (%ecx)
+; X86-X87-NEXT: movl %edi, (%ecx)
; X86-X87-NEXT: andl $15, %eax
; X86-X87-NEXT: movb %al, 12(%ecx)
; X86-X87-NEXT: movl %ecx, %eax
@@ -3842,7 +3842,7 @@ define i100 @test_unsigned_i100_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixunsxfti
; X86-X87-NEXT: subl $4, %esp
-; X86-X87-NEXT: xorl %esi, %esi
+; X86-X87-NEXT: xorl %edi, %edi
; X86-X87-NEXT: movb %bh, %ah
; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %eax
@@ -3850,16 +3850,16 @@ define i100 @test_unsigned_i100_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: .LBB38_2:
-; X86-X87-NEXT: movl $0, %edi
+; X86-X87-NEXT: movl $0, %esi
; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jb .LBB38_4
; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
-; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB38_4:
; X86-X87-NEXT: jb .LBB38_6
; X86-X87-NEXT: # %bb.5:
-; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB38_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -3872,20 +3872,20 @@ define i100 @test_unsigned_i100_f80(x86_fp80 %f) nounwind {
; X86-X87-NEXT: movl $15, %eax
; X86-X87-NEXT: ja .LBB38_8
; X86-X87-NEXT: # %bb.7:
-; X86-X87-NEXT: movl %esi, %eax
+; X86-X87-NEXT: movl %edi, %eax
; X86-X87-NEXT: .LBB38_8:
-; X86-X87-NEXT: movl $-1, %esi
+; X86-X87-NEXT: movl $-1, %edi
; X86-X87-NEXT: movl $-1, %ebp
; X86-X87-NEXT: movl $-1, %edx
; X86-X87-NEXT: ja .LBB38_10
; X86-X87-NEXT: # %bb.9:
-; X86-X87-NEXT: movl %ebx, %esi
-; X86-X87-NEXT: movl %edi, %ebp
+; X86-X87-NEXT: movl %ebx, %edi
+; X86-X87-NEXT: movl %esi, %ebp
; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-X87-NEXT: .LBB38_10:
; X86-X87-NEXT: movl %edx, 8(%ecx)
; X86-X87-NEXT: movl %ebp, 4(%ecx)
-; X86-X87-NEXT: movl %esi, (%ecx)
+; X86-X87-NEXT: movl %edi, (%ecx)
; X86-X87-NEXT: andl $15, %eax
; X86-X87-NEXT: movb %al, 12(%ecx)
; X86-X87-NEXT: movl %ecx, %eax
diff --git a/llvm/test/CodeGen/X86/fshl.ll b/llvm/test/CodeGen/X86/fshl.ll
index 9da2640ea8392..64be3208f0f56 100644
--- a/llvm/test/CodeGen/X86/fshl.ll
+++ b/llvm/test/CodeGen/X86/fshl.ll
@@ -270,55 +270,54 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind {
; X86-FAST-NEXT: pushl %esi
; X86-FAST-NEXT: andl $-16, %esp
; X86-FAST-NEXT: subl $16, %esp
-; X86-FAST-NEXT: movl 24(%ebp), %edi
+; X86-FAST-NEXT: movl 24(%ebp), %eax
; X86-FAST-NEXT: movl 28(%ebp), %edx
-; X86-FAST-NEXT: movl 48(%ebp), %esi
+; X86-FAST-NEXT: movl 48(%ebp), %edi
; X86-FAST-NEXT: movl 56(%ebp), %ecx
; X86-FAST-NEXT: testb $64, %cl
-; X86-FAST-NEXT: movl 52(%ebp), %eax
+; X86-FAST-NEXT: movl 52(%ebp), %esi
; X86-FAST-NEXT: jne .LBB6_1
; X86-FAST-NEXT: # %bb.2:
+; X86-FAST-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-FAST-NEXT: movl %eax, %edi
+; X86-FAST-NEXT: movl 32(%ebp), %eax
; X86-FAST-NEXT: movl %esi, %ebx
-; X86-FAST-NEXT: movl %edi, %esi
-; X86-FAST-NEXT: movl 32(%ebp), %edi
-; X86-FAST-NEXT: movl %eax, (%esp) # 4-byte Spill
-; X86-FAST-NEXT: movl %edx, %eax
+; X86-FAST-NEXT: movl %edx, %esi
; X86-FAST-NEXT: movl 36(%ebp), %edx
; X86-FAST-NEXT: testb $32, %cl
; X86-FAST-NEXT: je .LBB6_5
; X86-FAST-NEXT: .LBB6_4:
-; X86-FAST-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-FAST-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-FAST-NEXT: movl %esi, %eax
-; X86-FAST-NEXT: movl (%esp), %esi # 4-byte Reload
+; X86-FAST-NEXT: movl %edi, %edx
+; X86-FAST-NEXT: movl %ebx, %edi
+; X86-FAST-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-FAST-NEXT: jmp .LBB6_6
; X86-FAST-NEXT: .LBB6_1:
-; X86-FAST-NEXT: movl 44(%ebp), %ebx
-; X86-FAST-NEXT: movl %ebx, (%esp) # 4-byte Spill
; X86-FAST-NEXT: movl 40(%ebp), %ebx
+; X86-FAST-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-FAST-NEXT: movl 44(%ebp), %ebx
; X86-FAST-NEXT: testb $32, %cl
; X86-FAST-NEXT: jne .LBB6_4
; X86-FAST-NEXT: .LBB6_5:
-; X86-FAST-NEXT: movl (%esp), %ebx # 4-byte Reload
; X86-FAST-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-FAST-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-FAST-NEXT: movl %esi, %edx
+; X86-FAST-NEXT: movl %eax, %esi
; X86-FAST-NEXT: .LBB6_6:
+; X86-FAST-NEXT: movl %edi, %eax
+; X86-FAST-NEXT: shldl %cl, %ebx, %eax
+; X86-FAST-NEXT: movl %edx, %ebx
+; X86-FAST-NEXT: shldl %cl, %edi, %ebx
; X86-FAST-NEXT: movl %esi, %edi
-; X86-FAST-NEXT: shldl %cl, %ebx, %edi
-; X86-FAST-NEXT: movl %eax, %edx
-; X86-FAST-NEXT: movl %eax, %ebx
-; X86-FAST-NEXT: shldl %cl, %esi, %ebx
-; X86-FAST-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-FAST-NEXT: movl %eax, %esi
-; X86-FAST-NEXT: shldl %cl, %edx, %esi
+; X86-FAST-NEXT: shldl %cl, %edx, %edi
; X86-FAST-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-FAST-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-FAST-NEXT: shldl %cl, %eax, %edx
-; X86-FAST-NEXT: movl 8(%ebp), %eax
-; X86-FAST-NEXT: movl %edx, 12(%eax)
-; X86-FAST-NEXT: movl %esi, 8(%eax)
-; X86-FAST-NEXT: movl %ebx, 4(%eax)
-; X86-FAST-NEXT: movl %edi, (%eax)
+; X86-FAST-NEXT: shldl %cl, %esi, %edx
+; X86-FAST-NEXT: movl 8(%ebp), %ecx
+; X86-FAST-NEXT: movl %edx, 12(%ecx)
+; X86-FAST-NEXT: movl %edi, 8(%ecx)
+; X86-FAST-NEXT: movl %ebx, 4(%ecx)
+; X86-FAST-NEXT: movl %eax, (%ecx)
+; X86-FAST-NEXT: movl %ecx, %eax
; X86-FAST-NEXT: leal -12(%ebp), %esp
; X86-FAST-NEXT: popl %esi
; X86-FAST-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/fshr.ll b/llvm/test/CodeGen/X86/fshr.ll
index c307833e488c9..6069ad719c085 100644
--- a/llvm/test/CodeGen/X86/fshr.ll
+++ b/llvm/test/CodeGen/X86/fshr.ll
@@ -319,81 +319,82 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind {
; X86-SLOW-NEXT: pushl %edi
; X86-SLOW-NEXT: pushl %esi
; X86-SLOW-NEXT: andl $-16, %esp
-; X86-SLOW-NEXT: subl $16, %esp
-; X86-SLOW-NEXT: movl 24(%ebp), %edx
+; X86-SLOW-NEXT: subl $32, %esp
+; X86-SLOW-NEXT: movl 24(%ebp), %eax
; X86-SLOW-NEXT: movl 28(%ebp), %esi
; X86-SLOW-NEXT: movl 48(%ebp), %edi
-; X86-SLOW-NEXT: movl 56(%ebp), %eax
-; X86-SLOW-NEXT: testb $64, %al
-; X86-SLOW-NEXT: movl 52(%ebp), %eax
+; X86-SLOW-NEXT: movl 56(%ebp), %ecx
+; X86-SLOW-NEXT: testb $64, %cl
+; X86-SLOW-NEXT: movl 52(%ebp), %ecx
+; X86-SLOW-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-SLOW-NEXT: je .LBB6_1
; X86-SLOW-NEXT: # %bb.2:
-; X86-SLOW-NEXT: movl %edi, (%esp) # 4-byte Spill
-; X86-SLOW-NEXT: movl %edx, %edi
-; X86-SLOW-NEXT: movl 32(%ebp), %edx
-; X86-SLOW-NEXT: movl %eax, %ecx
-; X86-SLOW-NEXT: movl %esi, %eax
+; X86-SLOW-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-SLOW-NEXT: movl %eax, %edi
+; X86-SLOW-NEXT: movl 32(%ebp), %eax
+; X86-SLOW-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-SLOW-NEXT: movl 36(%ebp), %esi
; X86-SLOW-NEXT: jmp .LBB6_3
; X86-SLOW-NEXT: .LBB6_1:
; X86-SLOW-NEXT: movl 40(%ebp), %ecx
-; X86-SLOW-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-SLOW-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-SLOW-NEXT: movl 44(%ebp), %ecx
; X86-SLOW-NEXT: .LBB6_3:
-; X86-SLOW-NEXT: movl 56(%ebp), %ebx
-; X86-SLOW-NEXT: testb $32, %bl
+; X86-SLOW-NEXT: movl 56(%ebp), %edx
+; X86-SLOW-NEXT: testb $32, %dl
; X86-SLOW-NEXT: je .LBB6_4
; X86-SLOW-NEXT: # %bb.5:
+; X86-SLOW-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-SLOW-NEXT: movl %ecx, %esi
; X86-SLOW-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-SLOW-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-SLOW-NEXT: movl %ecx, %ebx
; X86-SLOW-NEXT: jmp .LBB6_6
; X86-SLOW-NEXT: .LBB6_4:
-; X86-SLOW-NEXT: movl %edx, %esi
+; X86-SLOW-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-SLOW-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-SLOW-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-SLOW-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-SLOW-NEXT: movl %ecx, %edi
-; X86-SLOW-NEXT: movl (%esp), %ebx # 4-byte Reload
+; X86-SLOW-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-SLOW-NEXT: .LBB6_6:
; X86-SLOW-NEXT: movl 56(%ebp), %ecx
-; X86-SLOW-NEXT: shrl %cl, %ebx
+; X86-SLOW-NEXT: shrl %cl, %esi
; X86-SLOW-NEXT: movl %ecx, %edx
+; X86-SLOW-NEXT: movl %ecx, %ebx
; X86-SLOW-NEXT: notb %dl
; X86-SLOW-NEXT: movl %edi, %eax
; X86-SLOW-NEXT: addl %edi, %edi
; X86-SLOW-NEXT: movl %edx, %ecx
; X86-SLOW-NEXT: shll %cl, %edi
-; X86-SLOW-NEXT: orl %ebx, %edi
-; X86-SLOW-NEXT: movl %edi, (%esp) # 4-byte Spill
-; X86-SLOW-NEXT: movl 56(%ebp), %ecx
-; X86-SLOW-NEXT: # kill: def $cl killed $cl killed $ecx
+; X86-SLOW-NEXT: orl %esi, %edi
+; X86-SLOW-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-SLOW-NEXT: movl %ebx, %ecx
; X86-SLOW-NEXT: shrl %cl, %eax
-; X86-SLOW-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-SLOW-NEXT: leal (%edi,%edi), %ebx
+; X86-SLOW-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; X86-SLOW-NEXT: leal (%ebx,%ebx), %esi
; X86-SLOW-NEXT: movl %edx, %ecx
-; X86-SLOW-NEXT: shll %cl, %ebx
-; X86-SLOW-NEXT: orl %eax, %ebx
+; X86-SLOW-NEXT: shll %cl, %esi
+; X86-SLOW-NEXT: orl %eax, %esi
; X86-SLOW-NEXT: movl 56(%ebp), %ecx
; X86-SLOW-NEXT: # kill: def $cl killed $cl killed $ecx
-; X86-SLOW-NEXT: shrl %cl, %edi
-; X86-SLOW-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-SLOW-NEXT: shrl %cl, %ebx
; X86-SLOW-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-SLOW-NEXT: leal (%eax,%eax), %edi
; X86-SLOW-NEXT: movl %edx, %ecx
; X86-SLOW-NEXT: shll %cl, %edi
-; X86-SLOW-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
+; X86-SLOW-NEXT: orl %ebx, %edi
; X86-SLOW-NEXT: movl 56(%ebp), %ecx
; X86-SLOW-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-SLOW-NEXT: shrl %cl, %eax
-; X86-SLOW-NEXT: addl %esi, %esi
+; X86-SLOW-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; X86-SLOW-NEXT: addl %ebx, %ebx
; X86-SLOW-NEXT: movl %edx, %ecx
-; X86-SLOW-NEXT: shll %cl, %esi
-; X86-SLOW-NEXT: orl %eax, %esi
+; X86-SLOW-NEXT: shll %cl, %ebx
+; X86-SLOW-NEXT: orl %eax, %ebx
; X86-SLOW-NEXT: movl 8(%ebp), %eax
-; X86-SLOW-NEXT: movl %esi, 12(%eax)
+; X86-SLOW-NEXT: movl %ebx, 12(%eax)
; X86-SLOW-NEXT: movl %edi, 8(%eax)
-; X86-SLOW-NEXT: movl %ebx, 4(%eax)
-; X86-SLOW-NEXT: movl (%esp), %ecx # 4-byte Reload
+; X86-SLOW-NEXT: movl %esi, 4(%eax)
+; X86-SLOW-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-SLOW-NEXT: movl %ecx, (%eax)
; X86-SLOW-NEXT: leal -12(%ebp), %esp
; X86-SLOW-NEXT: popl %esi
diff --git a/llvm/test/CodeGen/X86/gpr-to-mask.ll b/llvm/test/CodeGen/X86/gpr-to-mask.ll
index d1513b584887f..b661ec53f7fd6 100644
--- a/llvm/test/CodeGen/X86/gpr-to-mask.ll
+++ b/llvm/test/CodeGen/X86/gpr-to-mask.ll
@@ -120,19 +120,19 @@ define void @test_load_add(i1 %cond, ptr %fptr, ptr %iptr1, ptr %iptr2, float %f
; X86-32: # %bb.0: # %entry
; X86-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X86-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-32-NEXT: testb $1, {{[0-9]+}}(%esp)
; X86-32-NEXT: je .LBB2_2
; X86-32-NEXT: # %bb.1: # %if
-; X86-32-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-32-NEXT: movzbl (%edx), %edx
-; X86-32-NEXT: xorb (%ecx), %dl
+; X86-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-32-NEXT: movzbl (%ecx), %ecx
+; X86-32-NEXT: xorb (%edx), %cl
; X86-32-NEXT: jmp .LBB2_3
; X86-32-NEXT: .LBB2_2: # %else
-; X86-32-NEXT: movzbl (%ecx), %edx
+; X86-32-NEXT: movzbl (%edx), %ecx
; X86-32-NEXT: .LBB2_3: # %exit
-; X86-32-NEXT: kmovd %edx, %k1
+; X86-32-NEXT: kmovd %ecx, %k1
; X86-32-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
; X86-32-NEXT: vmovss %xmm0, (%eax)
; X86-32-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/i128-udiv.ll b/llvm/test/CodeGen/X86/i128-udiv.ll
index 543e9d13c50bf..a8efeb3977ff8 100644
--- a/llvm/test/CodeGen/X86/i128-udiv.ll
+++ b/llvm/test/CodeGen/X86/i128-udiv.ll
@@ -45,18 +45,18 @@ define i128 @test2(i128 %x) nounwind {
; X86-NEXT: andl $-16, %esp
; X86-NEXT: addl $-128, %esp
; X86-NEXT: movl 32(%ebp), %esi
-; X86-NEXT: movl 36(%ebp), %edi
+; X86-NEXT: movl 36(%ebp), %ebx
; X86-NEXT: movl 28(%ebp), %ecx
-; X86-NEXT: testl %edi, %edi
+; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: jne .LBB1_1
; X86-NEXT: # %bb.2: # %_udiv-special-cases
-; X86-NEXT: bsrl %esi, %ebx
-; X86-NEXT: xorl $31, %ebx
-; X86-NEXT: orl $32, %ebx
+; X86-NEXT: bsrl %esi, %edi
+; X86-NEXT: xorl $31, %edi
+; X86-NEXT: orl $32, %edi
; X86-NEXT: jmp .LBB1_3
; X86-NEXT: .LBB1_1:
-; X86-NEXT: bsrl %edi, %ebx
-; X86-NEXT: xorl $31, %ebx
+; X86-NEXT: bsrl %ebx, %edi
+; X86-NEXT: xorl $31, %edi
; X86-NEXT: .LBB1_3: # %_udiv-special-cases
; X86-NEXT: movl 24(%ebp), %edx
; X86-NEXT: testl %ecx, %ecx
@@ -70,82 +70,84 @@ define i128 @test2(i128 %x) nounwind {
; X86-NEXT: bsrl %ecx, %eax
; X86-NEXT: xorl $31, %eax
; X86-NEXT: .LBB1_6: # %_udiv-special-cases
-; X86-NEXT: orl %edi, %ecx
+; X86-NEXT: orl %ebx, %ecx
; X86-NEXT: orl %esi, %edx
-; X86-NEXT: orl %edi, %esi
+; X86-NEXT: orl %ebx, %esi
; X86-NEXT: jne .LBB1_8
; X86-NEXT: # %bb.7: # %_udiv-special-cases
; X86-NEXT: orl $64, %eax
-; X86-NEXT: movl %eax, %ebx
+; X86-NEXT: movl %eax, %edi
; X86-NEXT: .LBB1_8: # %_udiv-special-cases
-; X86-NEXT: negl %ebx
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: negl %edi
; X86-NEXT: movl $0, %esi
; X86-NEXT: sbbl %esi, %esi
; X86-NEXT: movl $0, %ebx
; X86-NEXT: sbbl %ebx, %ebx
-; X86-NEXT: movl $0, %edi
-; X86-NEXT: sbbl %edi, %edi
+; X86-NEXT: movl $0, %eax
+; X86-NEXT: sbbl %eax, %eax
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB1_9
; X86-NEXT: # %bb.10: # %select.false.sink
-; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: xorl %edx, %edx
; X86-NEXT: movl $127, %ecx
-; X86-NEXT: cmpl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
+; X86-NEXT: cmpl %edi, %ecx
; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %esi, %ecx
; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %ebx, %ecx
-; X86-NEXT: sbbl %edi, %eax
+; X86-NEXT: sbbl %eax, %edx
; X86-NEXT: setb %cl
; X86-NEXT: .LBB1_11: # %select.end
-; X86-NEXT: movl %ebx, %esi
+; X86-NEXT: movl %ebx, %edi
; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: movl $0, (%esp) # 4-byte Folded Spill
+; X86-NEXT: xorl %esi, %esi
; X86-NEXT: testb %cl, %cl
-; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl $0, %edi
+; X86-NEXT: movl $0, %edx
; X86-NEXT: movl $0, %ecx
+; X86-NEXT: movl $0, (%esp) # 4-byte Folded Spill
+; X86-NEXT: movl 28(%ebp), %ebx
; X86-NEXT: jne .LBB1_13
; X86-NEXT: # %bb.12: # %select.end
-; X86-NEXT: movl 28(%ebp), %ebx
+; X86-NEXT: movl %ebx, %esi
+; X86-NEXT: movl 24(%ebp), %edx
+; X86-NEXT: movl 32(%ebp), %ecx
+; X86-NEXT: movl 36(%ebp), %ebx
; X86-NEXT: movl %ebx, (%esp) # 4-byte Spill
-; X86-NEXT: movl 24(%ebp), %ecx
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 32(%ebp), %edi
-; X86-NEXT: movl 36(%ebp), %ecx
+; X86-NEXT: movl 28(%ebp), %ebx
; X86-NEXT: .LBB1_13: # %select.end
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jne .LBB1_14
; X86-NEXT: # %bb.20: # %select.end
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl %ecx, %ebx
; X86-NEXT: xorl $127, %ecx
-; X86-NEXT: orl %esi, %ecx
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %edi, %ecx
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: orl %ecx, %edx
-; X86-NEXT: movl (%esp), %ecx # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl 32(%ebp), %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: je .LBB1_21
; X86-NEXT: # %bb.18: # %udiv-bb1
; X86-NEXT: movl 24(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 28(%ebp), %eax
-; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 32(%ebp), %eax
-; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
; X86-NEXT: movl 36(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %ebx, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorb $127, %cl
; X86-NEXT: movl %ecx, %eax
; X86-NEXT: shrb $3, %al
@@ -153,19 +155,19 @@ define i128 @test2(i128 %x) nounwind {
; X86-NEXT: negb %al
; X86-NEXT: movsbl %al, %eax
; X86-NEXT: movl 120(%esp,%eax), %edx
-; X86-NEXT: movl 124(%esp,%eax), %edi
-; X86-NEXT: shldl %cl, %edx, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 112(%esp,%eax), %edi
+; X86-NEXT: movl 124(%esp,%eax), %ebx
+; X86-NEXT: shldl %cl, %edx, %ebx
+; X86-NEXT: movl %ebx, (%esp) # 4-byte Spill
+; X86-NEXT: movl 112(%esp,%eax), %esi
; X86-NEXT: movl 116(%esp,%eax), %eax
; X86-NEXT: shldl %cl, %eax, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl %cl, %edi, %eax
-; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
-; X86-NEXT: shll %cl, %edi
+; X86-NEXT: shldl %cl, %esi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shll %cl, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: addl $1, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: addl $1, %ebx
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
@@ -189,15 +191,15 @@ define i128 @test2(i128 %x) nounwind {
; X86-NEXT: andb $12, %al
; X86-NEXT: movzbl %al, %esi
; X86-NEXT: movl 76(%esp,%esi), %eax
-; X86-NEXT: movl 72(%esp,%esi), %edi
-; X86-NEXT: movl %edi, %edx
+; X86-NEXT: movl 72(%esp,%esi), %ebx
+; X86-NEXT: movl %ebx, %edx
; X86-NEXT: shrdl %cl, %eax, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 64(%esp,%esi), %edx
; X86-NEXT: movl 68(%esp,%esi), %esi
-; X86-NEXT: movl %esi, %ebx
-; X86-NEXT: shrdl %cl, %edi, %ebx
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: shrdl %cl, %ebx, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: shrl %cl, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: # kill: def $cl killed $cl killed $ecx
@@ -211,95 +213,97 @@ define i128 @test2(i128 %x) nounwind {
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl (%esp), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB1_16: # %udiv-do-while
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X86-NEXT: shldl $1, %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: shldl $1, %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: shldl $1, %esi, %ebx
+; X86-NEXT: shldl $1, %esi, %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: shldl $1, %ecx, %esi
+; X86-NEXT: shldl $1, %edx, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; X86-NEXT: shldl $1, %ebx, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shldl $1, %eax, %edi
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, (%esp) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: orl %edx, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl (%esp), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %eax
-; X86-NEXT: orl %edx, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shldl $1, %eax, %edi
-; X86-NEXT: orl %edx, %edi
-; X86-NEXT: movl %edi, (%esp) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: addl %eax, %eax
-; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %edx, %ebx
+; X86-NEXT: orl %edi, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; X86-NEXT: shldl $1, %ebx, %edx
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: addl %ebx, %ebx
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $-1, %eax
-; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: movl $-1, %edx
+; X86-NEXT: cmpl %ecx, %edx
; X86-NEXT: movl $-1, %ecx
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: sbbl %esi, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %ebx, %ecx
+; X86-NEXT: sbbl %eax, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: sbbl %edx, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: sbbl %edi, %ecx
; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: andl $1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: andl $1, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl %ecx, %esi
-; X86-NEXT: movl $-1, %eax
-; X86-NEXT: andl %eax, %esi
-; X86-NEXT: movl $-4, %eax
-; X86-NEXT: andl %eax, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: subl %ecx, %ebx
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edx, %ecx
-; X86-NEXT: sbbl %esi, %ecx
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl $-1, %edx
+; X86-NEXT: andl %edx, %esi
+; X86-NEXT: movl $-4, %edx
+; X86-NEXT: andl %edx, %ecx
+; X86-NEXT: movl (%esp), %edx # 4-byte Reload
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: sbbl %esi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: addl $-1, %esi
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: adcl $-1, %edx
; X86-NEXT: adcl $-1, %edi
-; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: orl %edi, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl $-1, %eax
+; X86-NEXT: adcl $-1, %ebx
+; X86-NEXT: movl %edi, %ecx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %ebx, %ecx
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edx, %esi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %eax, %esi
; X86-NEXT: orl %ecx, %esi
; X86-NEXT: jne .LBB1_16
; X86-NEXT: .LBB1_17: # %udiv-loop-exit
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %edx
-; X86-NEXT: movl (%esp), %ecx # 4-byte Reload
-; X86-NEXT: shldl $1, %ecx, %edi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl %edx, (%esp) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: shldl $1, %eax, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: leal (%esi,%eax,2), %esi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $1, %edx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: leal (%eax,%edx,2), %edx
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: .LBB1_21: # %udiv-end
-; X86-NEXT: movl %esi, (%eax)
-; X86-NEXT: movl %ecx, 4(%eax)
-; X86-NEXT: movl %edi, 8(%eax)
-; X86-NEXT: movl %edx, 12(%eax)
+; X86-NEXT: movl %edx, (%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl %edx, 4(%eax)
+; X86-NEXT: movl %ecx, 8(%eax)
+; X86-NEXT: movl (%esp), %ecx # 4-byte Reload
+; X86-NEXT: movl %ecx, 12(%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
@@ -310,12 +314,12 @@ define i128 @test2(i128 %x) nounwind {
; X86-NEXT: movb $1, %cl
; X86-NEXT: jmp .LBB1_11
; X86-NEXT: .LBB1_19:
+; X86-NEXT: movl (%esp), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB1_17
; X86-NEXT: .LBB1_14:
-; X86-NEXT: movl (%esp), %ecx # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: jmp .LBB1_21
;
; X64-LABEL: test2:
@@ -360,9 +364,9 @@ define i128 @test3(i128 %x) nounwind {
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $144, %esp
; X86-NEXT: movl 32(%ebp), %edi
-; X86-NEXT: movl 36(%ebp), %edx
-; X86-NEXT: movl 28(%ebp), %esi
-; X86-NEXT: testl %edx, %edx
+; X86-NEXT: movl 36(%ebp), %eax
+; X86-NEXT: movl 28(%ebp), %ecx
+; X86-NEXT: testl %eax, %eax
; X86-NEXT: jne .LBB2_1
; X86-NEXT: # %bb.2: # %_udiv-special-cases
; X86-NEXT: bsrl %edi, %ebx
@@ -370,123 +374,119 @@ define i128 @test3(i128 %x) nounwind {
; X86-NEXT: orl $32, %ebx
; X86-NEXT: jmp .LBB2_3
; X86-NEXT: .LBB2_1:
-; X86-NEXT: bsrl %edx, %ebx
+; X86-NEXT: bsrl %eax, %ebx
; X86-NEXT: xorl $31, %ebx
; X86-NEXT: .LBB2_3: # %_udiv-special-cases
-; X86-NEXT: movl 24(%ebp), %eax
-; X86-NEXT: testl %esi, %esi
+; X86-NEXT: movl 24(%ebp), %esi
+; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: jne .LBB2_4
; X86-NEXT: # %bb.5: # %_udiv-special-cases
-; X86-NEXT: bsrl %eax, %ecx
-; X86-NEXT: xorl $31, %ecx
-; X86-NEXT: orl $32, %ecx
+; X86-NEXT: bsrl %esi, %edx
+; X86-NEXT: xorl $31, %edx
+; X86-NEXT: orl $32, %edx
; X86-NEXT: jmp .LBB2_6
; X86-NEXT: .LBB2_4:
-; X86-NEXT: bsrl %esi, %ecx
-; X86-NEXT: xorl $31, %ecx
+; X86-NEXT: bsrl %ecx, %edx
+; X86-NEXT: xorl $31, %edx
; X86-NEXT: .LBB2_6: # %_udiv-special-cases
-; X86-NEXT: orl %edx, %esi
-; X86-NEXT: orl %edi, %eax
-; X86-NEXT: orl %edx, %edi
+; X86-NEXT: orl %eax, %ecx
+; X86-NEXT: orl %edi, %esi
+; X86-NEXT: orl %eax, %edi
; X86-NEXT: jne .LBB2_8
; X86-NEXT: # %bb.7: # %_udiv-special-cases
-; X86-NEXT: orl $64, %ecx
-; X86-NEXT: movl %ecx, %ebx
+; X86-NEXT: orl $64, %edx
+; X86-NEXT: movl %edx, %ebx
; X86-NEXT: .LBB2_8: # %_udiv-special-cases
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: negl %ebx
-; X86-NEXT: movl $0, %ecx
-; X86-NEXT: sbbl %ecx, %ecx
+; X86-NEXT: movl $0, %eax
+; X86-NEXT: sbbl %eax, %eax
; X86-NEXT: movl $0, %edx
; X86-NEXT: sbbl %edx, %edx
-; X86-NEXT: movl %ebx, %edi
-; X86-NEXT: movl $0, %ebx
-; X86-NEXT: sbbl %ebx, %ebx
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %edi
+; X86-NEXT: sbbl %edi, %edi
+; X86-NEXT: orl %ecx, %esi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB2_9
; X86-NEXT: # %bb.10: # %select.false.sink
-; X86-NEXT: movl $127, %eax
-; X86-NEXT: cmpl %edi, %eax
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: movl %ecx, %edi
-; X86-NEXT: sbbl %ecx, %eax
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: sbbl %edx, %eax
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: sbbl %ebx, %eax
+; X86-NEXT: movl $127, %ecx
+; X86-NEXT: cmpl %ebx, %ecx
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: sbbl %eax, %ecx
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: sbbl %edx, %ecx
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: sbbl %edi, %ecx
; X86-NEXT: setb %cl
; X86-NEXT: .LBB2_11: # %select.end
-; X86-NEXT: movl %ebx, %esi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: testb %cl, %cl
-; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, %ecx
-; X86-NEXT: movl $0, %ebx
+; X86-NEXT: movl $0, %esi
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl 32(%ebp), %edi
; X86-NEXT: jne .LBB2_13
; X86-NEXT: # %bb.12: # %select.end
; X86-NEXT: movl 28(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 24(%ebp), %ecx
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 32(%ebp), %ecx
-; X86-NEXT: movl 36(%ebp), %ebx
+; X86-NEXT: movl %edi, %esi
+; X86-NEXT: movl 36(%ebp), %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 32(%ebp), %edi
; X86-NEXT: .LBB2_13: # %select.end
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jne .LBB2_14
; X86-NEXT: # %bb.20: # %select.end
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: xorl $127, %ecx
-; X86-NEXT: orl %edx, %ecx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edi, %edx
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: movl %ebx, %edx
+; X86-NEXT: xorl $127, %edx
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: orl %esi, %edx
-; X86-NEXT: orl %ecx, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload
+; X86-NEXT: orl %edx, %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: je .LBB2_21
; X86-NEXT: # %bb.18: # %udiv-bb1
; X86-NEXT: movl 24(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 28(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 32(%ebp), %ebx
-; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 36(%ebp), %ebx
-; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %edi, {{[0-9]+}}(%esp)
+; X86-NEXT: movl 36(%ebp), %eax
+; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: xorb $127, %cl
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: shrb $3, %al
-; X86-NEXT: andb $12, %al
-; X86-NEXT: negb %al
-; X86-NEXT: movsbl %al, %eax
-; X86-NEXT: movl 136(%esp,%eax), %edx
-; X86-NEXT: movl 140(%esp,%eax), %esi
-; X86-NEXT: shldl %cl, %edx, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 128(%esp,%eax), %esi
-; X86-NEXT: movl 132(%esp,%eax), %eax
-; X86-NEXT: shldl %cl, %eax, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: shrb $3, %dl
+; X86-NEXT: andb $12, %dl
+; X86-NEXT: negb %dl
+; X86-NEXT: movsbl %dl, %edx
+; X86-NEXT: movl 136(%esp,%edx), %esi
+; X86-NEXT: movl 140(%esp,%edx), %eax
; X86-NEXT: shldl %cl, %esi, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shll %cl, %esi
+; X86-NEXT: movl 128(%esp,%edx), %edi
+; X86-NEXT: movl 132(%esp,%edx), %eax
+; X86-NEXT: shldl %cl, %eax, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: addl $1, %ebx
-; X86-NEXT: adcl $0, %edi
+; X86-NEXT: shldl %cl, %edi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shll %cl, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: addl $1, %ebx
+; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jb .LBB2_19
; X86-NEXT: # %bb.15: # %udiv-preheader
-; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: movl 24(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 28(%ebp), %eax
@@ -499,133 +499,139 @@ define i128 @test3(i128 %x) nounwind {
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: movl %ebx, %eax
; X86-NEXT: shrb $3, %al
; X86-NEXT: andb $12, %al
; X86-NEXT: movzbl %al, %edx
; X86-NEXT: movl 92(%esp,%edx), %edi
; X86-NEXT: movl 88(%esp,%edx), %esi
; X86-NEXT: movl %esi, %eax
+; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: shrdl %cl, %edi, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 80(%esp,%edx), %eax
-; X86-NEXT: movl 84(%esp,%edx), %ebx
-; X86-NEXT: movl %ebx, %edx
-; X86-NEXT: shrdl %cl, %esi, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ebx, %ecx
+; X86-NEXT: movl 80(%esp,%edx), %ebx
+; X86-NEXT: movl 84(%esp,%edx), %edx
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: shrdl %cl, %esi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: shrl %cl, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: # kill: def $cl killed $cl killed $ecx
-; X86-NEXT: shrdl %cl, %ebx, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $-3, %eax
-; X86-NEXT: addl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $-1, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $-5, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $-1, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrdl %cl, %edx, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $-3, %ecx
+; X86-NEXT: addl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $-1, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $-5, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $-1, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB2_16: # %udiv-do-while
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shldl $1, %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: shldl $1, %ebx, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %ebx
-; X86-NEXT: shldl $1, %ecx, %edi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $1, %edx, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: orl %eax, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl $1, %esi, %ecx
-; X86-NEXT: orl %eax, %ecx
+; X86-NEXT: shldl $1, %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %eax
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: shldl $1, %edi, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: orl %edx, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl $1, %edx, %esi
-; X86-NEXT: orl %eax, %esi
+; X86-NEXT: shldl $1, %esi, %edi
+; X86-NEXT: orl %edx, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: shldl $1, %ecx, %esi
+; X86-NEXT: orl %edx, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: addl %edx, %edx
-; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: cmpl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; X86-NEXT: addl %ecx, %ecx
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: cmpl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: sbbl %eax, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: sbbl %edx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
+; X86-NEXT: sbbl %ebx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %edx
-; X86-NEXT: andl $1, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: andl $1, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, %edi
; X86-NEXT: movl $-1, %esi
; X86-NEXT: andl %esi, %edi
; X86-NEXT: movl %ecx, %esi
-; X86-NEXT: movl $-5, %edx
-; X86-NEXT: andl %edx, %esi
-; X86-NEXT: movl $-3, %edx
-; X86-NEXT: andl %edx, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: subl %ecx, %ebx
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $-5, %ebx
+; X86-NEXT: andl %ebx, %esi
+; X86-NEXT: movl $-3, %ebx
+; X86-NEXT: andl %ebx, %ecx
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: sbbl %edi, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: sbbl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: sbbl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: sbbl %edi, %eax
+; X86-NEXT: movl %eax, %edi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: addl $-1, %esi
-; X86-NEXT: adcl $-1, %eax
+; X86-NEXT: adcl $-1, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: adcl $-1, %ebx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: adcl $-1, %edi
-; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edi, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl $-1, %eax
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %eax, %ecx
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: orl %ebx, %esi
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: orl %ecx, %esi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: jne .LBB2_16
; X86-NEXT: .LBB2_17: # %udiv-loop-exit
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X86-NEXT: shldl $1, %ecx, %ebx
-; X86-NEXT: shldl $1, %esi, %ecx
-; X86-NEXT: shldl $1, %edx, %esi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $1, %edx, %ecx
+; X86-NEXT: shldl $1, %esi, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: leal (%eax,%edx,2), %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %eax, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ecx, %edi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: leal (%ecx,%eax,2), %ecx
; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: movl %edi, %esi
; X86-NEXT: .LBB2_21: # %udiv-end
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl %ecx, (%eax)
-; X86-NEXT: movl %esi, 4(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl %ecx, 4(%eax)
; X86-NEXT: movl %edx, 8(%eax)
-; X86-NEXT: movl %ebx, 12(%eax)
+; X86-NEXT: movl %esi, 12(%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
@@ -633,18 +639,16 @@ define i128 @test3(i128 %x) nounwind {
; X86-NEXT: popl %ebp
; X86-NEXT: retl $4
; X86-NEXT: .LBB2_9:
-; X86-NEXT: movl %ecx, %edi
; X86-NEXT: movb $1, %cl
; X86-NEXT: jmp .LBB2_11
; X86-NEXT: .LBB2_19:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB2_17
; X86-NEXT: .LBB2_14:
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: jmp .LBB2_21
;
; X64-LABEL: test3:
@@ -689,95 +693,94 @@ define i128 @div_by_7(i128 %x) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $144, %esp
-; X86-NEXT: movl 32(%ebp), %edi
-; X86-NEXT: movl 36(%ebp), %ebx
-; X86-NEXT: movl 28(%ebp), %edx
-; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: movl 32(%ebp), %ebx
+; X86-NEXT: movl 36(%ebp), %esi
+; X86-NEXT: movl 28(%ebp), %eax
+; X86-NEXT: testl %esi, %esi
; X86-NEXT: jne .LBB3_1
; X86-NEXT: # %bb.2: # %entry_udiv-special-cases
-; X86-NEXT: bsrl %edi, %esi
-; X86-NEXT: xorl $31, %esi
-; X86-NEXT: orl $32, %esi
+; X86-NEXT: bsrl %ebx, %edx
+; X86-NEXT: xorl $31, %edx
+; X86-NEXT: orl $32, %edx
; X86-NEXT: jmp .LBB3_3
; X86-NEXT: .LBB3_1:
-; X86-NEXT: bsrl %ebx, %esi
-; X86-NEXT: xorl $31, %esi
+; X86-NEXT: bsrl %esi, %edx
+; X86-NEXT: xorl $31, %edx
; X86-NEXT: .LBB3_3: # %entry_udiv-special-cases
-; X86-NEXT: movl 24(%ebp), %eax
-; X86-NEXT: testl %edx, %edx
+; X86-NEXT: movl 24(%ebp), %edi
+; X86-NEXT: testl %eax, %eax
; X86-NEXT: jne .LBB3_4
; X86-NEXT: # %bb.5: # %entry_udiv-special-cases
-; X86-NEXT: bsrl %eax, %ecx
+; X86-NEXT: bsrl %edi, %ecx
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: orl $32, %ecx
; X86-NEXT: jmp .LBB3_6
; X86-NEXT: .LBB3_4:
-; X86-NEXT: bsrl %edx, %ecx
+; X86-NEXT: bsrl %eax, %ecx
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: .LBB3_6: # %entry_udiv-special-cases
-; X86-NEXT: orl %ebx, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edi, %eax
+; X86-NEXT: orl %esi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: orl %ebx, %edi
+; X86-NEXT: orl %esi, %ebx
; X86-NEXT: jne .LBB3_8
; X86-NEXT: # %bb.7: # %entry_udiv-special-cases
; X86-NEXT: orl $64, %ecx
-; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: .LBB3_8: # %entry_udiv-special-cases
; X86-NEXT: movl $125, %ebx
-; X86-NEXT: subl %esi, %ebx
-; X86-NEXT: movl $0, %edx
-; X86-NEXT: sbbl %edx, %edx
+; X86-NEXT: subl %edx, %ebx
; X86-NEXT: movl $0, %esi
; X86-NEXT: sbbl %esi, %esi
-; X86-NEXT: movl $0, %edi
-; X86-NEXT: sbbl %edi, %edi
-; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %edx
+; X86-NEXT: sbbl %edx, %edx
+; X86-NEXT: movl $0, %eax
+; X86-NEXT: sbbl %eax, %eax
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB3_9
; X86-NEXT: # %bb.10: # %select.false.sink
-; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: xorl %edi, %edi
; X86-NEXT: movl $127, %ecx
; X86-NEXT: cmpl %ebx, %ecx
; X86-NEXT: movl $0, %ecx
-; X86-NEXT: sbbl %edx, %ecx
-; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %esi, %ecx
-; X86-NEXT: sbbl %edi, %eax
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: sbbl %edx, %ecx
+; X86-NEXT: sbbl %eax, %edi
; X86-NEXT: setb %cl
; X86-NEXT: .LBB3_11: # %select.end
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: xorl %esi, %esi
; X86-NEXT: testb %cl, %cl
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, %ecx
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jne .LBB3_13
; X86-NEXT: # %bb.12: # %select.end
-; X86-NEXT: movl 28(%ebp), %edx
+; X86-NEXT: movl 28(%ebp), %esi
; X86-NEXT: movl 24(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 32(%ebp), %ecx
-; X86-NEXT: movl 36(%ebp), %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: .LBB3_13: # %select.end
+; X86-NEXT: movl 36(%ebp), %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: .LBB3_13: # %select.end
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: jne .LBB3_14
; X86-NEXT: # %bb.20: # %select.end
; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: xorl $127, %ecx
-; X86-NEXT: orl %esi, %ecx
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: movl %esi, %edx
-; X86-NEXT: orl %edi, %edx
+; X86-NEXT: orl %edx, %ecx
+; X86-NEXT: movl %edi, %edx
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl 36(%ebp), %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: je .LBB3_21
; X86-NEXT: # %bb.18: # %udiv-bb1
; X86-NEXT: movl 24(%ebp), %eax
@@ -786,8 +789,7 @@ define i128 @div_by_7(i128 %x) nounwind {
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 32(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
@@ -800,20 +802,20 @@ define i128 @div_by_7(i128 %x) nounwind {
; X86-NEXT: negb %al
; X86-NEXT: movsbl %al, %eax
; X86-NEXT: movl 136(%esp,%eax), %edx
-; X86-NEXT: movl 140(%esp,%eax), %edi
-; X86-NEXT: shldl %cl, %edx, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 128(%esp,%eax), %edi
+; X86-NEXT: movl 140(%esp,%eax), %esi
+; X86-NEXT: shldl %cl, %edx, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 128(%esp,%eax), %esi
; X86-NEXT: movl 132(%esp,%eax), %eax
; X86-NEXT: shldl %cl, %eax, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl %cl, %edi, %eax
+; X86-NEXT: shldl %cl, %esi, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shll %cl, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: addl $1, %ebx
-; X86-NEXT: adcl $0, %esi
+; X86-NEXT: shll %cl, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: addl $1, %ebx
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jb .LBB3_19
@@ -835,39 +837,39 @@ define i128 @div_by_7(i128 %x) nounwind {
; X86-NEXT: shrb $3, %al
; X86-NEXT: andb $12, %al
; X86-NEXT: movzbl %al, %edi
-; X86-NEXT: movl 92(%esp,%edi), %eax
+; X86-NEXT: movl 92(%esp,%edi), %esi
; X86-NEXT: movl 88(%esp,%edi), %ebx
-; X86-NEXT: movl %ebx, %esi
-; X86-NEXT: shrdl %cl, %eax, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 80(%esp,%edi), %esi
-; X86-NEXT: movl 84(%esp,%edi), %edi
-; X86-NEXT: movl %edi, %edx
-; X86-NEXT: shrdl %cl, %ebx, %edx
+; X86-NEXT: movl %ebx, %edx
+; X86-NEXT: shrdl %cl, %esi, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shrl %cl, %eax
+; X86-NEXT: movl 80(%esp,%edi), %edx
+; X86-NEXT: movl 84(%esp,%edi), %edi
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: shrdl %cl, %ebx, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrl %cl, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: # kill: def $cl killed $cl killed $ecx
-; X86-NEXT: shrdl %cl, %edi, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $7, %eax
-; X86-NEXT: addl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrdl %cl, %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $7, %ecx
+; X86-NEXT: addl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB3_16: # %udiv-do-while
@@ -876,76 +878,78 @@ define i128 @div_by_7(i128 %x) nounwind {
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: shldl $1, %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %ebx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edx, %edi
-; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: shldl $1, %ecx, %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %esi, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shldl $1, %eax, %ecx
-; X86-NEXT: orl %esi, %ecx
+; X86-NEXT: shldl $1, %eax, %esi
+; X86-NEXT: shldl $1, %edx, %eax
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $1, %edx, %ecx
+; X86-NEXT: orl %edi, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shldl $1, %ecx, %eax
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl %ecx, %ecx
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; X86-NEXT: cmpl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %edi, %ecx
+; X86-NEXT: sbbl %esi, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl %ebx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: andl $1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl $7, %eax
-; X86-NEXT: andl %eax, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: andl $1, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sbbl $0, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl $7, %edx
+; X86-NEXT: andl %edx, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sbbl $0, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: sbbl $0, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: sbbl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: addl $-1, %ebx
; X86-NEXT: adcl $-1, %edi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: adcl $-1, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl $-1, %eax
; X86-NEXT: adcl $-1, %esi
; X86-NEXT: movl %edi, %ecx
; X86-NEXT: orl %esi, %ecx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edx, %ebx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %eax, %ebx
; X86-NEXT: orl %ecx, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: jne .LBB3_16
; X86-NEXT: .LBB3_17: # %udiv-loop-exit
-; X86-NEXT: shldl $1, %ecx, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: shldl $1, %edx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: leal (%esi,%eax,2), %edi
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: leal (%edx,%eax,2), %edx
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: .LBB3_21: # %udiv-end
-; X86-NEXT: movl %edi, (%eax)
+; X86-NEXT: movl %edx, (%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 4(%eax)
; X86-NEXT: movl %ecx, 8(%eax)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
@@ -961,13 +965,12 @@ define i128 @div_by_7(i128 %x) nounwind {
; X86-NEXT: jmp .LBB3_11
; X86-NEXT: .LBB3_19:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB3_17
; X86-NEXT: .LBB3_14:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: jmp .LBB3_21
;
; X64-LABEL: div_by_7:
@@ -1015,95 +1018,94 @@ define i128 @div_by_11(i128 %x) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $144, %esp
-; X86-NEXT: movl 32(%ebp), %edi
-; X86-NEXT: movl 36(%ebp), %ebx
-; X86-NEXT: movl 28(%ebp), %edx
-; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: movl 32(%ebp), %ebx
+; X86-NEXT: movl 36(%ebp), %esi
+; X86-NEXT: movl 28(%ebp), %eax
+; X86-NEXT: testl %esi, %esi
; X86-NEXT: jne .LBB4_1
; X86-NEXT: # %bb.2: # %_udiv-special-cases
-; X86-NEXT: bsrl %edi, %esi
-; X86-NEXT: xorl $31, %esi
-; X86-NEXT: orl $32, %esi
+; X86-NEXT: bsrl %ebx, %edx
+; X86-NEXT: xorl $31, %edx
+; X86-NEXT: orl $32, %edx
; X86-NEXT: jmp .LBB4_3
; X86-NEXT: .LBB4_1:
-; X86-NEXT: bsrl %ebx, %esi
-; X86-NEXT: xorl $31, %esi
+; X86-NEXT: bsrl %esi, %edx
+; X86-NEXT: xorl $31, %edx
; X86-NEXT: .LBB4_3: # %_udiv-special-cases
-; X86-NEXT: movl 24(%ebp), %eax
-; X86-NEXT: testl %edx, %edx
+; X86-NEXT: movl 24(%ebp), %edi
+; X86-NEXT: testl %eax, %eax
; X86-NEXT: jne .LBB4_4
; X86-NEXT: # %bb.5: # %_udiv-special-cases
-; X86-NEXT: bsrl %eax, %ecx
+; X86-NEXT: bsrl %edi, %ecx
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: orl $32, %ecx
; X86-NEXT: jmp .LBB4_6
; X86-NEXT: .LBB4_4:
-; X86-NEXT: bsrl %edx, %ecx
+; X86-NEXT: bsrl %eax, %ecx
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: .LBB4_6: # %_udiv-special-cases
-; X86-NEXT: orl %ebx, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edi, %eax
+; X86-NEXT: orl %esi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: orl %ebx, %edi
+; X86-NEXT: orl %esi, %ebx
; X86-NEXT: jne .LBB4_8
; X86-NEXT: # %bb.7: # %_udiv-special-cases
; X86-NEXT: orl $64, %ecx
-; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: .LBB4_8: # %_udiv-special-cases
; X86-NEXT: movl $124, %ebx
-; X86-NEXT: subl %esi, %ebx
-; X86-NEXT: movl $0, %edx
-; X86-NEXT: sbbl %edx, %edx
+; X86-NEXT: subl %edx, %ebx
; X86-NEXT: movl $0, %esi
; X86-NEXT: sbbl %esi, %esi
-; X86-NEXT: movl $0, %edi
-; X86-NEXT: sbbl %edi, %edi
-; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %edx
+; X86-NEXT: sbbl %edx, %edx
+; X86-NEXT: movl $0, %eax
+; X86-NEXT: sbbl %eax, %eax
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB4_9
; X86-NEXT: # %bb.10: # %select.false.sink
-; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: xorl %edi, %edi
; X86-NEXT: movl $127, %ecx
; X86-NEXT: cmpl %ebx, %ecx
; X86-NEXT: movl $0, %ecx
-; X86-NEXT: sbbl %edx, %ecx
-; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %esi, %ecx
-; X86-NEXT: sbbl %edi, %eax
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: sbbl %edx, %ecx
+; X86-NEXT: sbbl %eax, %edi
; X86-NEXT: setb %cl
; X86-NEXT: .LBB4_11: # %select.end
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: xorl %esi, %esi
; X86-NEXT: testb %cl, %cl
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, %ecx
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jne .LBB4_13
; X86-NEXT: # %bb.12: # %select.end
-; X86-NEXT: movl 28(%ebp), %edx
+; X86-NEXT: movl 28(%ebp), %esi
; X86-NEXT: movl 24(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 32(%ebp), %ecx
-; X86-NEXT: movl 36(%ebp), %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: .LBB4_13: # %select.end
+; X86-NEXT: movl 36(%ebp), %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: .LBB4_13: # %select.end
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: jne .LBB4_14
; X86-NEXT: # %bb.20: # %select.end
; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: xorl $127, %ecx
-; X86-NEXT: orl %esi, %ecx
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: movl %esi, %edx
-; X86-NEXT: orl %edi, %edx
+; X86-NEXT: orl %edx, %ecx
+; X86-NEXT: movl %edi, %edx
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl 36(%ebp), %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: je .LBB4_21
; X86-NEXT: # %bb.18: # %udiv-bb1
; X86-NEXT: movl 24(%ebp), %eax
@@ -1112,8 +1114,7 @@ define i128 @div_by_11(i128 %x) nounwind {
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 32(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
@@ -1126,20 +1127,20 @@ define i128 @div_by_11(i128 %x) nounwind {
; X86-NEXT: negb %al
; X86-NEXT: movsbl %al, %eax
; X86-NEXT: movl 136(%esp,%eax), %edx
-; X86-NEXT: movl 140(%esp,%eax), %edi
-; X86-NEXT: shldl %cl, %edx, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 128(%esp,%eax), %edi
+; X86-NEXT: movl 140(%esp,%eax), %esi
+; X86-NEXT: shldl %cl, %edx, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 128(%esp,%eax), %esi
; X86-NEXT: movl 132(%esp,%eax), %eax
; X86-NEXT: shldl %cl, %eax, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl %cl, %edi, %eax
+; X86-NEXT: shldl %cl, %esi, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shll %cl, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: addl $1, %ebx
-; X86-NEXT: adcl $0, %esi
+; X86-NEXT: shll %cl, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: addl $1, %ebx
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jb .LBB4_19
@@ -1161,39 +1162,39 @@ define i128 @div_by_11(i128 %x) nounwind {
; X86-NEXT: shrb $3, %al
; X86-NEXT: andb $12, %al
; X86-NEXT: movzbl %al, %edi
-; X86-NEXT: movl 92(%esp,%edi), %eax
+; X86-NEXT: movl 92(%esp,%edi), %esi
; X86-NEXT: movl 88(%esp,%edi), %ebx
-; X86-NEXT: movl %ebx, %esi
-; X86-NEXT: shrdl %cl, %eax, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 80(%esp,%edi), %esi
-; X86-NEXT: movl 84(%esp,%edi), %edi
-; X86-NEXT: movl %edi, %edx
-; X86-NEXT: shrdl %cl, %ebx, %edx
+; X86-NEXT: movl %ebx, %edx
+; X86-NEXT: shrdl %cl, %esi, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shrl %cl, %eax
+; X86-NEXT: movl 80(%esp,%edi), %edx
+; X86-NEXT: movl 84(%esp,%edi), %edi
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: shrdl %cl, %ebx, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrl %cl, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: # kill: def $cl killed $cl killed $ecx
-; X86-NEXT: shrdl %cl, %edi, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $11, %eax
-; X86-NEXT: addl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrdl %cl, %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $11, %ecx
+; X86-NEXT: addl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB4_16: # %udiv-do-while
@@ -1202,76 +1203,78 @@ define i128 @div_by_11(i128 %x) nounwind {
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: shldl $1, %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %ebx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edx, %edi
-; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: shldl $1, %ecx, %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %esi, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shldl $1, %eax, %ecx
-; X86-NEXT: orl %esi, %ecx
+; X86-NEXT: shldl $1, %eax, %esi
+; X86-NEXT: shldl $1, %edx, %eax
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $1, %edx, %ecx
+; X86-NEXT: orl %edi, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shldl $1, %ecx, %eax
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl %ecx, %ecx
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; X86-NEXT: cmpl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %edi, %ecx
+; X86-NEXT: sbbl %esi, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl %ebx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: andl $1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl $11, %eax
-; X86-NEXT: andl %eax, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: andl $1, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sbbl $0, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl $11, %edx
+; X86-NEXT: andl %edx, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sbbl $0, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: sbbl $0, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: sbbl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: addl $-1, %ebx
; X86-NEXT: adcl $-1, %edi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: adcl $-1, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl $-1, %eax
; X86-NEXT: adcl $-1, %esi
; X86-NEXT: movl %edi, %ecx
; X86-NEXT: orl %esi, %ecx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edx, %ebx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %eax, %ebx
; X86-NEXT: orl %ecx, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: jne .LBB4_16
; X86-NEXT: .LBB4_17: # %udiv-loop-exit
-; X86-NEXT: shldl $1, %ecx, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: shldl $1, %edx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: leal (%esi,%eax,2), %edi
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: leal (%edx,%eax,2), %edx
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: .LBB4_21: # %udiv-end
-; X86-NEXT: movl %edi, (%eax)
+; X86-NEXT: movl %edx, (%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 4(%eax)
; X86-NEXT: movl %ecx, 8(%eax)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
@@ -1287,13 +1290,12 @@ define i128 @div_by_11(i128 %x) nounwind {
; X86-NEXT: jmp .LBB4_11
; X86-NEXT: .LBB4_19:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB4_17
; X86-NEXT: .LBB4_14:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: jmp .LBB4_21
;
; X64-LABEL: div_by_11:
@@ -1339,95 +1341,94 @@ define i128 @div_by_22(i128 %x) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $144, %esp
-; X86-NEXT: movl 32(%ebp), %edi
-; X86-NEXT: movl 36(%ebp), %ebx
-; X86-NEXT: movl 28(%ebp), %edx
-; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: movl 32(%ebp), %ebx
+; X86-NEXT: movl 36(%ebp), %esi
+; X86-NEXT: movl 28(%ebp), %eax
+; X86-NEXT: testl %esi, %esi
; X86-NEXT: jne .LBB5_1
; X86-NEXT: # %bb.2: # %entry_udiv-special-cases
-; X86-NEXT: bsrl %edi, %esi
-; X86-NEXT: xorl $31, %esi
-; X86-NEXT: orl $32, %esi
+; X86-NEXT: bsrl %ebx, %edx
+; X86-NEXT: xorl $31, %edx
+; X86-NEXT: orl $32, %edx
; X86-NEXT: jmp .LBB5_3
; X86-NEXT: .LBB5_1:
-; X86-NEXT: bsrl %ebx, %esi
-; X86-NEXT: xorl $31, %esi
+; X86-NEXT: bsrl %esi, %edx
+; X86-NEXT: xorl $31, %edx
; X86-NEXT: .LBB5_3: # %entry_udiv-special-cases
-; X86-NEXT: movl 24(%ebp), %eax
-; X86-NEXT: testl %edx, %edx
+; X86-NEXT: movl 24(%ebp), %edi
+; X86-NEXT: testl %eax, %eax
; X86-NEXT: jne .LBB5_4
; X86-NEXT: # %bb.5: # %entry_udiv-special-cases
-; X86-NEXT: bsrl %eax, %ecx
+; X86-NEXT: bsrl %edi, %ecx
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: orl $32, %ecx
; X86-NEXT: jmp .LBB5_6
; X86-NEXT: .LBB5_4:
-; X86-NEXT: bsrl %edx, %ecx
+; X86-NEXT: bsrl %eax, %ecx
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: .LBB5_6: # %entry_udiv-special-cases
-; X86-NEXT: orl %ebx, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edi, %eax
+; X86-NEXT: orl %esi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: orl %ebx, %edi
+; X86-NEXT: orl %esi, %ebx
; X86-NEXT: jne .LBB5_8
; X86-NEXT: # %bb.7: # %entry_udiv-special-cases
; X86-NEXT: orl $64, %ecx
-; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: .LBB5_8: # %entry_udiv-special-cases
; X86-NEXT: movl $123, %ebx
-; X86-NEXT: subl %esi, %ebx
-; X86-NEXT: movl $0, %edx
-; X86-NEXT: sbbl %edx, %edx
-; X86-NEXT: movl $0, %esi
-; X86-NEXT: sbbl %esi, %esi
-; X86-NEXT: movl $0, %edi
-; X86-NEXT: sbbl %edi, %edi
-; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: subl %edx, %ebx
+; X86-NEXT: movl $0, %esi
+; X86-NEXT: sbbl %esi, %esi
+; X86-NEXT: movl $0, %edx
+; X86-NEXT: sbbl %edx, %edx
+; X86-NEXT: movl $0, %eax
+; X86-NEXT: sbbl %eax, %eax
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB5_9
; X86-NEXT: # %bb.10: # %select.false.sink
-; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: xorl %edi, %edi
; X86-NEXT: movl $127, %ecx
; X86-NEXT: cmpl %ebx, %ecx
; X86-NEXT: movl $0, %ecx
-; X86-NEXT: sbbl %edx, %ecx
-; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %esi, %ecx
-; X86-NEXT: sbbl %edi, %eax
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: sbbl %edx, %ecx
+; X86-NEXT: sbbl %eax, %edi
; X86-NEXT: setb %cl
; X86-NEXT: .LBB5_11: # %select.end
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: xorl %esi, %esi
; X86-NEXT: testb %cl, %cl
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, %ecx
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jne .LBB5_13
; X86-NEXT: # %bb.12: # %select.end
-; X86-NEXT: movl 28(%ebp), %edx
+; X86-NEXT: movl 28(%ebp), %esi
; X86-NEXT: movl 24(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 32(%ebp), %ecx
-; X86-NEXT: movl 36(%ebp), %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: .LBB5_13: # %select.end
+; X86-NEXT: movl 36(%ebp), %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: .LBB5_13: # %select.end
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: jne .LBB5_14
; X86-NEXT: # %bb.20: # %select.end
; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: xorl $127, %ecx
-; X86-NEXT: orl %esi, %ecx
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: movl %esi, %edx
-; X86-NEXT: orl %edi, %edx
+; X86-NEXT: orl %edx, %ecx
+; X86-NEXT: movl %edi, %edx
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl 36(%ebp), %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: je .LBB5_21
; X86-NEXT: # %bb.18: # %udiv-bb1
; X86-NEXT: movl 24(%ebp), %eax
@@ -1436,8 +1437,7 @@ define i128 @div_by_22(i128 %x) nounwind {
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 32(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
@@ -1450,20 +1450,20 @@ define i128 @div_by_22(i128 %x) nounwind {
; X86-NEXT: negb %al
; X86-NEXT: movsbl %al, %eax
; X86-NEXT: movl 136(%esp,%eax), %edx
-; X86-NEXT: movl 140(%esp,%eax), %edi
-; X86-NEXT: shldl %cl, %edx, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 128(%esp,%eax), %edi
+; X86-NEXT: movl 140(%esp,%eax), %esi
+; X86-NEXT: shldl %cl, %edx, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 128(%esp,%eax), %esi
; X86-NEXT: movl 132(%esp,%eax), %eax
; X86-NEXT: shldl %cl, %eax, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl %cl, %edi, %eax
+; X86-NEXT: shldl %cl, %esi, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shll %cl, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: addl $1, %ebx
-; X86-NEXT: adcl $0, %esi
+; X86-NEXT: shll %cl, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: addl $1, %ebx
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jb .LBB5_19
@@ -1485,39 +1485,39 @@ define i128 @div_by_22(i128 %x) nounwind {
; X86-NEXT: shrb $3, %al
; X86-NEXT: andb $12, %al
; X86-NEXT: movzbl %al, %edi
-; X86-NEXT: movl 92(%esp,%edi), %eax
+; X86-NEXT: movl 92(%esp,%edi), %esi
; X86-NEXT: movl 88(%esp,%edi), %ebx
-; X86-NEXT: movl %ebx, %esi
-; X86-NEXT: shrdl %cl, %eax, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 80(%esp,%edi), %esi
-; X86-NEXT: movl 84(%esp,%edi), %edi
-; X86-NEXT: movl %edi, %edx
-; X86-NEXT: shrdl %cl, %ebx, %edx
+; X86-NEXT: movl %ebx, %edx
+; X86-NEXT: shrdl %cl, %esi, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shrl %cl, %eax
+; X86-NEXT: movl 80(%esp,%edi), %edx
+; X86-NEXT: movl 84(%esp,%edi), %edi
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: shrdl %cl, %ebx, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrl %cl, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: # kill: def $cl killed $cl killed $ecx
-; X86-NEXT: shrdl %cl, %edi, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $22, %eax
-; X86-NEXT: addl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrdl %cl, %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $22, %ecx
+; X86-NEXT: addl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB5_16: # %udiv-do-while
@@ -1526,76 +1526,78 @@ define i128 @div_by_22(i128 %x) nounwind {
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: shldl $1, %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %ebx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edx, %edi
-; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: shldl $1, %ecx, %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %esi, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shldl $1, %eax, %ecx
-; X86-NEXT: orl %esi, %ecx
+; X86-NEXT: shldl $1, %eax, %esi
+; X86-NEXT: shldl $1, %edx, %eax
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $1, %edx, %ecx
+; X86-NEXT: orl %edi, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shldl $1, %ecx, %eax
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl %ecx, %ecx
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; X86-NEXT: cmpl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %edi, %ecx
+; X86-NEXT: sbbl %esi, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl %ebx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: andl $1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl $22, %eax
-; X86-NEXT: andl %eax, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: andl $1, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sbbl $0, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl $22, %edx
+; X86-NEXT: andl %edx, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sbbl $0, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: sbbl $0, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: sbbl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: addl $-1, %ebx
; X86-NEXT: adcl $-1, %edi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: adcl $-1, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl $-1, %eax
; X86-NEXT: adcl $-1, %esi
; X86-NEXT: movl %edi, %ecx
; X86-NEXT: orl %esi, %ecx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edx, %ebx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %eax, %ebx
; X86-NEXT: orl %ecx, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: jne .LBB5_16
; X86-NEXT: .LBB5_17: # %udiv-loop-exit
-; X86-NEXT: shldl $1, %ecx, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: shldl $1, %edx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: leal (%esi,%eax,2), %edi
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: leal (%edx,%eax,2), %edx
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: .LBB5_21: # %udiv-end
-; X86-NEXT: movl %edi, (%eax)
+; X86-NEXT: movl %edx, (%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 4(%eax)
; X86-NEXT: movl %ecx, 8(%eax)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
@@ -1611,13 +1613,12 @@ define i128 @div_by_22(i128 %x) nounwind {
; X86-NEXT: jmp .LBB5_11
; X86-NEXT: .LBB5_19:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB5_17
; X86-NEXT: .LBB5_14:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: jmp .LBB5_21
;
; X64-LABEL: div_by_22:
@@ -1665,95 +1666,94 @@ define i128 @div_by_56(i128 %x) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $144, %esp
-; X86-NEXT: movl 32(%ebp), %edi
-; X86-NEXT: movl 36(%ebp), %ebx
-; X86-NEXT: movl 28(%ebp), %edx
-; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: movl 32(%ebp), %ebx
+; X86-NEXT: movl 36(%ebp), %esi
+; X86-NEXT: movl 28(%ebp), %eax
+; X86-NEXT: testl %esi, %esi
; X86-NEXT: jne .LBB6_1
; X86-NEXT: # %bb.2: # %_udiv-special-cases
-; X86-NEXT: bsrl %edi, %esi
-; X86-NEXT: xorl $31, %esi
-; X86-NEXT: orl $32, %esi
+; X86-NEXT: bsrl %ebx, %edx
+; X86-NEXT: xorl $31, %edx
+; X86-NEXT: orl $32, %edx
; X86-NEXT: jmp .LBB6_3
; X86-NEXT: .LBB6_1:
-; X86-NEXT: bsrl %ebx, %esi
-; X86-NEXT: xorl $31, %esi
+; X86-NEXT: bsrl %esi, %edx
+; X86-NEXT: xorl $31, %edx
; X86-NEXT: .LBB6_3: # %_udiv-special-cases
-; X86-NEXT: movl 24(%ebp), %eax
-; X86-NEXT: testl %edx, %edx
+; X86-NEXT: movl 24(%ebp), %edi
+; X86-NEXT: testl %eax, %eax
; X86-NEXT: jne .LBB6_4
; X86-NEXT: # %bb.5: # %_udiv-special-cases
-; X86-NEXT: bsrl %eax, %ecx
+; X86-NEXT: bsrl %edi, %ecx
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: orl $32, %ecx
; X86-NEXT: jmp .LBB6_6
; X86-NEXT: .LBB6_4:
-; X86-NEXT: bsrl %edx, %ecx
+; X86-NEXT: bsrl %eax, %ecx
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: .LBB6_6: # %_udiv-special-cases
-; X86-NEXT: orl %ebx, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edi, %eax
+; X86-NEXT: orl %esi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: orl %ebx, %edi
+; X86-NEXT: orl %esi, %ebx
; X86-NEXT: jne .LBB6_8
; X86-NEXT: # %bb.7: # %_udiv-special-cases
; X86-NEXT: orl $64, %ecx
-; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: .LBB6_8: # %_udiv-special-cases
; X86-NEXT: movl $122, %ebx
-; X86-NEXT: subl %esi, %ebx
-; X86-NEXT: movl $0, %edx
-; X86-NEXT: sbbl %edx, %edx
+; X86-NEXT: subl %edx, %ebx
; X86-NEXT: movl $0, %esi
; X86-NEXT: sbbl %esi, %esi
-; X86-NEXT: movl $0, %edi
-; X86-NEXT: sbbl %edi, %edi
-; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %edx
+; X86-NEXT: sbbl %edx, %edx
+; X86-NEXT: movl $0, %eax
+; X86-NEXT: sbbl %eax, %eax
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB6_9
; X86-NEXT: # %bb.10: # %select.false.sink
-; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: xorl %edi, %edi
; X86-NEXT: movl $127, %ecx
; X86-NEXT: cmpl %ebx, %ecx
; X86-NEXT: movl $0, %ecx
-; X86-NEXT: sbbl %edx, %ecx
-; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %esi, %ecx
-; X86-NEXT: sbbl %edi, %eax
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: sbbl %edx, %ecx
+; X86-NEXT: sbbl %eax, %edi
; X86-NEXT: setb %cl
; X86-NEXT: .LBB6_11: # %select.end
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: xorl %esi, %esi
; X86-NEXT: testb %cl, %cl
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, %ecx
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jne .LBB6_13
; X86-NEXT: # %bb.12: # %select.end
-; X86-NEXT: movl 28(%ebp), %edx
+; X86-NEXT: movl 28(%ebp), %esi
; X86-NEXT: movl 24(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 32(%ebp), %ecx
-; X86-NEXT: movl 36(%ebp), %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: .LBB6_13: # %select.end
+; X86-NEXT: movl 36(%ebp), %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: .LBB6_13: # %select.end
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: jne .LBB6_14
; X86-NEXT: # %bb.20: # %select.end
; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: xorl $127, %ecx
-; X86-NEXT: orl %esi, %ecx
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: movl %esi, %edx
-; X86-NEXT: orl %edi, %edx
+; X86-NEXT: orl %edx, %ecx
+; X86-NEXT: movl %edi, %edx
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl 36(%ebp), %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: je .LBB6_21
; X86-NEXT: # %bb.18: # %udiv-bb1
; X86-NEXT: movl 24(%ebp), %eax
@@ -1762,8 +1762,7 @@ define i128 @div_by_56(i128 %x) nounwind {
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 32(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
@@ -1776,20 +1775,20 @@ define i128 @div_by_56(i128 %x) nounwind {
; X86-NEXT: negb %al
; X86-NEXT: movsbl %al, %eax
; X86-NEXT: movl 136(%esp,%eax), %edx
-; X86-NEXT: movl 140(%esp,%eax), %edi
-; X86-NEXT: shldl %cl, %edx, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 128(%esp,%eax), %edi
+; X86-NEXT: movl 140(%esp,%eax), %esi
+; X86-NEXT: shldl %cl, %edx, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 128(%esp,%eax), %esi
; X86-NEXT: movl 132(%esp,%eax), %eax
; X86-NEXT: shldl %cl, %eax, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl %cl, %edi, %eax
+; X86-NEXT: shldl %cl, %esi, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shll %cl, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: addl $1, %ebx
-; X86-NEXT: adcl $0, %esi
+; X86-NEXT: shll %cl, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: addl $1, %ebx
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jb .LBB6_19
@@ -1811,39 +1810,39 @@ define i128 @div_by_56(i128 %x) nounwind {
; X86-NEXT: shrb $3, %al
; X86-NEXT: andb $12, %al
; X86-NEXT: movzbl %al, %edi
-; X86-NEXT: movl 92(%esp,%edi), %eax
+; X86-NEXT: movl 92(%esp,%edi), %esi
; X86-NEXT: movl 88(%esp,%edi), %ebx
-; X86-NEXT: movl %ebx, %esi
-; X86-NEXT: shrdl %cl, %eax, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 80(%esp,%edi), %esi
-; X86-NEXT: movl 84(%esp,%edi), %edi
-; X86-NEXT: movl %edi, %edx
-; X86-NEXT: shrdl %cl, %ebx, %edx
+; X86-NEXT: movl %ebx, %edx
+; X86-NEXT: shrdl %cl, %esi, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shrl %cl, %eax
+; X86-NEXT: movl 80(%esp,%edi), %edx
+; X86-NEXT: movl 84(%esp,%edi), %edi
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: shrdl %cl, %ebx, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrl %cl, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: # kill: def $cl killed $cl killed $ecx
-; X86-NEXT: shrdl %cl, %edi, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $56, %eax
-; X86-NEXT: addl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrdl %cl, %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $56, %ecx
+; X86-NEXT: addl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB6_16: # %udiv-do-while
@@ -1852,76 +1851,78 @@ define i128 @div_by_56(i128 %x) nounwind {
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: shldl $1, %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %ebx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edx, %edi
-; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: shldl $1, %ecx, %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %esi, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shldl $1, %eax, %ecx
-; X86-NEXT: orl %esi, %ecx
+; X86-NEXT: shldl $1, %eax, %esi
+; X86-NEXT: shldl $1, %edx, %eax
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $1, %edx, %ecx
+; X86-NEXT: orl %edi, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shldl $1, %ecx, %eax
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl %ecx, %ecx
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; X86-NEXT: cmpl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %edi, %ecx
+; X86-NEXT: sbbl %esi, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl %ebx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: andl $1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl $56, %eax
-; X86-NEXT: andl %eax, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: andl $1, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sbbl $0, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl $56, %edx
+; X86-NEXT: andl %edx, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sbbl $0, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: sbbl $0, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: sbbl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: addl $-1, %ebx
; X86-NEXT: adcl $-1, %edi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: adcl $-1, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl $-1, %eax
; X86-NEXT: adcl $-1, %esi
; X86-NEXT: movl %edi, %ecx
; X86-NEXT: orl %esi, %ecx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edx, %ebx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %eax, %ebx
; X86-NEXT: orl %ecx, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: jne .LBB6_16
; X86-NEXT: .LBB6_17: # %udiv-loop-exit
-; X86-NEXT: shldl $1, %ecx, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: shldl $1, %edx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: leal (%esi,%eax,2), %edi
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: leal (%edx,%eax,2), %edx
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: .LBB6_21: # %udiv-end
-; X86-NEXT: movl %edi, (%eax)
+; X86-NEXT: movl %edx, (%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 4(%eax)
; X86-NEXT: movl %ecx, 8(%eax)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
@@ -1937,13 +1938,12 @@ define i128 @div_by_56(i128 %x) nounwind {
; X86-NEXT: jmp .LBB6_11
; X86-NEXT: .LBB6_19:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB6_17
; X86-NEXT: .LBB6_14:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: jmp .LBB6_21
;
; X64-LABEL: div_by_56:
@@ -1990,7 +1990,7 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
-; X86-NEXT: addl $-128, %esp
+; X86-NEXT: subl $144, %esp
; X86-NEXT: movl 36(%ebp), %ebx
; X86-NEXT: movl 28(%ebp), %eax
; X86-NEXT: testl %ebx, %ebx
@@ -2017,7 +2017,7 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: .LBB7_6: # %_udiv-special-cases
; X86-NEXT: orl %ebx, %eax
-; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edi, %esi
; X86-NEXT: movl 32(%ebp), %edi
; X86-NEXT: orl %edi, %esi
@@ -2035,10 +2035,10 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: sbbl %edx, %edx
; X86-NEXT: movl $0, %eax
; X86-NEXT: sbbl %eax, %eax
-; X86-NEXT: orl (%esp), %esi # 4-byte Folded Reload
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB7_9
; X86-NEXT: # %bb.10: # %select.false.sink
; X86-NEXT: xorl %esi, %esi
@@ -2049,50 +2049,52 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %edx, %ecx
; X86-NEXT: sbbl %eax, %esi
-; X86-NEXT: setb %al
+; X86-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; X86-NEXT: .LBB7_11: # %select.end
-; X86-NEXT: movl 28(%ebp), %edi
-; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: movl 28(%ebp), %ebx
+; X86-NEXT: movl 24(%ebp), %ecx
+; X86-NEXT: movl %eax, %edi
; X86-NEXT: movl $7, %edx
-; X86-NEXT: xorl %ebx, %ebx
-; X86-NEXT: testb %al, %al
-; X86-NEXT: movl $0, (%esp) # 4-byte Folded Spill
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, %esi
; X86-NEXT: jne .LBB7_13
; X86-NEXT: # %bb.12: # %select.end
-; X86-NEXT: movl %edi, %ebx
-; X86-NEXT: movl 24(%ebp), %eax
-; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 32(%ebp), %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 36(%ebp), %esi
; X86-NEXT: .LBB7_13: # %select.end
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jne .LBB7_14
; X86-NEXT: # %bb.20: # %select.end
+; X86-NEXT: movl %edi, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $127, %eax
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %ecx, %eax
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl %edi, %ecx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %ebx, %ecx
; X86-NEXT: orl %eax, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl 32(%ebp), %ebx
; X86-NEXT: je .LBB7_21
; X86-NEXT: # %bb.18: # %udiv-bb1
; X86-NEXT: movl 24(%ebp), %esi
; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %edi, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 32(%ebp), %eax
+; X86-NEXT: movl 28(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp)
; X86-NEXT: movl 36(%ebp), %edx
; X86-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: xorb $127, %cl
; X86-NEXT: movl %ecx, %eax
@@ -2100,12 +2102,12 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: andb $12, %al
; X86-NEXT: negb %al
; X86-NEXT: movsbl %al, %eax
-; X86-NEXT: movl 120(%esp,%eax), %esi
-; X86-NEXT: movl 124(%esp,%eax), %edx
+; X86-NEXT: movl 136(%esp,%eax), %esi
+; X86-NEXT: movl 140(%esp,%eax), %edx
; X86-NEXT: shldl %cl, %esi, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 112(%esp,%eax), %edx
-; X86-NEXT: movl 116(%esp,%eax), %eax
+; X86-NEXT: movl 128(%esp,%eax), %edx
+; X86-NEXT: movl 132(%esp,%eax), %eax
; X86-NEXT: shldl %cl, %eax, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: shldl %cl, %edx, %eax
@@ -2114,14 +2116,16 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl $1, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jb .LBB7_19
; X86-NEXT: # %bb.15: # %udiv-preheader
; X86-NEXT: movl 24(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %edi, {{[0-9]+}}(%esp)
+; X86-NEXT: movl 28(%ebp), %eax
+; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 32(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 36(%ebp), %eax
@@ -2135,34 +2139,35 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: shrb $3, %al
; X86-NEXT: andb $12, %al
; X86-NEXT: movzbl %al, %eax
-; X86-NEXT: movl 76(%esp,%eax), %esi
-; X86-NEXT: movl 72(%esp,%eax), %edx
-; X86-NEXT: movl %edx, %edi
-; X86-NEXT: shrdl %cl, %esi, %edi
+; X86-NEXT: movl 92(%esp,%eax), %edi
+; X86-NEXT: movl 88(%esp,%eax), %edx
+; X86-NEXT: movl %edx, %ebx
+; X86-NEXT: shrdl %cl, %edi, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 80(%esp,%eax), %ebx
+; X86-NEXT: movl 84(%esp,%eax), %esi
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: shrdl %cl, %edx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrl %cl, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 64(%esp,%eax), %ebx
-; X86-NEXT: movl 68(%esp,%eax), %eax
-; X86-NEXT: movl %eax, %edi
-; X86-NEXT: shrdl %cl, %edx, %edi
-; X86-NEXT: shrl %cl, %esi
-; X86-NEXT: movl %esi, (%esp) # 4-byte Spill
; X86-NEXT: # kill: def $cl killed $cl killed $ecx
-; X86-NEXT: shrdl %cl, %eax, %ebx
+; X86-NEXT: shrdl %cl, %esi, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $7, %eax
-; X86-NEXT: addl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $7, %ecx
+; X86-NEXT: addl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
@@ -2170,62 +2175,61 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB7_16: # %udiv-do-while
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: shldl $1, %esi, (%esp) # 4-byte Folded Spill
-; X86-NEXT: movl %edi, %eax
-; X86-NEXT: shldl $1, %edi, %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %eax
-; X86-NEXT: shldl $1, %ecx, %edi
+; X86-NEXT: shldl $1, %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: shldl $1, %eax, %edi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: shldl $1, %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: shldl $1, %ecx, %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: shldl $1, %ebx, %ecx
; X86-NEXT: orl %edx, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shldl $1, %ecx, %ebx
+; X86-NEXT: shldl $1, %esi, %ebx
; X86-NEXT: orl %edx, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X86-NEXT: shldl $1, %ebx, %ecx
-; X86-NEXT: orl %edx, %ecx
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ebx, %esi
+; X86-NEXT: orl %edx, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl %ebx, %ebx
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
-; X86-NEXT: cmpl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; X86-NEXT: cmpl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %eax, %ecx
+; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %esi, %ecx
+; X86-NEXT: sbbl %edi, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl (%esp), %ecx # 4-byte Folded Reload
+; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %edx
-; X86-NEXT: andl $1, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: andl $1, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl $7, %edx
; X86-NEXT: andl %edx, %ecx
-; X86-NEXT: subl %ecx, %edi
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sbbl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: sbbl $0, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sbbl $0, %eax
-; X86-NEXT: movl %eax, %edi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: sbbl $0, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: sbbl $0, (%esp) # 4-byte Folded Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: sbbl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: addl $-1, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: adcl $-1, %ecx
-; X86-NEXT: adcl $-1, %esi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: adcl $-1, %eax
+; X86-NEXT: adcl $-1, %edi
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %eax, %ecx
+; X86-NEXT: orl %edi, %ecx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %esi, %edx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %eax, %edx
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: movl $0, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
@@ -2233,14 +2237,13 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: .LBB7_17: # %udiv-loop-exit
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: shldl $1, %eax, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edx, %eax
-; X86-NEXT: shldl $1, %ebx, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %esi, %eax
+; X86-NEXT: shldl $1, %ebx, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: leal (%edx,%ebx,2), %edx
-; X86-NEXT: movl %edx, (%esp) # 4-byte Spill
-; X86-NEXT: movl 28(%ebp), %edi
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 32(%ebp), %ebx
; X86-NEXT: movl $7, %edx
; X86-NEXT: movl %ecx, %esi
; X86-NEXT: .LBB7_21: # %udiv-end
@@ -2249,18 +2252,18 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: movl %edx, %ecx
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $7, %eax
-; X86-NEXT: mull (%esp) # 4-byte Folded Reload
-; X86-NEXT: movl %edx, %ebx
-; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: mull {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $7, %eax
; X86-NEXT: mull {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
-; X86-NEXT: addl %ebx, %eax
+; X86-NEXT: addl %edi, %eax
; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: adcl %esi, %ecx
; X86-NEXT: movl 24(%ebp), %esi
-; X86-NEXT: subl (%esp), %esi # 4-byte Folded Reload
+; X86-NEXT: subl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload
+; X86-NEXT: movl 28(%ebp), %edi
; X86-NEXT: sbbl %eax, %edi
-; X86-NEXT: movl 32(%ebp), %ebx
; X86-NEXT: sbbl %edx, %ebx
; X86-NEXT: movl 36(%ebp), %edx
; X86-NEXT: sbbl %ecx, %edx
@@ -2276,15 +2279,17 @@ define i128 @rem_by_7(i128 %x) nounwind {
; X86-NEXT: popl %ebp
; X86-NEXT: retl $4
; X86-NEXT: .LBB7_9:
-; X86-NEXT: movb $1, %al
+; X86-NEXT: movb $1, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; X86-NEXT: jmp .LBB7_11
; X86-NEXT: .LBB7_19:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB7_17
; X86-NEXT: .LBB7_14:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl 32(%ebp), %ebx
; X86-NEXT: jmp .LBB7_21
;
; X64-LABEL: rem_by_7:
@@ -2320,7 +2325,7 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
-; X86-NEXT: addl $-128, %esp
+; X86-NEXT: subl $144, %esp
; X86-NEXT: movl 36(%ebp), %ebx
; X86-NEXT: movl 28(%ebp), %eax
; X86-NEXT: testl %ebx, %ebx
@@ -2347,7 +2352,7 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: .LBB8_6: # %_udiv-special-cases
; X86-NEXT: orl %ebx, %eax
-; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edi, %esi
; X86-NEXT: movl 32(%ebp), %edi
; X86-NEXT: orl %edi, %esi
@@ -2365,10 +2370,10 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: sbbl %edx, %edx
; X86-NEXT: movl $0, %eax
; X86-NEXT: sbbl %eax, %eax
-; X86-NEXT: orl (%esp), %esi # 4-byte Folded Reload
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB8_9
; X86-NEXT: # %bb.10: # %select.false.sink
; X86-NEXT: xorl %esi, %esi
@@ -2379,50 +2384,52 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %edx, %ecx
; X86-NEXT: sbbl %eax, %esi
-; X86-NEXT: setb %al
+; X86-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; X86-NEXT: .LBB8_11: # %select.end
-; X86-NEXT: movl 28(%ebp), %edi
-; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: movl 28(%ebp), %ebx
+; X86-NEXT: movl 24(%ebp), %ecx
+; X86-NEXT: movl %eax, %edi
; X86-NEXT: movl $14, %edx
-; X86-NEXT: xorl %ebx, %ebx
-; X86-NEXT: testb %al, %al
-; X86-NEXT: movl $0, (%esp) # 4-byte Folded Spill
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, %esi
; X86-NEXT: jne .LBB8_13
; X86-NEXT: # %bb.12: # %select.end
-; X86-NEXT: movl %edi, %ebx
-; X86-NEXT: movl 24(%ebp), %eax
-; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 32(%ebp), %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 36(%ebp), %esi
; X86-NEXT: .LBB8_13: # %select.end
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jne .LBB8_14
; X86-NEXT: # %bb.20: # %select.end
+; X86-NEXT: movl %edi, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $127, %eax
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %ecx, %eax
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl %edi, %ecx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %ebx, %ecx
; X86-NEXT: orl %eax, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl 32(%ebp), %ebx
; X86-NEXT: je .LBB8_21
; X86-NEXT: # %bb.18: # %udiv-bb1
; X86-NEXT: movl 24(%ebp), %esi
; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %edi, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 32(%ebp), %eax
+; X86-NEXT: movl 28(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp)
; X86-NEXT: movl 36(%ebp), %edx
; X86-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: xorb $127, %cl
; X86-NEXT: movl %ecx, %eax
@@ -2430,12 +2437,12 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: andb $12, %al
; X86-NEXT: negb %al
; X86-NEXT: movsbl %al, %eax
-; X86-NEXT: movl 120(%esp,%eax), %esi
-; X86-NEXT: movl 124(%esp,%eax), %edx
+; X86-NEXT: movl 136(%esp,%eax), %esi
+; X86-NEXT: movl 140(%esp,%eax), %edx
; X86-NEXT: shldl %cl, %esi, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 112(%esp,%eax), %edx
-; X86-NEXT: movl 116(%esp,%eax), %eax
+; X86-NEXT: movl 128(%esp,%eax), %edx
+; X86-NEXT: movl 132(%esp,%eax), %eax
; X86-NEXT: shldl %cl, %eax, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: shldl %cl, %edx, %eax
@@ -2444,14 +2451,16 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl $1, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jb .LBB8_19
; X86-NEXT: # %bb.15: # %udiv-preheader
; X86-NEXT: movl 24(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %edi, {{[0-9]+}}(%esp)
+; X86-NEXT: movl 28(%ebp), %eax
+; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 32(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 36(%ebp), %eax
@@ -2463,36 +2472,37 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl %ecx, %eax
; X86-NEXT: shrb $3, %al
-; X86-NEXT: andb $12, %al
-; X86-NEXT: movzbl %al, %eax
-; X86-NEXT: movl 76(%esp,%eax), %esi
-; X86-NEXT: movl 72(%esp,%eax), %edx
-; X86-NEXT: movl %edx, %edi
-; X86-NEXT: shrdl %cl, %esi, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 64(%esp,%eax), %ebx
-; X86-NEXT: movl 68(%esp,%eax), %eax
-; X86-NEXT: movl %eax, %edi
-; X86-NEXT: shrdl %cl, %edx, %edi
-; X86-NEXT: shrl %cl, %esi
-; X86-NEXT: movl %esi, (%esp) # 4-byte Spill
-; X86-NEXT: # kill: def $cl killed $cl killed $ecx
-; X86-NEXT: shrdl %cl, %eax, %ebx
-; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $14, %eax
-; X86-NEXT: addl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
+; X86-NEXT: andb $12, %al
+; X86-NEXT: movzbl %al, %eax
+; X86-NEXT: movl 92(%esp,%eax), %edi
+; X86-NEXT: movl 88(%esp,%eax), %edx
+; X86-NEXT: movl %edx, %ebx
+; X86-NEXT: shrdl %cl, %edi, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 80(%esp,%eax), %ebx
+; X86-NEXT: movl 84(%esp,%eax), %esi
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: shrdl %cl, %edx, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrl %cl, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: # kill: def $cl killed $cl killed $ecx
+; X86-NEXT: shrdl %cl, %esi, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $14, %ecx
+; X86-NEXT: addl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
@@ -2500,62 +2510,61 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB8_16: # %udiv-do-while
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: shldl $1, %esi, (%esp) # 4-byte Folded Spill
-; X86-NEXT: movl %edi, %eax
-; X86-NEXT: shldl $1, %edi, %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %eax
-; X86-NEXT: shldl $1, %ecx, %edi
+; X86-NEXT: shldl $1, %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: shldl $1, %eax, %edi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: shldl $1, %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: shldl $1, %ecx, %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: shldl $1, %ebx, %ecx
; X86-NEXT: orl %edx, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shldl $1, %ecx, %ebx
+; X86-NEXT: shldl $1, %esi, %ebx
; X86-NEXT: orl %edx, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X86-NEXT: shldl $1, %ebx, %ecx
-; X86-NEXT: orl %edx, %ecx
-; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ebx, %esi
+; X86-NEXT: orl %edx, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl %ebx, %ebx
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
-; X86-NEXT: cmpl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; X86-NEXT: cmpl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %eax, %ecx
+; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %esi, %ecx
+; X86-NEXT: sbbl %edi, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl (%esp), %ecx # 4-byte Folded Reload
+; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %edx
-; X86-NEXT: andl $1, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: andl $1, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl $14, %edx
; X86-NEXT: andl %edx, %ecx
-; X86-NEXT: subl %ecx, %edi
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sbbl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: sbbl $0, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sbbl $0, %eax
-; X86-NEXT: movl %eax, %edi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: sbbl $0, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: sbbl $0, (%esp) # 4-byte Folded Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: sbbl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: addl $-1, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: adcl $-1, %ecx
-; X86-NEXT: adcl $-1, %esi
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: adcl $-1, %eax
+; X86-NEXT: adcl $-1, %edi
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %eax, %ecx
+; X86-NEXT: orl %edi, %ecx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %esi, %edx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %eax, %edx
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: movl $0, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
@@ -2563,14 +2572,13 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: .LBB8_17: # %udiv-loop-exit
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: shldl $1, %eax, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edx, %eax
-; X86-NEXT: shldl $1, %ebx, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %esi, %eax
+; X86-NEXT: shldl $1, %ebx, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: leal (%edx,%ebx,2), %edx
-; X86-NEXT: movl %edx, (%esp) # 4-byte Spill
-; X86-NEXT: movl 28(%ebp), %edi
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 32(%ebp), %ebx
; X86-NEXT: movl $14, %edx
; X86-NEXT: movl %ecx, %esi
; X86-NEXT: .LBB8_21: # %udiv-end
@@ -2579,18 +2587,18 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: movl %edx, %ecx
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $14, %eax
-; X86-NEXT: mull (%esp) # 4-byte Folded Reload
-; X86-NEXT: movl %edx, %ebx
-; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: mull {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; X86-NEXT: movl %edx, %edi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $14, %eax
; X86-NEXT: mull {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
-; X86-NEXT: addl %ebx, %eax
+; X86-NEXT: addl %edi, %eax
; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: adcl %esi, %ecx
; X86-NEXT: movl 24(%ebp), %esi
-; X86-NEXT: subl (%esp), %esi # 4-byte Folded Reload
+; X86-NEXT: subl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload
+; X86-NEXT: movl 28(%ebp), %edi
; X86-NEXT: sbbl %eax, %edi
-; X86-NEXT: movl 32(%ebp), %ebx
; X86-NEXT: sbbl %edx, %ebx
; X86-NEXT: movl 36(%ebp), %edx
; X86-NEXT: sbbl %ecx, %edx
@@ -2606,15 +2614,17 @@ define i128 @rem_by_14(i128 %x) nounwind {
; X86-NEXT: popl %ebp
; X86-NEXT: retl $4
; X86-NEXT: .LBB8_9:
-; X86-NEXT: movb $1, %al
+; X86-NEXT: movb $1, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; X86-NEXT: jmp .LBB8_11
; X86-NEXT: .LBB8_19:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB8_17
; X86-NEXT: .LBB8_14:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl 32(%ebp), %ebx
; X86-NEXT: jmp .LBB8_21
;
; X64-LABEL: rem_by_14:
@@ -2654,95 +2664,94 @@ define i128 @div_by_67(i128 %x) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $144, %esp
-; X86-NEXT: movl 32(%ebp), %edi
-; X86-NEXT: movl 36(%ebp), %ebx
-; X86-NEXT: movl 28(%ebp), %edx
-; X86-NEXT: testl %ebx, %ebx
+; X86-NEXT: movl 32(%ebp), %ebx
+; X86-NEXT: movl 36(%ebp), %esi
+; X86-NEXT: movl 28(%ebp), %eax
+; X86-NEXT: testl %esi, %esi
; X86-NEXT: jne .LBB9_1
; X86-NEXT: # %bb.2: # %entry_udiv-special-cases
-; X86-NEXT: bsrl %edi, %esi
-; X86-NEXT: xorl $31, %esi
-; X86-NEXT: orl $32, %esi
+; X86-NEXT: bsrl %ebx, %edx
+; X86-NEXT: xorl $31, %edx
+; X86-NEXT: orl $32, %edx
; X86-NEXT: jmp .LBB9_3
; X86-NEXT: .LBB9_1:
-; X86-NEXT: bsrl %ebx, %esi
-; X86-NEXT: xorl $31, %esi
+; X86-NEXT: bsrl %esi, %edx
+; X86-NEXT: xorl $31, %edx
; X86-NEXT: .LBB9_3: # %entry_udiv-special-cases
-; X86-NEXT: movl 24(%ebp), %eax
-; X86-NEXT: testl %edx, %edx
+; X86-NEXT: movl 24(%ebp), %edi
+; X86-NEXT: testl %eax, %eax
; X86-NEXT: jne .LBB9_4
; X86-NEXT: # %bb.5: # %entry_udiv-special-cases
-; X86-NEXT: bsrl %eax, %ecx
+; X86-NEXT: bsrl %edi, %ecx
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: orl $32, %ecx
; X86-NEXT: jmp .LBB9_6
; X86-NEXT: .LBB9_4:
-; X86-NEXT: bsrl %edx, %ecx
+; X86-NEXT: bsrl %eax, %ecx
; X86-NEXT: xorl $31, %ecx
; X86-NEXT: .LBB9_6: # %entry_udiv-special-cases
-; X86-NEXT: orl %ebx, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edi, %eax
+; X86-NEXT: orl %esi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: orl %ebx, %edi
+; X86-NEXT: orl %esi, %ebx
; X86-NEXT: jne .LBB9_8
; X86-NEXT: # %bb.7: # %entry_udiv-special-cases
; X86-NEXT: orl $64, %ecx
-; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: .LBB9_8: # %entry_udiv-special-cases
; X86-NEXT: movl $121, %ebx
-; X86-NEXT: subl %esi, %ebx
-; X86-NEXT: movl $0, %edx
-; X86-NEXT: sbbl %edx, %edx
+; X86-NEXT: subl %edx, %ebx
; X86-NEXT: movl $0, %esi
; X86-NEXT: sbbl %esi, %esi
-; X86-NEXT: movl $0, %edi
-; X86-NEXT: sbbl %edi, %edi
-; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %edx
+; X86-NEXT: sbbl %edx, %edx
+; X86-NEXT: movl $0, %eax
+; X86-NEXT: sbbl %eax, %eax
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB9_9
; X86-NEXT: # %bb.10: # %select.false.sink
-; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: xorl %edi, %edi
; X86-NEXT: movl $127, %ecx
; X86-NEXT: cmpl %ebx, %ecx
; X86-NEXT: movl $0, %ecx
-; X86-NEXT: sbbl %edx, %ecx
-; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %esi, %ecx
-; X86-NEXT: sbbl %edi, %eax
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: sbbl %edx, %ecx
+; X86-NEXT: sbbl %eax, %edi
; X86-NEXT: setb %cl
; X86-NEXT: .LBB9_11: # %select.end
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: xorl %esi, %esi
; X86-NEXT: testb %cl, %cl
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, %ecx
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jne .LBB9_13
; X86-NEXT: # %bb.12: # %select.end
-; X86-NEXT: movl 28(%ebp), %edx
+; X86-NEXT: movl 28(%ebp), %esi
; X86-NEXT: movl 24(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl 32(%ebp), %ecx
-; X86-NEXT: movl 36(%ebp), %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: .LBB9_13: # %select.end
+; X86-NEXT: movl 36(%ebp), %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: .LBB9_13: # %select.end
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: jne .LBB9_14
; X86-NEXT: # %bb.20: # %select.end
; X86-NEXT: movl %ebx, %ecx
; X86-NEXT: xorl $127, %ecx
-; X86-NEXT: orl %esi, %ecx
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: movl %esi, %edx
-; X86-NEXT: orl %edi, %edx
+; X86-NEXT: orl %edx, %ecx
+; X86-NEXT: movl %edi, %edx
+; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl 36(%ebp), %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: je .LBB9_21
; X86-NEXT: # %bb.18: # %udiv-bb1
; X86-NEXT: movl 24(%ebp), %eax
@@ -2751,8 +2760,7 @@ define i128 @div_by_67(i128 %x) nounwind {
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl 32(%ebp), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
@@ -2765,20 +2773,20 @@ define i128 @div_by_67(i128 %x) nounwind {
; X86-NEXT: negb %al
; X86-NEXT: movsbl %al, %eax
; X86-NEXT: movl 136(%esp,%eax), %edx
-; X86-NEXT: movl 140(%esp,%eax), %edi
-; X86-NEXT: shldl %cl, %edx, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 128(%esp,%eax), %edi
+; X86-NEXT: movl 140(%esp,%eax), %esi
+; X86-NEXT: shldl %cl, %edx, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl 128(%esp,%eax), %esi
; X86-NEXT: movl 132(%esp,%eax), %eax
; X86-NEXT: shldl %cl, %eax, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shldl %cl, %edi, %eax
+; X86-NEXT: shldl %cl, %esi, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shll %cl, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: addl $1, %ebx
-; X86-NEXT: adcl $0, %esi
+; X86-NEXT: shll %cl, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: addl $1, %ebx
+; X86-NEXT: adcl $0, %edi
+; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jb .LBB9_19
@@ -2800,39 +2808,39 @@ define i128 @div_by_67(i128 %x) nounwind {
; X86-NEXT: shrb $3, %al
; X86-NEXT: andb $12, %al
; X86-NEXT: movzbl %al, %edi
-; X86-NEXT: movl 92(%esp,%edi), %eax
+; X86-NEXT: movl 92(%esp,%edi), %esi
; X86-NEXT: movl 88(%esp,%edi), %ebx
-; X86-NEXT: movl %ebx, %esi
-; X86-NEXT: shrdl %cl, %eax, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl 80(%esp,%edi), %esi
-; X86-NEXT: movl 84(%esp,%edi), %edi
-; X86-NEXT: movl %edi, %edx
-; X86-NEXT: shrdl %cl, %ebx, %edx
+; X86-NEXT: movl %ebx, %edx
+; X86-NEXT: shrdl %cl, %esi, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shrl %cl, %eax
+; X86-NEXT: movl 80(%esp,%edi), %edx
+; X86-NEXT: movl 84(%esp,%edi), %edi
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: shrdl %cl, %ebx, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrl %cl, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: # kill: def $cl killed $cl killed $ecx
-; X86-NEXT: shrdl %cl, %edi, %esi
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $67, %eax
-; X86-NEXT: addl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, %eax
-; X86-NEXT: adcl $-1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrdl %cl, %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $67, %ecx
+; X86-NEXT: addl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl $0, %ecx
+; X86-NEXT: adcl $-1, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB9_16: # %udiv-do-while
@@ -2841,76 +2849,78 @@ define i128 @div_by_67(i128 %x) nounwind {
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: shldl $1, %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
-; X86-NEXT: shldl $1, %edi, %ebx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $1, %edx, %edi
-; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: shldl $1, %ecx, %eax
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %esi, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shldl $1, %eax, %ecx
-; X86-NEXT: orl %esi, %ecx
+; X86-NEXT: shldl $1, %eax, %esi
+; X86-NEXT: shldl $1, %edx, %eax
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $1, %edx, %ecx
+; X86-NEXT: orl %edi, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shldl $1, %ecx, %eax
-; X86-NEXT: orl %esi, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: orl %edi, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: addl %ecx, %ecx
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; X86-NEXT: cmpl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: sbbl %edi, %ecx
+; X86-NEXT: sbbl %esi, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl %ebx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: andl $1, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl $67, %eax
-; X86-NEXT: andl %eax, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: andl $1, %edx
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sbbl $0, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; X86-NEXT: movl $67, %edx
+; X86-NEXT: andl %edx, %ecx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sbbl $0, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: sbbl $0, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: sbbl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: addl $-1, %ebx
; X86-NEXT: adcl $-1, %edi
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: adcl $-1, %edx
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: adcl $-1, %eax
; X86-NEXT: adcl $-1, %esi
; X86-NEXT: movl %edi, %ecx
; X86-NEXT: orl %esi, %ecx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: orl %edx, %ebx
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: orl %eax, %ebx
; X86-NEXT: orl %ecx, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: jne .LBB9_16
; X86-NEXT: .LBB9_17: # %udiv-loop-exit
-; X86-NEXT: shldl $1, %ecx, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shldl $1, %ecx, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: shldl $1, %edx, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: shldl $1, %eax, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: leal (%esi,%eax,2), %edi
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: leal (%edx,%eax,2), %edx
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: .LBB9_21: # %udiv-end
-; X86-NEXT: movl %edi, (%eax)
+; X86-NEXT: movl %edx, (%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 4(%eax)
; X86-NEXT: movl %ecx, 8(%eax)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
@@ -2926,13 +2936,12 @@ define i128 @div_by_67(i128 %x) nounwind {
; X86-NEXT: jmp .LBB9_11
; X86-NEXT: .LBB9_19:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB9_17
; X86-NEXT: .LBB9_14:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: jmp .LBB9_21
;
; X64-LABEL: div_by_67:
diff --git a/llvm/test/CodeGen/X86/lea-opt-cse4.ll b/llvm/test/CodeGen/X86/lea-opt-cse4.ll
index 40868d11eb7d5..6c972e811c9a3 100644
--- a/llvm/test/CodeGen/X86/lea-opt-cse4.ll
+++ b/llvm/test/CodeGen/X86/lea-opt-cse4.ll
@@ -80,23 +80,23 @@ define void @foo_loop(ptr nocapture %ctx, i32 %n) local_unnamed_addr #0 {
; X86-NEXT: pushl %esi
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %esi, -8
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB1_1: # %loop
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: movl (%eax), %edx
+; X86-NEXT: movl (%eax), %esi
; X86-NEXT: movl 16(%eax), %ecx
-; X86-NEXT: leal 1(%edx,%ecx), %edx
-; X86-NEXT: movl %edx, 12(%eax)
-; X86-NEXT: decl %esi
+; X86-NEXT: leal 1(%esi,%ecx), %esi
+; X86-NEXT: movl %esi, 12(%eax)
+; X86-NEXT: decl %edx
; X86-NEXT: jne .LBB1_1
; X86-NEXT: # %bb.2: # %exit
-; X86-NEXT: leal (%ecx,%ecx), %esi
-; X86-NEXT: addl %esi, %edx
-; X86-NEXT: addl %esi, %ecx
+; X86-NEXT: leal (%ecx,%ecx), %edx
+; X86-NEXT: addl %edx, %esi
; X86-NEXT: addl %edx, %ecx
; X86-NEXT: addl %esi, %ecx
+; X86-NEXT: addl %edx, %ecx
; X86-NEXT: movl %ecx, 16(%eax)
; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 4
diff --git a/llvm/test/CodeGen/X86/legalize-shift-64.ll b/llvm/test/CodeGen/X86/legalize-shift-64.ll
index 53208de7ea27e..372c8a15ebf8a 100644
--- a/llvm/test/CodeGen/X86/legalize-shift-64.ll
+++ b/llvm/test/CodeGen/X86/legalize-shift-64.ll
@@ -97,24 +97,24 @@ define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) {
; CHECK-NEXT: shll %cl, %edi
; CHECK-NEXT: shldl %cl, %ebx, %esi
; CHECK-NEXT: testb $32, %cl
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
; CHECK-NEXT: je .LBB4_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: movl %edi, %esi
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: .LBB4_2:
-; CHECK-NEXT: movl %edx, %ebx
+; CHECK-NEXT: movl %edx, %ebp
; CHECK-NEXT: movb %ch, %cl
-; CHECK-NEXT: shll %cl, %ebx
-; CHECK-NEXT: shldl %cl, %edx, %ebp
+; CHECK-NEXT: shll %cl, %ebp
+; CHECK-NEXT: shldl %cl, %edx, %ebx
; CHECK-NEXT: testb $32, %ch
; CHECK-NEXT: je .LBB4_4
; CHECK-NEXT: # %bb.3:
-; CHECK-NEXT: movl %ebx, %ebp
-; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: movl %ebp, %ebx
+; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: .LBB4_4:
-; CHECK-NEXT: movl %ebp, 12(%eax)
-; CHECK-NEXT: movl %ebx, 8(%eax)
+; CHECK-NEXT: movl %ebx, 12(%eax)
+; CHECK-NEXT: movl %ebp, 8(%eax)
; CHECK-NEXT: movl %esi, 4(%eax)
; CHECK-NEXT: movl %edi, (%eax)
; CHECK-NEXT: popl %esi
diff --git a/llvm/test/CodeGen/X86/llc-pipeline-npm.ll b/llvm/test/CodeGen/X86/llc-pipeline-npm.ll
index d02b6e9ff4c9f..83b511eb590ac 100644
--- a/llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+++ b/llvm/test/CodeGen/X86/llc-pipeline-npm.ll
@@ -154,9 +154,9 @@
; O2-NEXT: process-imp-defs
; O2-NEXT: unreachable-mbb-elimination
; O2-NEXT: require<live-vars>
+; O2-NEXT: require<live-intervals>
; O2-NEXT: require<machine-loops>
; O2-NEXT: phi-node-elimination
-; O2-NEXT: require<live-intervals>
; O2-NEXT: two-address-instruction
; O2-NEXT: register-coalescer
; O2-NEXT: rename-independent-subregs
@@ -360,9 +360,9 @@
; O3-WINDOWS-NEXT: process-imp-defs
; O3-WINDOWS-NEXT: unreachable-mbb-elimination
; O3-WINDOWS-NEXT: require<live-vars>
+; O3-WINDOWS-NEXT: require<live-intervals>
; O3-WINDOWS-NEXT: require<machine-loops>
; O3-WINDOWS-NEXT: phi-node-elimination
-; O3-WINDOWS-NEXT: require<live-intervals>
; O3-WINDOWS-NEXT: two-address-instruction
; O3-WINDOWS-NEXT: register-coalescer
; O3-WINDOWS-NEXT: rename-independent-subregs
diff --git a/llvm/test/CodeGen/X86/masked_gather_scatter.ll b/llvm/test/CodeGen/X86/masked_gather_scatter.ll
index 18ba9c6b91c86..a751581f003ac 100644
--- a/llvm/test/CodeGen/X86/masked_gather_scatter.ll
+++ b/llvm/test/CodeGen/X86/masked_gather_scatter.ll
@@ -3047,27 +3047,27 @@ define <4 x i64> @test_pr28312(<4 x ptr> %p1, <4 x i1> %k, <4 x i1> %k2,<4 x i64
; X86-KNL-NEXT: vptestmd %zmm1, %zmm1, %k0
; X86-KNL-NEXT: kmovw %k0, %ebx
; X86-KNL-NEXT: testb $1, %bl
-; X86-KNL-NEXT: vmovd %xmm0, %eax
+; X86-KNL-NEXT: vmovd %xmm0, %edx
; X86-KNL-NEXT: # implicit-def: $ymm1
; X86-KNL-NEXT: je .LBB42_2
; X86-KNL-NEXT: # %bb.1: # %cond.load
; X86-KNL-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; X86-KNL-NEXT: .LBB42_2: # %else
; X86-KNL-NEXT: testb $2, %bl
-; X86-KNL-NEXT: vpextrd $1, %xmm0, %ecx
+; X86-KNL-NEXT: vpextrd $1, %xmm0, %eax
; X86-KNL-NEXT: je .LBB42_4
; X86-KNL-NEXT: # %bb.3: # %cond.load1
-; X86-KNL-NEXT: vpinsrd $2, (%ecx), %xmm1, %xmm2
-; X86-KNL-NEXT: vpinsrd $3, 4(%ecx), %xmm2, %xmm2
+; X86-KNL-NEXT: vpinsrd $2, (%eax), %xmm1, %xmm2
+; X86-KNL-NEXT: vpinsrd $3, 4(%eax), %xmm2, %xmm2
; X86-KNL-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7]
; X86-KNL-NEXT: .LBB42_4: # %else2
; X86-KNL-NEXT: testb $4, %bl
-; X86-KNL-NEXT: vpextrd $2, %xmm0, %edx
+; X86-KNL-NEXT: vpextrd $2, %xmm0, %ecx
; X86-KNL-NEXT: je .LBB42_6
; X86-KNL-NEXT: # %bb.5: # %cond.load4
-; X86-KNL-NEXT: vpbroadcastd (%edx), %ymm2
+; X86-KNL-NEXT: vpbroadcastd (%ecx), %ymm2
; X86-KNL-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4],ymm1[5,6,7]
-; X86-KNL-NEXT: vpbroadcastd 4(%edx), %ymm2
+; X86-KNL-NEXT: vpbroadcastd 4(%ecx), %ymm2
; X86-KNL-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm2[5],ymm1[6,7]
; X86-KNL-NEXT: .LBB42_6: # %else5
; X86-KNL-NEXT: testb $8, %bl
@@ -3131,15 +3131,15 @@ define <4 x i64> @test_pr28312(<4 x ptr> %p1, <4 x i1> %k, <4 x i1> %k2,<4 x i64
; X86-KNL-NEXT: testb $2, %bl
; X86-KNL-NEXT: je .LBB42_12
; X86-KNL-NEXT: .LBB42_11: # %cond.load17
-; X86-KNL-NEXT: vpinsrd $2, (%ecx), %xmm0, %xmm2
-; X86-KNL-NEXT: vpinsrd $3, 4(%ecx), %xmm2, %xmm2
+; X86-KNL-NEXT: vpinsrd $2, (%eax), %xmm0, %xmm2
+; X86-KNL-NEXT: vpinsrd $3, 4(%eax), %xmm2, %xmm2
; X86-KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7]
; X86-KNL-NEXT: testb $4, %bl
; X86-KNL-NEXT: je .LBB42_14
; X86-KNL-NEXT: .LBB42_13: # %cond.load23
-; X86-KNL-NEXT: vpbroadcastd (%edx), %ymm2
+; X86-KNL-NEXT: vpbroadcastd (%ecx), %ymm2
; X86-KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm2[4],ymm0[5,6,7]
-; X86-KNL-NEXT: vpbroadcastd 4(%edx), %ymm2
+; X86-KNL-NEXT: vpbroadcastd 4(%ecx), %ymm2
; X86-KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm2[5],ymm0[6,7]
; X86-KNL-NEXT: testb $8, %bl
; X86-KNL-NEXT: jne .LBB42_15
@@ -3149,15 +3149,15 @@ define <4 x i64> @test_pr28312(<4 x ptr> %p1, <4 x i1> %k, <4 x i1> %k2,<4 x i64
; X86-KNL-NEXT: testb $2, %bl
; X86-KNL-NEXT: je .LBB42_20
; X86-KNL-NEXT: .LBB42_19: # %cond.load42
-; X86-KNL-NEXT: vpinsrd $2, (%ecx), %xmm2, %xmm3
-; X86-KNL-NEXT: vpinsrd $3, 4(%ecx), %xmm3, %xmm3
+; X86-KNL-NEXT: vpinsrd $2, (%eax), %xmm2, %xmm3
+; X86-KNL-NEXT: vpinsrd $3, 4(%eax), %xmm3, %xmm3
; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7]
; X86-KNL-NEXT: testb $4, %bl
; X86-KNL-NEXT: je .LBB42_22
; X86-KNL-NEXT: .LBB42_21: # %cond.load48
-; X86-KNL-NEXT: vpbroadcastd (%edx), %ymm3
+; X86-KNL-NEXT: vpbroadcastd (%ecx), %ymm3
; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4],ymm2[5,6,7]
-; X86-KNL-NEXT: vpbroadcastd 4(%edx), %ymm3
+; X86-KNL-NEXT: vpbroadcastd 4(%ecx), %ymm3
; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4],ymm3[5],ymm2[6,7]
; X86-KNL-NEXT: testb $8, %bl
; X86-KNL-NEXT: jne .LBB42_23
diff --git a/llvm/test/CodeGen/X86/opt-pipeline.ll b/llvm/test/CodeGen/X86/opt-pipeline.ll
index 47d97871274ae..3e7840a7014d2 100644
--- a/llvm/test/CodeGen/X86/opt-pipeline.ll
+++ b/llvm/test/CodeGen/X86/opt-pipeline.ll
@@ -140,9 +140,9 @@
; CHECK-NEXT: Process Implicit Definitions
; CHECK-NEXT: Remove unreachable machine basic blocks
; CHECK-NEXT: Live Variable Analysis
-; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
+; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
diff --git a/llvm/test/CodeGen/X86/phi-elim-undef-livevars.mir b/llvm/test/CodeGen/X86/phi-elim-undef-livevars.mir
index ab27fe8550a00..c8d25f2cb618f 100644
--- a/llvm/test/CodeGen/X86/phi-elim-undef-livevars.mir
+++ b/llvm/test/CodeGen/X86/phi-elim-undef-livevars.mir
@@ -33,7 +33,7 @@ body: |
; CHECK-NEXT: JMP_1 %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY killed [[DEF]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[DEF]]
; CHECK-NEXT: $xmm0 = COPY killed [[COPY]]
; CHECK-NEXT: RET 0, implicit killed $xmm0
; CHECK-NEXT: {{ $}}
@@ -41,7 +41,7 @@ body: |
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[V_SET0_:%[0-9]+]]:vr128 = V_SET0
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr128 = COPY killed [[V_SET0_]]
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr128 = COPY [[V_SET0_]]
; CHECK-NEXT: JMP_1 %bb.3
bb.0:
successors: %bb.1, %bb.4
diff --git a/llvm/test/CodeGen/X86/phielim-undef.mir b/llvm/test/CodeGen/X86/phielim-undef.mir
index 1200449b49c78..ccbda8232ffb6 100644
--- a/llvm/test/CodeGen/X86/phielim-undef.mir
+++ b/llvm/test/CodeGen/X86/phielim-undef.mir
@@ -26,14 +26,14 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY killed [[MOV16rm]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY [[MOV16rm]]
; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead %5:gr16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY killed [[COPY]]
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]]
; CHECK-NEXT: TEST8ri undef %7:gr8, 1, implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed $eflags
; CHECK-NEXT: JMP_1 %bb.3
@@ -42,14 +42,14 @@ body: |
; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
- ; CHECK-NEXT: dead %9:gr16 = COPY killed [[MOV32r0_]].sub_16bit
+ ; CHECK-NEXT: dead [[COPY2:%[0-9]+]]:gr16 = COPY killed [[MOV32r0_]].sub_16bit
; CHECK-NEXT: CMP16ri8 killed [[COPY1]], 0, implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.6, 5, implicit killed $eflags
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr16 = IMPLICIT_DEF
; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
diff --git a/llvm/test/CodeGen/X86/pr38539.ll b/llvm/test/CodeGen/X86/pr38539.ll
index 722154e3bdd11..b4777aede1e20 100644
--- a/llvm/test/CodeGen/X86/pr38539.ll
+++ b/llvm/test/CodeGen/X86/pr38539.ll
@@ -24,8 +24,8 @@ define void @f() nounwind {
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $80, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movzbl (%eax), %eax
; X86-NEXT: movzbl (%eax), %ecx
; X86-NEXT: movzbl %al, %eax
@@ -37,18 +37,18 @@ define void @f() nounwind {
; X86-NEXT: sarl $30, %ecx
; X86-NEXT: sarl $31, %eax
; X86-NEXT: xorl %eax, %edx
-; X86-NEXT: xorl %eax, %esi
+; X86-NEXT: xorl %eax, %ebx
; X86-NEXT: shrdl $1, %eax, %ecx
-; X86-NEXT: xorl %ecx, %ebx
-; X86-NEXT: subl %ecx, %ebx
-; X86-NEXT: sbbl %eax, %esi
+; X86-NEXT: xorl %ecx, %esi
+; X86-NEXT: subl %ecx, %esi
+; X86-NEXT: sbbl %eax, %ebx
; X86-NEXT: sbbl %eax, %edx
; X86-NEXT: movl %edx, %eax
-; X86-NEXT: shldl $30, %esi, %eax
-; X86-NEXT: movl %ebx, %edi
-; X86-NEXT: movl %ebx, %ecx
-; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: shrdl $2, %esi, %ecx
+; X86-NEXT: shldl $30, %ebx, %eax
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: movl %esi, %ecx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: shrdl $2, %ebx, %ecx
; X86-NEXT: testl %eax, %eax
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jne .LBB0_1
diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
index 60ebb4bd41ebb..b7c49b4090f52 100644
--- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
+++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
@@ -95,23 +95,23 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne LBB0_11
; CHECK-NEXT: ## %bb.12: ## %while.body200.preheader
-; CHECK-NEXT: xorl %r12d, %r12d
+; CHECK-NEXT: xorl %r13d, %r13d
; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx
; CHECK-NEXT: leaq LJTI0_1(%rip), %r14
; CHECK-NEXT: movb $1, %sil
; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
-; CHECK-NEXT: xorl %r13d, %r13d
+; CHECK-NEXT: xorl %r12d, %r12d
; CHECK-NEXT: jmp LBB0_13
; CHECK-NEXT: LBB0_43: ## %while.cond1037.preheader
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: testb %r12b, %r12b
+; CHECK-NEXT: testb %r13b, %r13b
; CHECK-NEXT: je LBB0_54
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: LBB0_20: ## %while.cond197.backedge
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: decl %ebp
; CHECK-NEXT: testl %ebp, %ebp
-; CHECK-NEXT: movl %ebx, %r13d
+; CHECK-NEXT: movl %ebx, %r12d
; CHECK-NEXT: jle LBB0_21
; CHECK-NEXT: LBB0_13: ## %while.body200
; CHECK-NEXT: ## =>This Loop Header: Depth=1
@@ -127,12 +127,12 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: jmpq *%rax
; CHECK-NEXT: LBB0_25: ## %sw.bb474
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: testb %r12b, %r12b
+; CHECK-NEXT: testb %r13b, %r13b
; CHECK-NEXT: ## implicit-def: $r15
; CHECK-NEXT: jne LBB0_33
; CHECK-NEXT: ## %bb.26: ## %do.body479.preheader
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: testb %r12b, %r12b
+; CHECK-NEXT: testb %r13b, %r13b
; CHECK-NEXT: ## implicit-def: $r15
; CHECK-NEXT: jne LBB0_33
; CHECK-NEXT: ## %bb.27: ## %land.rhs485.preheader
@@ -143,7 +143,7 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: LBB0_31: ## %do.body479.backedge
; CHECK-NEXT: ## in Loop: Header=BB0_28 Depth=2
; CHECK-NEXT: leaq 1(%r15), %rax
-; CHECK-NEXT: testb %r12b, %r12b
+; CHECK-NEXT: testb %r13b, %r13b
; CHECK-NEXT: je LBB0_32
; CHECK-NEXT: LBB0_28: ## %land.rhs485
; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1
@@ -202,7 +202,7 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: incq %r15
; CHECK-NEXT: LBB0_33: ## %if.end517
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: leal -324(%r13), %eax
+; CHECK-NEXT: leal -324(%r12), %eax
; CHECK-NEXT: cmpl $59, %eax
; CHECK-NEXT: ja LBB0_34
; CHECK-NEXT: ## %bb.56: ## %if.end517
@@ -212,11 +212,11 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: jb LBB0_37
; CHECK-NEXT: LBB0_34: ## %if.end517
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: cmpl $11, %r13d
+; CHECK-NEXT: cmpl $11, %r12d
; CHECK-NEXT: je LBB0_37
; CHECK-NEXT: ## %bb.35: ## %if.end517
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: cmpl $24, %r13d
+; CHECK-NEXT: cmpl $24, %r12d
; CHECK-NEXT: je LBB0_37
; CHECK-NEXT: ## %bb.36: ## %if.then532
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
@@ -226,7 +226,7 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: LBB0_37: ## %for.cond534
; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
-; CHECK-NEXT: testb %r12b, %r12b
+; CHECK-NEXT: testb %r13b, %r13b
; CHECK-NEXT: jne LBB0_37
; CHECK-NEXT: ## %bb.38: ## %for.cond542.preheader
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
diff --git a/llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll b/llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
index 925a1f165396b..1d2bfd499eadd 100644
--- a/llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
+++ b/llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
@@ -364,13 +364,13 @@ define <2 x i64> @strict_vector_fptoui_v2f64_to_v2i64(<2 x double> %a) #0 {
;
; AVX-64-LABEL: strict_vector_fptoui_v2f64_to_v2i64:
; AVX-64: # %bb.0:
-; AVX-64-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
-; AVX-64-NEXT: vcomisd %xmm1, %xmm0
-; AVX-64-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; AVX-64-NEXT: vmovsd {{.*#+}} xmm2 = [9.2233720368547758E+18,0.0E+0]
+; AVX-64-NEXT: vcomisd %xmm2, %xmm0
+; AVX-64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX-64-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; AVX-64-NEXT: jb .LBB1_2
; AVX-64-NEXT: # %bb.1:
-; AVX-64-NEXT: vmovapd %xmm1, %xmm3
+; AVX-64-NEXT: vmovapd %xmm2, %xmm3
; AVX-64-NEXT: .LBB1_2:
; AVX-64-NEXT: vsubsd %xmm3, %xmm0, %xmm3
; AVX-64-NEXT: vcvttsd2si %xmm3, %rax
@@ -380,12 +380,12 @@ define <2 x i64> @strict_vector_fptoui_v2f64_to_v2i64(<2 x double> %a) #0 {
; AVX-64-NEXT: xorq %rax, %rcx
; AVX-64-NEXT: vmovq %rcx, %xmm3
; AVX-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX-64-NEXT: vcomisd %xmm1, %xmm0
+; AVX-64-NEXT: vcomisd %xmm2, %xmm0
; AVX-64-NEXT: jb .LBB1_4
; AVX-64-NEXT: # %bb.3:
-; AVX-64-NEXT: vmovapd %xmm1, %xmm2
+; AVX-64-NEXT: vmovapd %xmm2, %xmm1
; AVX-64-NEXT: .LBB1_4:
-; AVX-64-NEXT: vsubsd %xmm2, %xmm0, %xmm0
+; AVX-64-NEXT: vsubsd %xmm1, %xmm0, %xmm0
; AVX-64-NEXT: vcvttsd2si %xmm0, %rax
; AVX-64-NEXT: setae %cl
; AVX-64-NEXT: movzbl %cl, %ecx
@@ -1035,13 +1035,13 @@ define <2 x i64> @strict_vector_fptoui_v2f32_to_v2i64(<2 x float> %a) #0 {
;
; AVX-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64:
; AVX-64: # %bb.0:
-; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
-; AVX-64-NEXT: vcomiss %xmm1, %xmm0
-; AVX-64-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; AVX-64-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; AVX-64-NEXT: vcomiss %xmm2, %xmm0
+; AVX-64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; AVX-64-NEXT: jb .LBB4_2
; AVX-64-NEXT: # %bb.1:
-; AVX-64-NEXT: vmovaps %xmm1, %xmm3
+; AVX-64-NEXT: vmovaps %xmm2, %xmm3
; AVX-64-NEXT: .LBB4_2:
; AVX-64-NEXT: vsubss %xmm3, %xmm0, %xmm3
; AVX-64-NEXT: vcvttss2si %xmm3, %rax
@@ -1051,12 +1051,12 @@ define <2 x i64> @strict_vector_fptoui_v2f32_to_v2i64(<2 x float> %a) #0 {
; AVX-64-NEXT: xorq %rax, %rcx
; AVX-64-NEXT: vmovq %rcx, %xmm3
; AVX-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX-64-NEXT: vcomiss %xmm1, %xmm0
+; AVX-64-NEXT: vcomiss %xmm2, %xmm0
; AVX-64-NEXT: jb .LBB4_4
; AVX-64-NEXT: # %bb.3:
-; AVX-64-NEXT: vmovaps %xmm1, %xmm2
+; AVX-64-NEXT: vmovaps %xmm2, %xmm1
; AVX-64-NEXT: .LBB4_4:
-; AVX-64-NEXT: vsubss %xmm2, %xmm0, %xmm0
+; AVX-64-NEXT: vsubss %xmm1, %xmm0, %xmm0
; AVX-64-NEXT: vcvttss2si %xmm0, %rax
; AVX-64-NEXT: setae %cl
; AVX-64-NEXT: movzbl %cl, %ecx
@@ -1347,13 +1347,13 @@ define <2 x i64> @strict_vector_fptoui_v2f32_to_v2i64_load128(ptr %x) strictfp {
; AVX-64: # %bb.0:
; AVX-64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-64-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
-; AVX-64-NEXT: vcomiss %xmm1, %xmm3
-; AVX-64-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; AVX-64-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; AVX-64-NEXT: vcomiss %xmm2, %xmm3
+; AVX-64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-64-NEXT: vxorps %xmm4, %xmm4, %xmm4
; AVX-64-NEXT: jb .LBB5_2
; AVX-64-NEXT: # %bb.1:
-; AVX-64-NEXT: vmovaps %xmm1, %xmm4
+; AVX-64-NEXT: vmovaps %xmm2, %xmm4
; AVX-64-NEXT: .LBB5_2:
; AVX-64-NEXT: vsubss %xmm4, %xmm3, %xmm3
; AVX-64-NEXT: vcvttss2si %xmm3, %rax
@@ -1362,12 +1362,12 @@ define <2 x i64> @strict_vector_fptoui_v2f32_to_v2i64_load128(ptr %x) strictfp {
; AVX-64-NEXT: shlq $63, %rcx
; AVX-64-NEXT: xorq %rax, %rcx
; AVX-64-NEXT: vmovq %rcx, %xmm3
-; AVX-64-NEXT: vcomiss %xmm1, %xmm0
+; AVX-64-NEXT: vcomiss %xmm2, %xmm0
; AVX-64-NEXT: jb .LBB5_4
; AVX-64-NEXT: # %bb.3:
-; AVX-64-NEXT: vmovaps %xmm1, %xmm2
+; AVX-64-NEXT: vmovaps %xmm2, %xmm1
; AVX-64-NEXT: .LBB5_4:
-; AVX-64-NEXT: vsubss %xmm2, %xmm0, %xmm0
+; AVX-64-NEXT: vsubss %xmm1, %xmm0, %xmm0
; AVX-64-NEXT: vcvttss2si %xmm0, %rax
; AVX-64-NEXT: setae %cl
; AVX-64-NEXT: movzbl %cl, %ecx
@@ -2526,13 +2526,13 @@ define <2 x i1> @strict_vector_fptoui_v2f64_to_v2i1(<2 x double> %a) #0 {
;
; AVX-64-LABEL: strict_vector_fptoui_v2f64_to_v2i1:
; AVX-64: # %bb.0:
-; AVX-64-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
-; AVX-64-NEXT: vcomisd %xmm1, %xmm0
-; AVX-64-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; AVX-64-NEXT: vmovsd {{.*#+}} xmm2 = [9.2233720368547758E+18,0.0E+0]
+; AVX-64-NEXT: vcomisd %xmm2, %xmm0
+; AVX-64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX-64-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; AVX-64-NEXT: jb .LBB19_2
; AVX-64-NEXT: # %bb.1:
-; AVX-64-NEXT: vmovapd %xmm1, %xmm3
+; AVX-64-NEXT: vmovapd %xmm2, %xmm3
; AVX-64-NEXT: .LBB19_2:
; AVX-64-NEXT: vsubsd %xmm3, %xmm0, %xmm3
; AVX-64-NEXT: vcvttsd2si %xmm3, %rax
@@ -2542,12 +2542,12 @@ define <2 x i1> @strict_vector_fptoui_v2f64_to_v2i1(<2 x double> %a) #0 {
; AVX-64-NEXT: xorq %rax, %rcx
; AVX-64-NEXT: vmovq %rcx, %xmm3
; AVX-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX-64-NEXT: vcomisd %xmm1, %xmm0
+; AVX-64-NEXT: vcomisd %xmm2, %xmm0
; AVX-64-NEXT: jb .LBB19_4
; AVX-64-NEXT: # %bb.3:
-; AVX-64-NEXT: vmovapd %xmm1, %xmm2
+; AVX-64-NEXT: vmovapd %xmm2, %xmm1
; AVX-64-NEXT: .LBB19_4:
-; AVX-64-NEXT: vsubsd %xmm2, %xmm0, %xmm0
+; AVX-64-NEXT: vsubsd %xmm1, %xmm0, %xmm0
; AVX-64-NEXT: vcvttsd2si %xmm0, %rax
; AVX-64-NEXT: setae %cl
; AVX-64-NEXT: movzbl %cl, %ecx
@@ -2921,13 +2921,13 @@ define <2 x i1> @strict_vector_fptoui_v2f32_to_v2i1(<2 x float> %a) #0 {
;
; AVX-64-LABEL: strict_vector_fptoui_v2f32_to_v2i1:
; AVX-64: # %bb.0:
-; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
-; AVX-64-NEXT: vcomiss %xmm1, %xmm0
-; AVX-64-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; AVX-64-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; AVX-64-NEXT: vcomiss %xmm2, %xmm0
+; AVX-64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-64-NEXT: vxorps %xmm3, %xmm3, %xmm3
; AVX-64-NEXT: jb .LBB21_2
; AVX-64-NEXT: # %bb.1:
-; AVX-64-NEXT: vmovaps %xmm1, %xmm3
+; AVX-64-NEXT: vmovaps %xmm2, %xmm3
; AVX-64-NEXT: .LBB21_2:
; AVX-64-NEXT: vsubss %xmm3, %xmm0, %xmm3
; AVX-64-NEXT: vcvttss2si %xmm3, %rax
@@ -2937,12 +2937,12 @@ define <2 x i1> @strict_vector_fptoui_v2f32_to_v2i1(<2 x float> %a) #0 {
; AVX-64-NEXT: xorq %rax, %rcx
; AVX-64-NEXT: vmovq %rcx, %xmm3
; AVX-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX-64-NEXT: vcomiss %xmm1, %xmm0
+; AVX-64-NEXT: vcomiss %xmm2, %xmm0
; AVX-64-NEXT: jb .LBB21_4
; AVX-64-NEXT: # %bb.3:
-; AVX-64-NEXT: vmovaps %xmm1, %xmm2
+; AVX-64-NEXT: vmovaps %xmm2, %xmm1
; AVX-64-NEXT: .LBB21_4:
-; AVX-64-NEXT: vsubss %xmm2, %xmm0, %xmm0
+; AVX-64-NEXT: vsubss %xmm1, %xmm0, %xmm0
; AVX-64-NEXT: vcvttss2si %xmm0, %rax
; AVX-64-NEXT: setae %cl
; AVX-64-NEXT: movzbl %cl, %ecx
diff --git a/llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll b/llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
index 8cbf576677d1a..8c1b008bc473e 100644
--- a/llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
+++ b/llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
@@ -306,13 +306,13 @@ define <4 x i64> @strict_vector_fptoui_v4f64_to_v4i64(<4 x double> %a) #0 {
; AVX-64-LABEL: strict_vector_fptoui_v4f64_to_v4i64:
; AVX-64: # %bb.0:
; AVX-64-NEXT: vextractf128 $1, %ymm0, %xmm3
-; AVX-64-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
-; AVX-64-NEXT: vcomisd %xmm1, %xmm3
-; AVX-64-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; AVX-64-NEXT: vmovsd {{.*#+}} xmm2 = [9.2233720368547758E+18,0.0E+0]
+; AVX-64-NEXT: vcomisd %xmm2, %xmm3
+; AVX-64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX-64-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; AVX-64-NEXT: jb .LBB1_2
; AVX-64-NEXT: # %bb.1:
-; AVX-64-NEXT: vmovapd %xmm1, %xmm4
+; AVX-64-NEXT: vmovapd %xmm2, %xmm4
; AVX-64-NEXT: .LBB1_2:
; AVX-64-NEXT: vsubsd %xmm4, %xmm3, %xmm4
; AVX-64-NEXT: vcvttsd2si %xmm4, %rcx
@@ -321,11 +321,11 @@ define <4 x i64> @strict_vector_fptoui_v4f64_to_v4i64(<4 x double> %a) #0 {
; AVX-64-NEXT: shlq $63, %rax
; AVX-64-NEXT: xorq %rcx, %rax
; AVX-64-NEXT: vshufpd {{.*#+}} xmm4 = xmm3[1,0]
-; AVX-64-NEXT: vcomisd %xmm1, %xmm4
+; AVX-64-NEXT: vcomisd %xmm2, %xmm4
; AVX-64-NEXT: vxorpd %xmm5, %xmm5, %xmm5
; AVX-64-NEXT: jb .LBB1_4
; AVX-64-NEXT: # %bb.3:
-; AVX-64-NEXT: vmovapd %xmm1, %xmm5
+; AVX-64-NEXT: vmovapd %xmm2, %xmm5
; AVX-64-NEXT: .LBB1_4:
; AVX-64-NEXT: vmovq %rax, %xmm3
; AVX-64-NEXT: vsubsd %xmm5, %xmm4, %xmm4
@@ -335,11 +335,11 @@ define <4 x i64> @strict_vector_fptoui_v4f64_to_v4i64(<4 x double> %a) #0 {
; AVX-64-NEXT: shlq $63, %rcx
; AVX-64-NEXT: xorq %rax, %rcx
; AVX-64-NEXT: vmovq %rcx, %xmm4
-; AVX-64-NEXT: vcomisd %xmm1, %xmm0
+; AVX-64-NEXT: vcomisd %xmm2, %xmm0
; AVX-64-NEXT: vxorpd %xmm5, %xmm5, %xmm5
; AVX-64-NEXT: jb .LBB1_6
; AVX-64-NEXT: # %bb.5:
-; AVX-64-NEXT: vmovapd %xmm1, %xmm5
+; AVX-64-NEXT: vmovapd %xmm2, %xmm5
; AVX-64-NEXT: .LBB1_6:
; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; AVX-64-NEXT: vsubsd %xmm5, %xmm0, %xmm4
@@ -350,12 +350,12 @@ define <4 x i64> @strict_vector_fptoui_v4f64_to_v4i64(<4 x double> %a) #0 {
; AVX-64-NEXT: xorq %rax, %rcx
; AVX-64-NEXT: vmovq %rcx, %xmm4
; AVX-64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX-64-NEXT: vcomisd %xmm1, %xmm0
+; AVX-64-NEXT: vcomisd %xmm2, %xmm0
; AVX-64-NEXT: jb .LBB1_8
; AVX-64-NEXT: # %bb.7:
-; AVX-64-NEXT: vmovapd %xmm1, %xmm2
+; AVX-64-NEXT: vmovapd %xmm2, %xmm1
; AVX-64-NEXT: .LBB1_8:
-; AVX-64-NEXT: vsubsd %xmm2, %xmm0, %xmm0
+; AVX-64-NEXT: vsubsd %xmm1, %xmm0, %xmm0
; AVX-64-NEXT: vcvttsd2si %xmm0, %rax
; AVX-64-NEXT: setae %cl
; AVX-64-NEXT: movzbl %cl, %ecx
@@ -837,13 +837,13 @@ define <4 x i64> @strict_vector_fptoui_v4f32_to_v4i64(<4 x float> %a) #0 {
; AVX-64-LABEL: strict_vector_fptoui_v4f32_to_v4i64:
; AVX-64: # %bb.0:
; AVX-64-NEXT: vshufps {{.*#+}} xmm3 = xmm0[3,3,3,3]
-; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
-; AVX-64-NEXT: vcomiss %xmm1, %xmm3
-; AVX-64-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; AVX-64-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; AVX-64-NEXT: vcomiss %xmm2, %xmm3
+; AVX-64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-64-NEXT: vxorps %xmm4, %xmm4, %xmm4
; AVX-64-NEXT: jb .LBB3_2
; AVX-64-NEXT: # %bb.1:
-; AVX-64-NEXT: vmovaps %xmm1, %xmm4
+; AVX-64-NEXT: vmovaps %xmm2, %xmm4
; AVX-64-NEXT: .LBB3_2:
; AVX-64-NEXT: vsubss %xmm4, %xmm3, %xmm3
; AVX-64-NEXT: vcvttss2si %xmm3, %rcx
@@ -852,11 +852,11 @@ define <4 x i64> @strict_vector_fptoui_v4f32_to_v4i64(<4 x float> %a) #0 {
; AVX-64-NEXT: shlq $63, %rax
; AVX-64-NEXT: xorq %rcx, %rax
; AVX-64-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX-64-NEXT: vcomiss %xmm1, %xmm4
+; AVX-64-NEXT: vcomiss %xmm2, %xmm4
; AVX-64-NEXT: vxorps %xmm5, %xmm5, %xmm5
; AVX-64-NEXT: jb .LBB3_4
; AVX-64-NEXT: # %bb.3:
-; AVX-64-NEXT: vmovaps %xmm1, %xmm5
+; AVX-64-NEXT: vmovaps %xmm2, %xmm5
; AVX-64-NEXT: .LBB3_4:
; AVX-64-NEXT: vmovq %rax, %xmm3
; AVX-64-NEXT: vsubss %xmm5, %xmm4, %xmm4
@@ -866,11 +866,11 @@ define <4 x i64> @strict_vector_fptoui_v4f32_to_v4i64(<4 x float> %a) #0 {
; AVX-64-NEXT: shlq $63, %rcx
; AVX-64-NEXT: xorq %rax, %rcx
; AVX-64-NEXT: vmovq %rcx, %xmm4
-; AVX-64-NEXT: vcomiss %xmm1, %xmm0
+; AVX-64-NEXT: vcomiss %xmm2, %xmm0
; AVX-64-NEXT: vxorps %xmm5, %xmm5, %xmm5
; AVX-64-NEXT: jb .LBB3_6
; AVX-64-NEXT: # %bb.5:
-; AVX-64-NEXT: vmovaps %xmm1, %xmm5
+; AVX-64-NEXT: vmovaps %xmm2, %xmm5
; AVX-64-NEXT: .LBB3_6:
; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
; AVX-64-NEXT: vsubss %xmm5, %xmm0, %xmm4
@@ -881,12 +881,12 @@ define <4 x i64> @strict_vector_fptoui_v4f32_to_v4i64(<4 x float> %a) #0 {
; AVX-64-NEXT: xorq %rax, %rcx
; AVX-64-NEXT: vmovq %rcx, %xmm4
; AVX-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX-64-NEXT: vcomiss %xmm1, %xmm0
+; AVX-64-NEXT: vcomiss %xmm2, %xmm0
; AVX-64-NEXT: jb .LBB3_8
; AVX-64-NEXT: # %bb.7:
-; AVX-64-NEXT: vmovaps %xmm1, %xmm2
+; AVX-64-NEXT: vmovaps %xmm2, %xmm1
; AVX-64-NEXT: .LBB3_8:
-; AVX-64-NEXT: vsubss %xmm2, %xmm0, %xmm0
+; AVX-64-NEXT: vsubss %xmm1, %xmm0, %xmm0
; AVX-64-NEXT: vcvttss2si %xmm0, %rax
; AVX-64-NEXT: setae %cl
; AVX-64-NEXT: movzbl %cl, %ecx
diff --git a/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
index 25870f22ee98d..7b6eebc0440e9 100644
--- a/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
@@ -4747,14 +4747,14 @@ define <1 x i64> @constrained_vector_fptoui_v1i64_v1f32() #0 {
; AVX1-LABEL: constrained_vector_fptoui_v1i64_v1f32:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovss {{.*#+}} xmm0 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vcomiss %xmm0, %xmm1
-; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vmovss {{.*#+}} xmm2 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; AVX1-NEXT: vcomiss %xmm0, %xmm2
+; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: ja .LBB121_2
; AVX1-NEXT: # %bb.1: # %entry
-; AVX1-NEXT: vmovaps %xmm1, %xmm2
+; AVX1-NEXT: vmovaps %xmm2, %xmm1
; AVX1-NEXT: .LBB121_2: # %entry
-; AVX1-NEXT: vsubss %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vsubss %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vcvttss2si %xmm0, %rcx
; AVX1-NEXT: setbe %al
; AVX1-NEXT: movzbl %al, %eax
@@ -4811,13 +4811,13 @@ define <2 x i64> @constrained_vector_fptoui_v2i64_v2f32() #0 {
; AVX1-LABEL: constrained_vector_fptoui_v2i64_v2f32:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovss {{.*#+}} xmm2 = [4.3E+1,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vmovss {{.*#+}} xmm0 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vcomiss %xmm2, %xmm0
-; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; AVX1-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; AVX1-NEXT: vcomiss %xmm2, %xmm1
+; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vxorps %xmm3, %xmm3, %xmm3
; AVX1-NEXT: ja .LBB122_2
; AVX1-NEXT: # %bb.1: # %entry
-; AVX1-NEXT: vmovaps %xmm0, %xmm3
+; AVX1-NEXT: vmovaps %xmm1, %xmm3
; AVX1-NEXT: .LBB122_2: # %entry
; AVX1-NEXT: vsubss %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vcvttss2si %xmm2, %rax
@@ -4827,12 +4827,12 @@ define <2 x i64> @constrained_vector_fptoui_v2i64_v2f32() #0 {
; AVX1-NEXT: xorq %rax, %rcx
; AVX1-NEXT: vmovq %rcx, %xmm2
; AVX1-NEXT: vmovss {{.*#+}} xmm3 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vcomiss %xmm3, %xmm0
+; AVX1-NEXT: vcomiss %xmm3, %xmm1
; AVX1-NEXT: ja .LBB122_4
; AVX1-NEXT: # %bb.3: # %entry
-; AVX1-NEXT: vmovaps %xmm0, %xmm1
+; AVX1-NEXT: vmovaps %xmm1, %xmm0
; AVX1-NEXT: .LBB122_4: # %entry
-; AVX1-NEXT: vsubss %xmm1, %xmm3, %xmm0
+; AVX1-NEXT: vsubss %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vcvttss2si %xmm0, %rax
; AVX1-NEXT: setbe %cl
; AVX1-NEXT: movzbl %cl, %ecx
@@ -4912,13 +4912,13 @@ define <3 x i64> @constrained_vector_fptoui_v3i64_v3f32() #0 {
; AVX1-LABEL: constrained_vector_fptoui_v3i64_v3f32:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovss {{.*#+}} xmm2 = [4.4E+1,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vmovss {{.*#+}} xmm0 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vcomiss %xmm2, %xmm0
-; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; AVX1-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; AVX1-NEXT: vcomiss %xmm2, %xmm1
+; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vxorps %xmm3, %xmm3, %xmm3
; AVX1-NEXT: ja .LBB123_2
; AVX1-NEXT: # %bb.1: # %entry
-; AVX1-NEXT: vmovaps %xmm0, %xmm3
+; AVX1-NEXT: vmovaps %xmm1, %xmm3
; AVX1-NEXT: .LBB123_2: # %entry
; AVX1-NEXT: vsubss %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vcvttss2si %xmm2, %rcx
@@ -4927,11 +4927,11 @@ define <3 x i64> @constrained_vector_fptoui_v3i64_v3f32() #0 {
; AVX1-NEXT: shlq $63, %rax
; AVX1-NEXT: xorq %rcx, %rax
; AVX1-NEXT: vmovss {{.*#+}} xmm2 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vcomiss %xmm2, %xmm0
+; AVX1-NEXT: vcomiss %xmm2, %xmm1
; AVX1-NEXT: vxorps %xmm3, %xmm3, %xmm3
; AVX1-NEXT: ja .LBB123_4
; AVX1-NEXT: # %bb.3: # %entry
-; AVX1-NEXT: vmovaps %xmm0, %xmm3
+; AVX1-NEXT: vmovaps %xmm1, %xmm3
; AVX1-NEXT: .LBB123_4: # %entry
; AVX1-NEXT: vsubss %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vcvttss2si %xmm2, %rdx
@@ -4940,12 +4940,12 @@ define <3 x i64> @constrained_vector_fptoui_v3i64_v3f32() #0 {
; AVX1-NEXT: shlq $63, %rcx
; AVX1-NEXT: xorq %rdx, %rcx
; AVX1-NEXT: vmovss {{.*#+}} xmm2 = [4.3E+1,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vcomiss %xmm2, %xmm0
+; AVX1-NEXT: vcomiss %xmm2, %xmm1
; AVX1-NEXT: ja .LBB123_6
; AVX1-NEXT: # %bb.5: # %entry
-; AVX1-NEXT: vmovaps %xmm0, %xmm1
+; AVX1-NEXT: vmovaps %xmm1, %xmm0
; AVX1-NEXT: .LBB123_6: # %entry
-; AVX1-NEXT: vsubss %xmm1, %xmm2, %xmm0
+; AVX1-NEXT: vsubss %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vcvttss2si %xmm0, %rdx
; AVX1-NEXT: setbe %sil
; AVX1-NEXT: movzbl %sil, %esi
@@ -5044,13 +5044,13 @@ define <4 x i64> @constrained_vector_fptoui_v4i64_v4f32() #0 {
; AVX1-LABEL: constrained_vector_fptoui_v4i64_v4f32:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovss {{.*#+}} xmm2 = [4.5E+1,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vmovss {{.*#+}} xmm0 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vcomiss %xmm2, %xmm0
-; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; AVX1-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; AVX1-NEXT: vcomiss %xmm2, %xmm1
+; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vxorps %xmm3, %xmm3, %xmm3
; AVX1-NEXT: ja .LBB124_2
; AVX1-NEXT: # %bb.1: # %entry
-; AVX1-NEXT: vmovaps %xmm0, %xmm3
+; AVX1-NEXT: vmovaps %xmm1, %xmm3
; AVX1-NEXT: .LBB124_2: # %entry
; AVX1-NEXT: vsubss %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vcvttss2si %xmm2, %rcx
@@ -5059,11 +5059,11 @@ define <4 x i64> @constrained_vector_fptoui_v4i64_v4f32() #0 {
; AVX1-NEXT: shlq $63, %rax
; AVX1-NEXT: xorq %rcx, %rax
; AVX1-NEXT: vmovss {{.*#+}} xmm3 = [4.4E+1,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vcomiss %xmm3, %xmm0
+; AVX1-NEXT: vcomiss %xmm3, %xmm1
; AVX1-NEXT: vxorps %xmm4, %xmm4, %xmm4
; AVX1-NEXT: ja .LBB124_4
; AVX1-NEXT: # %bb.3: # %entry
-; AVX1-NEXT: vmovaps %xmm0, %xmm4
+; AVX1-NEXT: vmovaps %xmm1, %xmm4
; AVX1-NEXT: .LBB124_4: # %entry
; AVX1-NEXT: vmovq %rax, %xmm2
; AVX1-NEXT: vsubss %xmm4, %xmm3, %xmm3
@@ -5074,11 +5074,11 @@ define <4 x i64> @constrained_vector_fptoui_v4i64_v4f32() #0 {
; AVX1-NEXT: xorq %rax, %rcx
; AVX1-NEXT: vmovq %rcx, %xmm3
; AVX1-NEXT: vmovss {{.*#+}} xmm4 = [4.3E+1,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vcomiss %xmm4, %xmm0
+; AVX1-NEXT: vcomiss %xmm4, %xmm1
; AVX1-NEXT: vxorps %xmm5, %xmm5, %xmm5
; AVX1-NEXT: ja .LBB124_6
; AVX1-NEXT: # %bb.5: # %entry
-; AVX1-NEXT: vmovaps %xmm0, %xmm5
+; AVX1-NEXT: vmovaps %xmm1, %xmm5
; AVX1-NEXT: .LBB124_6: # %entry
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX1-NEXT: vsubss %xmm5, %xmm4, %xmm3
@@ -5089,12 +5089,12 @@ define <4 x i64> @constrained_vector_fptoui_v4i64_v4f32() #0 {
; AVX1-NEXT: xorq %rax, %rcx
; AVX1-NEXT: vmovq %rcx, %xmm3
; AVX1-NEXT: vmovss {{.*#+}} xmm4 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]
-; AVX1-NEXT: vcomiss %xmm4, %xmm0
+; AVX1-NEXT: vcomiss %xmm4, %xmm1
; AVX1-NEXT: ja .LBB124_8
; AVX1-NEXT: # %bb.7: # %entry
-; AVX1-NEXT: vmovaps %xmm0, %xmm1
+; AVX1-NEXT: vmovaps %xmm1, %xmm0
; AVX1-NEXT: .LBB124_8: # %entry
-; AVX1-NEXT: vsubss %xmm1, %xmm4, %xmm0
+; AVX1-NEXT: vsubss %xmm0, %xmm4, %xmm0
; AVX1-NEXT: vcvttss2si %xmm0, %rax
; AVX1-NEXT: setbe %cl
; AVX1-NEXT: movzbl %cl, %ecx
@@ -5301,14 +5301,14 @@ define <1 x i64> @constrained_vector_fptoui_v1i64_v1f64() #0 {
; AVX1-LABEL: constrained_vector_fptoui_v1i64_v1f64:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovsd {{.*#+}} xmm0 = [4.2100000000000001E+1,0.0E+0]
-; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm0, %xmm1
-; AVX1-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vmovsd {{.*#+}} xmm2 = [9.2233720368547758E+18,0.0E+0]
+; AVX1-NEXT: vcomisd %xmm0, %xmm2
+; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: ja .LBB129_2
; AVX1-NEXT: # %bb.1: # %entry
-; AVX1-NEXT: vmovapd %xmm1, %xmm2
+; AVX1-NEXT: vmovapd %xmm2, %xmm1
; AVX1-NEXT: .LBB129_2: # %entry
-; AVX1-NEXT: vsubsd %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vcvttsd2si %xmm0, %rcx
; AVX1-NEXT: setbe %al
; AVX1-NEXT: movzbl %al, %eax
@@ -5365,13 +5365,13 @@ define <2 x i64> @constrained_vector_fptoui_v2i64_v2f64() #0 {
; AVX1-LABEL: constrained_vector_fptoui_v2i64_v2f64:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovsd {{.*#+}} xmm2 = [4.2200000000000003E+1,0.0E+0]
-; AVX1-NEXT: vmovsd {{.*#+}} xmm0 = [9.2233720368547758E+18,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm2, %xmm0
-; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
+; AVX1-NEXT: vcomisd %xmm2, %xmm1
+; AVX1-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; AVX1-NEXT: ja .LBB130_2
; AVX1-NEXT: # %bb.1: # %entry
-; AVX1-NEXT: vmovapd %xmm0, %xmm3
+; AVX1-NEXT: vmovapd %xmm1, %xmm3
; AVX1-NEXT: .LBB130_2: # %entry
; AVX1-NEXT: vsubsd %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vcvttsd2si %xmm2, %rax
@@ -5381,12 +5381,12 @@ define <2 x i64> @constrained_vector_fptoui_v2i64_v2f64() #0 {
; AVX1-NEXT: xorq %rax, %rcx
; AVX1-NEXT: vmovq %rcx, %xmm2
; AVX1-NEXT: vmovsd {{.*#+}} xmm3 = [4.2100000000000001E+1,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm3, %xmm0
+; AVX1-NEXT: vcomisd %xmm3, %xmm1
; AVX1-NEXT: ja .LBB130_4
; AVX1-NEXT: # %bb.3: # %entry
-; AVX1-NEXT: vmovapd %xmm0, %xmm1
+; AVX1-NEXT: vmovapd %xmm1, %xmm0
; AVX1-NEXT: .LBB130_4: # %entry
-; AVX1-NEXT: vsubsd %xmm1, %xmm3, %xmm0
+; AVX1-NEXT: vsubsd %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vcvttsd2si %xmm0, %rax
; AVX1-NEXT: setbe %cl
; AVX1-NEXT: movzbl %cl, %ecx
@@ -5467,13 +5467,13 @@ define <3 x i64> @constrained_vector_fptoui_v3i64_v3f64() #0 {
; AVX1-LABEL: constrained_vector_fptoui_v3i64_v3f64:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovsd {{.*#+}} xmm2 = [4.2299999999999997E+1,0.0E+0]
-; AVX1-NEXT: vmovsd {{.*#+}} xmm0 = [9.2233720368547758E+18,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm2, %xmm0
-; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
+; AVX1-NEXT: vcomisd %xmm2, %xmm1
+; AVX1-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; AVX1-NEXT: ja .LBB131_2
; AVX1-NEXT: # %bb.1: # %entry
-; AVX1-NEXT: vmovapd %xmm0, %xmm3
+; AVX1-NEXT: vmovapd %xmm1, %xmm3
; AVX1-NEXT: .LBB131_2: # %entry
; AVX1-NEXT: vsubsd %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vcvttsd2si %xmm2, %rcx
@@ -5482,11 +5482,11 @@ define <3 x i64> @constrained_vector_fptoui_v3i64_v3f64() #0 {
; AVX1-NEXT: shlq $63, %rax
; AVX1-NEXT: xorq %rcx, %rax
; AVX1-NEXT: vmovsd {{.*#+}} xmm2 = [4.2100000000000001E+1,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm2, %xmm0
+; AVX1-NEXT: vcomisd %xmm2, %xmm1
; AVX1-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; AVX1-NEXT: ja .LBB131_4
; AVX1-NEXT: # %bb.3: # %entry
-; AVX1-NEXT: vmovapd %xmm0, %xmm3
+; AVX1-NEXT: vmovapd %xmm1, %xmm3
; AVX1-NEXT: .LBB131_4: # %entry
; AVX1-NEXT: vsubsd %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vcvttsd2si %xmm2, %rdx
@@ -5495,12 +5495,12 @@ define <3 x i64> @constrained_vector_fptoui_v3i64_v3f64() #0 {
; AVX1-NEXT: shlq $63, %rcx
; AVX1-NEXT: xorq %rdx, %rcx
; AVX1-NEXT: vmovsd {{.*#+}} xmm2 = [4.2200000000000003E+1,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm2, %xmm0
+; AVX1-NEXT: vcomisd %xmm2, %xmm1
; AVX1-NEXT: ja .LBB131_6
; AVX1-NEXT: # %bb.5: # %entry
-; AVX1-NEXT: vmovapd %xmm0, %xmm1
+; AVX1-NEXT: vmovapd %xmm1, %xmm0
; AVX1-NEXT: .LBB131_6: # %entry
-; AVX1-NEXT: vsubsd %xmm1, %xmm2, %xmm0
+; AVX1-NEXT: vsubsd %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vcvttsd2si %xmm0, %rdx
; AVX1-NEXT: setbe %sil
; AVX1-NEXT: movzbl %sil, %esi
@@ -5599,13 +5599,13 @@ define <4 x i64> @constrained_vector_fptoui_v4i64_v4f64() #0 {
; AVX1-LABEL: constrained_vector_fptoui_v4i64_v4f64:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovsd {{.*#+}} xmm2 = [4.2399999999999999E+1,0.0E+0]
-; AVX1-NEXT: vmovsd {{.*#+}} xmm0 = [9.2233720368547758E+18,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm2, %xmm0
-; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
+; AVX1-NEXT: vcomisd %xmm2, %xmm1
+; AVX1-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; AVX1-NEXT: ja .LBB132_2
; AVX1-NEXT: # %bb.1: # %entry
-; AVX1-NEXT: vmovapd %xmm0, %xmm3
+; AVX1-NEXT: vmovapd %xmm1, %xmm3
; AVX1-NEXT: .LBB132_2: # %entry
; AVX1-NEXT: vsubsd %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vcvttsd2si %xmm2, %rcx
@@ -5614,11 +5614,11 @@ define <4 x i64> @constrained_vector_fptoui_v4i64_v4f64() #0 {
; AVX1-NEXT: shlq $63, %rax
; AVX1-NEXT: xorq %rcx, %rax
; AVX1-NEXT: vmovsd {{.*#+}} xmm3 = [4.2299999999999997E+1,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm3, %xmm0
+; AVX1-NEXT: vcomisd %xmm3, %xmm1
; AVX1-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; AVX1-NEXT: ja .LBB132_4
; AVX1-NEXT: # %bb.3: # %entry
-; AVX1-NEXT: vmovapd %xmm0, %xmm4
+; AVX1-NEXT: vmovapd %xmm1, %xmm4
; AVX1-NEXT: .LBB132_4: # %entry
; AVX1-NEXT: vmovq %rax, %xmm2
; AVX1-NEXT: vsubsd %xmm4, %xmm3, %xmm3
@@ -5629,11 +5629,11 @@ define <4 x i64> @constrained_vector_fptoui_v4i64_v4f64() #0 {
; AVX1-NEXT: xorq %rax, %rcx
; AVX1-NEXT: vmovq %rcx, %xmm3
; AVX1-NEXT: vmovsd {{.*#+}} xmm4 = [4.2200000000000003E+1,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm4, %xmm0
+; AVX1-NEXT: vcomisd %xmm4, %xmm1
; AVX1-NEXT: vxorpd %xmm5, %xmm5, %xmm5
; AVX1-NEXT: ja .LBB132_6
; AVX1-NEXT: # %bb.5: # %entry
-; AVX1-NEXT: vmovapd %xmm0, %xmm5
+; AVX1-NEXT: vmovapd %xmm1, %xmm5
; AVX1-NEXT: .LBB132_6: # %entry
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX1-NEXT: vsubsd %xmm5, %xmm4, %xmm3
@@ -5644,12 +5644,12 @@ define <4 x i64> @constrained_vector_fptoui_v4i64_v4f64() #0 {
; AVX1-NEXT: xorq %rax, %rcx
; AVX1-NEXT: vmovq %rcx, %xmm3
; AVX1-NEXT: vmovsd {{.*#+}} xmm4 = [4.2100000000000001E+1,0.0E+0]
-; AVX1-NEXT: vcomisd %xmm4, %xmm0
+; AVX1-NEXT: vcomisd %xmm4, %xmm1
; AVX1-NEXT: ja .LBB132_8
; AVX1-NEXT: # %bb.7: # %entry
-; AVX1-NEXT: vmovapd %xmm0, %xmm1
+; AVX1-NEXT: vmovapd %xmm1, %xmm0
; AVX1-NEXT: .LBB132_8: # %entry
-; AVX1-NEXT: vsubsd %xmm1, %xmm4, %xmm0
+; AVX1-NEXT: vsubsd %xmm0, %xmm4, %xmm0
; AVX1-NEXT: vcvttsd2si %xmm0, %rax
; AVX1-NEXT: setbe %cl
; AVX1-NEXT: movzbl %cl, %ecx
diff --git a/llvm/test/CodeGen/X86/x86-cmov-converter.ll b/llvm/test/CodeGen/X86/x86-cmov-converter.ll
index b02da217e76b2..e9ce548e79834 100644
--- a/llvm/test/CodeGen/X86/x86-cmov-converter.ll
+++ b/llvm/test/CodeGen/X86/x86-cmov-converter.ll
@@ -451,29 +451,29 @@ define i32 @MaxValue(i32 %n, ptr nocapture readonly %a) #0 {
;
; CHECK-FORCEALL-LABEL: MaxValue:
; CHECK-FORCEALL: # %bb.0: # %entry
-; CHECK-FORCEALL-NEXT: movl (%rsi), %r8d
+; CHECK-FORCEALL-NEXT: movl (%rsi), %edx
; CHECK-FORCEALL-NEXT: cmpl $2, %edi
; CHECK-FORCEALL-NEXT: jge .LBB4_3
; CHECK-FORCEALL-NEXT: # %bb.1:
-; CHECK-FORCEALL-NEXT: movl %r8d, %eax
+; CHECK-FORCEALL-NEXT: movl %edx, %eax
; CHECK-FORCEALL-NEXT: .LBB4_2: # %for.cond.cleanup
; CHECK-FORCEALL-NEXT: retq
; CHECK-FORCEALL-NEXT: .LBB4_3: # %for.body.preheader
; CHECK-FORCEALL-NEXT: movl %edi, %ecx
-; CHECK-FORCEALL-NEXT: movl $1, %edx
+; CHECK-FORCEALL-NEXT: movl $1, %edi
; CHECK-FORCEALL-NEXT: .LBB4_4: # %for.body
; CHECK-FORCEALL-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-FORCEALL-NEXT: movl (%rsi,%rdx,4), %eax
-; CHECK-FORCEALL-NEXT: cmpl %r8d, %eax
+; CHECK-FORCEALL-NEXT: movl (%rsi,%rdi,4), %eax
+; CHECK-FORCEALL-NEXT: cmpl %edx, %eax
; CHECK-FORCEALL-NEXT: jg .LBB4_6
; CHECK-FORCEALL-NEXT: # %bb.5: # %for.body
; CHECK-FORCEALL-NEXT: # in Loop: Header=BB4_4 Depth=1
-; CHECK-FORCEALL-NEXT: movl %r8d, %eax
+; CHECK-FORCEALL-NEXT: movl %edx, %eax
; CHECK-FORCEALL-NEXT: .LBB4_6: # %for.body
; CHECK-FORCEALL-NEXT: # in Loop: Header=BB4_4 Depth=1
-; CHECK-FORCEALL-NEXT: addq $1, %rdx
-; CHECK-FORCEALL-NEXT: movl %eax, %r8d
-; CHECK-FORCEALL-NEXT: cmpq %rdx, %rcx
+; CHECK-FORCEALL-NEXT: addq $1, %rdi
+; CHECK-FORCEALL-NEXT: movl %eax, %edx
+; CHECK-FORCEALL-NEXT: cmpq %rdi, %rcx
; CHECK-FORCEALL-NEXT: je .LBB4_2
; CHECK-FORCEALL-NEXT: jmp .LBB4_4
entry:
diff --git a/llvm/test/Transforms/LoopStrengthReduce/AArch64/postidx-load.ll b/llvm/test/Transforms/LoopStrengthReduce/AArch64/postidx-load.ll
index 5976658ccdf86..6c0f4d5d8b8ef 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/AArch64/postidx-load.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/AArch64/postidx-load.ll
@@ -10,23 +10,22 @@ define i32 @i32_initially_postidx(ptr %p, i64 %n) {
; CHECK-NEXT: cmp x1, #1
; CHECK-NEXT: b.lt .LBB0_5
; CHECK-NEXT: // %bb.1: // %for.body.preheader
-; CHECK-NEXT: mov w8, wzr
+; CHECK-NEXT: mov x8, x0
+; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: .LBB0_2: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldr w9, [x0], #4
-; CHECK-NEXT: add w8, w8, w9
-; CHECK-NEXT: cmp w8, #0
+; CHECK-NEXT: ldr w9, [x8], #4
+; CHECK-NEXT: add w0, w0, w9
+; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: b.lo .LBB0_5
; CHECK-NEXT: // %bb.3: // %for.inc
; CHECK-NEXT: // in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: subs x1, x1, #1
; CHECK-NEXT: b.ne .LBB0_2
; CHECK-NEXT: // %bb.4: // %cleanup
-; CHECK-NEXT: mov w0, w8
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_5:
-; CHECK-NEXT: mov w8, wzr
-; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: ret
entry:
%cmp1 = icmp sgt i64 %n, 0
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