[llvm] [AArch64][SDAG] Generate TBL for shuffles in single block loops. (PR #227593)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 4 00:19:50 PDT 2026
https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/227593
>From ff85ca72b19623c16257d5c4a8ad61053bf83d1d Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Sun, 4 Oct 2026 08:19:31 +0100
Subject: [PATCH] [AArch64][SDAG] Generate TBL for shuffles in single block
loops.
When lowering shuffles we can either generate multiple zip/trn/ins/etc, or a
single tbl with a mask generated from a constant pool. The sequence of 2
instructions will be quicker and smaller for a one-off instruction, the tbl
will be quicker if the mask load is loop invarinant and can be loaded once and
used many times.
This and several other places are examples of where the lowering should be
dependant on whether the current basic block is inside a relatively small loop.
(Very large loops act like standard straight-line code).
This patch adds a simple heiristic that makes use of the current BasicBlock
being selected, changing the behaviour of shuffle generation if it is a single
self-looping block. This keeps the types of block where this would apply
constrained and ensures it will only trigger for small loops that can reliably
pull the constant pool out of the loop. If this is acceptable there are a few
other optimizations that could reuse the same pattern.
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 2 +
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 +
.../Target/AArch64/AArch64ISelLowering.cpp | 19 +-
llvm/test/CodeGen/AArch64/tbl-loops.ll | 221 +++++++++---------
llvm/test/CodeGen/AArch64/vldn_shuffle.ll | 178 +++++++-------
5 files changed, 224 insertions(+), 200 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 764858702b732..61f3100ba38ae 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -2711,6 +2711,8 @@ class SelectionDAG {
LLVM_ABI bool shouldOptForSize() const;
+ LLVM_ABI const BasicBlock *getBasicBlock() const;
+
/// Get the (commutative) identity element for the given opcode, if it exists.
LLVM_ABI SDValue getIdentityElement(unsigned Opcode, const SDLoc &DL, EVT VT,
SDNodeFlags Flags);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index abc8172fb67b5..570648759a861 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1486,6 +1486,10 @@ bool SelectionDAG::shouldOptForSize() const {
return llvm::shouldOptimizeForSize(FLI->MBB->getBasicBlock(), PSI, BFI);
}
+const BasicBlock *SelectionDAG::getBasicBlock() const {
+ return FLI->MBB->getBasicBlock();
+}
+
void SelectionDAG::allnodes_clear() {
assert(&*AllNodes.begin() == &EntryNode);
AllNodes.remove(AllNodes.begin());
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 9885dfc854d11..2e5c930d86d50 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16066,6 +16066,14 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
DAG.getNode(AArch64ISD::NVCAST, DL, BSVT, V1)));
}
+ auto preferTBLToMultiInstrShuffle = [&]() {
+ if (DAG.shouldOptForSize())
+ return false;
+ // Look for a simple single block loop.
+ const BasicBlock *Block = DAG.getBasicBlock();
+ return is_contained(successors(Block), Block);
+ };
+
if (((NumElts == 8 && EltSize == 16) || (NumElts == 16 && EltSize == 8) ||
(NumElts == 4 && EltSize == 32)) &&
ShuffleVectorInst::isReverseMask(ShuffleMask, ShuffleMask.size())) {
@@ -16078,9 +16086,11 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
return convertFromScalableVector(DAG, VT, Rev);
}
- SDValue Rev = DAG.getNode(AArch64ISD::REV64, DL, VT, V1);
- return DAG.getNode(AArch64ISD::EXT, DL, VT, Rev, Rev,
- DAG.getConstant(8, DL, MVT::i32));
+ if (!preferTBLToMultiInstrShuffle()) {
+ SDValue Rev = DAG.getNode(AArch64ISD::REV64, DL, VT, V1);
+ return DAG.getNode(AArch64ISD::EXT, DL, VT, Rev, Rev,
+ DAG.getConstant(8, DL, MVT::i32));
+ }
}
// Check for slide-with-zeros pattern before EXT (slide is also valid EXT)
@@ -16199,7 +16209,8 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
// If the shuffle is not directly supported and it has 4 elements, use
// the PerfectShuffle-generated table to synthesize it from other shuffles.
- if (NumElts == 4) {
+ if (NumElts == 4 && (getPerfectShuffleCost(ShuffleMask) == 1 ||
+ !preferTBLToMultiInstrShuffle())) {
SmallVector<ShuffleEntry> Entries;
if (generatePerfectShuffle(ShuffleMask, NumElts, Entries)) {
SmallVector<SDValue> Vals;
diff --git a/llvm/test/CodeGen/AArch64/tbl-loops.ll b/llvm/test/CodeGen/AArch64/tbl-loops.ll
index b72556bf2aefe..d1849a684c6ca 100644
--- a/llvm/test/CodeGen/AArch64/tbl-loops.ll
+++ b/llvm/test/CodeGen/AArch64/tbl-loops.ll
@@ -693,53 +693,55 @@ define void @loop3(ptr noalias nocapture noundef writeonly %dst, ptr nocapture n
; CHECK-IADISABLED-NEXT: ret
; CHECK-IADISABLED-NEXT: .LBB2_7: // %vector.ph
; CHECK-IADISABLED-NEXT: add x11, x8, #1
-; CHECK-IADISABLED-NEXT: mov w8, #1132396544 // =0x437f0000
-; CHECK-IADISABLED-NEXT: adrp x12, .LCPI2_0
+; CHECK-IADISABLED-NEXT: adrp x8, .LCPI2_0
+; CHECK-IADISABLED-NEXT: adrp x9, .LCPI2_1
; CHECK-IADISABLED-NEXT: and x10, x11, #0x1fffffffc
-; CHECK-IADISABLED-NEXT: dup v0.4s, w8
-; CHECK-IADISABLED-NEXT: ldr q1, [x12, :lo12:.LCPI2_0]
-; CHECK-IADISABLED-NEXT: add x9, x10, x10, lsl #1
+; CHECK-IADISABLED-NEXT: ldr q0, [x8, :lo12:.LCPI2_0]
+; CHECK-IADISABLED-NEXT: mov w8, #1132396544 // =0x437f0000
+; CHECK-IADISABLED-NEXT: add x12, x10, x10, lsl #1
+; CHECK-IADISABLED-NEXT: ldr q1, [x9, :lo12:.LCPI2_1]
+; CHECK-IADISABLED-NEXT: adrp x9, .LCPI2_2
+; CHECK-IADISABLED-NEXT: dup v2.4s, w8
+; CHECK-IADISABLED-NEXT: adrp x13, .LCPI2_3
+; CHECK-IADISABLED-NEXT: ldr q3, [x9, :lo12:.LCPI2_2]
+; CHECK-IADISABLED-NEXT: add x8, x1, x12, lsl #2
+; CHECK-IADISABLED-NEXT: ldr q4, [x13, :lo12:.LCPI2_3]
+; CHECK-IADISABLED-NEXT: add x9, x0, x12
; CHECK-IADISABLED-NEXT: and x12, x11, #0x1fffffffc
-; CHECK-IADISABLED-NEXT: add x8, x1, x9, lsl #2
-; CHECK-IADISABLED-NEXT: add x9, x0, x9
; CHECK-IADISABLED-NEXT: .LBB2_8: // %vector.body
; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q2, q4, [x1]
+; CHECK-IADISABLED-NEXT: ldp q5, q6, [x1]
; CHECK-IADISABLED-NEXT: subs x12, x12, #4
-; CHECK-IADISABLED-NEXT: ldr q6, [x1, #32]
+; CHECK-IADISABLED-NEXT: ldr q7, [x1, #32]
+; CHECK-IADISABLED-NEXT: tbl v16.16b, { v5.16b, v6.16b }, v0.16b
+; CHECK-IADISABLED-NEXT: tbl v17.16b, { v5.16b, v6.16b }, v1.16b
; CHECK-IADISABLED-NEXT: add x1, x1, #48
-; CHECK-IADISABLED-NEXT: mov v3.16b, v2.16b
-; CHECK-IADISABLED-NEXT: rev64 v5.4s, v4.4s
-; CHECK-IADISABLED-NEXT: mov v3.s[1], v2.s[3]
-; CHECK-IADISABLED-NEXT: mov v5.s[0], v2.s[1]
-; CHECK-IADISABLED-NEXT: mov v3.s[2], v4.s[2]
-; CHECK-IADISABLED-NEXT: mov v4.s[0], v2.s[2]
-; CHECK-IADISABLED-NEXT: mov v5.s[3], v6.s[2]
-; CHECK-IADISABLED-NEXT: mov v4.s[2], v6.s[0]
-; CHECK-IADISABLED-NEXT: mov v3.s[3], v6.s[1]
-; CHECK-IADISABLED-NEXT: mov v4.s[3], v6.s[3]
-; CHECK-IADISABLED-NEXT: fcmgt v2.4s, v3.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fcmgt v6.4s, v5.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fcmgt v7.4s, v4.4s, v0.4s
-; CHECK-IADISABLED-NEXT: bsl v2.16b, v0.16b, v3.16b
-; CHECK-IADISABLED-NEXT: fcmlt v3.4s, v3.4s, #0.0
-; CHECK-IADISABLED-NEXT: bsl v6.16b, v0.16b, v5.16b
+; CHECK-IADISABLED-NEXT: mov v16.s[3], v7.s[1]
+; CHECK-IADISABLED-NEXT: mov v17.s[3], v7.s[2]
+; CHECK-IADISABLED-NEXT: mov v6.s[0], v5.s[2]
+; CHECK-IADISABLED-NEXT: tbl v5.16b, { v6.16b, v7.16b }, v3.16b
+; CHECK-IADISABLED-NEXT: fcmgt v6.4s, v16.4s, v2.4s
+; CHECK-IADISABLED-NEXT: fcmgt v7.4s, v17.4s, v2.4s
+; CHECK-IADISABLED-NEXT: fcmgt v18.4s, v5.4s, v2.4s
+; CHECK-IADISABLED-NEXT: bsl v6.16b, v2.16b, v16.16b
+; CHECK-IADISABLED-NEXT: fcmlt v16.4s, v16.4s, #0.0
+; CHECK-IADISABLED-NEXT: bsl v7.16b, v2.16b, v17.16b
+; CHECK-IADISABLED-NEXT: fcmlt v17.4s, v17.4s, #0.0
+; CHECK-IADISABLED-NEXT: bsl v18.16b, v2.16b, v5.16b
; CHECK-IADISABLED-NEXT: fcmlt v5.4s, v5.4s, #0.0
-; CHECK-IADISABLED-NEXT: bsl v7.16b, v0.16b, v4.16b
-; CHECK-IADISABLED-NEXT: fcmlt v4.4s, v4.4s, #0.0
-; CHECK-IADISABLED-NEXT: bic v2.16b, v2.16b, v3.16b
-; CHECK-IADISABLED-NEXT: bic v3.16b, v6.16b, v5.16b
-; CHECK-IADISABLED-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: bic v4.16b, v7.16b, v4.16b
-; CHECK-IADISABLED-NEXT: fcvtzs v3.4s, v3.4s
-; CHECK-IADISABLED-NEXT: fcvtzs v4.4s, v4.4s
-; CHECK-IADISABLED-NEXT: xtn v5.4h, v2.4s
-; CHECK-IADISABLED-NEXT: xtn v6.4h, v3.4s
-; CHECK-IADISABLED-NEXT: xtn v7.4h, v4.4s
-; CHECK-IADISABLED-NEXT: tbl v2.16b, { v5.16b, v6.16b, v7.16b }, v1.16b
-; CHECK-IADISABLED-NEXT: mov s3, v2.s[2]
-; CHECK-IADISABLED-NEXT: str d2, [x0]
-; CHECK-IADISABLED-NEXT: str s3, [x0, #8]
+; CHECK-IADISABLED-NEXT: bic v6.16b, v6.16b, v16.16b
+; CHECK-IADISABLED-NEXT: bic v7.16b, v7.16b, v17.16b
+; CHECK-IADISABLED-NEXT: fcvtzs v6.4s, v6.4s
+; CHECK-IADISABLED-NEXT: bic v5.16b, v18.16b, v5.16b
+; CHECK-IADISABLED-NEXT: fcvtzs v7.4s, v7.4s
+; CHECK-IADISABLED-NEXT: fcvtzs v5.4s, v5.4s
+; CHECK-IADISABLED-NEXT: xtn v16.4h, v6.4s
+; CHECK-IADISABLED-NEXT: xtn v17.4h, v7.4s
+; CHECK-IADISABLED-NEXT: xtn v18.4h, v5.4s
+; CHECK-IADISABLED-NEXT: tbl v5.16b, { v16.16b, v17.16b, v18.16b }, v4.16b
+; CHECK-IADISABLED-NEXT: mov s6, v5.s[2]
+; CHECK-IADISABLED-NEXT: str d5, [x0]
+; CHECK-IADISABLED-NEXT: str s6, [x0, #8]
; CHECK-IADISABLED-NEXT: add x0, x0, #12
; CHECK-IADISABLED-NEXT: b.ne .LBB2_8
; CHECK-IADISABLED-NEXT: // %bb.9: // %middle.block
@@ -1147,56 +1149,59 @@ define void @loop4(ptr noalias nocapture noundef writeonly %dst, ptr nocapture n
; CHECK-IADISABLED-NEXT: add x11, x8, #1
; CHECK-IADISABLED-NEXT: mov w8, #1132396544 // =0x437f0000
; CHECK-IADISABLED-NEXT: adrp x12, .LCPI3_0
+; CHECK-IADISABLED-NEXT: adrp x13, .LCPI3_1
+; CHECK-IADISABLED-NEXT: adrp x14, .LCPI3_2
; CHECK-IADISABLED-NEXT: and x10, x11, #0x1fffffffc
; CHECK-IADISABLED-NEXT: dup v0.4s, w8
-; CHECK-IADISABLED-NEXT: ldr q1, [x12, :lo12:.LCPI3_0]
; CHECK-IADISABLED-NEXT: add x8, x1, x10, lsl #4
; CHECK-IADISABLED-NEXT: add x9, x0, x10, lsl #2
+; CHECK-IADISABLED-NEXT: ldr q1, [x12, :lo12:.LCPI3_0]
+; CHECK-IADISABLED-NEXT: ldr q2, [x13, :lo12:.LCPI3_1]
+; CHECK-IADISABLED-NEXT: ldr q3, [x14, :lo12:.LCPI3_2]
; CHECK-IADISABLED-NEXT: and x12, x11, #0x1fffffffc
; CHECK-IADISABLED-NEXT: .LBB3_8: // %vector.body
; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q3, q2, [x1, #32]
+; CHECK-IADISABLED-NEXT: ldp q4, q5, [x1, #32]
; CHECK-IADISABLED-NEXT: subs x12, x12, #4
-; CHECK-IADISABLED-NEXT: ldp q6, q5, [x1], #64
-; CHECK-IADISABLED-NEXT: zip1 v4.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: trn1 v19.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: zip2 v2.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: uzp2 v7.4s, v6.4s, v5.4s
-; CHECK-IADISABLED-NEXT: zip1 v16.4s, v6.4s, v5.4s
-; CHECK-IADISABLED-NEXT: trn2 v18.4s, v6.4s, v5.4s
-; CHECK-IADISABLED-NEXT: zip2 v5.4s, v6.4s, v5.4s
-; CHECK-IADISABLED-NEXT: ext v17.16b, v3.16b, v4.16b, #8
-; CHECK-IADISABLED-NEXT: uzp2 v3.4s, v7.4s, v6.4s
-; CHECK-IADISABLED-NEXT: mov v18.d[1], v4.d[1]
-; CHECK-IADISABLED-NEXT: mov v5.d[1], v19.d[1]
+; CHECK-IADISABLED-NEXT: ldp q6, q7, [x1], #64
+; CHECK-IADISABLED-NEXT: tbl v17.16b, { v4.16b, v5.16b }, v1.16b
+; CHECK-IADISABLED-NEXT: zip1 v18.4s, v4.4s, v5.4s
+; CHECK-IADISABLED-NEXT: trn1 v20.4s, v4.4s, v5.4s
+; CHECK-IADISABLED-NEXT: zip1 v16.4s, v6.4s, v7.4s
+; CHECK-IADISABLED-NEXT: trn2 v19.4s, v6.4s, v7.4s
+; CHECK-IADISABLED-NEXT: zip2 v21.4s, v6.4s, v7.4s
+; CHECK-IADISABLED-NEXT: zip2 v4.4s, v4.4s, v5.4s
+; CHECK-IADISABLED-NEXT: tbl v5.16b, { v6.16b, v7.16b }, v2.16b
; CHECK-IADISABLED-NEXT: mov v16.d[1], v17.d[1]
-; CHECK-IADISABLED-NEXT: mov v3.d[1], v2.d[1]
-; CHECK-IADISABLED-NEXT: fcmgt v4.4s, v18.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fcmlt v17.4s, v18.4s, #0.0
-; CHECK-IADISABLED-NEXT: fcmgt v6.4s, v5.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fcmgt v2.4s, v16.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fcmgt v7.4s, v3.4s, v0.4s
-; CHECK-IADISABLED-NEXT: bsl v4.16b, v0.16b, v18.16b
-; CHECK-IADISABLED-NEXT: bsl v6.16b, v0.16b, v5.16b
-; CHECK-IADISABLED-NEXT: fcmlt v5.4s, v5.4s, #0.0
-; CHECK-IADISABLED-NEXT: bsl v2.16b, v0.16b, v16.16b
+; CHECK-IADISABLED-NEXT: mov v19.d[1], v18.d[1]
+; CHECK-IADISABLED-NEXT: mov v21.d[1], v20.d[1]
+; CHECK-IADISABLED-NEXT: mov v5.d[1], v4.d[1]
+; CHECK-IADISABLED-NEXT: fcmgt v4.4s, v16.4s, v0.4s
+; CHECK-IADISABLED-NEXT: fcmgt v6.4s, v19.4s, v0.4s
+; CHECK-IADISABLED-NEXT: fcmgt v7.4s, v21.4s, v0.4s
+; CHECK-IADISABLED-NEXT: fcmgt v17.4s, v5.4s, v0.4s
+; CHECK-IADISABLED-NEXT: fcmlt v18.4s, v19.4s, #0.0
+; CHECK-IADISABLED-NEXT: bsl v4.16b, v0.16b, v16.16b
; CHECK-IADISABLED-NEXT: fcmlt v16.4s, v16.4s, #0.0
-; CHECK-IADISABLED-NEXT: bsl v7.16b, v0.16b, v3.16b
-; CHECK-IADISABLED-NEXT: fcmlt v3.4s, v3.4s, #0.0
-; CHECK-IADISABLED-NEXT: bic v4.16b, v4.16b, v17.16b
-; CHECK-IADISABLED-NEXT: bic v5.16b, v6.16b, v5.16b
-; CHECK-IADISABLED-NEXT: bic v2.16b, v2.16b, v16.16b
+; CHECK-IADISABLED-NEXT: bsl v6.16b, v0.16b, v19.16b
+; CHECK-IADISABLED-NEXT: bsl v7.16b, v0.16b, v21.16b
+; CHECK-IADISABLED-NEXT: fcmlt v19.4s, v21.4s, #0.0
+; CHECK-IADISABLED-NEXT: bsl v17.16b, v0.16b, v5.16b
+; CHECK-IADISABLED-NEXT: fcmlt v5.4s, v5.4s, #0.0
+; CHECK-IADISABLED-NEXT: bic v4.16b, v4.16b, v16.16b
+; CHECK-IADISABLED-NEXT: bic v6.16b, v6.16b, v18.16b
+; CHECK-IADISABLED-NEXT: bic v7.16b, v7.16b, v19.16b
+; CHECK-IADISABLED-NEXT: bic v5.16b, v17.16b, v5.16b
; CHECK-IADISABLED-NEXT: fcvtzs v4.4s, v4.4s
-; CHECK-IADISABLED-NEXT: bic v3.16b, v7.16b, v3.16b
+; CHECK-IADISABLED-NEXT: fcvtzs v6.4s, v6.4s
+; CHECK-IADISABLED-NEXT: fcvtzs v7.4s, v7.4s
; CHECK-IADISABLED-NEXT: fcvtzs v5.4s, v5.4s
-; CHECK-IADISABLED-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fcvtzs v3.4s, v3.4s
-; CHECK-IADISABLED-NEXT: xtn v16.4h, v2.4s
-; CHECK-IADISABLED-NEXT: xtn v17.4h, v4.4s
-; CHECK-IADISABLED-NEXT: xtn v18.4h, v5.4s
-; CHECK-IADISABLED-NEXT: xtn v19.4h, v3.4s
-; CHECK-IADISABLED-NEXT: tbl v2.16b, { v16.16b, v17.16b, v18.16b, v19.16b }, v1.16b
-; CHECK-IADISABLED-NEXT: str q2, [x0], #16
+; CHECK-IADISABLED-NEXT: xtn v16.4h, v4.4s
+; CHECK-IADISABLED-NEXT: xtn v17.4h, v6.4s
+; CHECK-IADISABLED-NEXT: xtn v18.4h, v7.4s
+; CHECK-IADISABLED-NEXT: xtn v19.4h, v5.4s
+; CHECK-IADISABLED-NEXT: tbl v4.16b, { v16.16b, v17.16b, v18.16b, v19.16b }, v3.16b
+; CHECK-IADISABLED-NEXT: str q4, [x0], #16
; CHECK-IADISABLED-NEXT: b.ne .LBB3_8
; CHECK-IADISABLED-NEXT: // %bb.9: // %middle.block
; CHECK-IADISABLED-NEXT: cmp x11, x10
@@ -2443,24 +2448,22 @@ for.body: ; preds = %for.body.preheader5
define void @reverse4_shuffle_1024(ptr noalias %out, ptr noalias readonly %in) {
; CHECK-LABEL: reverse4_shuffle_1024:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #1024 // =0x400
-; CHECK-NEXT: add x9, x1, #32
-; CHECK-NEXT: add x10, x0, #32
+; CHECK-NEXT: adrp x8, .LCPI7_0
+; CHECK-NEXT: add x9, x0, #32
+; CHECK-NEXT: mov w10, #1024 // =0x400
+; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI7_0]
+; CHECK-NEXT: add x8, x1, #32
; CHECK-NEXT: .LBB7_1: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldp q0, q1, [x9, #-32]
-; CHECK-NEXT: subs x8, x8, #1
-; CHECK-NEXT: ldp q2, q3, [x9], #64
-; CHECK-NEXT: rev64 v0.16b, v0.16b
-; CHECK-NEXT: rev64 v1.16b, v1.16b
-; CHECK-NEXT: rev64 v2.16b, v2.16b
-; CHECK-NEXT: rev64 v3.16b, v3.16b
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v2.16b, v2.16b, v2.16b, #8
-; CHECK-NEXT: ext v3.16b, v3.16b, v3.16b, #8
-; CHECK-NEXT: stp q0, q1, [x10, #-32]
-; CHECK-NEXT: stp q2, q3, [x10], #64
+; CHECK-NEXT: ldp q1, q2, [x8, #-32]
+; CHECK-NEXT: subs x10, x10, #1
+; CHECK-NEXT: ldp q3, q4, [x8], #64
+; CHECK-NEXT: tbl v1.16b, { v1.16b }, v0.16b
+; CHECK-NEXT: tbl v2.16b, { v2.16b }, v0.16b
+; CHECK-NEXT: tbl v3.16b, { v3.16b }, v0.16b
+; CHECK-NEXT: tbl v4.16b, { v4.16b }, v0.16b
+; CHECK-NEXT: stp q1, q2, [x9, #-32]
+; CHECK-NEXT: stp q3, q4, [x9], #64
; CHECK-NEXT: b.ne .LBB7_1
; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret
@@ -2527,24 +2530,22 @@ exit:
define void @reverse4_shuffle_0231(ptr noalias %out, ptr noalias readonly %in) {
; CHECK-LABEL: reverse4_shuffle_0231:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #1024 // =0x400
-; CHECK-NEXT: add x9, x1, #32
-; CHECK-NEXT: add x10, x0, #32
+; CHECK-NEXT: adrp x8, .LCPI8_0
+; CHECK-NEXT: add x9, x0, #32
+; CHECK-NEXT: mov w10, #1024 // =0x400
+; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI8_0]
+; CHECK-NEXT: add x8, x1, #32
; CHECK-NEXT: .LBB8_1: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldp q0, q1, [x9, #-32]
-; CHECK-NEXT: subs x8, x8, #1
-; CHECK-NEXT: ldp q3, q4, [x9], #64
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #12
-; CHECK-NEXT: ext v5.16b, v1.16b, v1.16b, #12
-; CHECK-NEXT: ext v6.16b, v3.16b, v3.16b, #12
-; CHECK-NEXT: ext v7.16b, v4.16b, v4.16b, #12
-; CHECK-NEXT: uzp1 v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: uzp1 v1.4s, v1.4s, v5.4s
-; CHECK-NEXT: uzp1 v2.4s, v3.4s, v6.4s
-; CHECK-NEXT: uzp1 v3.4s, v4.4s, v7.4s
-; CHECK-NEXT: stp q0, q1, [x10, #-32]
-; CHECK-NEXT: stp q2, q3, [x10], #64
+; CHECK-NEXT: ldp q1, q2, [x8, #-32]
+; CHECK-NEXT: subs x10, x10, #1
+; CHECK-NEXT: ldp q3, q4, [x8], #64
+; CHECK-NEXT: tbl v1.16b, { v1.16b }, v0.16b
+; CHECK-NEXT: tbl v2.16b, { v2.16b }, v0.16b
+; CHECK-NEXT: tbl v3.16b, { v3.16b }, v0.16b
+; CHECK-NEXT: tbl v4.16b, { v4.16b }, v0.16b
+; CHECK-NEXT: stp q1, q2, [x9, #-32]
+; CHECK-NEXT: stp q3, q4, [x9], #64
; CHECK-NEXT: b.ne .LBB8_1
; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
index 5926cb61572f5..e85c699518e43 100644
--- a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
@@ -109,28 +109,29 @@ define void @vld3(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32
; CHECK-IADISABLED: .Lfunc_begin1:
; CHECK-IADISABLED-NEXT: .cfi_startproc
; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
+; CHECK-IADISABLED-NEXT: adrp x8, .LCPI1_0
+; CHECK-IADISABLED-NEXT: adrp x9, .LCPI1_1
+; CHECK-IADISABLED-NEXT: adrp x10, .LCPI1_2
+; CHECK-IADISABLED-NEXT: ldr q0, [x8, :lo12:.LCPI1_0]
+; CHECK-IADISABLED-NEXT: ldr q1, [x9, :lo12:.LCPI1_1]
+; CHECK-IADISABLED-NEXT: ldr q2, [x10, :lo12:.LCPI1_2]
; CHECK-IADISABLED-NEXT: mov x8, xzr
; CHECK-IADISABLED-NEXT: .LBB1_1: // %vector.body
; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q0, q1, [x0]
-; CHECK-IADISABLED-NEXT: ldr q4, [x0, #32]
-; CHECK-IADISABLED-NEXT: add x0, x0, #48
-; CHECK-IADISABLED-NEXT: fmul v4.4s, v4.4s, v4.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v1.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: mov v2.16b, v0.16b
-; CHECK-IADISABLED-NEXT: rev64 v3.4s, v1.4s
-; CHECK-IADISABLED-NEXT: mov v2.s[1], v0.s[3]
-; CHECK-IADISABLED-NEXT: mov v3.s[0], v0.s[1]
-; CHECK-IADISABLED-NEXT: mov v2.s[2], v1.s[2]
-; CHECK-IADISABLED-NEXT: mov v1.s[0], v0.s[2]
-; CHECK-IADISABLED-NEXT: mov v3.s[3], v4.s[2]
-; CHECK-IADISABLED-NEXT: mov v2.s[3], v4.s[1]
-; CHECK-IADISABLED-NEXT: mov v1.s[2], v4.s[0]
-; CHECK-IADISABLED-NEXT: fadd v0.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: mov v1.s[3], v4.s[3]
-; CHECK-IADISABLED-NEXT: fadd v0.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: str q0, [x1, x8]
+; CHECK-IADISABLED-NEXT: ldp q4, q3, [x0, #16]
+; CHECK-IADISABLED-NEXT: ldr q5, [x0], #48
+; CHECK-IADISABLED-NEXT: fmul v18.4s, v3.4s, v3.4s
+; CHECK-IADISABLED-NEXT: fmul v17.4s, v4.4s, v4.4s
+; CHECK-IADISABLED-NEXT: fmul v16.4s, v5.4s, v5.4s
+; CHECK-IADISABLED-NEXT: tbl v3.16b, { v16.16b, v17.16b }, v0.16b
+; CHECK-IADISABLED-NEXT: tbl v4.16b, { v16.16b, v17.16b }, v1.16b
+; CHECK-IADISABLED-NEXT: mov v3.s[3], v18.s[1]
+; CHECK-IADISABLED-NEXT: mov v4.s[3], v18.s[2]
+; CHECK-IADISABLED-NEXT: mov v17.s[0], v16.s[2]
+; CHECK-IADISABLED-NEXT: fadd v3.4s, v4.4s, v3.4s
+; CHECK-IADISABLED-NEXT: tbl v4.16b, { v17.16b, v18.16b }, v2.16b
+; CHECK-IADISABLED-NEXT: fadd v3.4s, v3.4s, v4.4s
+; CHECK-IADISABLED-NEXT: str q3, [x1, x8]
; CHECK-IADISABLED-NEXT: add x8, x8, #16
; CHECK-IADISABLED-NEXT: cmp x8, #1, lsl #12 // =4096
; CHECK-IADISABLED-NEXT: b.ne .LBB1_1
@@ -221,37 +222,39 @@ define void @vld4(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32
; CHECK-IADISABLED: .Lfunc_begin2:
; CHECK-IADISABLED-NEXT: .cfi_startproc
; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
+; CHECK-IADISABLED-NEXT: adrp x8, .LCPI2_0
+; CHECK-IADISABLED-NEXT: adrp x9, .LCPI2_1
+; CHECK-IADISABLED-NEXT: ldr q0, [x8, :lo12:.LCPI2_0]
+; CHECK-IADISABLED-NEXT: ldr q1, [x9, :lo12:.LCPI2_1]
; CHECK-IADISABLED-NEXT: mov x8, xzr
; CHECK-IADISABLED-NEXT: .LBB2_1: // %vector.body
; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q0, q1, [x0]
+; CHECK-IADISABLED-NEXT: ldp q5, q2, [x0, #32]
; CHECK-IADISABLED-NEXT: add x9, x1, x8
-; CHECK-IADISABLED-NEXT: ldp q2, q3, [x0, #32]
+; CHECK-IADISABLED-NEXT: ldp q4, q3, [x0], #64
; CHECK-IADISABLED-NEXT: add x8, x8, #32
+; CHECK-IADISABLED-NEXT: fmul v7.4s, v2.4s, v2.4s
; CHECK-IADISABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IADISABLED-NEXT: add x0, x0, #64
-; CHECK-IADISABLED-NEXT: fmul v1.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v0.4s, v0.4s
; CHECK-IADISABLED-NEXT: fmul v3.4s, v3.4s, v3.4s
-; CHECK-IADISABLED-NEXT: fmul v2.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: uzp2 v4.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: zip1 v6.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: trn2 v7.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: zip1 v5.4s, v2.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v1.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp2 v0.4s, v4.4s, v0.4s
-; CHECK-IADISABLED-NEXT: trn1 v4.4s, v2.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v3.4s, v2.4s, v3.4s
-; CHECK-IADISABLED-NEXT: ext v2.16b, v2.16b, v5.16b, #8
-; CHECK-IADISABLED-NEXT: mov v7.d[1], v5.d[1]
-; CHECK-IADISABLED-NEXT: mov v1.d[1], v4.d[1]
-; CHECK-IADISABLED-NEXT: mov v0.d[1], v3.d[1]
-; CHECK-IADISABLED-NEXT: mov v6.d[1], v2.d[1]
-; CHECK-IADISABLED-NEXT: fadd v0.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fadd v2.4s, v7.4s, v6.4s
-; CHECK-IADISABLED-NEXT: zip2 v1.4s, v2.4s, v0.4s
-; CHECK-IADISABLED-NEXT: zip1 v0.4s, v2.4s, v0.4s
-; CHECK-IADISABLED-NEXT: stp q0, q1, [x9]
+; CHECK-IADISABLED-NEXT: fmul v6.4s, v5.4s, v5.4s
+; CHECK-IADISABLED-NEXT: fmul v2.4s, v4.4s, v4.4s
+; CHECK-IADISABLED-NEXT: tbl v5.16b, { v6.16b, v7.16b }, v0.16b
+; CHECK-IADISABLED-NEXT: zip1 v16.4s, v6.4s, v7.4s
+; CHECK-IADISABLED-NEXT: trn1 v18.4s, v6.4s, v7.4s
+; CHECK-IADISABLED-NEXT: zip1 v4.4s, v2.4s, v3.4s
+; CHECK-IADISABLED-NEXT: trn2 v17.4s, v2.4s, v3.4s
+; CHECK-IADISABLED-NEXT: zip2 v6.4s, v6.4s, v7.4s
+; CHECK-IADISABLED-NEXT: zip2 v7.4s, v2.4s, v3.4s
+; CHECK-IADISABLED-NEXT: tbl v2.16b, { v2.16b, v3.16b }, v1.16b
+; CHECK-IADISABLED-NEXT: mov v4.d[1], v5.d[1]
+; CHECK-IADISABLED-NEXT: mov v17.d[1], v16.d[1]
+; CHECK-IADISABLED-NEXT: mov v7.d[1], v18.d[1]
+; CHECK-IADISABLED-NEXT: mov v2.d[1], v6.d[1]
+; CHECK-IADISABLED-NEXT: fadd v3.4s, v17.4s, v4.4s
+; CHECK-IADISABLED-NEXT: fadd v2.4s, v2.4s, v7.4s
+; CHECK-IADISABLED-NEXT: zip2 v4.4s, v3.4s, v2.4s
+; CHECK-IADISABLED-NEXT: zip1 v2.4s, v3.4s, v2.4s
+; CHECK-IADISABLED-NEXT: stp q2, q4, [x9]
; CHECK-IADISABLED-NEXT: b.ne .LBB2_1
; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
; CHECK-IADISABLED-NEXT: ret
@@ -513,28 +516,29 @@ define void @vld3_multiuse(ptr nocapture readonly %pSrc, ptr noalias nocapture %
; CHECK-IADISABLED: .Lfunc_begin5:
; CHECK-IADISABLED-NEXT: .cfi_startproc
; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
+; CHECK-IADISABLED-NEXT: adrp x8, .LCPI5_0
+; CHECK-IADISABLED-NEXT: adrp x9, .LCPI5_1
+; CHECK-IADISABLED-NEXT: adrp x10, .LCPI5_2
+; CHECK-IADISABLED-NEXT: ldr q0, [x8, :lo12:.LCPI5_0]
+; CHECK-IADISABLED-NEXT: ldr q1, [x9, :lo12:.LCPI5_1]
+; CHECK-IADISABLED-NEXT: ldr q2, [x10, :lo12:.LCPI5_2]
; CHECK-IADISABLED-NEXT: mov x8, xzr
; CHECK-IADISABLED-NEXT: .LBB5_1: // %vector.body
; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q0, q1, [x0]
-; CHECK-IADISABLED-NEXT: ldr q4, [x0, #32]
-; CHECK-IADISABLED-NEXT: add x0, x0, #48
-; CHECK-IADISABLED-NEXT: fmul v4.4s, v4.4s, v4.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v1.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: mov v2.16b, v0.16b
-; CHECK-IADISABLED-NEXT: rev64 v3.4s, v1.4s
-; CHECK-IADISABLED-NEXT: mov v2.s[1], v0.s[3]
-; CHECK-IADISABLED-NEXT: mov v3.s[0], v0.s[1]
-; CHECK-IADISABLED-NEXT: mov v2.s[2], v1.s[2]
-; CHECK-IADISABLED-NEXT: mov v1.s[0], v0.s[2]
-; CHECK-IADISABLED-NEXT: mov v3.s[3], v4.s[2]
-; CHECK-IADISABLED-NEXT: mov v2.s[3], v4.s[1]
-; CHECK-IADISABLED-NEXT: mov v1.s[2], v4.s[0]
-; CHECK-IADISABLED-NEXT: fadd v0.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: mov v1.s[3], v4.s[3]
-; CHECK-IADISABLED-NEXT: fadd v0.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: str q0, [x1, x8]
+; CHECK-IADISABLED-NEXT: ldp q4, q3, [x0, #16]
+; CHECK-IADISABLED-NEXT: ldr q5, [x0], #48
+; CHECK-IADISABLED-NEXT: fmul v18.4s, v3.4s, v3.4s
+; CHECK-IADISABLED-NEXT: fmul v17.4s, v4.4s, v4.4s
+; CHECK-IADISABLED-NEXT: fmul v16.4s, v5.4s, v5.4s
+; CHECK-IADISABLED-NEXT: tbl v3.16b, { v16.16b, v17.16b }, v0.16b
+; CHECK-IADISABLED-NEXT: tbl v4.16b, { v16.16b, v17.16b }, v1.16b
+; CHECK-IADISABLED-NEXT: mov v3.s[3], v18.s[1]
+; CHECK-IADISABLED-NEXT: mov v4.s[3], v18.s[2]
+; CHECK-IADISABLED-NEXT: mov v17.s[0], v16.s[2]
+; CHECK-IADISABLED-NEXT: fadd v3.4s, v4.4s, v3.4s
+; CHECK-IADISABLED-NEXT: tbl v4.16b, { v17.16b, v18.16b }, v2.16b
+; CHECK-IADISABLED-NEXT: fadd v3.4s, v3.4s, v4.4s
+; CHECK-IADISABLED-NEXT: str q3, [x1, x8]
; CHECK-IADISABLED-NEXT: add x8, x8, #16
; CHECK-IADISABLED-NEXT: cmp x8, #1, lsl #12 // =4096
; CHECK-IADISABLED-NEXT: b.ne .LBB5_1
@@ -623,37 +627,39 @@ define void @vld4_multiuse(ptr nocapture readonly %pSrc, ptr noalias nocapture %
; CHECK-IADISABLED: .Lfunc_begin6:
; CHECK-IADISABLED-NEXT: .cfi_startproc
; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
+; CHECK-IADISABLED-NEXT: adrp x8, .LCPI6_0
+; CHECK-IADISABLED-NEXT: adrp x9, .LCPI6_1
+; CHECK-IADISABLED-NEXT: ldr q0, [x8, :lo12:.LCPI6_0]
+; CHECK-IADISABLED-NEXT: ldr q1, [x9, :lo12:.LCPI6_1]
; CHECK-IADISABLED-NEXT: mov x8, xzr
; CHECK-IADISABLED-NEXT: .LBB6_1: // %vector.body
; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q0, q1, [x0]
+; CHECK-IADISABLED-NEXT: ldp q5, q2, [x0, #32]
; CHECK-IADISABLED-NEXT: add x9, x1, x8
-; CHECK-IADISABLED-NEXT: ldp q2, q3, [x0, #32]
+; CHECK-IADISABLED-NEXT: ldp q4, q3, [x0], #64
; CHECK-IADISABLED-NEXT: add x8, x8, #32
+; CHECK-IADISABLED-NEXT: fmul v7.4s, v2.4s, v2.4s
; CHECK-IADISABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IADISABLED-NEXT: add x0, x0, #64
-; CHECK-IADISABLED-NEXT: fmul v1.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v0.4s, v0.4s
; CHECK-IADISABLED-NEXT: fmul v3.4s, v3.4s, v3.4s
-; CHECK-IADISABLED-NEXT: fmul v2.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: uzp2 v4.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: zip1 v6.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: trn2 v7.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: zip1 v5.4s, v2.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v1.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp2 v0.4s, v4.4s, v0.4s
-; CHECK-IADISABLED-NEXT: trn1 v4.4s, v2.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v3.4s, v2.4s, v3.4s
-; CHECK-IADISABLED-NEXT: ext v2.16b, v2.16b, v5.16b, #8
-; CHECK-IADISABLED-NEXT: mov v7.d[1], v5.d[1]
-; CHECK-IADISABLED-NEXT: mov v1.d[1], v4.d[1]
-; CHECK-IADISABLED-NEXT: mov v0.d[1], v3.d[1]
-; CHECK-IADISABLED-NEXT: mov v6.d[1], v2.d[1]
-; CHECK-IADISABLED-NEXT: fadd v0.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fadd v2.4s, v7.4s, v6.4s
-; CHECK-IADISABLED-NEXT: zip2 v1.4s, v2.4s, v0.4s
-; CHECK-IADISABLED-NEXT: zip1 v0.4s, v2.4s, v0.4s
-; CHECK-IADISABLED-NEXT: stp q0, q1, [x9]
+; CHECK-IADISABLED-NEXT: fmul v6.4s, v5.4s, v5.4s
+; CHECK-IADISABLED-NEXT: fmul v2.4s, v4.4s, v4.4s
+; CHECK-IADISABLED-NEXT: tbl v5.16b, { v6.16b, v7.16b }, v0.16b
+; CHECK-IADISABLED-NEXT: zip1 v16.4s, v6.4s, v7.4s
+; CHECK-IADISABLED-NEXT: trn1 v18.4s, v6.4s, v7.4s
+; CHECK-IADISABLED-NEXT: zip1 v4.4s, v2.4s, v3.4s
+; CHECK-IADISABLED-NEXT: trn2 v17.4s, v2.4s, v3.4s
+; CHECK-IADISABLED-NEXT: zip2 v6.4s, v6.4s, v7.4s
+; CHECK-IADISABLED-NEXT: zip2 v7.4s, v2.4s, v3.4s
+; CHECK-IADISABLED-NEXT: tbl v2.16b, { v2.16b, v3.16b }, v1.16b
+; CHECK-IADISABLED-NEXT: mov v4.d[1], v5.d[1]
+; CHECK-IADISABLED-NEXT: mov v17.d[1], v16.d[1]
+; CHECK-IADISABLED-NEXT: mov v7.d[1], v18.d[1]
+; CHECK-IADISABLED-NEXT: mov v2.d[1], v6.d[1]
+; CHECK-IADISABLED-NEXT: fadd v3.4s, v17.4s, v4.4s
+; CHECK-IADISABLED-NEXT: fadd v2.4s, v2.4s, v7.4s
+; CHECK-IADISABLED-NEXT: zip2 v4.4s, v3.4s, v2.4s
+; CHECK-IADISABLED-NEXT: zip1 v2.4s, v3.4s, v2.4s
+; CHECK-IADISABLED-NEXT: stp q2, q4, [x9]
; CHECK-IADISABLED-NEXT: b.ne .LBB6_1
; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
; CHECK-IADISABLED-NEXT: ret
More information about the llvm-commits
mailing list