[llvm] [TableGen] Split large printInstruction() for NVPTX to avoid compiler limits (PR #218530)

[Kazu Hirata via llvm-commits]

https://github.com/kazutakahirata approved this pull request.

LGTM.  Thanks for the update!  Could you update the PR title and description before merging so the squash-merge commit message reflects the current bytecode approach?  Here is a suggested message:

Title:
```
[TableGen] Emit bytecode table for AsmWriter overflow instructions
```

Description:
```
For targets with many instructions (NVPTX in particular), the overflow switch
emitted inside printInstruction() for operand sequences that do not fit in the
64-bit table-driven printer can grow large enough (over 15,000 lines for NVPTX)
to trigger:

  - MSVC C1001/C1053 ICE on AArch64 (function body too large)
  - R_RISCV_JAL relocation truncated to fit (JAL ±1 MB range exceeded)

This patch adds an opt-in UseBytecode bit to AsmWriter (enabled for NVPTX) that
replaces the overflow switch in printInstruction() with two function-local
static const arrays and a small bytecode interpreter loop:

  - OpcodeToOffset[]: maps each instruction opcode to its starting offset in
    OverflowProgram (or 0 for non-overflow instructions).
  - OverflowProgram[]: stores deduplicated bytecode sequences of operand-printing
    commands terminated by 1 ("return;").

Instructions with identical remaining operand sequences are grouped via:

    groupInstructions(Instructions, UseBytecode)

so they share the same offset in OverflowProgram[].
```


https://github.com/llvm/llvm-project/pull/218530