[llvm] d42998a - [SelectionDAG] Remove vector_extract_subvec/vector_insert_subvec from TargetSelectionDAG.td. NFC (#228662)

[via llvm-commits]

Author: Craig Topper
Date: 2026-10-04T01:10:57Z
New Revision: d42998a2c314be90cedd8c0c0f35e6e04dc19909

URL: https://github.com/llvm/llvm-project/commit/d42998a2c314be90cedd8c0c0f35e6e04dc19909
DIFF: https://github.com/llvm/llvm-project/commit/d42998a2c314be90cedd8c0c0f35e6e04dc19909.diff

LOG: [SelectionDAG] Remove vector_extract_subvec/vector_insert_subvec from TargetSelectionDAG.td. NFC (#228662)

These no longer have in tree users after #228542 and #228552.

Added: 
    

Modified: 
    llvm/include/llvm/Target/TargetSelectionDAG.td

Removed: 
    


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diff  --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 22fe30fea4fea..4f8a4987ff838 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -923,16 +923,6 @@ def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
     SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
 
-// This operator does not do subvector type checking.  The ARM
-// backend, at least, needs it.
-def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
-    SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
-    []>;
-def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR",
-    SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVec<2>, SDTCisInt<3>]>,
-    []>;
-
-// This operator does subvector type checking.
 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;