[llvm] [RISCV] Optimize CLMULH of i32 loads on RV64 (PR #228669)

[Craig Topper via llvm-commits]

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@@ -18283,6 +18184,32 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
       if (!Subtarget.is64Bit() || N->getValueType(0) != MVT::i32)
         return;
 
+      // A simple single-use sign-extending i32 load can use lwu directly.
+      // Widening these operands and using clmul avoids the shifts required by
+      // the general register-input lowering below.
+      auto IsSingleUseLoad = [](SDValue Op) {
+        if (Op.getOpcode() != ISD::TRUNCATE || !Op.hasOneUse())
+          return false;
+        auto *Load = dyn_cast<LoadSDNode>(Op.getOperand(0));
+        return Load && Load->isSimple() && !Load->isIndexed() &&
+               Load->getExtensionType() == ISD::SEXTLOAD &&
+               Load->getMemoryVT() == MVT::i32 && Op.getOperand(0).hasOneUse();
+      };
+      if (IntNo == Intrinsic::riscv_clmulh &&
+          (Subtarget.hasStdExtZbc() || Subtarget.hasStdExtZbkc()) &&
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topperc wrote:

We don't need to check Zbc, if its true then Zbkc is also true.

https://github.com/llvm/llvm-project/pull/228669