[llvm] [AArch64][GlobalISel] Ignore debug instructions when reusing carry. (PR #228128)
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Sat Oct 3 10:02:34 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Mihai Zegheru (mihaizegheru)
<details>
<summary>Changes</summary>
Ignore immediately in-between continuous block of debug instructions when a carry-producing instruction precedes a carry-consuming operation in AArch64 GlobalISel.
`emitCarryIn()` previously compared the carry producer directly against `I.getPrevNode()`. As a result, inserting a debug-only instruction (e.g., `DBG_VALUE`) between otherwise adjacent carry operations prevented reuse of the `NZCV` flags produced by the previous instruction. This caused instruction selection to unnecessarily materialize the carry into a virtual register and reconstruct `NZCV` before the following carry operation.
Walk backwards over consecutive debug instructions before performing the adjacency check. Debug instructions do not modify `NZCV`, so they should not prevent reuse of the existing carry flags.
#### Context
Adding a `DBG_VALUE` immediately in-between adjacent GlobalISel carry operations changes AArch64 instruction selection. Without the debug instruction, the carry consumer directly reuses the `NZCV` flags produced by the previous operation. With the debug instruction, instruction selection emits additional `CSINC` and `SUBS` instructions to materialize and reconstruct the carry.
#### Changes summary
- Skip consecutive debug instructions when locating the previous carry-producing instruction in `emitCarryIn()`.
- Add new MIR regression coverage for add/sub carry producer-consumer combinations separated by debug instructions.
- Add coverage for multiple consecutive debug instructions and for debug instructions at the beginning of a basic block to exercise the `nullptr` boundary case.
Fixes #<!-- -->227927
---
Full diff: https://github.com/llvm/llvm-project/pull/228128.diff
2 Files Affected:
- (modified) llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp (+8-1)
- (added) llvm/test/CodeGen/AArch64/GlobalISel/select-addsub-carry-adjacent-debug.mir (+319)
``````````diff
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index e12acd42bfdfd..e9a5cc1e4f4d4 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -4854,7 +4854,14 @@ MachineInstr *AArch64InstructionSelector::emitCarryIn(MachineInstr &I,
// instruction is deleted by the calling function, otherwise the previous
// instruction might become dead and would get deleted.
MachineInstr *SrcMI = MRI->getVRegDef(CarryReg);
- if (SrcMI == I.getPrevNode()) {
+
+ // Debug instructions (e.g., DBG_VALUE) do not modify NZCV, so skip all that
+ // immediately precede I.
+ MachineInstr *PrevMI = I.getPrevNode();
+ while (PrevMI && PrevMI->isDebugInstr())
+ PrevMI = PrevMI->getPrevNode();
+
+ if (SrcMI == PrevMI) {
if (auto *CarrySrcMI = dyn_cast<GAddSubCarryOut>(SrcMI)) {
bool ProducesNegatedCarry = CarrySrcMI->isSub();
if (NeedsNegatedCarry == ProducesNegatedCarry &&
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-addsub-carry-adjacent-debug.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-addsub-carry-adjacent-debug.mir
new file mode 100644
index 0000000000000..df328b9ac8a98
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-addsub-carry-adjacent-debug.mir
@@ -0,0 +1,319 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -verify-machineinstrs -mtriple=aarch64-unknown-unknown -global-isel-abort=1 -run-pass=instruction-select %s -o - | FileCheck %s
+
+--- |
+ source_filename = "select-addsub-carry-adjacent-debug.mir"
+ target triple = "aarch64-unknown-unknown"
+
+ define void @uaddo_uadde_dbg() !dbg !5 {
+ entry:
+ call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !10
+ unreachable, !dbg !10
+ }
+
+ define void @uadde_sadde_dbg() !dbg !11 {
+ entry:
+ call void @llvm.dbg.value(metadata i32 0, metadata !13, metadata !DIExpression()), !dbg !14
+ unreachable, !dbg !14
+ }
+
+ define void @usubo_usube_dbg() !dbg !15 {
+ entry:
+ call void @llvm.dbg.value(metadata i32 0, metadata !17, metadata !DIExpression()), !dbg !18
+ unreachable, !dbg !18
+ }
+
+ define void @usube_ssube_dbg() !dbg !19 {
+ entry:
+ call void @llvm.dbg.value(metadata i32 0, metadata !21, metadata !DIExpression()), !dbg !22
+ unreachable, !dbg !22
+ }
+
+ define void @uadde_multiple_dbg() !dbg !23 {
+ entry:
+ call void @llvm.dbg.value(metadata i32 0, metadata !25, metadata !DIExpression()), !dbg !27
+ unreachable, !dbg !27
+ }
+
+ define void @uadde_dbg_block_start() !dbg !28 {
+ entry:
+ call void @llvm.dbg.value(metadata i32 0, metadata !30, metadata !DIExpression()), !dbg !32
+ unreachable, !dbg !32
+ }
+
+ declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+ !llvm.dbg.cu = !{!0}
+ !llvm.mir.debugify = !{!2, !3}
+ !llvm.debugify = !{!3, !3}
+ !llvm.module.flags = !{!4}
+
+ !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+ !1 = !DIFile(filename: "select-uadde-adjacent-debug.mir", directory: "/")
+ !2 = !{i32 6}
+ !3 = !{i32 6}
+ !4 = !{i32 2, !"Debug Info Version", i32 3}
+
+ !5 = distinct !DISubprogram(name: "uaddo_uadde_dbg", linkageName: "uaddo_uadde_dbg", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8)
+ !6 = !DISubroutineType(types: !7)
+ !7 = !{}
+ !8 = !{!9}
+ !9 = !DILocalVariable(name: "carry", scope: !5, file: !1, line: 1, type: !33)
+ !10 = !DILocation(line: 1, column: 1, scope: !5)
+
+ !11 = distinct !DISubprogram(name: "uadde_sadde_dbg", linkageName: "uadde_sadde_dbg", scope: null, file: !1, line: 2, type: !6, scopeLine: 2, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12)
+ !12 = !{!13}
+ !13 = !DILocalVariable(name: "carry", scope: !11, file: !1, line: 2, type: !33)
+ !14 = !DILocation(line: 2, column: 1, scope: !11)
+
+ !15 = distinct !DISubprogram(name: "usubo_usube_dbg", linkageName: "usubo_usube_dbg", scope: null, file: !1, line: 3, type: !6, scopeLine: 3, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !16)
+ !16 = !{!17}
+ !17 = !DILocalVariable(name: "carry", scope: !15, file: !1, line: 3, type: !33)
+ !18 = !DILocation(line: 3, column: 1, scope: !15)
+
+ !19 = distinct !DISubprogram(name: "usube_ssube_dbg", linkageName: "usube_ssube_dbg", scope: null, file: !1, line: 4, type: !6, scopeLine: 4, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !20)
+ !20 = !{!21}
+ !21 = !DILocalVariable(name: "carry", scope: !19, file: !1, line: 4, type: !33)
+ !22 = !DILocation(line: 4, column: 1, scope: !19)
+
+ !23 = distinct !DISubprogram(name: "uadde_multiple_dbg", linkageName: "uadde_multiple_dbg", scope: null, file: !1, line: 5, type: !6, scopeLine: 5, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !24)
+ !24 = !{!25, !26}
+ !25 = !DILocalVariable(name: "carry", scope: !23, file: !1, line: 5, type: !33)
+ !26 = !DILabel(scope: !23, name: "carry_label", file: !1, line: 5)
+ !27 = !DILocation(line: 5, column: 1, scope: !23)
+
+ !28 = distinct !DISubprogram(name: "uadde_dbg_block_start", linkageName: "uadde_dbg_block_start", scope: null, file: !1, line: 6, type: !6, scopeLine: 6, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !29)
+ !29 = !{!30, !31}
+ !30 = !DILocalVariable(name: "carry", scope: !28, file: !1, line: 6, type: !33)
+ !31 = !DILabel(scope: !28, name: "block_start", file: !1, line: 6)
+ !32 = !DILocation(line: 6, column: 1, scope: !28)
+
+ !33 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned)
+...
+
+---
+name: uaddo_uadde_dbg
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0, $x1, $x2, $x3
+
+ ; CHECK-LABEL: name: uaddo_uadde_dbg
+ ; CHECK: liveins: $x0, $x1, $x2, $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
+ ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-NEXT: DBG_VALUE %5:gpr32, $noreg, !8, !DIExpression(), debug-location !10
+ ; CHECK-NEXT: [[ADCSXr:%[0-9]+]]:gpr64 = ADCSXr [[COPY1]], [[COPY3]], implicit-def dead $nzcv, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY [[ADDSXrr]]
+ ; CHECK-NEXT: $x1 = COPY [[ADCSXr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %4:gpr(i64), %5:gpr(i32) = G_UADDO %0, %2
+ DBG_VALUE %5(i32), $noreg, !9, !DIExpression(), debug-location !10
+ %6:gpr(i64), %7:gpr(i32) = G_UADDE %1, %3, %5
+ $x0 = COPY %4(i64)
+ $x1 = COPY %6(i64)
+ RET_ReallyLR implicit $x0, implicit $x1
+...
+
+---
+name: uadde_sadde_dbg
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0, $x1, $x2, $x3, $w4
+
+ ; CHECK-LABEL: name: uadde_sadde_dbg
+ ; CHECK: liveins: $x0, $x1, $x2, $x3, $w4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32sp = COPY $w4
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY4]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[ADCSXr:%[0-9]+]]:gpr64 = ADCSXr [[COPY]], [[COPY2]], implicit-def $nzcv, implicit $nzcv
+ ; CHECK-NEXT: DBG_VALUE %6:gpr32, $noreg, !13, !DIExpression(), debug-location !14
+ ; CHECK-NEXT: [[ADCSXr1:%[0-9]+]]:gpr64 = ADCSXr [[COPY1]], [[COPY3]], implicit-def dead $nzcv, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY [[ADCSXr]]
+ ; CHECK-NEXT: $x1 = COPY [[ADCSXr1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %4:gpr(i32) = COPY $w4
+ %5:gpr(i64), %6:gpr(i32) = G_UADDE %0, %2, %4
+ DBG_VALUE %6(i32), $noreg, !13, !DIExpression(), debug-location !14
+ %7:gpr(i64), %8:gpr(i32) = G_SADDE %1, %3, %6
+ $x0 = COPY %5(i64)
+ $x1 = COPY %7(i64)
+ RET_ReallyLR implicit $x0, implicit $x1
+...
+
+---
+name: usubo_usube_dbg
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0, $x1, $x2, $x3
+
+ ; CHECK-LABEL: name: usubo_usube_dbg
+ ; CHECK: liveins: $x0, $x1, $x2, $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
+ ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-NEXT: DBG_VALUE %5:gpr32, $noreg, !17, !DIExpression(), debug-location !18
+ ; CHECK-NEXT: [[SBCSXr:%[0-9]+]]:gpr64 = SBCSXr [[COPY1]], [[COPY3]], implicit-def dead $nzcv, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
+ ; CHECK-NEXT: $x1 = COPY [[SBCSXr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %4:gpr(i64), %5:gpr(i32) = G_USUBO %0, %2
+ DBG_VALUE %5(i32), $noreg, !17, !DIExpression(), debug-location !18
+ %6:gpr(i64), %7:gpr(i32) = G_USUBE %1, %3, %5
+ $x0 = COPY %4(i64)
+ $x1 = COPY %6(i64)
+ RET_ReallyLR implicit $x0, implicit $x1
+...
+
+---
+name: usube_ssube_dbg
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0, $x1, $x2, $x3, $w4
+
+ ; CHECK-LABEL: name: usube_ssube_dbg
+ ; CHECK: liveins: $x0, $x1, $x2, $x3, $w4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY $w4
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr $wzr, [[COPY4]], implicit-def $nzcv
+ ; CHECK-NEXT: [[SBCSXr:%[0-9]+]]:gpr64 = SBCSXr [[COPY]], [[COPY2]], implicit-def $nzcv, implicit $nzcv
+ ; CHECK-NEXT: DBG_VALUE %6:gpr32, $noreg, !21, !DIExpression(), debug-location !22
+ ; CHECK-NEXT: [[SBCSXr1:%[0-9]+]]:gpr64 = SBCSXr [[COPY1]], [[COPY3]], implicit-def dead $nzcv, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY [[SBCSXr]]
+ ; CHECK-NEXT: $x1 = COPY [[SBCSXr1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %4:gpr(i32) = COPY $w4
+ %5:gpr(i64), %6:gpr(i32) = G_USUBE %0, %2, %4
+ DBG_VALUE %6(i32), $noreg, !21, !DIExpression(), debug-location !22
+ %7:gpr(i64), %8:gpr(i32) = G_SSUBE %1, %3, %6
+ $x0 = COPY %5(i64)
+ $x1 = COPY %7(i64)
+ RET_ReallyLR implicit $x0, implicit $x1
+...
+
+---
+name: uadde_multiple_dbg
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0, $x1, $x2, $x3
+
+ ; CHECK-LABEL: name: uadde_multiple_dbg
+ ; CHECK: liveins: $x0, $x1, $x2, $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
+ ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-NEXT: DBG_VALUE %5:gpr32, $noreg, !25, !DIExpression(), debug-location !27
+ ; CHECK-NEXT: DBG_LABEL !26, debug-location !27
+ ; CHECK-NEXT: DBG_VALUE %5:gpr32, $noreg, !25, !DIExpression(), debug-location !27
+ ; CHECK-NEXT: [[ADCSXr:%[0-9]+]]:gpr64 = ADCSXr [[COPY1]], [[COPY3]], implicit-def dead $nzcv, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY [[ADDSXrr]]
+ ; CHECK-NEXT: $x1 = COPY [[ADCSXr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %4:gpr(i64), %5:gpr(i32) = G_UADDO %0, %2
+ DBG_VALUE %5(i32), $noreg, !25, !DIExpression(), debug-location !27
+ DBG_LABEL !26, debug-location !27
+ DBG_VALUE %5(i32), $noreg, !25, !DIExpression(), debug-location !27
+ %6:gpr(i64), %7:gpr(i32) = G_UADDE %1, %3, %5
+ $x0 = COPY %4(i64)
+ $x1 = COPY %6(i64)
+ RET_ReallyLR implicit $x0, implicit $x1
+...
+
+---
+name: uadde_dbg_block_start
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: uadde_dbg_block_start
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
+ ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32common = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: DBG_VALUE [[CSINCWr]], $noreg, !30, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: DBG_LABEL !31, debug-location !32
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[CSINCWr]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[ADCSXr:%[0-9]+]]:gpr64 = ADCSXr [[COPY1]], [[COPY3]], implicit-def $nzcv, implicit $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY [[ADCSXr]]
+ ; CHECK-NEXT: $w1 = COPY [[CSINCWr1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
+ bb.0:
+ liveins: $x0, $x1, $x2, $x3
+
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %4:gpr(i64), %5:gpr(i32) = G_UADDO %0, %2
+ G_BR %bb.1
+
+ bb.1:
+ DBG_VALUE %5(i32), $noreg, !30, !DIExpression(), debug-location !32
+ DBG_LABEL !31, debug-location !32
+ %6:gpr(i64), %7:gpr(i32) = G_UADDE %1, %3, %5
+ $x0 = COPY %6(i64)
+ $w1 = COPY %7(i32)
+ RET_ReallyLR implicit $x0, implicit $w1
+...
``````````
</details>
https://github.com/llvm/llvm-project/pull/228128
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