[llvm] [X86] Correct the SDTypeProfile for VNNI instructions. (PR #228745)
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llvm-commits at lists.llvm.org
Sat Oct 3 09:57:08 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
Operand 1 and 2 have i8 or i16 elements while the result and operand 0 have i32 elements. The type profile previously said all operands were the same type.
I've split the type profile to capture the i8 and i16 element size accurately.
Assisted-by: Claude
---
Full diff: https://github.com/llvm/llvm-project/pull/228745.diff
4 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+9-8)
- (modified) llvm/lib/Target/X86/X86InstrAVX512.td (+4-3)
- (modified) llvm/lib/Target/X86/X86InstrFragmentsSIMD.td (+27-21)
- (modified) llvm/lib/Target/X86/X86InstrSSE.td (+53-53)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a84d017d9c6cd..7d896fb5e6504 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -34825,14 +34825,15 @@ static SDValue LowerPARTIAL_REDUCE_MLA(SDValue Op,
if (VT.is512BitVector() && !Has512)
return splitVectorOp(Op, DAG, DL);
- // The dot products take their i8/i16 elements packed in i32 lanes.
- LHS = DAG.getBitcast(VT, LHS);
- RHS = DAG.getBitcast(VT, RHS);
-
- // Without VLX only the 512-bit EVEX form exists, so use that unless the VEX
- // encoding is available.
- if (!VT.is512BitVector() && !Subtarget.hasVLX() && !HasVEX)
- return getAVX512Node(Opc, DL, VT, {Acc, LHS, RHS}, DAG, Subtarget);
+ // Without VLX only the 512-bit EVEX form exists, so widen to that and extract
+ // unless the VEX encoding is available.
+ if (!VT.is512BitVector() && !Subtarget.hasVLX() && !HasVEX) {
+ Acc = widenSubVector(Acc, false, Subtarget, DAG, DL, 512);
+ LHS = widenSubVector(LHS, false, Subtarget, DAG, DL, 512);
+ RHS = widenSubVector(RHS, false, Subtarget, DAG, DL, 512);
+ SDValue Res = DAG.getNode(Opc, DL, MVT::v16i32, Acc, LHS, RHS);
+ return extractSubVector(Res, 0, DAG, DL, VT.getSizeInBits());
+ }
return DAG.getNode(Opc, DL, VT, Acc, LHS, RHS);
}
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 66802a936f201..e8c8c82a5de14 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -12632,7 +12632,7 @@ multiclass VNNI_rmb<bits<8> Op, string OpStr, SDNode OpNode,
(ins VTI.RC:$src2, VTI.MemOp:$src3), OpStr,
"$src3, $src2", "$src2, $src3",
(VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2,
- (VTI.VT (VTI.LdFrag addr:$src3))))>,
+ (load addr:$src3)))>,
EVEX, VVVV, EVEX_CD8<32, CD8VF>, T8,
Sched<[sched.Folded, sched.ReadAfterFold,
sched.ReadAfterFold]>;
@@ -12640,8 +12640,9 @@ multiclass VNNI_rmb<bits<8> Op, string OpStr, SDNode OpNode,
(ins VTI.RC:$src2, VTI.ScalarMemOp:$src3),
OpStr, "${src3}"#VTI.BroadcastStr#", $src2",
"$src2, ${src3}"#VTI.BroadcastStr,
- (OpNode VTI.RC:$src1, VTI.RC:$src2,
- (VTI.VT (VTI.BroadcastLdFrag addr:$src3)))>,
+ (VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2,
+ (bitconvert
+ (VTI.VT (VTI.BroadcastLdFrag addr:$src3)))))>,
EVEX, VVVV, EVEX_CD8<32, CD8VF>, EVEX_B,
T8, Sched<[sched.Folded, sched.ReadAfterFold,
sched.ReadAfterFold]>;
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
index 841634a0c4322..31674d7d66b10 100644
--- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -832,15 +832,19 @@ def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>;
def X86rcp14 : SDNode<"X86ISD::RCP14", SDTFPUnaryOp>;
def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>;
-// VNNI
-def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
- SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
+// VNNI dot products of i8 or i16 elements accumulated into i32 elements.
+def SDTVnniB : SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i32>, SDTCisSameAs<0,1>,
+ SDTCVecEltisVT<2, i8>, SDTCisSameSizeAs<0,2>,
+ SDTCisSameAs<2,3>]>;
+def SDTVnniW : SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i32>, SDTCisSameAs<0,1>,
+ SDTCVecEltisVT<2, i16>, SDTCisSameSizeAs<0,2>,
+ SDTCisSameAs<2,3>]>;
// VNNI
-def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>;
-def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>;
-def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>;
-def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>;
+def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnniB>;
+def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnniB>;
+def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnniW>;
+def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnniW>;
// Compress and expand.
def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
@@ -1093,19 +1097,19 @@ def SDTX86MaskedStore: SDTypeProfile<0, 3, [ // masked store
SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>
]>;
-def X86vpdpbssd : SDNode<"X86ISD::VPDPBSSD", SDTVnni>;
-def X86vpdpbssds : SDNode<"X86ISD::VPDPBSSDS", SDTVnni>;
-def X86vpdpbsud : SDNode<"X86ISD::VPDPBSUD", SDTVnni>;
-def X86vpdpbsuds : SDNode<"X86ISD::VPDPBSUDS", SDTVnni>;
-def X86vpdpbuud : SDNode<"X86ISD::VPDPBUUD", SDTVnni>;
-def X86vpdpbuuds : SDNode<"X86ISD::VPDPBUUDS", SDTVnni>;
+def X86vpdpbssd : SDNode<"X86ISD::VPDPBSSD", SDTVnniB>;
+def X86vpdpbssds : SDNode<"X86ISD::VPDPBSSDS", SDTVnniB>;
+def X86vpdpbsud : SDNode<"X86ISD::VPDPBSUD", SDTVnniB>;
+def X86vpdpbsuds : SDNode<"X86ISD::VPDPBSUDS", SDTVnniB>;
+def X86vpdpbuud : SDNode<"X86ISD::VPDPBUUD", SDTVnniB>;
+def X86vpdpbuuds : SDNode<"X86ISD::VPDPBUUDS", SDTVnniB>;
-def X86vpdpwsud : SDNode<"X86ISD::VPDPWSUD", SDTVnni>;
-def X86vpdpwsuds : SDNode<"X86ISD::VPDPWSUDS", SDTVnni>;
-def X86vpdpwusd : SDNode<"X86ISD::VPDPWUSD", SDTVnni>;
-def X86vpdpwusds : SDNode<"X86ISD::VPDPWUSDS", SDTVnni>;
-def X86vpdpwuud : SDNode<"X86ISD::VPDPWUUD", SDTVnni>;
-def X86vpdpwuuds : SDNode<"X86ISD::VPDPWUUDS", SDTVnni>;
+def X86vpdpwsud : SDNode<"X86ISD::VPDPWSUD", SDTVnniW>;
+def X86vpdpwsuds : SDNode<"X86ISD::VPDPWSUDS", SDTVnniW>;
+def X86vpdpwusd : SDNode<"X86ISD::VPDPWUSD", SDTVnniW>;
+def X86vpdpwusds : SDNode<"X86ISD::VPDPWUSDS", SDTVnniW>;
+def X86vpdpwuud : SDNode<"X86ISD::VPDPWUUD", SDTVnniW>;
+def X86vpdpwuuds : SDNode<"X86ISD::VPDPWUUDS", SDTVnniW>;
def X86Vmpsadbw : SDNode<"X86ISD::MPSADBW", SDTX86PSADBW>;
@@ -1862,5 +1866,7 @@ def X86vpmaddwd_su : PatFrag<(ops node:$lhs, node:$rhs),
}]>;
// BMM matrix multiplication operations
-def x86vbmacor : SDNode<"X86ISD::VBMACOR", SDTVnni>;
-def x86vbmacxor : SDNode<"X86ISD::VBMACXOR", SDTVnni>;
+def SDTBmac : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
+ SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
+def x86vbmacor : SDNode<"X86ISD::VBMACOR", SDTBmac>;
+def x86vbmacxor : SDNode<"X86ISD::VBMACXOR", SDTBmac>;
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 2332cb81d54cc..27bfdb4aa18f9 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -7481,7 +7481,7 @@ multiclass avx_vnni_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
(ins VR128:$src1, VR128:$src2, i128mem:$src3),
!strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR128:$dst, (v4i32 (OpNode VR128:$src1, VR128:$src2,
- (loadv4i32 addr:$src3))))]>,
+ (load addr:$src3))))]>,
VEX, VVVV, Sched<[SchedWriteVecIMul.XMM.Folded,
SchedWriteVecIMul.XMM.ReadAfterFold,
SchedWriteVecIMul.XMM.ReadAfterFold]>;
@@ -7498,7 +7498,7 @@ multiclass avx_vnni_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
(ins VR256:$src1, VR256:$src2, i256mem:$src3),
!strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR256:$dst, (v8i32 (OpNode VR256:$src1, VR256:$src2,
- (loadv8i32 addr:$src3))))]>,
+ (load addr:$src3))))]>,
VEX, VVVV, VEX_L, Sched<[SchedWriteVecIMul.YMM.Folded,
SchedWriteVecIMul.YMM.ReadAfterFold,
SchedWriteVecIMul.YMM.ReadAfterFold]>;
@@ -8336,8 +8336,8 @@ defm VPMADD52LUQ : avx_ifma_rm<0xb4, "vpmadd52luq", x86vpmadd52l>, REX_W, Explic
// AVX-VNNI-INT8
let Constraints = "$src1 = $dst" in
multiclass avx_dotprod_rm<bits<8> Opc, string OpcodeStr, ValueType OpVT,
- RegisterClass RC, PatFrag MemOpFrag,
- X86MemOperand X86memop, SDNode OpNode,
+ RegisterClass RC, X86MemOperand X86memop,
+ SDNode OpNode,
X86FoldableSchedWrite Sched,
bit IsCommutable> {
let isCommutable = IsCommutable in
@@ -8350,46 +8350,46 @@ multiclass avx_dotprod_rm<bits<8> Opc, string OpcodeStr, ValueType OpVT,
(ins RC:$src1, RC:$src2, X86memop:$src3),
!strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
- (MemOpFrag addr:$src3))))]>,
+ (load addr:$src3))))]>,
VEX, VVVV, Sched<[Sched.Folded, Sched.ReadAfterFold]>;
}
let Predicates = [HasAVXVNNIINT8] in {
- defm VPDPBSSD : avx_dotprod_rm<0x50,"vpdpbssd", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpbssd, SchedWriteVecIMul.XMM,
+ defm VPDPBSSD : avx_dotprod_rm<0x50,"vpdpbssd", v4i32, VR128, i128mem,
+ X86vpdpbssd, SchedWriteVecIMul.XMM,
1>, T8, XD;
- defm VPDPBSSDY : avx_dotprod_rm<0x50,"vpdpbssd", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpbssd, SchedWriteVecIMul.YMM,
+ defm VPDPBSSDY : avx_dotprod_rm<0x50,"vpdpbssd", v8i32, VR256, i256mem,
+ X86vpdpbssd, SchedWriteVecIMul.YMM,
1>, VEX_L, T8, XD;
- defm VPDPBUUD : avx_dotprod_rm<0x50,"vpdpbuud", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpbuud, SchedWriteVecIMul.XMM,
+ defm VPDPBUUD : avx_dotprod_rm<0x50,"vpdpbuud", v4i32, VR128, i128mem,
+ X86vpdpbuud, SchedWriteVecIMul.XMM,
1>, T8;
- defm VPDPBUUDY : avx_dotprod_rm<0x50,"vpdpbuud", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpbuud, SchedWriteVecIMul.YMM,
+ defm VPDPBUUDY : avx_dotprod_rm<0x50,"vpdpbuud", v8i32, VR256, i256mem,
+ X86vpdpbuud, SchedWriteVecIMul.YMM,
1>, VEX_L, T8;
- defm VPDPBSSDS : avx_dotprod_rm<0x51,"vpdpbssds", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpbssds, SchedWriteVecIMul.XMM,
+ defm VPDPBSSDS : avx_dotprod_rm<0x51,"vpdpbssds", v4i32, VR128, i128mem,
+ X86vpdpbssds, SchedWriteVecIMul.XMM,
1>, T8, XD;
- defm VPDPBSSDSY : avx_dotprod_rm<0x51,"vpdpbssds", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpbssds, SchedWriteVecIMul.YMM,
+ defm VPDPBSSDSY : avx_dotprod_rm<0x51,"vpdpbssds", v8i32, VR256, i256mem,
+ X86vpdpbssds, SchedWriteVecIMul.YMM,
1>, VEX_L, T8, XD;
- defm VPDPBUUDS : avx_dotprod_rm<0x51,"vpdpbuuds", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpbuuds, SchedWriteVecIMul.XMM,
+ defm VPDPBUUDS : avx_dotprod_rm<0x51,"vpdpbuuds", v4i32, VR128, i128mem,
+ X86vpdpbuuds, SchedWriteVecIMul.XMM,
1>, T8;
- defm VPDPBUUDSY : avx_dotprod_rm<0x51,"vpdpbuuds", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpbuuds, SchedWriteVecIMul.YMM,
+ defm VPDPBUUDSY : avx_dotprod_rm<0x51,"vpdpbuuds", v8i32, VR256, i256mem,
+ X86vpdpbuuds, SchedWriteVecIMul.YMM,
1>, VEX_L, T8;
- defm VPDPBSUD : avx_dotprod_rm<0x50,"vpdpbsud", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpbsud, SchedWriteVecIMul.XMM,
+ defm VPDPBSUD : avx_dotprod_rm<0x50,"vpdpbsud", v4i32, VR128, i128mem,
+ X86vpdpbsud, SchedWriteVecIMul.XMM,
0>, T8, XS;
- defm VPDPBSUDY : avx_dotprod_rm<0x50,"vpdpbsud", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpbsud, SchedWriteVecIMul.YMM,
+ defm VPDPBSUDY : avx_dotprod_rm<0x50,"vpdpbsud", v8i32, VR256, i256mem,
+ X86vpdpbsud, SchedWriteVecIMul.YMM,
0>, VEX_L, T8, XS;
- defm VPDPBSUDS : avx_dotprod_rm<0x51,"vpdpbsuds", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpbsuds, SchedWriteVecIMul.XMM,
+ defm VPDPBSUDS : avx_dotprod_rm<0x51,"vpdpbsuds", v4i32, VR128, i128mem,
+ X86vpdpbsuds, SchedWriteVecIMul.XMM,
0>, T8, XS;
- defm VPDPBSUDSY : avx_dotprod_rm<0x51,"vpdpbsuds", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpbsuds, SchedWriteVecIMul.YMM,
+ defm VPDPBSUDSY : avx_dotprod_rm<0x51,"vpdpbsuds", v8i32, VR256, i256mem,
+ X86vpdpbsuds, SchedWriteVecIMul.YMM,
0>, VEX_L, T8, XS;
}
@@ -8545,40 +8545,40 @@ defm VSM4RNDS4 : SM4_Base<"vsm4rnds4", VR128, "128", loadv4i32, i128mem>, T8, X
defm VSM4RNDS4Y : SM4_Base<"vsm4rnds4", VR256, "256", loadv8i32, i256mem>, T8, XD, VEX_L, VEX, VVVV;
let Predicates = [HasAVXVNNIINT16] in {
- defm VPDPWSUD : avx_dotprod_rm<0xd2,"vpdpwsud", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpwsud, SchedWriteVecIMul.XMM,
+ defm VPDPWSUD : avx_dotprod_rm<0xd2,"vpdpwsud", v4i32, VR128, i128mem,
+ X86vpdpwsud, SchedWriteVecIMul.XMM,
0>, T8, XS;
- defm VPDPWSUDY : avx_dotprod_rm<0xd2,"vpdpwsud", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpwsud, SchedWriteVecIMul.YMM,
+ defm VPDPWSUDY : avx_dotprod_rm<0xd2,"vpdpwsud", v8i32, VR256, i256mem,
+ X86vpdpwsud, SchedWriteVecIMul.YMM,
0>, VEX_L, T8, XS;
- defm VPDPWSUDS : avx_dotprod_rm<0xd3,"vpdpwsuds", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpwsuds, SchedWriteVecIMul.XMM,
+ defm VPDPWSUDS : avx_dotprod_rm<0xd3,"vpdpwsuds", v4i32, VR128, i128mem,
+ X86vpdpwsuds, SchedWriteVecIMul.XMM,
0>, T8, XS;
- defm VPDPWSUDSY : avx_dotprod_rm<0xd3,"vpdpwsuds", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpwsuds, SchedWriteVecIMul.YMM,
+ defm VPDPWSUDSY : avx_dotprod_rm<0xd3,"vpdpwsuds", v8i32, VR256, i256mem,
+ X86vpdpwsuds, SchedWriteVecIMul.YMM,
0>, VEX_L, T8, XS;
- defm VPDPWUSD : avx_dotprod_rm<0xd2,"vpdpwusd", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpwusd, SchedWriteVecIMul.XMM,
+ defm VPDPWUSD : avx_dotprod_rm<0xd2,"vpdpwusd", v4i32, VR128, i128mem,
+ X86vpdpwusd, SchedWriteVecIMul.XMM,
0>, T8, PD;
- defm VPDPWUSDY : avx_dotprod_rm<0xd2,"vpdpwusd", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpwusd, SchedWriteVecIMul.YMM,
+ defm VPDPWUSDY : avx_dotprod_rm<0xd2,"vpdpwusd", v8i32, VR256, i256mem,
+ X86vpdpwusd, SchedWriteVecIMul.YMM,
0>, VEX_L, T8, PD;
- defm VPDPWUSDS : avx_dotprod_rm<0xd3,"vpdpwusds", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpwusds, SchedWriteVecIMul.XMM,
+ defm VPDPWUSDS : avx_dotprod_rm<0xd3,"vpdpwusds", v4i32, VR128, i128mem,
+ X86vpdpwusds, SchedWriteVecIMul.XMM,
0>, T8, PD;
- defm VPDPWUSDSY : avx_dotprod_rm<0xd3,"vpdpwusds", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpwusds, SchedWriteVecIMul.YMM,
+ defm VPDPWUSDSY : avx_dotprod_rm<0xd3,"vpdpwusds", v8i32, VR256, i256mem,
+ X86vpdpwusds, SchedWriteVecIMul.YMM,
0>, VEX_L, T8, PD;
- defm VPDPWUUD : avx_dotprod_rm<0xd2,"vpdpwuud", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpwuud, SchedWriteVecIMul.XMM,
+ defm VPDPWUUD : avx_dotprod_rm<0xd2,"vpdpwuud", v4i32, VR128, i128mem,
+ X86vpdpwuud, SchedWriteVecIMul.XMM,
1>, T8;
- defm VPDPWUUDY : avx_dotprod_rm<0xd2,"vpdpwuud", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpwuud, SchedWriteVecIMul.YMM,
+ defm VPDPWUUDY : avx_dotprod_rm<0xd2,"vpdpwuud", v8i32, VR256, i256mem,
+ X86vpdpwuud, SchedWriteVecIMul.YMM,
1>, VEX_L, T8;
- defm VPDPWUUDS : avx_dotprod_rm<0xd3,"vpdpwuuds", v4i32, VR128, loadv4i32,
- i128mem, X86vpdpwuuds, SchedWriteVecIMul.XMM,
+ defm VPDPWUUDS : avx_dotprod_rm<0xd3,"vpdpwuuds", v4i32, VR128, i128mem,
+ X86vpdpwuuds, SchedWriteVecIMul.XMM,
1>, T8;
- defm VPDPWUUDSY : avx_dotprod_rm<0xd3,"vpdpwuuds", v8i32, VR256, loadv8i32,
- i256mem, X86vpdpwuuds, SchedWriteVecIMul.YMM,
+ defm VPDPWUUDSY : avx_dotprod_rm<0xd3,"vpdpwuuds", v8i32, VR256, i256mem,
+ X86vpdpwuuds, SchedWriteVecIMul.YMM,
1>, VEX_L, T8;
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/228745
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