[llvm] [RISCV] Fix FP properties for Zvbdota instructions (PR #228737)

[Zeyi Xu via llvm-commits]

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@@ -59,15 +59,16 @@ defm VQWBDOTAS : VBdotVV<"vqwbdotas.vv", 0b101111>;  // Signed (funct6 = 0x2f)
 } // Predicates = [HasStdExtZvqwbdota8iOrZvqwbdota16i]
 
 // BF16 Batched Dot-Product Instructions
-let Predicates = [HasStdExtZvfwbdota16bf] in
+let Predicates = [HasStdExtZvfwbdota16bf], mayRaiseFPException = true in
 defm VFWBDOTA : VBdotFVV<"vfwbdota.vv", 0b101100>; // funct6 = 0x2c
 
 // OCP FP8 Batched Dot-Product Instructions
-let Predicates = [HasStdExtZvfqwbdota8f] in {
+let Predicates = [HasStdExtZvfqwbdota8f], mayRaiseFPException = true in {
 defm VFQWBDOTA : VBdotFVV<"vfqwbdota.vv", 0b101110>;         // E4M3 (funct6 = 0x2e)
 defm VFQWBDOTA_ALT : VBdotFVV<"vfqwbdota.alt.vv", 0b101111>; // E5M2 (funct6 = 0x2f)
 } // Predicates = [HasStdExtZvfqwbdota8f]
 
 // FP32 Batched Dot-Product Instructions
-let Predicates = [HasStdExtZvfbdota32f] in
+let Predicates = [HasStdExtZvfbdota32f],
+    Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in
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zeyi2 wrote:

[vfbdota.vv](https://github.com/riscv/riscv-isa-manual/blob/c152059fd5db62fe5fe2b3e302bdfa130306e41c/src/zvdota.adoc?plain=1#L332-L337) uses the dynamic rounding mode and sets FP exception flags. Since [the dynamic rounding mode is held in frm](https://github.com/riscv/riscv-isa-manual/blob/c152059fd5db62fe5fe2b3e302bdfa130306e41c/src/f-st-ext.adoc?plain=1#L119-L123), I think this instruction needs an implicit FRM use and mayRaiseFPException = true.

https://github.com/llvm/llvm-project/pull/228737