[llvm] [RISCV] Fix FP properties for Zvbdota instructions (PR #228737)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Zeyi Xu (zeyi2)

<details>
<summary>Changes</summary>

Mark all floating-point Zvbdota instructions as potentially raising FP exceptions. Add an implicit FRM use to vfbdota.vv, which uses the dynamic rounding mode. The BF16 and FP8 variants use fixed round-to-odd rounding and do not depend on FRM.

AI Usage: Assisted by AmpCode (6.1 Sol)

---
Full diff: https://github.com/llvm/llvm-project/pull/228737.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvbdota.td (+4-3) 
- (modified) llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp (+17) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvbdota.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvbdota.td
index 6a3642be0ac941..ba06253b646399 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvbdota.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvbdota.td
@@ -59,15 +59,16 @@ defm VQWBDOTAS : VBdotVV<"vqwbdotas.vv", 0b101111>;  // Signed (funct6 = 0x2f)
 } // Predicates = [HasStdExtZvqwbdota8iOrZvqwbdota16i]
 
 // BF16 Batched Dot-Product Instructions
-let Predicates = [HasStdExtZvfwbdota16bf] in
+let Predicates = [HasStdExtZvfwbdota16bf], mayRaiseFPException = true in
 defm VFWBDOTA : VBdotFVV<"vfwbdota.vv", 0b101100>; // funct6 = 0x2c
 
 // OCP FP8 Batched Dot-Product Instructions
-let Predicates = [HasStdExtZvfqwbdota8f] in {
+let Predicates = [HasStdExtZvfqwbdota8f], mayRaiseFPException = true in {
 defm VFQWBDOTA : VBdotFVV<"vfqwbdota.vv", 0b101110>;         // E4M3 (funct6 = 0x2e)
 defm VFQWBDOTA_ALT : VBdotFVV<"vfqwbdota.alt.vv", 0b101111>; // E5M2 (funct6 = 0x2f)
 } // Predicates = [HasStdExtZvfqwbdota8f]
 
 // FP32 Batched Dot-Product Instructions
-let Predicates = [HasStdExtZvfbdota32f] in
+let Predicates = [HasStdExtZvfbdota32f],
+    Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in
 defm VFBDOTA : VBdotFVV<"vfbdota.vv", 0b101011>;  // funct6 = 0x2b
diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index 3a70ceace00ec6..4d36083f83ae43 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -384,6 +384,23 @@ TEST_P(RISCVInstrInfoTest, GetDestEEW) {
   EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::TH_VMAQA_VV), 5), 5u);
 }
 
+TEST_P(RISCVInstrInfoTest, ZvbdotaFPProperties) {
+  const RISCVInstrInfo *TII = ST->getInstrInfo();
+
+  auto CheckProperties = [&](unsigned Opcode, bool UsesFRM) {
+    const MCInstrDesc &Desc = TII->get(Opcode);
+    EXPECT_TRUE(Desc.mayRaiseFPException());
+    EXPECT_EQ(Desc.hasImplicitUseOfPhysReg(RISCV::FRM), UsesFRM);
+    EXPECT_TRUE(Desc.hasImplicitUseOfPhysReg(RISCV::VL));
+    EXPECT_TRUE(Desc.hasImplicitUseOfPhysReg(RISCV::VTYPE));
+  };
+
+  CheckProperties(RISCV::VFWBDOTA_VV, false);
+  CheckProperties(RISCV::VFQWBDOTA_VV, false);
+  CheckProperties(RISCV::VFQWBDOTA_ALT_VV, false);
+  CheckProperties(RISCV::VFBDOTA_VV, true);
+}
+
 TEST_P(RISCVXQCIInstrInfoTest, XQCIEInstSize) {
   const RISCVInstrInfo *TII = ST->getInstrInfo();
   MachineBasicBlock *MBB = MF->CreateMachineBasicBlock();

``````````

</details>


https://github.com/llvm/llvm-project/pull/228737