[llvm] [CodeGen] Stop exporting cl::opts. NFC (PR #228728)
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 3 08:56:02 PDT 2026
https://github.com/MaskRay created https://github.com/llvm/llvm-project/pull/228728
AMDGPU reads -misched-prera-direction and -verify-misched, every
target's TTI reads -partial-unrolling-threshold through BasicTTIImpl.h,
and AsmPrinter reads -emit-bb-hash through extern declarations. Add
getters for them, move inline code that reads options (LiveIntervals,
MachinePipeliner, MIR2Vec) out of line, and let unittests use default
weights, so that the options can be file-local.
Aided by Opus 5.5
---
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>From 054203019607a23f04fd8df4a66799c333d091ba Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Fri, 2 Oct 2026 23:34:54 -0700
Subject: [PATCH] [CodeGen] Stop exporting cl::opts. NFC
AMDGPU reads -misched-prera-direction and -verify-misched, every
target's TTI reads -partial-unrolling-threshold through BasicTTIImpl.h,
and AsmPrinter reads -emit-bb-hash through extern declarations. Add
getters for them, move inline code that reads options (LiveIntervals,
MachinePipeliner, MIR2Vec) out of line, and let unittests use default
weights, so that the options can be file-local.
Aided by Opus 5.5
---
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 7 ++--
llvm/include/llvm/CodeGen/LiveIntervals.h | 7 +---
llvm/include/llvm/CodeGen/MIR2Vec.h | 7 +---
.../llvm/CodeGen/MachineBlockHashInfo.h | 3 ++
llvm/include/llvm/CodeGen/MachinePipeliner.h | 28 ++-----------
llvm/include/llvm/CodeGen/MachineScheduler.h | 6 ++-
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 6 +--
llvm/lib/CodeGen/BasicTargetTransformInfo.cpp | 16 +++++---
llvm/lib/CodeGen/LiveIntervals.cpp | 10 +++--
llvm/lib/CodeGen/MIR2Vec.cpp | 17 +++++---
llvm/lib/CodeGen/MachineBlockHashInfo.cpp | 9 ++++
llvm/lib/CodeGen/MachinePipeliner.cpp | 41 ++++++++++++++++---
llvm/lib/CodeGen/MachineScheduler.cpp | 7 +++-
llvm/lib/CodeGen/RegAllocScore.cpp | 22 +++++-----
llvm/lib/CodeGen/TargetPassConfig.cpp | 9 +---
llvm/lib/CodeGen/VLIWMachineScheduler.cpp | 4 +-
.../AMDGPU/AMDGPUCoExecSchedStrategy.cpp | 4 +-
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | 4 +-
llvm/unittests/CodeGen/MIR2VecTest.cpp | 32 ++++++++-------
llvm/unittests/CodeGen/RegAllocScoreTest.cpp | 13 ++----
20 files changed, 138 insertions(+), 114 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 742251de3c2426..0d9b361e95ad5e 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -68,7 +68,8 @@ class ScalarEvolution;
class SCEV;
class TargetMachine;
-extern LLVM_ABI cl::opt<unsigned> PartialUnrollingThreshold;
+/// Returns -partial-unrolling-threshold if specified.
+LLVM_ABI std::optional<unsigned> getPartialUnrollingThreshold();
/// Base class which can be used to help build a TTI implementation.
///
@@ -763,8 +764,8 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
unsigned MaxOps;
const TargetSubtargetInfo *ST = getST();
- if (PartialUnrollingThreshold.getNumOccurrences() > 0)
- MaxOps = PartialUnrollingThreshold;
+ if (std::optional<unsigned> Threshold = getPartialUnrollingThreshold())
+ MaxOps = *Threshold;
else if (ST->getSchedModel().LoopMicroOpBufferSize > 0)
MaxOps = ST->getSchedModel().LoopMicroOpBufferSize;
else
diff --git a/llvm/include/llvm/CodeGen/LiveIntervals.h b/llvm/include/llvm/CodeGen/LiveIntervals.h
index acb6faf13e791b..966c38692d0048 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervals.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervals.h
@@ -39,8 +39,6 @@
namespace llvm {
-LLVM_ABI extern cl::opt<bool> UseSegmentSetForPhysRegs;
-
class BitVector;
class MachineBlockFrequencyInfo;
class MachineDominatorTree;
@@ -439,9 +437,7 @@ class LiveIntervals {
LiveRange *LR = RegUnitRanges[static_cast<unsigned>(Unit)];
if (!LR) {
// Compute missing ranges on demand.
- // Use segment set to speed-up initial computation of the live range.
- RegUnitRanges[static_cast<unsigned>(Unit)] = LR =
- new LiveRange(UseSegmentSetForPhysRegs);
+ RegUnitRanges[static_cast<unsigned>(Unit)] = LR = createRegUnitRange();
computeRegUnitRange(*LR, Unit);
}
return *LR;
@@ -520,6 +516,7 @@ class LiveIntervals {
SmallVectorImpl<MachineInstr *> *dead);
LLVM_ABI static LiveInterval *createInterval(Register Reg);
+ LLVM_ABI static LiveRange *createRegUnitRange();
void printInstrs(raw_ostream &O) const;
void dumpInstrs() const;
diff --git a/llvm/include/llvm/CodeGen/MIR2Vec.h b/llvm/include/llvm/CodeGen/MIR2Vec.h
index 7d936c6d3c8f54..815836ae957dad 100644
--- a/llvm/include/llvm/CodeGen/MIR2Vec.h
+++ b/llvm/include/llvm/CodeGen/MIR2Vec.h
@@ -75,7 +75,6 @@ class MIREmbedder;
class SymbolicMIREmbedder;
LLVM_ABI extern llvm::cl::OptionCategory MIR2VecCategory;
-LLVM_ABI extern cl::opt<float> OpcWeight, CommonOperandWeight, RegOperandWeight;
using Embedding = ir2vec::Embedding;
using MachineInstEmbeddingsMap = DenseMap<const MachineInstr *, Embedding>;
@@ -307,11 +306,7 @@ class MIREmbedder {
/// Weight for opcode embeddings
const float OpcWeight, CommonOperandWeight, RegOperandWeight;
- MIREmbedder(const MachineFunction &MF, const MIRVocabulary &Vocab)
- : MF(MF), Vocab(Vocab), Dimension(Vocab.getDimension()),
- OpcWeight(mir2vec::OpcWeight),
- CommonOperandWeight(mir2vec::CommonOperandWeight),
- RegOperandWeight(mir2vec::RegOperandWeight) {}
+ LLVM_ABI MIREmbedder(const MachineFunction &MF, const MIRVocabulary &Vocab);
/// Function to compute embeddings.
LLVM_ABI Embedding computeEmbeddings() const;
diff --git a/llvm/include/llvm/CodeGen/MachineBlockHashInfo.h b/llvm/include/llvm/CodeGen/MachineBlockHashInfo.h
index c7e70543617012..2e4c839060ca53 100644
--- a/llvm/include/llvm/CodeGen/MachineBlockHashInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineBlockHashInfo.h
@@ -18,6 +18,9 @@
namespace llvm {
+/// Returns whether -emit-bb-hash is set.
+LLVM_ABI bool shouldEmitBBHash();
+
/// An object wrapping several components of a basic block hash. The combined
/// (blended) hash is represented and stored as one uint64_t, while individual
/// components are of smaller size (e.g., uint16_t or uint8_t).
diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h
index cfc69bb1be018c..6c72d98723ef39 100644
--- a/llvm/include/llvm/CodeGen/MachinePipeliner.h
+++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h
@@ -62,9 +62,6 @@ class LiveIntervals;
class NodeSet;
class SMSchedule;
-extern LLVM_ABI cl::opt<bool> SwpEnableCopyToPhi;
-extern LLVM_ABI cl::opt<int> SwpForceIssueWidth;
-
/// Software pipelining policy for a loop, which a target can customize by
/// implementing TargetSubtargetInfo::overridePipelinerPolicy.
struct MachinePipelinerPolicy {
@@ -367,16 +364,7 @@ class LLVM_ABI SwingSchedulerDAG : public ScheduleDAGInstrs {
MachineOptimizationRemarkEmitter *ORE, MachineLoop &L,
LiveIntervals &lis, const RegisterClassInfo &rci,
unsigned II, TargetInstrInfo::PipelinerLoopInfo *PLI,
- AliasAnalysis *AA)
- : ScheduleDAGInstrs(MF, MLI, false), ORE(ORE), Loop(L), LIS(lis),
- RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI),
- Topo(SUnits, &ExitSU), AA(AA), BAA(*AA) {
- initPolicy();
- MF.getSubtarget().getSMSMutations(Mutations);
- if (SwpEnableCopyToPhi)
- Mutations.push_back(std::make_unique<CopyToPhiMutation>());
- BAA.enableCrossIterationMode();
- }
+ AliasAnalysis *AA);
void schedule() override;
void finishBlock() override;
@@ -678,18 +666,8 @@ class ResourceManager {
#endif
public:
- ResourceManager(const TargetSubtargetInfo *ST, ScheduleDAGInstrs *DAG)
- : STI(ST), SM(ST->getSchedModel()), ST(ST), TII(ST->getInstrInfo()),
- DAG(DAG), UseDFA(ST->useDFAforSMS()),
- ProcResourceMasks(SM.getNumProcResourceKinds(), 0),
- IssueWidth(SM.IssueWidth) {
- initProcResourceVectors(SM, ProcResourceMasks);
- if (IssueWidth <= 0)
- // If IssueWidth is not specified, set a sufficiently large value
- IssueWidth = 100;
- if (SwpForceIssueWidth > 0)
- IssueWidth = SwpForceIssueWidth;
- }
+ LLVM_ABI ResourceManager(const TargetSubtargetInfo *ST,
+ ScheduleDAGInstrs *DAG);
LLVM_ABI void initProcResourceVectors(const MCSchedModel &SM,
SmallVectorImpl<uint64_t> &Masks);
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 5280a2376c34a0..a9eac924aa7f3e 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -117,8 +117,10 @@ enum Direction {
};
} // namespace MISched
-LLVM_ABI extern cl::opt<MISched::Direction> PreRADirection;
-LLVM_ABI extern cl::opt<bool> VerifyScheduling;
+/// Returns -misched-prera-direction.
+LLVM_ABI MISched::Direction getPreRADirection();
+/// Returns whether -verify-misched is set.
+LLVM_ABI bool shouldVerifyScheduling();
#ifndef NDEBUG
extern cl::opt<bool> ViewMISchedDAGs;
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index ae8d8fbe84c03d..37de384df866fd 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -195,8 +195,6 @@ static cl::opt<std::string>
cl::desc("Output filename for stack usage information"),
cl::value_desc("filename"), cl::Hidden);
-extern cl::opt<bool> EmitBBHash;
-
STATISTIC(EmittedInsts, "Number of machine instrs printed");
char AsmPrinter::ID = 0;
@@ -512,7 +510,7 @@ void AsmPrinter::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<GCModuleInfo>();
AU.addRequired<LazyMachineBlockFrequencyInfoPass>();
AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
- if (EmitBBHash)
+ if (shouldEmitBBHash())
AU.addRequired<MachineBlockHashInfo>();
AU.addUsedIfAvailable<BasicBlockSectionsProfileReaderWrapperPass>();
}
@@ -1516,7 +1514,7 @@ getBBAddrMapFeature(const MachineFunction &MF, int NumMBBSectionRanges,
MF.hasBBSections() && NumMBBSectionRanges > 1,
// Use static_cast to avoid breakage of tests on windows.
static_cast<bool>(BBAddrMapSkipEmitBBEntries), HasCalls,
- static_cast<bool>(EmitBBHash), PostLinkCfgEnabled};
+ shouldEmitBBHash(), PostLinkCfgEnabled};
}
void AsmPrinter::emitBBAddrMapSection(const MachineFunction &MF) {
diff --git a/llvm/lib/CodeGen/BasicTargetTransformInfo.cpp b/llvm/lib/CodeGen/BasicTargetTransformInfo.cpp
index 80a4eb86cf9ef0..73fb78fe296f81 100644
--- a/llvm/lib/CodeGen/BasicTargetTransformInfo.cpp
+++ b/llvm/lib/CodeGen/BasicTargetTransformInfo.cpp
@@ -22,12 +22,16 @@
using namespace llvm;
-// This flag is used by the template base class for BasicTTIImpl, and here to
-// provide a definition.
-cl::opt<unsigned>
-llvm::PartialUnrollingThreshold("partial-unrolling-threshold", cl::init(0),
- cl::desc("Threshold for partial unrolling"),
- cl::Hidden);
+static cl::opt<unsigned>
+ PartialUnrollingThreshold("partial-unrolling-threshold", cl::init(0),
+ cl::desc("Threshold for partial unrolling"),
+ cl::Hidden);
+
+std::optional<unsigned> llvm::getPartialUnrollingThreshold() {
+ if (PartialUnrollingThreshold.getNumOccurrences())
+ return PartialUnrollingThreshold;
+ return std::nullopt;
+}
BasicTTIImpl::BasicTTIImpl(const TargetMachine *TM, const Function &F)
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index 0e4435ddc2c0dc..b0c18d5d5fe5da 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -104,7 +104,7 @@ static cl::opt<bool> EnablePrecomputePhysRegs(
static bool EnablePrecomputePhysRegs = false;
#endif // NDEBUG
-cl::opt<bool> llvm::UseSegmentSetForPhysRegs(
+static cl::opt<bool> UseSegmentSetForPhysRegs(
"use-segment-set-for-physregs", cl::Hidden, cl::init(true),
cl::desc(
"Use segment set for the computation of the live ranges of physregs."));
@@ -224,6 +224,11 @@ LiveInterval *LiveIntervals::createInterval(Register reg) {
return new LiveInterval(reg, Weight);
}
+LiveRange *LiveIntervals::createRegUnitRange() {
+ // Use segment set to speed-up initial computation of the live range.
+ return new LiveRange(UseSegmentSetForPhysRegs);
+}
+
/// Compute the live interval of a virtual register, based on defs and uses.
bool LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
assert(LICalc && "LICalc not initialized.");
@@ -411,9 +416,8 @@ void LiveIntervals::computeLiveInRegUnits() {
for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
LiveRange *LR = RegUnitRanges[static_cast<unsigned>(Unit)];
if (!LR) {
- // Use segment set to speed-up initial computation of the live range.
LR = RegUnitRanges[static_cast<unsigned>(Unit)] =
- new LiveRange(UseSegmentSetForPhysRegs);
+ createRegUnitRange();
NewRanges.push_back(Unit);
}
VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
diff --git a/llvm/lib/CodeGen/MIR2Vec.cpp b/llvm/lib/CodeGen/MIR2Vec.cpp
index 30f30ec57020d7..945acdc07584b1 100644
--- a/llvm/lib/CodeGen/MIR2Vec.cpp
+++ b/llvm/lib/CodeGen/MIR2Vec.cpp
@@ -41,14 +41,15 @@ static cl::opt<std::string>
VocabFile("mir2vec-vocab-path",
cl::desc("Path to the vocabulary file for MIR2Vec"), cl::init(""),
cl::cat(MIR2VecCategory));
-cl::opt<float> OpcWeight("mir2vec-opc-weight", cl::init(1.0),
- cl::desc("Weight for machine opcode embeddings"),
- cl::cat(MIR2VecCategory));
-cl::opt<float>
+static cl::opt<float>
+ OpcWeight("mir2vec-opc-weight", cl::init(1.0),
+ cl::desc("Weight for machine opcode embeddings"),
+ cl::cat(MIR2VecCategory));
+static cl::opt<float>
CommonOperandWeight("mir2vec-common-operand-weight", cl::init(1.0),
cl::desc("Weight for common operand embeddings"),
cl::cat(MIR2VecCategory));
-cl::opt<float>
+static cl::opt<float>
RegOperandWeight("mir2vec-reg-operand-weight", cl::init(1.0),
cl::desc("Weight for register operand embeddings"),
cl::cat(MIR2VecCategory));
@@ -549,6 +550,12 @@ std::unique_ptr<MIREmbedder> MIREmbedder::create(MIR2VecKind Mode,
return nullptr;
}
+MIREmbedder::MIREmbedder(const MachineFunction &MF, const MIRVocabulary &Vocab)
+ : MF(MF), Vocab(Vocab), Dimension(Vocab.getDimension()),
+ OpcWeight(mir2vec::OpcWeight),
+ CommonOperandWeight(mir2vec::CommonOperandWeight),
+ RegOperandWeight(mir2vec::RegOperandWeight) {}
+
Embedding MIREmbedder::computeEmbeddings(const MachineBasicBlock &MBB) const {
Embedding MBBVector(Dimension, 0);
diff --git a/llvm/lib/CodeGen/MachineBlockHashInfo.cpp b/llvm/lib/CodeGen/MachineBlockHashInfo.cpp
index cf284ada5b7106..f7d1729629bf3a 100644
--- a/llvm/lib/CodeGen/MachineBlockHashInfo.cpp
+++ b/llvm/lib/CodeGen/MachineBlockHashInfo.cpp
@@ -15,11 +15,20 @@
#include "llvm/CodeGen/MachineStableHash.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/InitializePasses.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
+static cl::opt<bool> EmitBBHash(
+ "emit-bb-hash",
+ cl::desc(
+ "Emit the hash of basic block in the SHT_LLVM_BB_ADDR_MAP section."),
+ cl::init(false));
+
+bool llvm::shouldEmitBBHash() { return EmitBBHash; }
+
// Frozen mixer; the block hashes computed below are serialized into BB
// section profile data, so this function's exact output is part of the
// on-disk format. Do not change without versioning that format.
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 8bf7b804ddc756..3d7c1f1f8a9e56 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -203,14 +203,14 @@ static cl::opt<unsigned> SwpMaxNumStores(
cl::init(200));
// A command line option to enable the CopyToPhi DAG mutation.
-cl::opt<bool>
- llvm::SwpEnableCopyToPhi("pipeliner-enable-copytophi", cl::ReallyHidden,
- cl::init(true),
- cl::desc("Enable CopyToPhi DAG Mutation"));
+static cl::opt<bool>
+ SwpEnableCopyToPhi("pipeliner-enable-copytophi", cl::ReallyHidden,
+ cl::init(true),
+ cl::desc("Enable CopyToPhi DAG Mutation"));
/// A command line argument to force pipeliner to use specified issue
/// width.
-cl::opt<int> llvm::SwpForceIssueWidth(
+static cl::opt<int> SwpForceIssueWidth(
"pipeliner-force-issue-width",
cl::desc("Force pipeliner to use specified issue width."), cl::Hidden,
cl::init(-1));
@@ -867,6 +867,23 @@ void SwingSchedulerDAG::setMAX_II() {
MAX_II = MII + SwpIISearchRange;
}
+SwingSchedulerDAG::SwingSchedulerDAG(MachineFunction &MF,
+ const MachineLoopInfo *MLI,
+ MachineOptimizationRemarkEmitter *ORE,
+ MachineLoop &L, LiveIntervals &lis,
+ const RegisterClassInfo &rci, unsigned II,
+ TargetInstrInfo::PipelinerLoopInfo *PLI,
+ AliasAnalysis *AA)
+ : ScheduleDAGInstrs(MF, MLI, false), ORE(ORE), Loop(L), LIS(lis),
+ RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI),
+ Topo(SUnits, &ExitSU), AA(AA), BAA(*AA) {
+ initPolicy();
+ MF.getSubtarget().getSMSMutations(Mutations);
+ if (SwpEnableCopyToPhi)
+ Mutations.push_back(std::make_unique<CopyToPhiMutation>());
+ BAA.enableCrossIterationMode();
+}
+
/// We override the schedule function in ScheduleDAGInstrs to implement the
/// scheduling part of the Swing Modulo Scheduling algorithm.
void SwingSchedulerDAG::schedule() {
@@ -3997,6 +4014,20 @@ void ResourceManager::dumpMRT() const {
}
#endif
+ResourceManager::ResourceManager(const TargetSubtargetInfo *ST,
+ ScheduleDAGInstrs *DAG)
+ : STI(ST), SM(ST->getSchedModel()), ST(ST), TII(ST->getInstrInfo()),
+ DAG(DAG), UseDFA(ST->useDFAforSMS()),
+ ProcResourceMasks(SM.getNumProcResourceKinds(), 0),
+ IssueWidth(SM.IssueWidth) {
+ initProcResourceVectors(SM, ProcResourceMasks);
+ if (IssueWidth <= 0)
+ // If IssueWidth is not specified, set a sufficiently large value
+ IssueWidth = 100;
+ if (SwpForceIssueWidth > 0)
+ IssueWidth = SwpForceIssueWidth;
+}
+
void ResourceManager::initProcResourceVectors(
const MCSchedModel &SM, SmallVectorImpl<uint64_t> &Masks) {
unsigned ProcResourceID = 0;
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index facf741f124005..5272931d6c5f3c 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -176,7 +176,7 @@ STATISTIC(NumNodeOrderPostRA,
STATISTIC(NumFirstValidPostRA,
"Number of scheduling units chosen for FirstValid heuristic post-RA");
-cl::opt<MISched::Direction> llvm::PreRADirection(
+static cl::opt<MISched::Direction> PreRADirection(
"misched-prera-direction", cl::Hidden,
cl::desc("Pre reg-alloc list scheduling direction"),
cl::init(MISched::Unspecified),
@@ -204,10 +204,13 @@ static cl::opt<bool>
DumpCriticalPathLength("misched-dcpl", cl::Hidden,
cl::desc("Print critical path length to stdout"));
-cl::opt<bool> llvm::VerifyScheduling(
+static cl::opt<bool> VerifyScheduling(
"verify-misched", cl::Hidden,
cl::desc("Verify machine instrs before and after machine scheduling"));
+MISched::Direction llvm::getPreRADirection() { return PreRADirection; }
+bool llvm::shouldVerifyScheduling() { return VerifyScheduling; }
+
#ifndef NDEBUG
cl::opt<bool> llvm::ViewMISchedDAGs(
"view-misched-dags", cl::Hidden,
diff --git a/llvm/lib/CodeGen/RegAllocScore.cpp b/llvm/lib/CodeGen/RegAllocScore.cpp
index 280946bb0d0b32..114decec7e5f08 100644
--- a/llvm/lib/CodeGen/RegAllocScore.cpp
+++ b/llvm/lib/CodeGen/RegAllocScore.cpp
@@ -24,18 +24,16 @@
using namespace llvm;
-namespace llvm {
-LLVM_ABI cl::opt<double> CopyWeight("regalloc-copy-weight", cl::init(0.2),
- cl::Hidden);
-LLVM_ABI cl::opt<double> LoadWeight("regalloc-load-weight", cl::init(4.0),
- cl::Hidden);
-LLVM_ABI cl::opt<double> StoreWeight("regalloc-store-weight", cl::init(1.0),
- cl::Hidden);
-LLVM_ABI cl::opt<double> CheapRematWeight("regalloc-cheap-remat-weight",
- cl::init(0.2), cl::Hidden);
-LLVM_ABI cl::opt<double> ExpensiveRematWeight("regalloc-expensive-remat-weight",
- cl::init(1.0), cl::Hidden);
-} // end namespace llvm
+static cl::opt<double> CopyWeight("regalloc-copy-weight", cl::init(0.2),
+ cl::Hidden);
+static cl::opt<double> LoadWeight("regalloc-load-weight", cl::init(4.0),
+ cl::Hidden);
+static cl::opt<double> StoreWeight("regalloc-store-weight", cl::init(1.0),
+ cl::Hidden);
+static cl::opt<double> CheapRematWeight("regalloc-cheap-remat-weight",
+ cl::init(0.2), cl::Hidden);
+static cl::opt<double> ExpensiveRematWeight("regalloc-expensive-remat-weight",
+ cl::init(1.0), cl::Hidden);
#define DEBUG_TYPE "regalloc-score"
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index d7bb131c972564..9683d988e80848 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/BasicBlockSectionsProfileReader.h"
#include "llvm/CodeGen/CSEConfigBase.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
+#include "llvm/CodeGen/MachineBlockHashInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/Passes.h"
@@ -292,12 +293,6 @@ static cl::opt<bool> BasicBlockSectionMatchInfer(
"Enable matching and inference when generating basic block sections"),
cl::init(false));
-cl::opt<bool> EmitBBHash(
- "emit-bb-hash",
- cl::desc(
- "Emit the hash of basic block in the SHT_LLVM_BB_ADDR_MAP section."),
- cl::init(false));
-
/// Allow standard passes to be disabled by command line options. This supports
/// simple binary flags that either suppress the pass or do nothing.
/// i.e. -disable-mypass=false has no effect.
@@ -1304,7 +1299,7 @@ void TargetPassConfig::addMachinePasses() {
// address map (or both).
if (TM->getBBSectionsType() != llvm::BasicBlockSection::None ||
TM->Options.BBAddrMap) {
- if (EmitBBHash || BasicBlockSectionMatchInfer)
+ if (shouldEmitBBHash() || BasicBlockSectionMatchInfer)
addPass(llvm::createMachineBlockHashInfoPass());
if (TM->getBBSectionsType() == llvm::BasicBlockSection::List) {
addPass(llvm::createBasicBlockSectionsProfileReaderWrapperPass(
diff --git a/llvm/lib/CodeGen/VLIWMachineScheduler.cpp b/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
index 53d166d277cb87..605664c41359ee 100644
--- a/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
+++ b/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
@@ -950,7 +950,7 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
return nullptr;
}
SUnit *SU;
- if (PreRADirection == MISched::TopDown) {
+ if (getPreRADirection() == MISched::TopDown) {
SU = Top.pickOnlyChoice();
if (!SU) {
SchedCandidate TopCand;
@@ -961,7 +961,7 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
SU = TopCand.SU;
}
IsTopNode = true;
- } else if (PreRADirection == MISched::BottomUp) {
+ } else if (getPreRADirection() == MISched::BottomUp) {
SU = Bot.pickOnlyChoice();
if (!SU) {
SchedCandidate BotCand;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
index a0704ce975dde3..2955b7c86a34b9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
@@ -1083,8 +1083,8 @@ void AMDGPUCoExecSchedStrategy::initPolicy(MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) {
GCNSchedStrategy::initPolicy(Begin, End, NumRegionInstrs);
- if (PreRADirection == MISched::BottomUp ||
- PreRADirection == MISched::Bidirectional)
+ if (getPreRADirection() == MISched::BottomUp ||
+ getPreRADirection() == MISched::Bidirectional)
report_fatal_error("CoExecSchedStrategy only support TopDown scheduling.");
RegionPolicy.OnlyTopDown = true;
RegionPolicy.OnlyBottomUp = false;
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 070122415ad5a6..028a61e8af17d6 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -568,7 +568,7 @@ SUnit *GCNSchedStrategy::pickNodeBidirectional(bool &IsTopNode,
} else {
LLVM_DEBUG(traceCandidate(BotCand));
#ifndef NDEBUG
- if (VerifyScheduling) {
+ if (shouldVerifyScheduling()) {
SchedCandidate TCand;
TCand.reset(CandPolicy());
pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), TCand,
@@ -593,7 +593,7 @@ SUnit *GCNSchedStrategy::pickNodeBidirectional(bool &IsTopNode,
} else {
LLVM_DEBUG(traceCandidate(TopCand));
#ifndef NDEBUG
- if (VerifyScheduling) {
+ if (shouldVerifyScheduling()) {
SchedCandidate TCand;
TCand.reset(CandPolicy());
pickNodeFromQueue(Top, TopPolicy, DAG->getTopRPTracker(), TCand,
diff --git a/llvm/unittests/CodeGen/MIR2VecTest.cpp b/llvm/unittests/CodeGen/MIR2VecTest.cpp
index 723fedb18735c7..38c0b2ca26ee5e 100644
--- a/llvm/unittests/CodeGen/MIR2VecTest.cpp
+++ b/llvm/unittests/CodeGen/MIR2VecTest.cpp
@@ -29,6 +29,10 @@ using VocabMap = std::map<std::string, ir2vec::Embedding>;
namespace {
+// Defaults of -mir2vec-*-weight.
+constexpr float OpcWeight = 1.0f, CommonOperandWeight = 1.0f,
+ RegOperandWeight = 1.0f;
+
TEST(MIR2VecTest, RegexExtraction) {
// Test simple instruction names
EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("NOP"), "NOP");
@@ -422,7 +426,7 @@ TEST_F(MIR2VecEmbeddingTestFixture, TestSymbolicEmbedder) {
auto TrapEmb = Embedder->getMInstVector(*TrapInst);
// Verify embeddings match expected values (accounting for weight scaling)
- float ExpectedWeight = mir2vec::OpcWeight; // Global weight from command line
+ float ExpectedWeight = OpcWeight;
EXPECT_TRUE(NoopEmb.approximatelyEquals(Embedding(4, 1.0f * ExpectedWeight)));
EXPECT_TRUE(RetEmb.approximatelyEquals(Embedding(4, 2.0f * ExpectedWeight)));
EXPECT_TRUE(TrapEmb.approximatelyEquals(Embedding(4, 3.0f * ExpectedWeight)));
@@ -466,7 +470,7 @@ TEST_F(MIR2VecEmbeddingTestFixture, MultipleBasicBlocks) {
auto MBB1Vector = Embedder->getMBBVector(*MBB1);
auto MBB2Vector = Embedder->getMBBVector(*MBB2);
- float ExpectedWeight = mir2vec::OpcWeight;
+ float ExpectedWeight = OpcWeight;
// BB1: NOOP + NOOP = 2 * ([1, 1] * weight)
Embedding ExpectedMBB1Vector(2, 2.0f * ExpectedWeight);
EXPECT_TRUE(MBB1Vector.approximatelyEquals(ExpectedMBB1Vector));
@@ -547,7 +551,7 @@ TEST_F(MIR2VecEmbeddingTestFixture, UnknownOpcodes) {
auto AddVector = Embedder->getMInstVector(*AddInstr);
auto SubVector = Embedder->getMInstVector(*SubInstr);
- float ExpectedWeight = mir2vec::OpcWeight;
+ float ExpectedWeight = OpcWeight;
// ADD should have the embedding from vocabulary
EXPECT_TRUE(
AddVector.approximatelyEquals(Embedding(2, 1.0f * ExpectedWeight)));
@@ -657,14 +661,14 @@ TEST_F(MIR2VecEmbeddingTestFixture, InvalidRegisterHandling) {
EXPECT_EQ(InstEmb.size(), 3u);
// Test the expected embedding value
- Embedding ExpectedOpcodeContribution(3, MOVValue * mir2vec::OpcWeight);
+ Embedding ExpectedOpcodeContribution(3, MOVValue * OpcWeight);
auto ExpectedOperandContribution =
- Embedding(3, PhyRegValue * mir2vec::RegOperandWeight) // Base
- + Embedding(3, ImmValue * mir2vec::CommonOperandWeight) // Scale
- + Embedding(3, 0.0f) // noreg
- + Embedding(3, ImmValue * mir2vec::CommonOperandWeight) // displacement
- + Embedding(3, 0.0f) // noreg
- + Embedding(3, (PhyRegValue + 0.1f) * mir2vec::RegOperandWeight); // Value
+ Embedding(3, PhyRegValue * RegOperandWeight) // Base
+ + Embedding(3, ImmValue * CommonOperandWeight) // Scale
+ + Embedding(3, 0.0f) // noreg
+ + Embedding(3, ImmValue * CommonOperandWeight) // displacement
+ + Embedding(3, 0.0f) // noreg
+ + Embedding(3, (PhyRegValue + 0.1f) * RegOperandWeight); // Value
auto ExpectedEmb = ExpectedOpcodeContribution + ExpectedOperandContribution;
EXPECT_TRUE(InstEmb.approximatelyEquals(ExpectedEmb))
<< "MOV instruction embedding should match expected embedding";
@@ -725,10 +729,10 @@ TEST_F(MIR2VecEmbeddingTestFixture, PhysicalAndVirtualRegisterHandling) {
EXPECT_EQ(InstEmb.size(), 4u);
// Test the expected embedding value
- Embedding ExpectedOpcodeContribution(4, MOVValue * mir2vec::OpcWeight);
+ Embedding ExpectedOpcodeContribution(4, MOVValue * OpcWeight);
auto ExpectedOperandContribution =
- Embedding(4, PhyRegValue * mir2vec::RegOperandWeight) // dst (physical)
- + Embedding(4, VirtRegValue * mir2vec::RegOperandWeight); // src (virtual)
+ Embedding(4, PhyRegValue * RegOperandWeight) // dst (physical)
+ + Embedding(4, VirtRegValue * RegOperandWeight); // src (virtual)
auto ExpectedEmb = ExpectedOpcodeContribution + ExpectedOperandContribution;
EXPECT_TRUE(InstEmb.approximatelyEquals(ExpectedEmb))
<< "MOV32rr instruction embedding should match expected embedding";
@@ -757,7 +761,7 @@ TEST_F(MIR2VecEmbeddingTestFixture, EmbeddingCalculation) {
// For NOOP with no operands, the embedding should be exactly the opcode
// embedding
- float ExpectedWeight = mir2vec::OpcWeight;
+ float ExpectedWeight = OpcWeight;
Embedding ExpectedEmb(2, 2.0f * ExpectedWeight);
EXPECT_TRUE(InstEmb.approximatelyEquals(ExpectedEmb))
diff --git a/llvm/unittests/CodeGen/RegAllocScoreTest.cpp b/llvm/unittests/CodeGen/RegAllocScoreTest.cpp
index 432dc9348fbd3c..2a8edd0439a68e 100644
--- a/llvm/unittests/CodeGen/RegAllocScoreTest.cpp
+++ b/llvm/unittests/CodeGen/RegAllocScoreTest.cpp
@@ -24,7 +24,6 @@
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/TargetRegistry.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/Triple.h"
@@ -32,15 +31,11 @@
using namespace llvm;
-namespace llvm {
-LLVM_ABI extern cl::opt<double> CopyWeight;
-LLVM_ABI extern cl::opt<double> LoadWeight;
-LLVM_ABI extern cl::opt<double> StoreWeight;
-LLVM_ABI extern cl::opt<double> CheapRematWeight;
-LLVM_ABI extern cl::opt<double> ExpensiveRematWeight;
-} // namespace llvm
-
namespace {
+// Defaults of -regalloc-*-weight.
+constexpr double CopyWeight = 0.2, LoadWeight = 4.0, StoreWeight = 1.0,
+ CheapRematWeight = 0.2, ExpensiveRematWeight = 1.0;
+
// Include helper functions to ease the manipulation of MachineFunctions.
#include "MFCommon.inc"
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