[llvm] [AMDGPU] Add an SCC def to the wave.reduce pseudos (PR #228723)
Mian Miftah via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 3 08:24:51 PDT 2026
https://github.com/mmiftahx created https://github.com/llvm/llvm-project/pull/228723
The wave.reduce pseudos expand into code that writes SCC: the Iterative
loop's compare, s_bcnt1 for a uniform value, and the s_sub that negates
the result of a DPP sub. They don't declare it, so SelectionDAG can keep
a compare's result in SCC across the reduction, and a branch or select
after it then reads SCC from the expansion instead. The verifier reports
"Using an undefined physical register" in both cases. Without the
verifier, llc with assertions aborts in the machine scheduler on the
branch after the Iterative loop, and the select after a uniform
reduction is silently wrong.
Add Defs = [SCC], as #227604 did for the kill pseudos. The SCC defs that
#226370 marked dead in the expansion are then correct.
>From efcba1dbad3d0ecd0292e55a7127eb31aca5a363 Mon Sep 17 00:00:00 2001
From: mmiftahx <mmiftah.duna at gmail.com>
Date: Thu, 1 Oct 2026 21:41:58 -0500
Subject: [PATCH 1/2] [AMDGPU] Add a test for SCC live across wave.reduce (NFC)
A select of a uniform compare after a uniform wave.reduce reads the SCC
written by the reduction's s_bcnt1 instead of the compare's.
---
.../CodeGen/AMDGPU/wave-reduce-live-scc.ll | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/wave-reduce-live-scc.ll
diff --git a/llvm/test/CodeGen/AMDGPU/wave-reduce-live-scc.ll b/llvm/test/CodeGen/AMDGPU/wave-reduce-live-scc.ll
new file mode 100644
index 00000000000000..0aa8c0176e434e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/wave-reduce-live-scc.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu9.00 -global-isel=0 < %s | FileCheck %s
+
+; The wave.reduce expansions write SCC. A uniform condition that is live
+; across the call must not be read from SCC after it.
+; FIXME: The select reads the SCC written by s_bcnt1, not by the compare.
+
+define amdgpu_kernel void @add_uniform_live_scc(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %u) {
+; CHECK-LABEL: add_uniform_live_scc:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; CHECK-NEXT: ; kill: killed $sgpr4_sgpr5
+; CHECK-NEXT: s_mov_b64 s[4:5], exec
+; CHECK-NEXT: s_bcnt1_i32_b64 s3, s[4:5]
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: s_mul_i32 s2, s2, s3
+; CHECK-NEXT: s_cselect_b32 s2, s2, 1
+; CHECK-NEXT: v_mov_b32_e32 v1, s2
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: global_store_dword v0, v1, s[0:1]
+; CHECK-NEXT: s_endpgm
+ %c = icmp eq i32 %a, %b
+ %r = call i32 @llvm.amdgcn.wave.reduce.add.i32(i32 %u, i32 0)
+ %s = select i1 %c, i32 %r, i32 1
+ store i32 %s, ptr addrspace(1) %out
+ ret void
+}
>From b89442bcd4748be970eb9e33a6c2dbcd6226808c Mon Sep 17 00:00:00 2001
From: mmiftahx <mmiftah.duna at gmail.com>
Date: Thu, 1 Oct 2026 21:41:58 -0500
Subject: [PATCH 2/2] [AMDGPU] Add an SCC def to the wave.reduce pseudos
The wave.reduce pseudos expand into code that writes SCC: the Iterative
loop's compare, s_bcnt1 for a uniform value, and the s_sub that negates
the result of a DPP sub. They don't declare it, so SelectionDAG can keep
a compare's result in SCC across the reduction, and a branch or select
after it then reads SCC from the expansion instead. The verifier reports
"Using an undefined physical register" in both cases. Without the
verifier, llc with assertions aborts in the machine scheduler on the
branch after the Iterative loop, and the select after a uniform
reduction is silently wrong.
Add Defs = [SCC], as #227604 did for the kill pseudos. The SCC defs that
#226370 marked dead in the expansion are then correct.
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 2 +-
.../global-atomic-fadd.f32-no-rtn.ll | 8 +--
.../AMDGPU/global-atomic-fadd.f32-no-rtn.ll | 6 +-
.../CodeGen/AMDGPU/wave-reduce-live-scc.ll | 57 +++++++++++++++----
4 files changed, 55 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index c7976983b727f4..417940c551805b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -363,7 +363,7 @@ def : GCNPat<(i32 (int_amdgcn_set_inactive_chain_arg i32:$src, i32:$inactive)),
multiclass
AMDGPUWaveReducePseudoGenerator<string Op, string DataType, ValueType ty, RegisterClass RetReg, SrcRegOrImm9 Reg> {
- let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, UseNamedOperandTable = 1, Uses = [EXEC] in {
+ let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, UseNamedOperandTable = 1, Uses = [EXEC], Defs = [SCC] in {
def !toupper(Op) #"_PSEUDO_" #DataType
: VPseudoInstSI<(outs RetReg : $sdst),
(ins Reg : $src, i32imm : $strategy),
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
index 0e6e02ae611047..97b71b0c2affe1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
@@ -80,7 +80,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX908-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY7]], [[COPY8]], implicit $exec
; GFX908-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
; GFX908-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY9]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
- ; GFX908-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit $exec
+ ; GFX908-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit-def dead $scc, implicit $exec
; GFX908-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
; GFX908-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX908-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY11]], implicit $exec
@@ -129,7 +129,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX90A-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY7]], [[COPY8]], implicit $exec
; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
; GFX90A-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY9]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
- ; GFX90A-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit $exec
+ ; GFX90A-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX90A-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY11]], implicit $exec
@@ -178,7 +178,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX942-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY7]], [[COPY8]], implicit $exec
; GFX942-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
; GFX942-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY9]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
- ; GFX942-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit $exec
+ ; GFX942-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit-def dead $scc, implicit $exec
; GFX942-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
; GFX942-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX942-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY11]], implicit $exec
@@ -222,7 +222,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX11-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY4]], [[COPY5]], implicit $exec
- ; GFX11-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit $exec
+ ; GFX11-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[V_MBCNT_LO_U32_B32_e64_]], [[COPY7]], implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll b/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
index b29d3cfe46f966..6069f2a2b5a563 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
@@ -58,7 +58,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX908-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 killed [[COPY6]], [[COPY7]], implicit $exec
; GFX908-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 killed [[COPY5]], killed [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
- ; GFX908-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY]], 2, implicit $exec
+ ; GFX908-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY]], 2, implicit-def dead $scc, implicit $exec
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
; GFX908-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_MBCNT_HI_U32_B32_e64_]], [[S_MOV_B32_]], implicit $exec
; GFX908-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_EQ_U32_e64_]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
@@ -103,7 +103,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX90A_GFX942-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX90A_GFX942-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 killed [[COPY6]], [[COPY7]], implicit $exec
; GFX90A_GFX942-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 killed [[COPY5]], killed [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
- ; GFX90A_GFX942-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY]], 2, implicit $exec
+ ; GFX90A_GFX942-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY]], 2, implicit-def dead $scc, implicit $exec
; GFX90A_GFX942-NEXT: [[COPY8:%[0-9]+]]:av_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
; GFX90A_GFX942-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_MBCNT_HI_U32_B32_e64_]], [[S_MOV_B32_]], implicit $exec
; GFX90A_GFX942-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_EQ_U32_e64_]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
@@ -144,7 +144,7 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX11_GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $exec_lo
; GFX11_GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GFX11_GFX12-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY4]], [[S_MOV_B32_]], implicit $exec
- ; GFX11_GFX12-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY]], 2, implicit $exec
+ ; GFX11_GFX12-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY]], 2, implicit-def dead $scc, implicit $exec
; GFX11_GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
; GFX11_GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 killed [[V_MBCNT_LO_U32_B32_e64_]], [[S_MOV_B32_]], implicit $exec
; GFX11_GFX12-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_EQ_U32_e64_]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/wave-reduce-live-scc.ll b/llvm/test/CodeGen/AMDGPU/wave-reduce-live-scc.ll
index 0aa8c0176e434e..c531638ec90d14 100644
--- a/llvm/test/CodeGen/AMDGPU/wave-reduce-live-scc.ll
+++ b/llvm/test/CodeGen/AMDGPU/wave-reduce-live-scc.ll
@@ -1,25 +1,62 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu9.00 -global-isel=0 < %s | FileCheck %s
-; The wave.reduce expansions write SCC. A uniform condition that is live
-; across the call must not be read from SCC after it.
-; FIXME: The select reads the SCC written by s_bcnt1, not by the compare.
+; The wave.reduce expansions write SCC: the Iterative loop's compare, and
+; s_bcnt1 for a uniform value. A uniform condition that is live across the
+; call must not be read from SCC after it.
+
+define amdgpu_kernel void @add_iterative_live_scc(ptr addrspace(1) %out, i32 %a, i32 %b) {
+; CHECK-LABEL: add_iterative_live_scc:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
+; CHECK-NEXT: s_mov_b64 s[2:3], exec
+; CHECK-NEXT: s_mov_b32 s6, 0
+; CHECK-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: s_ff1_i32_b64 s7, s[2:3]
+; CHECK-NEXT: v_readlane_b32 s8, v0, s7
+; CHECK-NEXT: s_bitset0_b64 s[2:3], s7
+; CHECK-NEXT: s_add_i32 s6, s6, s8
+; CHECK-NEXT: s_cmp_lg_u64 s[2:3], 0
+; CHECK-NEXT: s_cbranch_scc1 .LBB0_1
+; CHECK-NEXT: ; %bb.2:
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: s_cmp_lg_u32 s0, s1
+; CHECK-NEXT: s_cbranch_scc1 .LBB0_4
+; CHECK-NEXT: ; %bb.3: ; %t
+; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; CHECK-NEXT: v_mov_b32_e32 v0, s6
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: global_store_dword v1, v0, s[0:1]
+; CHECK-NEXT: .LBB0_4: ; %e
+; CHECK-NEXT: s_endpgm
+ %id = call i32 @llvm.amdgcn.workitem.id.x()
+ %c = icmp eq i32 %a, %b
+ %r = call i32 @llvm.amdgcn.wave.reduce.add.i32(i32 %id, i32 1)
+ br i1 %c, label %t, label %e
+
+t:
+ store i32 %r, ptr addrspace(1) %out
+ br label %e
+
+e:
+ ret void
+}
define amdgpu_kernel void @add_uniform_live_scc(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %u) {
; CHECK-LABEL: add_uniform_live_scc:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; CHECK-NEXT: ; kill: killed $sgpr4_sgpr5
+; CHECK-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; CHECK-NEXT: s_mov_b64 s[4:5], exec
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_bcnt1_i32_b64 s3, s[4:5]
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_mul_i32 s2, s2, s3
-; CHECK-NEXT: s_cselect_b32 s2, s2, 1
-; CHECK-NEXT: v_mov_b32_e32 v1, s2
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: global_store_dword v0, v1, s[0:1]
+; CHECK-NEXT: s_cmp_eq_u32 s0, s1
+; CHECK-NEXT: s_cselect_b32 s0, s2, 1
+; CHECK-NEXT: v_mov_b32_e32 v1, s0
+; CHECK-NEXT: global_store_dword v0, v1, s[6:7]
; CHECK-NEXT: s_endpgm
%c = icmp eq i32 %a, %b
%r = call i32 @llvm.amdgcn.wave.reduce.add.i32(i32 %u, i32 0)
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