[llvm] [GlobalISel] [AArch64] Generate NEG for shift by (N - X) in SelectShiftMask (PR #226114)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 3 07:59:00 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Deepak Shirke (deepakshirkem)
<details>
<summary>Changes</summary>
AArch64 shift instructions only use the low log2(ShiftWidth) bits of the shift amount. When shifting by N-X where N == 0 mod ShiftWidth, this is equivalent to shifting by -X, so we can generate a NEG instead of a SUB from a constant.
For example, shl x, (sub 64, y) becomes shl x, neg(y).
This implements both SelectionDAG and GlobalISel. The GlobalISel side builds the NEG (SUBWrr/SUBXrr with the zero register) in the ComplexPattern renderer and constrains its operands with constrainSelectedInstRegOperands.
Part of the incremental work tracked in #<!-- -->224245 to replace tryShiftAmountMod with ComplexPattern-based isel.
Depends on #<!-- -->225842.
---
Patch is 67.84 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/226114.diff
8 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+20)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp (+24)
- (modified) llvm/test/CodeGen/AArch64/and-mask-variable.ll (+6-7)
- (modified) llvm/test/CodeGen/AArch64/fcvt-i256.ll (+242-250)
- (modified) llvm/test/CodeGen/AArch64/fsh.ll (+298-310)
- (modified) llvm/test/CodeGen/AArch64/funnel-shift.ll (+22-23)
- (modified) llvm/test/CodeGen/AArch64/shift-mod.ll (+23)
- (modified) llvm/test/CodeGen/AArch64/shift.ll (+53-59)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 962340bd9a4ce4..31bedd86859a93 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -802,6 +802,26 @@ bool AArch64DAGToDAGISel::SelectShiftMask(SDValue N, SDValue &ShAmt) {
}
}
+ // If shifting by N-X where N == 0 mod ShiftWidth, then just shift by -X
+ // to generate a NEG instead of a SUB from a constant.
+ if (N.getOpcode() == ISD::SUB && N.hasOneUse() &&
+ N.getValueType() == (ShiftWidth == 32 ? MVT::i32 : MVT::i64)) {
+ uint64_t Imm;
+ if (isIntImmediate(N.getOperand(0).getNode(), Imm) && Imm != 0 &&
+ (Imm % ShiftWidth == 0)) {
+ SDLoc DL(N);
+ EVT VT = N.getValueType();
+ unsigned NegOpc = (ShiftWidth == 32) ? AArch64::SUBWrr : AArch64::SUBXrr;
+ unsigned ZeroReg = (ShiftWidth == 32) ? AArch64::WZR : AArch64::XZR;
+ SDValue Zero =
+ CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, VT);
+ MachineSDNode *Neg =
+ CurDAG->getMachineNode(NegOpc, DL, VT, Zero, N.getOperand(1));
+ ShAmt = SDValue(Neg, 0);
+ return true;
+ }
+ }
+
return false;
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index e12acd42bfdfd9..29c1f32911d3c2 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -7353,6 +7353,30 @@ AArch64InstructionSelector::selectShiftMask(MachineOperand &Root) const {
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(ShAmtReg); }}};
}
+ // If shifting by N-X where N == 0 mod ShiftWidth, then just shift by -X
+ // to generate a NEG instead of a SUB from a constant.
+ Register SubSrcReg;
+ int64_t SubImm;
+ if (MRI.hasOneUse(ShAmtReg) &&
+ mi_match(ShAmtReg, MRI, m_GSub(m_ICst(SubImm), m_Reg(SubSrcReg))) &&
+ SubImm != 0 && (SubImm % ShiftWidth == 0)) {
+ return {{[=](MachineInstrBuilder &MIB) {
+ MachineInstr *I = MIB.getInstr();
+ MachineRegisterInfo &MRI2 = I->getMF()->getRegInfo();
+ const TargetRegisterClass &RC =
+ ShiftWidth == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass;
+ unsigned SubOpc = ShiftWidth == 32 ? AArch64::SUBWrr : AArch64::SUBXrr;
+ Register ZeroReg = ShiftWidth == 32 ? AArch64::WZR : AArch64::XZR;
+ Register NegReg = MRI2.createVirtualRegister(&RC);
+ auto NegMI = BuildMI(*I->getParent(), *I, I->getDebugLoc(),
+ TII.get(SubOpc), NegReg)
+ .addReg(ZeroReg)
+ .addReg(SubSrcReg);
+ constrainSelectedInstRegOperands(*NegMI, TII, TRI, RBI);
+ MIB.addReg(NegReg);
+ }}};
+ }
+
// Only succeed if we changed the shift amount; otherwise let other
// patterns (e.g. zext GPR32 -> SUBREG_TO_REG) match instead.
if (ShAmtReg == Root.getReg())
diff --git a/llvm/test/CodeGen/AArch64/and-mask-variable.ll b/llvm/test/CodeGen/AArch64/and-mask-variable.ll
index ea5079770b2435..bcdff64e592a34 100644
--- a/llvm/test/CodeGen/AArch64/and-mask-variable.ll
+++ b/llvm/test/CodeGen/AArch64/and-mask-variable.ll
@@ -56,17 +56,16 @@ define i128 @mask_pair_128(i128 %x, i128 %y) {
;
; CHECK-GI-LABEL: mask_pair_128:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #64 // =0x40
-; CHECK-GI-NEXT: mov x9, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: neg x9, x2
; CHECK-GI-NEXT: cmp x2, #64
-; CHECK-GI-NEXT: sub x8, x8, x2
-; CHECK-GI-NEXT: lsl x10, x9, x2
-; CHECK-GI-NEXT: lsr x8, x9, x8
-; CHECK-GI-NEXT: csel x9, x10, xzr, lo
+; CHECK-GI-NEXT: lsl x10, x8, x2
+; CHECK-GI-NEXT: lsr x8, x8, x9
; CHECK-GI-NEXT: orr x8, x8, x10
-; CHECK-GI-NEXT: and x0, x9, x0
+; CHECK-GI-NEXT: csel x9, x10, xzr, lo
; CHECK-GI-NEXT: csel x8, x8, x10, lo
; CHECK-GI-NEXT: cmp x2, #0
+; CHECK-GI-NEXT: and x0, x9, x0
; CHECK-GI-NEXT: csinv x8, x8, xzr, ne
; CHECK-GI-NEXT: and x1, x8, x1
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fcvt-i256.ll b/llvm/test/CodeGen/AArch64/fcvt-i256.ll
index 10b16c0b205d5f..5b4d428be44341 100644
--- a/llvm/test/CodeGen/AArch64/fcvt-i256.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt-i256.ll
@@ -698,69 +698,68 @@ define i256 @f32_to_s256(float %val) {
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB4_3: // %fp-to-i-if-exp.large
; CHECK-GI-NEXT: sub w11, w11, #150
-; CHECK-GI-NEXT: mov w13, #64 // =0x40
; CHECK-GI-NEXT: mov w12, #128 // =0x80
-; CHECK-GI-NEXT: sub x15, x13, x11
+; CHECK-GI-NEXT: neg x14, x11
+; CHECK-GI-NEXT: lsl x15, x10, x11
; CHECK-GI-NEXT: lsl x16, x10, x11
-; CHECK-GI-NEXT: lsl x17, x10, x11
-; CHECK-GI-NEXT: lsr x15, x10, x15
+; CHECK-GI-NEXT: lsr x14, x10, x14
; CHECK-GI-NEXT: sub x12, x12, x11
; CHECK-GI-NEXT: cmp x11, #64
-; CHECK-GI-NEXT: sub x14, x11, #128
-; CHECK-GI-NEXT: lsr x18, x10, x12
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: csel x15, x15, x17, lo
+; CHECK-GI-NEXT: sub x13, x11, #128
+; CHECK-GI-NEXT: lsr x17, x10, x12
+; CHECK-GI-NEXT: csel x15, x15, xzr, lo
+; CHECK-GI-NEXT: csel x14, x14, x16, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: sub x13, x13, x14
-; CHECK-GI-NEXT: csel x15, xzr, x15, eq
+; CHECK-GI-NEXT: neg x18, x13
+; CHECK-GI-NEXT: csel x14, xzr, x14, eq
; CHECK-GI-NEXT: cmp x12, #64
-; CHECK-GI-NEXT: lsl x0, x10, x14
-; CHECK-GI-NEXT: lsr x13, x10, x13
-; CHECK-GI-NEXT: csel x18, x18, xzr, lo
-; CHECK-GI-NEXT: cmp x12, #0
-; CHECK-GI-NEXT: csel x12, x10, x18, eq
-; CHECK-GI-NEXT: cmp x14, #64
+; CHECK-GI-NEXT: lsl x0, x10, x13
+; CHECK-GI-NEXT: lsr x18, x10, x18
; CHECK-GI-NEXT: csel x17, x17, xzr, lo
-; CHECK-GI-NEXT: csel x10, x13, x0, lo
-; CHECK-GI-NEXT: cmp x14, #0
+; CHECK-GI-NEXT: cmp x12, #0
+; CHECK-GI-NEXT: csel x12, x10, x17, eq
+; CHECK-GI-NEXT: cmp x13, #64
+; CHECK-GI-NEXT: csel x16, x16, xzr, lo
+; CHECK-GI-NEXT: csel x10, x18, x0, lo
+; CHECK-GI-NEXT: cmp x13, #0
; CHECK-GI-NEXT: csel x13, xzr, x10, eq
; CHECK-GI-NEXT: cmp x11, #128
-; CHECK-GI-NEXT: csel x10, x16, xzr, lo
-; CHECK-GI-NEXT: csel x15, x15, xzr, lo
-; CHECK-GI-NEXT: csel x12, x12, x17, lo
+; CHECK-GI-NEXT: csel x10, x15, xzr, lo
+; CHECK-GI-NEXT: csel x14, x14, xzr, lo
+; CHECK-GI-NEXT: csel x12, x12, x16, lo
; CHECK-GI-NEXT: csel x13, xzr, x13, lo
; CHECK-GI-NEXT: cmp x11, #0
; CHECK-GI-NEXT: umulh x18, x10, x9
; CHECK-GI-NEXT: csel x12, xzr, x12, eq
; CHECK-GI-NEXT: csel x13, xzr, x13, eq
-; CHECK-GI-NEXT: umulh x11, x15, x9
-; CHECK-GI-NEXT: umulh x17, x12, x8
-; CHECK-GI-NEXT: umulh x14, x10, x8
+; CHECK-GI-NEXT: umulh x11, x14, x9
+; CHECK-GI-NEXT: umulh x16, x12, x8
+; CHECK-GI-NEXT: umulh x15, x10, x8
; CHECK-GI-NEXT: add x11, x11, x18
-; CHECK-GI-NEXT: mul x16, x10, x9
-; CHECK-GI-NEXT: add x11, x17, x11
-; CHECK-GI-NEXT: mul x0, x15, x8
-; CHECK-GI-NEXT: umulh x2, x15, x8
-; CHECK-GI-NEXT: adds x14, x14, x16
+; CHECK-GI-NEXT: mul x17, x10, x9
+; CHECK-GI-NEXT: add x11, x16, x11
+; CHECK-GI-NEXT: mul x0, x14, x8
+; CHECK-GI-NEXT: umulh x2, x14, x8
; CHECK-GI-NEXT: madd x11, x10, x9, x11
+; CHECK-GI-NEXT: mul x16, x14, x9
+; CHECK-GI-NEXT: madd x11, x14, x9, x11
+; CHECK-GI-NEXT: adds x14, x15, x17
; CHECK-GI-NEXT: cset w3, hs
; CHECK-GI-NEXT: adds x1, x14, x0
-; CHECK-GI-NEXT: mul x17, x15, x9
+; CHECK-GI-NEXT: mul x15, x12, x8
; CHECK-GI-NEXT: cset w14, hs
; CHECK-GI-NEXT: adds x18, x2, x18
-; CHECK-GI-NEXT: madd x11, x15, x9, x11
; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: adds x16, x18, x16
-; CHECK-GI-NEXT: and x18, x0, #0x1
-; CHECK-GI-NEXT: mul x15, x12, x8
+; CHECK-GI-NEXT: adds x17, x18, x17
; CHECK-GI-NEXT: madd x9, x12, x9, x11
; CHECK-GI-NEXT: and x11, x3, #0x1
; CHECK-GI-NEXT: and x12, x14, #0x1
; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: and x18, x0, #0x1
; CHECK-GI-NEXT: and x14, x14, #0x1
; CHECK-GI-NEXT: mul x0, x10, x8
; CHECK-GI-NEXT: add x10, x11, x12
-; CHECK-GI-NEXT: adds x12, x16, x17
+; CHECK-GI-NEXT: adds x12, x17, x16
; CHECK-GI-NEXT: add x11, x18, x14
; CHECK-GI-NEXT: cset w14, hs
; CHECK-GI-NEXT: adds x12, x12, x15
@@ -868,36 +867,35 @@ define i256 @f32_to_u256(float %val) {
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB5_3: // %fp-to-i-if-exp.large
; CHECK-GI-NEXT: sub w9, w9, #150
-; CHECK-GI-NEXT: mov w11, #64 // =0x40
; CHECK-GI-NEXT: mov w10, #128 // =0x80
-; CHECK-GI-NEXT: sub x12, x11, x9
+; CHECK-GI-NEXT: neg x11, x9
+; CHECK-GI-NEXT: lsl x12, x8, x9
; CHECK-GI-NEXT: lsl x13, x8, x9
-; CHECK-GI-NEXT: lsl x14, x8, x9
-; CHECK-GI-NEXT: lsr x12, x8, x12
+; CHECK-GI-NEXT: lsr x11, x8, x11
; CHECK-GI-NEXT: sub x10, x10, x9
; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: lsr x15, x8, x10
-; CHECK-GI-NEXT: csel x13, x13, xzr, lo
-; CHECK-GI-NEXT: sub x16, x9, #128
-; CHECK-GI-NEXT: csel x12, x12, x14, lo
+; CHECK-GI-NEXT: lsr x14, x8, x10
+; CHECK-GI-NEXT: csel x12, x12, xzr, lo
+; CHECK-GI-NEXT: sub x15, x9, #128
+; CHECK-GI-NEXT: csel x11, x11, x13, lo
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: sub x11, x11, x16
-; CHECK-GI-NEXT: csel x12, xzr, x12, eq
+; CHECK-GI-NEXT: neg x16, x15
+; CHECK-GI-NEXT: csel x11, xzr, x11, eq
; CHECK-GI-NEXT: cmp x10, #64
-; CHECK-GI-NEXT: lsr x11, x8, x11
-; CHECK-GI-NEXT: csel x15, x15, xzr, lo
-; CHECK-GI-NEXT: cmp x10, #0
-; CHECK-GI-NEXT: lsl x10, x8, x16
-; CHECK-GI-NEXT: csel x8, x8, x15, eq
-; CHECK-GI-NEXT: cmp x16, #64
+; CHECK-GI-NEXT: lsr x16, x8, x16
; CHECK-GI-NEXT: csel x14, x14, xzr, lo
-; CHECK-GI-NEXT: csel x10, x11, x10, lo
-; CHECK-GI-NEXT: cmp x16, #0
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: lsl x10, x8, x15
+; CHECK-GI-NEXT: csel x8, x8, x14, eq
+; CHECK-GI-NEXT: cmp x15, #64
+; CHECK-GI-NEXT: csel x13, x13, xzr, lo
+; CHECK-GI-NEXT: csel x10, x16, x10, lo
+; CHECK-GI-NEXT: cmp x15, #0
; CHECK-GI-NEXT: csel x10, xzr, x10, eq
; CHECK-GI-NEXT: cmp x9, #128
-; CHECK-GI-NEXT: csel x0, x13, xzr, lo
-; CHECK-GI-NEXT: csel x1, x12, xzr, lo
-; CHECK-GI-NEXT: csel x8, x8, x14, lo
+; CHECK-GI-NEXT: csel x0, x12, xzr, lo
+; CHECK-GI-NEXT: csel x1, x11, xzr, lo
+; CHECK-GI-NEXT: csel x8, x8, x13, lo
; CHECK-GI-NEXT: csel x10, xzr, x10, lo
; CHECK-GI-NEXT: cmp x9, #0
; CHECK-GI-NEXT: csel x2, xzr, x8, eq
@@ -1053,77 +1051,76 @@ define i256 @f64_to_s256(double %val) {
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB6_3: // %fp-to-i-if-exp.large
; CHECK-GI-NEXT: sub x11, x11, #1075
-; CHECK-GI-NEXT: mov w12, #64 // =0x40
-; CHECK-GI-NEXT: mov w13, #128 // =0x80
-; CHECK-GI-NEXT: sub x15, x12, x11
-; CHECK-GI-NEXT: lsl x16, x10, x11
-; CHECK-GI-NEXT: sub x13, x13, x11
-; CHECK-GI-NEXT: lsr x15, x10, x15
+; CHECK-GI-NEXT: mov w12, #128 // =0x80
+; CHECK-GI-NEXT: neg x14, x11
+; CHECK-GI-NEXT: lsl x15, x10, x11
+; CHECK-GI-NEXT: sub x12, x12, x11
+; CHECK-GI-NEXT: lsr x14, x10, x14
; CHECK-GI-NEXT: cmp x11, #64
-; CHECK-GI-NEXT: sub x14, x11, #128
-; CHECK-GI-NEXT: lsr x17, x10, x13
-; CHECK-GI-NEXT: csel x18, x16, xzr, lo
-; CHECK-GI-NEXT: sub x12, x12, x14
-; CHECK-GI-NEXT: csel x15, x15, x16, lo
+; CHECK-GI-NEXT: sub x13, x11, #128
+; CHECK-GI-NEXT: lsr x16, x10, x12
+; CHECK-GI-NEXT: csel x18, x15, xzr, lo
+; CHECK-GI-NEXT: neg x17, x13
+; CHECK-GI-NEXT: csel x14, x14, x15, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: lsl x0, x10, x14
-; CHECK-GI-NEXT: csel x15, xzr, x15, eq
+; CHECK-GI-NEXT: lsl x0, x10, x13
+; CHECK-GI-NEXT: csel x14, xzr, x14, eq
+; CHECK-GI-NEXT: cmp x12, #64
+; CHECK-GI-NEXT: lsr x17, x10, x17
+; CHECK-GI-NEXT: csel x16, x16, xzr, lo
+; CHECK-GI-NEXT: cmp x12, #0
+; CHECK-GI-NEXT: csel x12, x10, x16, eq
; CHECK-GI-NEXT: cmp x13, #64
-; CHECK-GI-NEXT: lsr x12, x10, x12
-; CHECK-GI-NEXT: csel x17, x17, xzr, lo
+; CHECK-GI-NEXT: csel x15, x15, xzr, lo
+; CHECK-GI-NEXT: csel x10, x17, x0, lo
; CHECK-GI-NEXT: cmp x13, #0
-; CHECK-GI-NEXT: csel x13, x10, x17, eq
-; CHECK-GI-NEXT: cmp x14, #64
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: csel x10, x12, x0, lo
-; CHECK-GI-NEXT: cmp x14, #0
-; CHECK-GI-NEXT: csel x12, xzr, x10, eq
+; CHECK-GI-NEXT: csel x13, xzr, x10, eq
; CHECK-GI-NEXT: cmp x11, #128
; CHECK-GI-NEXT: csel x10, x18, xzr, lo
-; CHECK-GI-NEXT: csel x15, x15, xzr, lo
-; CHECK-GI-NEXT: csel x13, x13, x16, lo
-; CHECK-GI-NEXT: csel x12, xzr, x12, lo
+; CHECK-GI-NEXT: csel x14, x14, xzr, lo
+; CHECK-GI-NEXT: csel x12, x12, x15, lo
+; CHECK-GI-NEXT: csel x13, xzr, x13, lo
; CHECK-GI-NEXT: cmp x11, #0
; CHECK-GI-NEXT: umulh x18, x10, x9
-; CHECK-GI-NEXT: csel x13, xzr, x13, eq
; CHECK-GI-NEXT: csel x12, xzr, x12, eq
-; CHECK-GI-NEXT: umulh x11, x15, x9
-; CHECK-GI-NEXT: umulh x16, x13, x8
-; CHECK-GI-NEXT: umulh x14, x10, x8
+; CHECK-GI-NEXT: csel x13, xzr, x13, eq
+; CHECK-GI-NEXT: umulh x11, x14, x9
+; CHECK-GI-NEXT: umulh x15, x12, x8
+; CHECK-GI-NEXT: umulh x16, x10, x8
; CHECK-GI-NEXT: add x11, x11, x18
; CHECK-GI-NEXT: mul x17, x10, x9
-; CHECK-GI-NEXT: add x11, x16, x11
-; CHECK-GI-NEXT: mul x0, x15, x8
-; CHECK-GI-NEXT: umulh x2, x15, x8
-; CHECK-GI-NEXT: adds x14, x14, x17
+; CHECK-GI-NEXT: add x11, x15, x11
+; CHECK-GI-NEXT: mul x0, x14, x8
+; CHECK-GI-NEXT: umulh x2, x14, x8
; CHECK-GI-NEXT: madd x11, x10, x9, x11
+; CHECK-GI-NEXT: mul x15, x14, x9
+; CHECK-GI-NEXT: madd x11, x14, x9, x11
+; CHECK-GI-NEXT: adds x14, x16, x17
; CHECK-GI-NEXT: cset w3, hs
; CHECK-GI-NEXT: adds x1, x14, x0
-; CHECK-GI-NEXT: mul x16, x15, x9
+; CHECK-GI-NEXT: mul x16, x12, x8
; CHECK-GI-NEXT: cset w14, hs
; CHECK-GI-NEXT: adds x18, x2, x18
-; CHECK-GI-NEXT: madd x11, x15, x9, x11
; CHECK-GI-NEXT: cset w0, hs
; CHECK-GI-NEXT: adds x17, x18, x17
-; CHECK-GI-NEXT: and x18, x0, #0x1
-; CHECK-GI-NEXT: mul x15, x13, x8
-; CHECK-GI-NEXT: madd x9, x13, x9, x11
+; CHECK-GI-NEXT: madd x9, x12, x9, x11
; CHECK-GI-NEXT: and x11, x3, #0x1
-; CHECK-GI-NEXT: and x13, x14, #0x1
+; CHECK-GI-NEXT: and x12, x14, #0x1
; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: and x18, x0, #0x1
; CHECK-GI-NEXT: and x14, x14, #0x1
; CHECK-GI-NEXT: mul x0, x10, x8
-; CHECK-GI-NEXT: add x10, x11, x13
-; CHECK-GI-NEXT: adds x13, x17, x16
+; CHECK-GI-NEXT: add x10, x11, x12
+; CHECK-GI-NEXT: adds x12, x17, x15
; CHECK-GI-NEXT: add x11, x18, x14
; CHECK-GI-NEXT: cset w14, hs
-; CHECK-GI-NEXT: adds x13, x13, x15
-; CHECK-GI-NEXT: madd x8, x12, x8, x9
+; CHECK-GI-NEXT: adds x12, x12, x16
+; CHECK-GI-NEXT: madd x8, x13, x8, x9
; CHECK-GI-NEXT: and x9, x14, #0x1
-; CHECK-GI-NEXT: cset w12, hs
-; CHECK-GI-NEXT: adds x2, x13, x10
+; CHECK-GI-NEXT: cset w13, hs
+; CHECK-GI-NEXT: adds x2, x12, x10
; CHECK-GI-NEXT: add x9, x11, x9
-; CHECK-GI-NEXT: and x10, x12, #0x1
+; CHECK-GI-NEXT: and x10, x13, #0x1
; CHECK-GI-NEXT: cset w11, hs
; CHECK-GI-NEXT: add x9, x9, x10
; CHECK-GI-NEXT: and x10, x11, #0x1
@@ -1222,35 +1219,34 @@ define i256 @f64_to_u256(double %val) {
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB7_3: // %fp-to-i-if-exp.large
; CHECK-GI-NEXT: sub x9, x9, #1075
-; CHECK-GI-NEXT: mov w10, #64 // =0x40
-; CHECK-GI-NEXT: mov w11, #128 // =0x80
-; CHECK-GI-NEXT: sub x12, x10, x9
-; CHECK-GI-NEXT: lsl x13, x8, x9
-; CHECK-GI-NEXT: sub x11, x11, x9
-; CHECK-GI-NEXT: lsr x12, x8, x12
+; CHECK-GI-NEXT: mov w10, #128 // =0x80
+; CHECK-GI-NEXT: neg x11, x9
+; CHECK-GI-NEXT: lsl x12, x8, x9
+; CHECK-GI-NEXT: sub x10, x10, x9
+; CHECK-GI-NEXT: lsr x11, x8, x11
; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: lsr x14, x8, x11
-; CHECK-GI-NEXT: csel x15, x13, xzr, lo
-; CHECK-GI-NEXT: sub x16, x9, #128
-; CHECK-GI-NEXT: csel x12, x12, x13, lo
+; CHECK-GI-NEXT: lsr x13, x8, x10
+; CHECK-GI-NEXT: csel x14, x12, xzr, lo
+; CHECK-GI-NEXT: sub x15, x9, #128
+; CHECK-GI-NEXT: csel x11, x11, x12, lo
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: sub x10, x10, x16
-; CHECK-GI-NEXT: csel x12, xzr, x12, eq
-; CHECK-GI-NEXT: cmp x11, #64
-; CHECK-GI-NEXT: lsr x10, x8, x10
-; CHECK-GI-NEXT: csel x14, x14, xzr, lo
-; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: lsl x11, x8, x16
-; CHECK-GI-NEXT: csel x8, x8, x14, eq
-; CHECK-GI-NEXT: cmp x16, #64
+; CHECK-GI-NEXT: neg x16, x15
+; CHECK-GI-NEXT: csel x11, xzr, x11, eq
+; CHECK-GI-NEXT: cmp x10, #64
+; CHECK-GI-NEXT: lsr x16, x8, x16
; CHECK-GI-NEXT: csel x13, x13, xzr, lo
-; CHECK-GI-NEXT: csel x10, x10, x11, lo
-; CHECK-GI-NEXT: cmp x16, #0
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: lsl x10, x8, x15
+; CHECK-GI-NEXT: csel x8, x8, x13, eq
+; CHECK-GI-NEXT: cmp x15, #64
+; CHECK-GI-NEXT: csel x12, x12, xzr, lo
+; CHECK-GI-NEXT: csel x10, x16, x10, lo
+; CHECK-GI-NEXT: cmp x15, #0
; CHECK-GI-NEXT: csel x10, xzr, x10, eq
; CHECK-GI-NEXT: cmp x9, #128
-; CHECK-GI-NEXT: csel x0, x15, xzr, lo
-; CHECK-GI-NEXT: csel x1, x12, xzr, lo
-; CHECK-GI-NEXT: csel x8, x8, x13, lo
+; CHECK-GI-NEXT: csel x0, x14, xzr, lo
+; CHECK-GI-NEXT: csel x1, x11, xzr, lo
+; CHECK-GI-NEXT: csel x8, x8, x12, lo
; CHECK-GI-NEXT: csel x10, xzr, x10, lo
; CHECK-GI-NEXT: cmp x9, #0
; CHECK-GI-NEXT: csel x2, xzr, x8, eq
@@ -1434,69 +1430,68 @@ define i256 @f32_to_s256_sat(float %val) {
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB8_6: // %fp-to-i-if-exp.large
; CHECK-GI-NEXT: sub w11, w11, #150
-; CHECK-GI-NEXT: mov w13, #64 // =0x40
; CHECK-GI-NEXT: mov w12, #128 // =0x80
-; CHECK-GI-NEXT: sub x15, x13, x11
+; CHECK-GI-NEXT: neg x14, x11
+; CHECK-GI-NEXT: lsl x15, x10, x11
; CHECK-GI-NEXT: lsl x16, x10, x11
-; CHECK-GI-NEXT: lsl x17, x10, x11
-; CHECK-GI-NEXT: lsr x15, x10, x15
+; CHECK-GI-NEXT: lsr x14, x10, x14
; CHECK-GI-NEXT: sub x12, x12, x11
; CHECK-GI-NEXT: cmp x11, #64
-; CHECK-GI-NEXT: sub x14, x11, #128
-; CHECK-GI-NEXT: lsr x18, x10, x12
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: csel x15, x15, x17, lo
+; CHECK-GI-NEXT: sub x13, x11, #128
+; CHECK-GI-NEXT: lsr x17, x10, x12
+; CHECK-GI-NEXT: csel x15, x15, xzr, lo
+; CHECK-GI-NEXT: csel x14, x14, x16, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: sub x13, x13, x14
-; CHECK-GI-NEXT: csel x15, xzr, x15, eq
+; CHECK-GI-NEXT: neg x18, x13
+; CHECK-GI-NEXT: csel x14, xzr, x14, eq
; CHECK-GI-NEXT: cmp x12, #64
-; CHECK-GI-NEXT: lsl x0, x10, x14
-; CHECK-GI-NEXT: lsr x13, x10, x13
-; CHECK-GI-NEXT: csel x18, x18, xzr, lo
-; CHECK-GI-NEXT: cmp x12, #0
-; CHECK-GI-NEXT: csel x12, x10, x18, eq
-; CHECK-GI-NEXT: cmp x14, #64
+; CHECK-GI-NEXT: lsl x0, x10, x13
+; CHECK-GI-NEXT: lsr x18, x10, x18
; CHECK-GI-NEXT: csel x17, x17, xzr, lo
-; CHECK-GI-NEXT: csel x10, x13, x0, lo
-; CHECK-GI-NEXT: cmp x14, #0
+; CHECK-GI-NEXT: cmp x12, #0
+; CHECK-GI-NEXT: csel x12, x10, x17, eq
+; CHECK-GI-NEXT: cmp x13, #64
+; CHECK-GI-NEXT: csel x16, x16, xzr, lo
+; CHECK-GI-NEXT: csel x10, x18, x0, lo
+; CHECK-GI-NEXT: cmp x13, #0
; CHECK-GI-NEXT: csel x13, xzr, x10, eq
; CHECK-GI-NEXT: cmp x11, #128
-; CHECK-GI-NEXT: csel x10, x16, xzr, lo
-; CHECK-GI-NEXT: csel x15, x15, xzr, lo
-; CHECK-GI-NEXT: csel x12, x12, x17, lo
+; CHECK-GI-NEXT: csel x10, x15, xzr, lo
+; CHECK-GI-NEXT: csel x14, x14, xzr, lo
+; CHECK-GI-NEXT: csel x12, x12, x16, lo
; CHECK-GI-NEXT: csel x13, xzr, x13, lo
; CHECK-GI-NEXT: cmp x11, #0
; CHECK-GI-NEXT: umulh x18, x10, x9
; CHECK-GI-NEXT: csel x12, xzr, x12, eq
; CHECK-GI-NEXT: csel x13, xzr, x13, eq
-; CHECK-GI-NEXT: umulh x11, x15, x9
-; CHECK-GI-NEXT: umulh x17, x12, x8
-; ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/226114
More information about the llvm-commits
mailing list