[llvm] [BranchFolding] Ignore debug instructions in singleton cond branch check (PR #228715)

[Aochang Liu via llvm-commits]

https://github.com/HelloWorldU updated https://github.com/llvm/llvm-project/pull/228715

>From fdb724cdfcad53aa6103e798a1b5e468af6a39ae Mon Sep 17 00:00:00 2001
From: HelloWorldU <asd001liu at gmail.com>
Date: Sat, 3 Oct 2026 22:25:24 +0800
Subject: [PATCH] [BranchFolding] Ignore debug instructions when removing a
 duplicate cond branch

OptimizeBlock removes the conditional branch of the layout predecessor when
MBB consists of an identical conditional branch. The singleton check used
MBB->size(), so a DBG_VALUE in MBB disabled the transform and changed codegen
with -g. Count only non-debug instructions, as IsEmptyBlock and
IsBranchOnlyBlock already do. MBB itself is kept, so its debug instructions
are preserved.

Fixes #228713

Assisted-by: Claude Opus 5.5
---
 llvm/lib/CodeGen/BranchFolding.cpp            |  3 +-
 .../X86/branchfolding-debug-invariant.mir     | 68 +++++++++++++++++++
 2 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index aef63f6bdc1c52..d1d7f42caafb2a 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -1586,7 +1586,8 @@ bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
     // If we have a block that consists of a single conditional branch
     // instruction that is exactly identical to the terminator in the previous
     // block, we can remove this block.
-    if (MBB->size() == 1 && PrevBB.canFallThrough() && CurTBB == PriorTBB &&
+    if (MBB->getFirstNonDebugInstr() == MBB->getLastNonDebugInstr() &&
+        PrevBB.canFallThrough() && CurTBB == PriorTBB &&
         areConditionalsEqual(CurCond, PriorCond)) {
       // We remove the branch from the previous basic block rather than this
       // one in case there are other blocks that specifically branch to this
diff --git a/llvm/test/CodeGen/X86/branchfolding-debug-invariant.mir b/llvm/test/CodeGen/X86/branchfolding-debug-invariant.mir
index 95c96d06393a2b..a4331c918ca945 100644
--- a/llvm/test/CodeGen/X86/branchfolding-debug-invariant.mir
+++ b/llvm/test/CodeGen/X86/branchfolding-debug-invariant.mir
@@ -133,3 +133,71 @@ body:             |
     MOV8mi $r13, 1, $noreg, 0, $noreg, 0
     RET 0
 ...
+
+---
+name:            test3a
+body:             |
+  ; The conditional branch in bb.1 duplicates the one in bb.0, so bb.0 falls
+  ; through to it and the two blocks are merged.
+  ;
+  ; CHECK-LABEL: name: test3a
+  ; CHECK: bb.0:
+  ; CHECK:   TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
+  ; CHECK:   JCC_1 %bb.2, 5, implicit $eflags
+  ; CHECK: bb.1:
+  ; CHECK-NOT: JCC_1
+  ; CHECK:   MOV8mi $r12, 1, $noreg, 0, $noreg, 0
+  ; CHECK:   RET 0
+  ; CHECK: bb.2:
+  ; CHECK:   MOV8mi $r13, 1, $noreg, 0, $noreg, 0
+  ; CHECK:   RET 0
+  bb.0:
+    TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
+    JCC_1 %bb.3, 5, implicit $eflags
+
+  bb.1:
+    JCC_1 %bb.3, 5, implicit killed $eflags
+
+  bb.2:
+    MOV8mi $r12, 1, $noreg, 0, $noreg, 0
+    RET 0
+
+  bb.3:
+    MOV8mi $r13, 1, $noreg, 0, $noreg, 0
+    RET 0
+...
+
+---
+name:            test3b
+body:             |
+  ; Verify that we get the same rewrites as in test3a when adding a DBG_VALUE
+  ; instruction in the mix.
+  ;
+  ; CHECK-LABEL: name: test3b
+  ; CHECK: bb.0:
+  ; CHECK:   TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
+  ; CHECK:   DBG_VALUE
+  ; CHECK:   JCC_1 %bb.2, 5, implicit $eflags
+  ; CHECK: bb.1:
+  ; CHECK-NOT: JCC_1
+  ; CHECK:   MOV8mi $r12, 1, $noreg, 0, $noreg, 0
+  ; CHECK:   RET 0
+  ; CHECK: bb.2:
+  ; CHECK:   MOV8mi $r13, 1, $noreg, 0, $noreg, 0
+  ; CHECK:   RET 0
+  bb.0:
+    TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
+    JCC_1 %bb.3, 5, implicit $eflags
+
+  bb.1:
+    DBG_VALUE
+    JCC_1 %bb.3, 5, implicit killed $eflags
+
+  bb.2:
+    MOV8mi $r12, 1, $noreg, 0, $noreg, 0
+    RET 0
+
+  bb.3:
+    MOV8mi $r13, 1, $noreg, 0, $noreg, 0
+    RET 0
+...