[llvm] [X86] Improve llvm.get.active.lane.mask codegen (PR #225832)

[via llvm-commits]

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@@ -32768,6 +32768,25 @@ X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
                                  : AtomicExpansionKind::None;
 }
 
+bool X86TargetLowering::shouldExpandGetActiveLaneMaskUsingScalar(EVT VT) const {
+  if (!VT.isFixedLengthVector())
+    return false;
+
+  unsigned NumElts = VT.getVectorNumElements();
+
+  // Only consider power-of-2 vector lengths up to 64.
+  if (NumElts > 64 || !isPowerOf2_32(NumElts))
+    return false;
+
+  // AVX-512 natively supports mask registers (kmov/bzhi) for >=16.
+  if (Subtarget.hasAVX512())
+    return NumElts >= 16;
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Andarwinux wrote:

It still avoided the relatively expensive GPR broadcast and constant pool load, and I thought it should be able to be promoted to i32 like v16i1 to use bzhi?



https://github.com/llvm/llvm-project/pull/225832