[llvm] edeaf21 - ARM: Preserve the dead flag when activating the optional CPSR def (#227655)

[via llvm-commits]

Author: Matt Arsenault
Date: 2026-10-03T10:20:12+02:00
New Revision: edeaf21083ce4e4c43e50100db2775a4f78ad7a5

URL: https://github.com/llvm/llvm-project/commit/edeaf21083ce4e4c43e50100db2775a4f78ad7a5
DIFF: https://github.com/llvm/llvm-project/commit/edeaf21083ce4e4c43e50100db2775a4f78ad7a5.diff

LOG: ARM: Preserve the dead flag when activating the optional CPSR def (#227655)

This did not preserve the original dead flag, so it would be recomputed later by 
LiveVariables or RegAllocFast.

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>

Added: 
    llvm/test/CodeGen/Thumb/optional-def-dead-cpsr.ll

Modified: 
    llvm/lib/Target/ARM/ARMISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 2f4a4b47677c56..9dfbef53ca1bd6 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -12493,6 +12493,7 @@ void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
   MachineOperand &MO = MI.getOperand(ccOutIdx);
   MO.setReg(ARM::CPSR);
   MO.setIsDef(true);
+  MO.setIsDead(deadCPSR);
 }
 
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/test/CodeGen/Thumb/optional-def-dead-cpsr.ll b/llvm/test/CodeGen/Thumb/optional-def-dead-cpsr.ll
new file mode 100644
index 00000000000000..01e0e1de9c8b3a
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb/optional-def-dead-cpsr.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=thumbv6m-none-eabi -stop-after=finalize-isel -o - %s | FileCheck %s
+
+define i64 @add64(i64 %a, i64 %b) {
+  ; CHECK-LABEL: name: add64
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $r0, $r1, $r2, $r3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:tgpr = COPY $r3
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:tgpr = COPY $r2
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:tgpr = COPY $r1
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK-NEXT:   %4:tgpr, $cpsr = tADDrr [[COPY3]], [[COPY1]], 14 /* CC::al */, $noreg
+  ; CHECK-NEXT:   %5:tgpr, dead $cpsr = tADC [[COPY2]], [[COPY]], 14 /* CC::al */, $noreg, implicit $cpsr
+  ; CHECK-NEXT:   $r0 = COPY %4
+  ; CHECK-NEXT:   $r1 = COPY %5
+  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
+  %r = add i64 %a, %b
+  ret i64 %r
+}
+
+define i32 @shl1(i32 %a) {
+  ; CHECK-LABEL: name: shl1
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $r0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK-NEXT:   %1:tgpr, dead $cpsr = tLSLri [[COPY]], 1, 14 /* CC::al */, $noreg
+  ; CHECK-NEXT:   $r0 = COPY %1
+  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+  %r = shl i32 %a, 1
+  ret i32 %r
+}
+
+define i32 @ashr1(i32 %a) {
+  ; CHECK-LABEL: name: ashr1
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $r0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK-NEXT:   %1:tgpr, dead $cpsr = tASRri [[COPY]], 1, 14 /* CC::al */, $noreg
+  ; CHECK-NEXT:   $r0 = COPY %1
+  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+  %r = ashr i32 %a, 1
+  ret i32 %r
+}