[llvm] [ARM] Don't select hard-float fastcc for soft-float subtargets (PR #228394)

[Chris Copeland via llvm-commits]

================
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=armv7-unknown-linux-gnueabi < %s | FileCheck %s
+
+; A soft-float subtarget can still have FP registers (e.g. Rust's
+; armv7-unknown-linux-gnueabi target uses "+v7,+thumb2,+soft-float,-neon").
+; fastcc must not be mapped to the hard-float ARM_AAPCS_VFP calling convention
----------------
chrisnc wrote:

I'm not sure how this test aligns with what's described here. The effective calling convention didn't actually affect codegen before when +soft-float was active (which was the problem being flagged by the diagnostic). A more targeted test of the "effective calling convention" advertised by the backend for these cases might be warranted, rather than testing the +soft-float codegen itself for all permutations.

https://github.com/llvm/llvm-project/pull/228394