[llvm] [RISCV] Remove redundant sign extensions from BEXT indices (PR #228398)

[via llvm-commits]

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@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s | FileCheck %s
+
+; The index operand only reads log2(XLEN) bits, while the data operand can
+; still read any bit selected by the index.
+; These unmasked IR shifts are poison for actual shift amounts >= 64.
+; The MIR test also covers unknown register values without that IR constraint.
+
+define i64 @bext_index(i64 %data, i64 %index, i1 %condition) {
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tinfengyu wrote:

Good catch. I added BEXT to `RISCVDAGToDAGISel::hasAllNBitUsers` as well. This handles the IR case during SelectionDAG instruction selection. I kept the `RISCVOptWInstrs` handling so the machine pass has the same demanded-bit knowledge.


https://github.com/llvm/llvm-project/pull/228398