[llvm] [SelectionDAG] Remove vector_extract_subvec/vector_insert_subvec from TargetSelectionDAG.td. NFC (PR #228662)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/228662

These no longer have in tree users after #228542 and #228552.

>From fa97c16a8270633882175282b2193f5a29b350f7 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 2 Oct 2026 22:25:23 -0700
Subject: [PATCH] [SelectionDAG] Remove
 vector_extract_subvec/vector_insert_subvec from TargetSelectionDAG.td. NFC

These no longer have in tree users after #228542 and #228552.
---
 llvm/include/llvm/Target/TargetSelectionDAG.td | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 22fe30fea4feae4..ab2fc2117512f28 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -923,15 +923,6 @@ def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
     SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
 
-// This operator does not do subvector type checking.  The ARM
-// backend, at least, needs it.
-def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
-    SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
-    []>;
-def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR",
-    SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVec<2>, SDTCisInt<3>]>,
-    []>;
-
 // This operator does subvector type checking.
 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;