[llvm] [RISCV] Factor out LI/QC_LI matching in RISCVRedundantCopyElimination. NFC (PR #228610)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/228610

None

>From 6f08fe07d71b362ffe3286734094dfa8d1d76530 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 2 Oct 2026 15:44:25 -0700
Subject: [PATCH] [RISCV] Factor out LI/QC_LI matching in
 RISCVRedundantCopyElimination. NFC

---
 .../RISCV/RISCVRedundantCopyElimination.cpp   | 49 +++++++++----------
 1 file changed, 23 insertions(+), 26 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
index ccf9fc2b040f6..67785f666531f 100644
--- a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
@@ -109,6 +109,20 @@ guaranteesRegEqualsImmInBlock(MachineBasicBlock &MBB,
   return false;
 }
 
+// Match "addi rd, x0, imm" or "qc.li rd, imm", returning the defined
+// register and the materialized immediate. Reg is invalid if MI isn't a
+// match.
+static RegImmPair matchRegImmediate(const MachineInstr &MI) {
+  if (MI.getOpcode() == RISCV::ADDI && MI.getOperand(0).isReg() &&
+      MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0 &&
+      MI.getOperand(2).isImm())
+    return RegImmPair(MI.getOperand(0).getReg(), MI.getOperand(2).getImm());
+  if (MI.getOpcode() == RISCV::QC_LI && MI.getOperand(0).isReg() &&
+      MI.getOperand(1).isImm())
+    return RegImmPair(MI.getOperand(0).getReg(), MI.getOperand(1).getImm());
+  return RegImmPair(Register(), 0);
+}
+
 static std::optional<int64_t>
 getRegImmediateBeforeTerminator(MachineBasicBlock &MBB, Register Reg,
                                 const TargetRegisterInfo *TRI) {
@@ -121,13 +135,9 @@ getRegImmediateBeforeTerminator(MachineBasicBlock &MBB, Register Reg,
     if (!MI.modifiesRegister(Reg, TRI))
       continue;
     // The last modification must define Reg itself to a known immediate.
-    if (MI.getOpcode() == RISCV::ADDI && MI.getOperand(0).isReg() &&
-        MI.getOperand(0).getReg() == Reg && MI.getOperand(1).isReg() &&
-        MI.getOperand(1).getReg() == RISCV::X0 && MI.getOperand(2).isImm())
-      return MI.getOperand(2).getImm();
-    if (MI.getOpcode() == RISCV::QC_LI && MI.getOperand(0).isReg() &&
-        MI.getOperand(0).getReg() == Reg && MI.getOperand(1).isImm())
-      return MI.getOperand(1).getImm();
+    RegImmPair Match = matchRegImmediate(MI);
+    if (Match.Reg == Reg)
+      return Match.Imm;
     return std::nullopt;
   }
   return std::nullopt;
@@ -199,29 +209,16 @@ bool RISCVRedundantCopyElimination::optimizeBlock(MachineBasicBlock &MBB) {
         Register DefReg = MI->getOperand(0).getReg();
         Register SrcReg = MI->getOperand(1).getReg();
 
-        if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) &&
-            TargetReg == DefReg)
+        if (SrcReg == RISCV::X0 && TargetReg == DefReg &&
+            !MRI->isReserved(DefReg))
           RemoveMI = true;
       }
     } else {
-      // Xqcibi, XAndesPref and Zibi compare with non-zero immediate:
+      // Compare with non-zero immediate or a known register value:
       // remove redundant addi rd,x0,imm or qc.li rd,imm as applicable.
-      if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(0).isReg() &&
-          MI->getOperand(1).isReg() && MI->getOperand(2).isImm()) {
-        Register DefReg = MI->getOperand(0).getReg();
-        Register SrcReg = MI->getOperand(1).getReg();
-        int64_t Imm = MI->getOperand(2).getImm();
-        if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) &&
-            TargetReg == DefReg && Imm == CompareImm)
-          RemoveMI = true;
-      } else if (MI->getOpcode() == RISCV::QC_LI && MI->getOperand(0).isReg() &&
-                 MI->getOperand(1).isImm()) {
-        Register DefReg = MI->getOperand(0).getReg();
-        int64_t Imm = MI->getOperand(1).getImm();
-        if (!MRI->isReserved(DefReg) && TargetReg == DefReg &&
-            Imm == CompareImm)
-          RemoveMI = true;
-      }
+      RegImmPair Match = matchRegImmediate(*MI);
+      if (Match.Reg && TargetReg == Match.Reg && Match.Imm == CompareImm)
+        RemoveMI = true;
     }
 
     if (RemoveMI) {