[llvm] [AMDGPU] op_sel[0] must be zero for v_cvt_sr_fp8/bf8_f16 (PR #227413)

[Changpeng Fang via llvm-commits]

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@@ -654,6 +654,13 @@ def VGPR_16_Lo128 : SIRegisterClass<"AMDGPU",  Reg16Types.types, 16,
   let BaseClassOrder = 16;
 }
 
+def VGPR_16_Lo : SIRegisterClass<"AMDGPU",  Reg16Types.types, 16,
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changpeng wrote:

> I think this should be called `VGPR_16_LO16`, because `Lo` usually means the lower 128 VGPRs, like the one above, instead of the lower 16-bit of those VGPRs.

Renamed as suggested. Thanks

https://github.com/llvm/llvm-project/pull/227413