[llvm] ARM: Mark cpsr def dead in FastISel integer extends (PR #227705)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/227705

>From 67fd10773c1536a76e387aafe148bcd4a3a62196 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 29 Sep 2026 02:37:02 +0200
Subject: [PATCH] ARM: Mark cpsr def dead in FastISel integer extends

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
---
 llvm/lib/Target/ARM/ARMFastISel.cpp           |  2 +-
 .../CodeGen/ARM/fast-isel-ext-dead-cpsr.ll    | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/ARM/fast-isel-ext-dead-cpsr.ll

diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 88ee3156ee3392..e79f8d6557abbb 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -2803,7 +2803,7 @@ Register ARMFastISel::ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT,
     MachineInstrBuilder MIB = BuildMI(
         *FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opcode), ResultReg);
     if (setsCPSR)
-      MIB.addReg(ARM::CPSR, RegState::Define);
+      MIB.addReg(ARM::CPSR, RegState::Define | RegState::Dead);
     SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
     MIB.addReg(SrcReg, getKillRegState(isKill))
         .addImm(ImmEnc)
diff --git a/llvm/test/CodeGen/ARM/fast-isel-ext-dead-cpsr.ll b/llvm/test/CodeGen/ARM/fast-isel-ext-dead-cpsr.ll
new file mode 100644
index 00000000000000..30b8534c9ba335
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/fast-isel-ext-dead-cpsr.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -O0 -fast-isel-abort=1 -mtriple=thumbv7-apple-ios -stop-after=finalize-isel -o - %s | FileCheck %s
+
+; The flags set by the 16-bit Thumb shifts used to extend are dead.
+
+define i32 @sext_1_32(i1 %a) nounwind ssp {
+  ; CHECK-LABEL: name: sext_1_32
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $r0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $r0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:tgpr = COPY [[COPY]]
+  ; CHECK-NEXT:   %3:tgpr, dead $cpsr = tLSLri [[COPY1]], 31, 14 /* CC::al */, $noreg
+  ; CHECK-NEXT:   %4:tgpr, dead $cpsr = tASRri killed %3, 31, 14 /* CC::al */, $noreg
+  ; CHECK-NEXT:   $r0 = COPY %4
+  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+  %r = sext i1 %a to i32
+  ret i32 %r
+}