[llvm] [AMDGPU][NFC] Pre-commit test for spilling a read-undef IMPLICIT_DEF (PR #227858)
Pablo Reble via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 2 07:21:08 PDT 2026
https://github.com/reble updated https://github.com/llvm/llvm-project/pull/227858
>From 3ff37e48d69afc1eef0d7a5a01354b09e237b694 Mon Sep 17 00:00:00 2001
From: Pablo Reble <pablo.reble at amd.com>
Date: Tue, 29 Sep 2026 16:53:12 -0500
Subject: [PATCH 1/2] [AMDGPU] Pre-commit test for spilling a read-undef
IMPLICIT_DEF
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
---
.../AMDGPU/spill-undef-subreg-impdef.mir | 131 ++++++++++++++++++
1 file changed, 131 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/spill-undef-subreg-impdef.mir
diff --git a/llvm/test/CodeGen/AMDGPU/spill-undef-subreg-impdef.mir b/llvm/test/CodeGen/AMDGPU/spill-undef-subreg-impdef.mir
new file mode 100644
index 00000000000000..dfccc0d4ac1906
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/spill-undef-subreg-impdef.mir
@@ -0,0 +1,131 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=greedy -stress-regalloc=4 -verify-machineinstrs %s -o - | FileCheck %s
+
+# TODO: A read-undef subregister IMPLICIT_DEF leaves the whole register
+# undefined, but this test currently shows a real spill. Without the
+# undef flag, the other lanes are live and the value must be spilled.
+
+---
+name: spill_undef_subreg_impdef
+tracksRegLiveness: true
+machineFunctionInfo:
+ scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
+ stackPtrOffsetReg: '$sgpr32'
+body: |
+ ; CHECK-LABEL: name: spill_undef_subreg_impdef
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit undef $scc
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:vreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: SI_SPILL_V64_SAVE [[DEF]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, align 4, addrspace 5)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:vreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: SI_SPILL_V64_SAVE [[COPY2]], %stack.1, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.1, align 4, addrspace 5)
+ ; CHECK-NEXT: S_BRANCH %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: SI_SPILL_V64_SAVE [[COPY]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, align 4, addrspace 5)
+ ; CHECK-NEXT: SI_SPILL_V64_SAVE [[COPY]], %stack.1, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.1, align 4, addrspace 5)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, clobber, implicit-def dead early-clobber $vgpr0, clobber, implicit-def dead early-clobber $vgpr1, clobber, implicit-def dead early-clobber $vgpr2, clobber, implicit-def dead early-clobber $vgpr3
+ ; CHECK-NEXT: [[SI_SPILL_V64_RESTORE:%[0-9]+]]:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.0, align 4, addrspace 5)
+ ; CHECK-NEXT: BUFFER_STORE_DWORDX2_OFFSET [[SI_SPILL_V64_RESTORE]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s64), addrspace 1)
+ ; CHECK-NEXT: [[SI_SPILL_V64_RESTORE1:%[0-9]+]]:vreg_64 = SI_SPILL_V64_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.1, align 4, addrspace 5)
+ ; CHECK-NEXT: BUFFER_STORE_DWORDX2_OFFSET [[SI_SPILL_V64_RESTORE1]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s64), addrspace 1)
+ ; CHECK-NEXT: S_ENDPGM 0
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ successors: %bb.1, %bb.2
+
+ %2:vreg_64 = COPY $vgpr2_vgpr3
+ %3:vreg_64 = COPY $vgpr0_vgpr1
+ S_CBRANCH_SCC1 %bb.2, implicit undef $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.3
+ undef %0.sub0:vreg_64 = IMPLICIT_DEF
+ %1:vreg_64 = COPY %3
+ %1.sub1:vreg_64 = IMPLICIT_DEF
+ S_BRANCH %bb.3
+
+ bb.2:
+ successors: %bb.3
+ %0:vreg_64 = COPY %2
+ %1:vreg_64 = COPY %2
+
+ bb.3:
+ INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $vgpr0, 12 /* clobber */, implicit-def dead early-clobber $vgpr1, 12 /* clobber */, implicit-def dead early-clobber $vgpr2, 12 /* clobber */, implicit-def dead early-clobber $vgpr3
+ BUFFER_STORE_DWORDX2_OFFSET %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s64), addrspace 1)
+ BUFFER_STORE_DWORDX2_OFFSET %1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s64), addrspace 1)
+ S_ENDPGM 0
+...
+
+# Same with a multi-lane read-undef def that doesn't start at sub0.
+---
+name: spill_undef_subreg_impdef_multi_lane
+tracksRegLiveness: true
+machineFunctionInfo:
+ scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
+ stackPtrOffsetReg: '$sgpr32'
+body: |
+ ; CHECK-LABEL: name: spill_undef_subreg_impdef_multi_lane
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit undef $scc
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub2_sub3:vreg_128 = IMPLICIT_DEF
+ ; CHECK-NEXT: SI_SPILL_V128_SAVE [[DEF]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5)
+ ; CHECK-NEXT: S_BRANCH %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: SI_SPILL_V128_SAVE [[COPY]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, clobber, implicit-def dead early-clobber $vgpr0, clobber, implicit-def dead early-clobber $vgpr1, clobber, implicit-def dead early-clobber $vgpr2, clobber, implicit-def dead early-clobber $vgpr3
+ ; CHECK-NEXT: [[SI_SPILL_V128_RESTORE:%[0-9]+]]:vreg_128 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5)
+ ; CHECK-NEXT: BUFFER_STORE_DWORDX4_OFFSET [[SI_SPILL_V128_RESTORE]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s128), addrspace 1)
+ ; CHECK-NEXT: S_ENDPGM 0
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ successors: %bb.1, %bb.2
+
+ %1:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ S_CBRANCH_SCC1 %bb.2, implicit undef $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.3
+ undef %0.sub2_sub3:vreg_128 = IMPLICIT_DEF
+ S_BRANCH %bb.3
+
+ bb.2:
+ successors: %bb.3
+ %0:vreg_128 = COPY %1
+
+ bb.3:
+ INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $vgpr0, 12 /* clobber */, implicit-def dead early-clobber $vgpr1, 12 /* clobber */, implicit-def dead early-clobber $vgpr2, 12 /* clobber */, implicit-def dead early-clobber $vgpr3
+ BUFFER_STORE_DWORDX4_OFFSET %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s128), addrspace 1)
+ S_ENDPGM 0
+...
>From b4fc93653fc32d7f0d605b6116727779783bc59e Mon Sep 17 00:00:00 2001
From: Pablo Reble <pablo.reble at amd.com>
Date: Fri, 2 Oct 2026 09:07:12 -0500
Subject: [PATCH 2/2] Addressing feedback from review.
---
llvm/test/CodeGen/AMDGPU/spill-undef-subreg-impdef.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/spill-undef-subreg-impdef.mir b/llvm/test/CodeGen/AMDGPU/spill-undef-subreg-impdef.mir
index dfccc0d4ac1906..f1295b02d4978a 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-undef-subreg-impdef.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-undef-subreg-impdef.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgpu9.00 -run-pass=greedy -stress-regalloc=4 -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -passes='greedy<vgpr>' -stress-regalloc=4 -verify-regalloc %s -o - | FileCheck %s
# TODO: A read-undef subregister IMPLICIT_DEF leaves the whole register
# undefined, but this test currently shows a real spill. Without the
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