[llvm] RegisterCoalescer: Don't mark a remat def dead when the copy destination covers it (PR #226037)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 2 07:20:22 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/226037
>From ca879ff8a0fcc06496a47415d627ed409906c354 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 18 Sep 2026 18:55:22 +0200
Subject: [PATCH] RegisterCoalescer: Don't mark a remat def dead when the copy
destination covers it
When rematerializing into a physical register that is not exactly the copy's
destination, reMaterializeDef marks the rematerialized def dead and adds an
implicit-def of the copy destination. That is only correct when the rematerialized
instruction defines more than the copy asked for, so the extra part really is unused.
It is wrong when the def is covered by the copy destination, since then it is
part of that live value:
undef %0.sub_32bit:gr64 = MOV32ri -11
$rax = COPY %0
; coalesces to
dead $eax = MOV32ri -11, implicit-def $rax
$eax is the live low half of $rax, so it must not be dead. Only set the dead
flag when the def has register units the copy destination does not cover.
This makes the dead flags consistent with what LiveVariables would produce
in these scenarios.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
---
llvm/lib/CodeGen/RegisterCoalescer.cpp | 14 +-
...esce-commute-partial-def-implicit-read.mir | 2 +-
llvm/test/CodeGen/X86/masked-udiv.ll | 433 +++++++++---------
.../CodeGen/X86/min-legal-vector-width.ll | 64 +--
...rematerialize-sub-super-reg-dead-flags.mir | 84 ++++
.../X86/rematerialize-sub-super-reg.mir | 65 ++-
.../statepoint-invoke-ra-inline-spiller.mir | 2 +-
...tatepoint-invoke-ra-remove-back-copies.mir | 4 +-
.../test/CodeGen/X86/statepoint-invoke-ra.mir | 2 +-
llvm/test/CodeGen/X86/statepoint-ra.ll | 2 +-
.../CodeGen/X86/statepoint-vreg-details.ll | 4 +-
llvm/test/CodeGen/X86/udiv_fix.ll | 34 +-
llvm/test/CodeGen/X86/udiv_fix_sat.ll | 82 ++--
llvm/test/CodeGen/X86/vector-idiv-strictfp.ll | 191 ++++----
llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll | 132 +++---
15 files changed, 604 insertions(+), 511 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/rematerialize-sub-super-reg-dead-flags.mir
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 23b151ed7b981b5..85831d46a5dcb7f 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1639,11 +1639,15 @@ bool RegisterCoalescer::reMaterializeDef(const CoalescerPair &CP,
assert(DstReg.isPhysical() &&
"Only expect virtual or physical registers in remat");
- // When we're rematerializing into a not-quite-right register we already add
- // the real definition as an implicit-def, but we should also be marking the
- // "official" register as dead, since nothing else is going to use it as a
- // result of this remat. Not doing this can affect pressure tracking.
- NewMI.getOperand(0).setIsDead(true);
+ // CopyDstReg is added as an implicit-def below. The remat may also define
+ // units CopyDstReg does not cover; nothing uses those, so the def is dead.
+ // If CopyDstReg covers every defined unit, the def is part of that live
+ // value and must stay live.
+ Register DefReg = NewMI.getOperand(0).getReg();
+ if (any_of(TRI->regunits(DefReg.asMCReg()), [&](MCRegUnit Unit) {
+ return !TRI->hasRegUnit(CopyDstReg, Unit);
+ }))
+ NewMI.getOperand(0).setIsDead(true);
bool HasDefMatchingCopy = false;
for (auto [OpIndex, Reg] : NewMIImplDefs) {
diff --git a/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir b/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir
index ca087b17eab3fc1..87fdc47a526ba9e 100644
--- a/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir
+++ b/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir
@@ -34,7 +34,7 @@ body: |
; CHECK-NEXT: successors: %bb.6(0x3efbefbf), %bb.3(0x41041041)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
- ; CHECK-NEXT: dead $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
+ ; CHECK-NEXT: $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
; CHECK-NEXT: $rsi = COPY [[MOV32r0_1]]
; CHECK-NEXT: CALL64r [[MOV32r0_]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
diff --git a/llvm/test/CodeGen/X86/masked-udiv.ll b/llvm/test/CodeGen/X86/masked-udiv.ll
index 51114074232cb31..7fbddc22cc38a0f 100644
--- a/llvm/test/CodeGen/X86/masked-udiv.ll
+++ b/llvm/test/CodeGen/X86/masked-udiv.ll
@@ -204,40 +204,39 @@ define <2 x i64> @udiv_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m) {
define <4 x i64> @udiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; SSE2-LABEL: udiv_v4i64:
; SSE2: # %bb.0:
-; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,1,1]
+; SSE2-NEXT: movdqa %xmm0, %xmm5
+; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,2,3,3]
; SSE2-NEXT: pslld $31, %xmm6
; SSE2-NEXT: psrad $31, %xmm6
-; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1,1]
-; SSE2-NEXT: pand %xmm6, %xmm2
-; SSE2-NEXT: pandn %xmm5, %xmm6
-; SSE2-NEXT: por %xmm2, %xmm6
-; SSE2-NEXT: movq %xmm6, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
+; SSE2-NEXT: pslld $31, %xmm4
+; SSE2-NEXT: psrad $31, %xmm4
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [1,1]
+; SSE2-NEXT: pand %xmm4, %xmm2
+; SSE2-NEXT: pandn %xmm7, %xmm4
+; SSE2-NEXT: por %xmm2, %xmm4
+; SSE2-NEXT: movq %xmm4, %rcx
; SSE2-NEXT: movq %xmm0, %rax
; SSE2-NEXT: xorl %edx, %edx
; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %rcx
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm6[2,3,2,3]
-; SSE2-NEXT: movq %xmm2, %rsi
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %rax
+; SSE2-NEXT: movq %rax, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[2,3,2,3]
+; SSE2-NEXT: movq %xmm2, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm5[2,3,2,3]
+; SSE2-NEXT: movq %xmm2, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rsi
-; SSE2-NEXT: movq %rax, %rsi
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,2,3,3]
-; SSE2-NEXT: pslld $31, %xmm4
-; SSE2-NEXT: psrad $31, %xmm4
-; SSE2-NEXT: pand %xmm4, %xmm3
-; SSE2-NEXT: pandn %xmm5, %xmm4
-; SSE2-NEXT: por %xmm3, %xmm4
-; SSE2-NEXT: movq %xmm4, %rdi
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm2
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-NEXT: pand %xmm6, %xmm3
+; SSE2-NEXT: pandn %xmm7, %xmm6
+; SSE2-NEXT: por %xmm3, %xmm6
+; SSE2-NEXT: movq %xmm6, %rcx
; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rdi
-; SSE2-NEXT: movq %rcx, %xmm0
-; SSE2-NEXT: movq %rsi, %xmm2
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-NEXT: divq %rcx
; SSE2-NEXT: movq %rax, %xmm2
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[2,3,2,3]
+; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm6[2,3,2,3]
; SSE2-NEXT: movq %xmm3, %rcx
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE2-NEXT: movq %xmm1, %rax
@@ -251,39 +250,38 @@ define <4 x i64> @udiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; SSE42-LABEL: udiv_v4i64:
; SSE42: # %bb.0:
; SSE42-NEXT: movdqa %xmm0, %xmm5
+; SSE42-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,2,3,3]
; SSE42-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm4[0],zero,xmm4[1],zero
; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movapd {{.*#+}} xmm6 = [1,1]
-; SSE42-NEXT: movapd %xmm6, %xmm7
+; SSE42-NEXT: movapd {{.*#+}} xmm4 = [1,1]
+; SSE42-NEXT: movapd %xmm4, %xmm7
; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm7
; SSE42-NEXT: pextrq $1, %xmm7, %rcx
; SSE42-NEXT: pextrq $1, %xmm5, %rax
+; SSE42-NEXT: psllq $63, %xmm6
; SSE42-NEXT: xorl %edx, %edx
; SSE42-NEXT: divq %rcx
-; SSE42-NEXT: movq %rax, %rcx
-; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm4[2,2,3,3]
-; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movq %xmm7, %rdi
-; SSE42-NEXT: blendvpd %xmm0, %xmm3, %xmm6
-; SSE42-NEXT: pextrq $1, %xmm6, %r8
-; SSE42-NEXT: pextrq $1, %xmm1, %rsi
+; SSE42-NEXT: movq %rax, %xmm8
+; SSE42-NEXT: movq %xmm7, %rcx
; SSE42-NEXT: movq %xmm5, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %rdi
-; SSE42-NEXT: movq %rax, %rdi
-; SSE42-NEXT: movq %rsi, %rax
-; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %r8
-; SSE42-NEXT: movq %rcx, %xmm2
-; SSE42-NEXT: movq %rdi, %xmm0
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE42-NEXT: divq %rcx
; SSE42-NEXT: movq %rax, %xmm2
-; SSE42-NEXT: movq %xmm6, %rcx
+; SSE42-NEXT: movdqa %xmm6, %xmm0
+; SSE42-NEXT: blendvpd %xmm0, %xmm3, %xmm4
+; SSE42-NEXT: pextrq $1, %xmm4, %rcx
+; SSE42-NEXT: pextrq $1, %xmm1, %rax
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm8[0]
+; SSE42-NEXT: xorl %edx, %edx
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm0
+; SSE42-NEXT: movq %xmm4, %rcx
; SSE42-NEXT: movq %xmm1, %rax
; SSE42-NEXT: xorl %edx, %edx
; SSE42-NEXT: divq %rcx
; SSE42-NEXT: movq %rax, %xmm1
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE42-NEXT: movdqa %xmm2, %xmm0
; SSE42-NEXT: retq
;
; AVX2-LABEL: udiv_v4i64:
@@ -303,20 +301,19 @@ define <4 x i64> @udiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; AVX2-NEXT: vmovq %xmm3, %rax
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: divq %rsi
-; AVX2-NEXT: movq %rax, %rsi
-; AVX2-NEXT: vpextrq $1, %xmm1, %rdi
+; AVX2-NEXT: vmovq %rcx, %xmm2
+; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
+; AVX2-NEXT: vmovq %rax, %xmm3
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %rdi
-; AVX2-NEXT: movq %rax, %rdi
-; AVX2-NEXT: vmovq %rcx, %xmm2
-; AVX2-NEXT: vmovq %rsi, %xmm3
+; AVX2-NEXT: divq %rcx
+; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; AVX2-NEXT: vmovq %xmm1, %rcx
+; AVX2-NEXT: vmovq %xmm1, %rsi
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %rcx
-; AVX2-NEXT: vmovq %rdi, %xmm0
+; AVX2-NEXT: divq %rsi
+; AVX2-NEXT: vmovq %rcx, %xmm0
; AVX2-NEXT: vmovq %rax, %xmm1
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -819,181 +816,169 @@ define <3 x i10> @udiv_v3i10(<3 x i10> %x, <3 x i10> %y, <3 x i1> %m) {
define <8 x i64> @udiv_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i1> %m) {
; SSE2-LABEL: udiv_v8i64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
-; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm8[0,0,0,0]
+; SSE2-NEXT: movdqa %xmm0, %xmm8
+; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm0[3,3,3,3]
; SSE2-NEXT: pshufhw {{.*#+}} xmm9 = xmm9[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
+; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm9[0,0,2,2]
+; SSE2-NEXT: pslld $31, %xmm9
+; SSE2-NEXT: psrad $31, %xmm9
+; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm0[2,2,2,2]
+; SSE2-NEXT: pshufhw {{.*#+}} xmm10 = xmm10[0,1,2,3,5,5,5,5]
+; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm10[0,0,2,2]
; SSE2-NEXT: pslld $31, %xmm10
; SSE2-NEXT: psrad $31, %xmm10
-; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [1,1]
-; SSE2-NEXT: pand %xmm10, %xmm4
-; SSE2-NEXT: pandn %xmm9, %xmm10
-; SSE2-NEXT: por %xmm4, %xmm10
-; SSE2-NEXT: movq %xmm10, %rcx
-; SSE2-NEXT: movq %xmm0, %rax
+; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm0[1,1,1,1]
+; SSE2-NEXT: pshufhw {{.*#+}} xmm11 = xmm11[0,1,2,3,5,5,5,5]
+; SSE2-NEXT: pshufd {{.*#+}} xmm12 = xmm11[0,0,2,2]
+; SSE2-NEXT: pslld $31, %xmm12
+; SSE2-NEXT: psrad $31, %xmm12
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
+; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
+; SSE2-NEXT: pshufd {{.*#+}} xmm13 = xmm0[0,0,2,2]
+; SSE2-NEXT: pslld $31, %xmm13
+; SSE2-NEXT: psrad $31, %xmm13
+; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [1,1]
+; SSE2-NEXT: pand %xmm13, %xmm4
+; SSE2-NEXT: pandn %xmm11, %xmm13
+; SSE2-NEXT: por %xmm4, %xmm13
+; SSE2-NEXT: movq %xmm13, %rcx
+; SSE2-NEXT: movq %xmm8, %rax
; SSE2-NEXT: xorl %edx, %edx
; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %rcx
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm10[2,3,2,3]
-; SSE2-NEXT: movq %xmm4, %rsi
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %rax
+; SSE2-NEXT: movq %rax, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm13[2,3,2,3]
+; SSE2-NEXT: movq %xmm4, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm8[2,3,2,3]
+; SSE2-NEXT: movq %xmm4, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rsi
-; SSE2-NEXT: movq %rax, %rsi
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm8[1,1,1,1]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; SSE2-NEXT: pslld $31, %xmm0
-; SSE2-NEXT: psrad $31, %xmm0
-; SSE2-NEXT: pand %xmm0, %xmm5
-; SSE2-NEXT: pandn %xmm9, %xmm0
-; SSE2-NEXT: por %xmm5, %xmm0
-; SSE2-NEXT: movq %xmm0, %rdi
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm4
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
+; SSE2-NEXT: pand %xmm12, %xmm5
+; SSE2-NEXT: pandn %xmm11, %xmm12
+; SSE2-NEXT: por %xmm5, %xmm12
+; SSE2-NEXT: movq %xmm12, %rcx
; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rdi
-; SSE2-NEXT: movq %rax, %rdi
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %r8
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %rax
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm4
+; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm12[2,3,2,3]
+; SSE2-NEXT: movq %xmm5, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %r8
-; SSE2-NEXT: movq %rax, %r8
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm8[2,2,2,2]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; SSE2-NEXT: pslld $31, %xmm0
-; SSE2-NEXT: psrad $31, %xmm0
-; SSE2-NEXT: pand %xmm0, %xmm6
-; SSE2-NEXT: pandn %xmm9, %xmm0
-; SSE2-NEXT: por %xmm6, %xmm0
-; SSE2-NEXT: movq %xmm0, %r9
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm1[0]
+; SSE2-NEXT: pand %xmm10, %xmm6
+; SSE2-NEXT: pandn %xmm11, %xmm10
+; SSE2-NEXT: por %xmm6, %xmm10
+; SSE2-NEXT: movq %xmm10, %rcx
; SSE2-NEXT: movq %xmm2, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %r9
-; SSE2-NEXT: movq %rax, %r9
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %r10
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %rax
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm5
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm10[2,3,2,3]
+; SSE2-NEXT: movq %xmm1, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3]
+; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %r10
-; SSE2-NEXT: movq %rax, %r10
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm8[3,3,3,3]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm0[0,0,2,2]
-; SSE2-NEXT: pslld $31, %xmm5
-; SSE2-NEXT: psrad $31, %xmm5
-; SSE2-NEXT: pand %xmm5, %xmm7
-; SSE2-NEXT: pandn %xmm9, %xmm5
-; SSE2-NEXT: por %xmm7, %xmm5
-; SSE2-NEXT: movq %xmm5, %r11
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm1[0]
+; SSE2-NEXT: pand %xmm9, %xmm7
+; SSE2-NEXT: pandn %xmm11, %xmm9
+; SSE2-NEXT: por %xmm7, %xmm9
+; SSE2-NEXT: movq %xmm9, %rcx
; SSE2-NEXT: movq %xmm3, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %r11
-; SSE2-NEXT: movq %rcx, %xmm0
-; SSE2-NEXT: movq %rsi, %xmm4
-; SSE2-NEXT: movq %rdi, %xmm1
-; SSE2-NEXT: movq %r8, %xmm6
-; SSE2-NEXT: movq %r9, %xmm2
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm6[0]
-; SSE2-NEXT: movq %r10, %xmm4
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
-; SSE2-NEXT: movq %rax, %xmm4
-; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3]
-; SSE2-NEXT: movq %xmm5, %rcx
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
-; SSE2-NEXT: movq %xmm3, %rax
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm6
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm9[2,3,2,3]
+; SSE2-NEXT: movq %xmm1, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[2,3,2,3]
+; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %xmm3
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0]
-; SSE2-NEXT: movdqa %xmm4, %xmm3
+; SSE2-NEXT: movq %rax, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm1[0]
+; SSE2-NEXT: movdqa %xmm4, %xmm1
+; SSE2-NEXT: movdqa %xmm5, %xmm2
+; SSE2-NEXT: movdqa %xmm6, %xmm3
; SSE2-NEXT: retq
;
; SSE42-LABEL: udiv_v8i64:
; SSE42: # %bb.0:
-; SSE42-NEXT: pushq %rbx
-; SSE42-NEXT: .cfi_def_cfa_offset 16
-; SSE42-NEXT: .cfi_offset %rbx, -16
-; SSE42-NEXT: movdqa %xmm0, %xmm8
-; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
-; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm10[0],zero,zero,zero,xmm10[1],zero,zero,zero
+; SSE42-NEXT: movdqa %xmm0, %xmm11
+; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
+; SSE42-NEXT: pshufd {{.*#+}} xmm8 = xmm0[3,3,3,3]
+; SSE42-NEXT: pmovzxwq {{.*#+}} xmm8 = xmm8[0],zero,zero,zero,xmm8[1],zero,zero,zero
+; SSE42-NEXT: psllq $63, %xmm8
+; SSE42-NEXT: pshufd {{.*#+}} xmm9 = xmm0[2,3,2,3]
+; SSE42-NEXT: pmovzxwq {{.*#+}} xmm9 = xmm9[0],zero,zero,zero,xmm9[1],zero,zero,zero
+; SSE42-NEXT: psllq $63, %xmm9
+; SSE42-NEXT: pshufd {{.*#+}} xmm10 = xmm0[1,1,1,1]
+; SSE42-NEXT: pmovzxwq {{.*#+}} xmm10 = xmm10[0],zero,zero,zero,xmm10[1],zero,zero,zero
+; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movapd {{.*#+}} xmm9 = [1,1]
-; SSE42-NEXT: movapd %xmm9, %xmm11
-; SSE42-NEXT: blendvpd %xmm0, %xmm4, %xmm11
-; SSE42-NEXT: pextrq $1, %xmm11, %rcx
-; SSE42-NEXT: pextrq $1, %xmm8, %rax
+; SSE42-NEXT: movapd {{.*#+}} xmm12 = [1,1]
+; SSE42-NEXT: movapd %xmm12, %xmm13
+; SSE42-NEXT: blendvpd %xmm0, %xmm4, %xmm13
+; SSE42-NEXT: pextrq $1, %xmm13, %rcx
+; SSE42-NEXT: pextrq $1, %xmm11, %rax
+; SSE42-NEXT: psllq $63, %xmm10
; SSE42-NEXT: xorl %edx, %edx
; SSE42-NEXT: divq %rcx
-; SSE42-NEXT: movq %rax, %rcx
-; SSE42-NEXT: movq %xmm11, %rsi
-; SSE42-NEXT: movq %xmm8, %rax
+; SSE42-NEXT: movq %rax, %xmm0
+; SSE42-NEXT: movq %xmm13, %rcx
+; SSE42-NEXT: movq %xmm11, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %rsi
-; SSE42-NEXT: movq %rax, %rsi
-; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm10[1,1,1,1]
-; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
-; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movapd %xmm9, %xmm4
-; SSE42-NEXT: blendvpd %xmm0, %xmm5, %xmm4
-; SSE42-NEXT: pextrq $1, %xmm4, %rdi
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm4
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0]
+; SSE42-NEXT: movapd %xmm12, %xmm11
+; SSE42-NEXT: movdqa %xmm10, %xmm0
+; SSE42-NEXT: blendvpd %xmm0, %xmm5, %xmm11
+; SSE42-NEXT: pextrq $1, %xmm11, %rcx
; SSE42-NEXT: pextrq $1, %xmm1, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %rdi
-; SSE42-NEXT: movq %rax, %rdi
-; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm10[2,3,2,3]
-; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
-; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movq %xmm4, %r8
-; SSE42-NEXT: movapd %xmm9, %xmm4
-; SSE42-NEXT: blendvpd %xmm0, %xmm6, %xmm4
-; SSE42-NEXT: pextrq $1, %xmm4, %r10
-; SSE42-NEXT: pextrq $1, %xmm2, %r9
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm5
+; SSE42-NEXT: movq %xmm11, %rcx
; SSE42-NEXT: movq %xmm1, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %r8
-; SSE42-NEXT: movq %rax, %r8
-; SSE42-NEXT: movq %r9, %rax
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm1
+; SSE42-NEXT: movapd %xmm12, %xmm10
+; SSE42-NEXT: movdqa %xmm9, %xmm0
+; SSE42-NEXT: blendvpd %xmm0, %xmm6, %xmm10
+; SSE42-NEXT: pextrq $1, %xmm10, %rcx
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm5[0]
+; SSE42-NEXT: pextrq $1, %xmm2, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %r10
-; SSE42-NEXT: movq %rax, %r9
-; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm10[3,3,3,3]
-; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
-; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movq %xmm4, %r11
-; SSE42-NEXT: blendvpd %xmm0, %xmm7, %xmm9
-; SSE42-NEXT: pextrq $1, %xmm9, %rbx
-; SSE42-NEXT: pextrq $1, %xmm3, %r10
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm5
+; SSE42-NEXT: movq %xmm10, %rcx
; SSE42-NEXT: movq %xmm2, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %r11
-; SSE42-NEXT: movq %rax, %r11
-; SSE42-NEXT: movq %r10, %rax
-; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %rbx
-; SSE42-NEXT: movq %rcx, %xmm2
-; SSE42-NEXT: movq %rsi, %xmm0
-; SSE42-NEXT: movq %rdi, %xmm4
-; SSE42-NEXT: movq %r8, %xmm1
-; SSE42-NEXT: movq %r9, %xmm5
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0]
-; SSE42-NEXT: movq %r11, %xmm2
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm2
+; SSE42-NEXT: movdqa %xmm8, %xmm0
+; SSE42-NEXT: blendvpd %xmm0, %xmm7, %xmm12
+; SSE42-NEXT: pextrq $1, %xmm12, %rcx
; SSE42-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm5[0]
-; SSE42-NEXT: movq %rax, %xmm4
-; SSE42-NEXT: movq %xmm9, %rcx
+; SSE42-NEXT: pextrq $1, %xmm3, %rax
+; SSE42-NEXT: xorl %edx, %edx
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm0
+; SSE42-NEXT: movq %xmm12, %rcx
; SSE42-NEXT: movq %xmm3, %rax
; SSE42-NEXT: xorl %edx, %edx
; SSE42-NEXT: divq %rcx
; SSE42-NEXT: movq %rax, %xmm3
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
-; SSE42-NEXT: popq %rbx
-; SSE42-NEXT: .cfi_def_cfa_offset 8
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
+; SSE42-NEXT: movdqa %xmm4, %xmm0
; SSE42-NEXT: retq
;
; AVX2-LABEL: udiv_v8i64:
@@ -1010,57 +995,55 @@ define <8 x i64> @udiv_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i1> %m) {
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: divq %rcx
; AVX2-NEXT: movq %rax, %rcx
+; AVX2-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm4[4,4,5,5,6,6,7,7]
; AVX2-NEXT: vmovq %xmm6, %rsi
; AVX2-NEXT: vmovq %xmm7, %rax
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: divq %rsi
; AVX2-NEXT: movq %rax, %rsi
+; AVX2-NEXT: vpslld $31, %xmm4, %xmm4
+; AVX2-NEXT: vpmovsxdq %xmm4, %ymm4
; AVX2-NEXT: vpextrq $1, %xmm2, %rdi
+; AVX2-NEXT: vmovq %rcx, %xmm6
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: divq %rdi
-; AVX2-NEXT: movq %rax, %rdi
-; AVX2-NEXT: vmovq %xmm2, %r8
+; AVX2-NEXT: movq %rax, %rcx
+; AVX2-NEXT: vmovq %rsi, %xmm7
+; AVX2-NEXT: vmovq %xmm2, %rsi
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %r8
-; AVX2-NEXT: movq %rax, %r8
-; AVX2-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm4[4,4,5,5,6,6,7,7]
-; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
-; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
-; AVX2-NEXT: vblendvpd %ymm0, %ymm3, %ymm5, %ymm2
-; AVX2-NEXT: vextractf128 $1, %ymm2, %xmm0
-; AVX2-NEXT: vpextrq $1, %xmm0, %r9
-; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm3
-; AVX2-NEXT: vpextrq $1, %xmm3, %rax
+; AVX2-NEXT: divq %rsi
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm7[0],xmm6[0]
+; AVX2-NEXT: vmovq %rcx, %xmm6
+; AVX2-NEXT: vblendvpd %ymm4, %ymm3, %ymm5, %ymm2
+; AVX2-NEXT: vmovq %rax, %xmm3
+; AVX2-NEXT: vextractf128 $1, %ymm2, %xmm4
+; AVX2-NEXT: vpextrq $1, %xmm4, %rcx
+; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm5
+; AVX2-NEXT: vpextrq $1, %xmm5, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %r9
-; AVX2-NEXT: movq %rax, %r9
-; AVX2-NEXT: vmovq %xmm0, %r10
-; AVX2-NEXT: vmovq %xmm3, %rax
+; AVX2-NEXT: divq %rcx
+; AVX2-NEXT: movq %rax, %rcx
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm6[0]
+; AVX2-NEXT: vmovq %xmm4, %rsi
+; AVX2-NEXT: vmovq %xmm5, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %r10
-; AVX2-NEXT: movq %rax, %r10
-; AVX2-NEXT: vpextrq $1, %xmm2, %r11
+; AVX2-NEXT: divq %rsi
+; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0
+; AVX2-NEXT: vmovq %rcx, %xmm3
+; AVX2-NEXT: vpextrq $1, %xmm2, %rcx
+; AVX2-NEXT: vmovq %rax, %xmm4
; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %r11
-; AVX2-NEXT: movq %rax, %r11
-; AVX2-NEXT: vmovq %rcx, %xmm0
-; AVX2-NEXT: vmovq %rsi, %xmm3
-; AVX2-NEXT: vmovq %rdi, %xmm4
-; AVX2-NEXT: vmovq %r8, %xmm5
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm5[0],xmm4[0]
-; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0
-; AVX2-NEXT: vmovq %r9, %xmm3
-; AVX2-NEXT: vmovq %r10, %xmm4
+; AVX2-NEXT: divq %rcx
+; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
-; AVX2-NEXT: vmovq %xmm2, %rcx
+; AVX2-NEXT: vmovq %xmm2, %rsi
; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %rcx
-; AVX2-NEXT: vmovq %r11, %xmm1
+; AVX2-NEXT: divq %rsi
+; AVX2-NEXT: vmovq %rcx, %xmm1
; AVX2-NEXT: vmovq %rax, %xmm2
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1
diff --git a/llvm/test/CodeGen/X86/min-legal-vector-width.ll b/llvm/test/CodeGen/X86/min-legal-vector-width.ll
index b4f5a50ba1b46ac..5d80435618dd549 100644
--- a/llvm/test/CodeGen/X86/min-legal-vector-width.ll
+++ b/llvm/test/CodeGen/X86/min-legal-vector-width.ll
@@ -2072,54 +2072,54 @@ define <8 x i64> @udiv_v8i64_prefer256(<8 x i64> %x, <8 x i64> %y) nounwind "min
; CHECK-NEXT: vpextrq $1, %xmm5, %rcx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divq %rcx
-; CHECK-NEXT: movq %rax, %rcx
+; CHECK-NEXT: movq %rax, %rdi
; CHECK-NEXT: vmovq %xmm4, %rax
-; CHECK-NEXT: vmovq %xmm5, %rsi
+; CHECK-NEXT: vmovq %xmm5, %rcx
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divq %rsi
-; CHECK-NEXT: movq %rax, %rsi
+; CHECK-NEXT: divq %rcx
+; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: vpextrq $1, %xmm0, %rax
-; CHECK-NEXT: vpextrq $1, %xmm2, %rdi
+; CHECK-NEXT: vpextrq $1, %xmm2, %rsi
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divq %rdi
-; CHECK-NEXT: movq %rax, %rdi
+; CHECK-NEXT: divq %rsi
+; CHECK-NEXT: movq %rax, %rsi
; CHECK-NEXT: vmovq %xmm0, %rax
; CHECK-NEXT: vmovq %xmm2, %r8
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divq %r8
; CHECK-NEXT: movq %rax, %r8
-; CHECK-NEXT: vextracti128 $1, %ymm1, %xmm0
-; CHECK-NEXT: vpextrq $1, %xmm0, %rax
-; CHECK-NEXT: vextracti128 $1, %ymm3, %xmm2
-; CHECK-NEXT: vpextrq $1, %xmm2, %r9
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divq %r9
-; CHECK-NEXT: movq %rax, %r9
-; CHECK-NEXT: vmovq %xmm0, %rax
-; CHECK-NEXT: vmovq %xmm2, %r10
+; CHECK-NEXT: vmovq %rdi, %xmm0
+; CHECK-NEXT: vextracti128 $1, %ymm1, %xmm2
+; CHECK-NEXT: vpextrq $1, %xmm2, %rax
+; CHECK-NEXT: vextracti128 $1, %ymm3, %xmm4
+; CHECK-NEXT: vpextrq $1, %xmm4, %rdi
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divq %r10
-; CHECK-NEXT: movq %rax, %r10
-; CHECK-NEXT: vpextrq $1, %xmm1, %rax
-; CHECK-NEXT: vpextrq $1, %xmm3, %r11
+; CHECK-NEXT: divq %rdi
+; CHECK-NEXT: movq %rax, %rdi
+; CHECK-NEXT: vmovq %rcx, %xmm5
+; CHECK-NEXT: vmovq %xmm2, %rax
+; CHECK-NEXT: vmovq %xmm4, %rcx
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divq %r11
-; CHECK-NEXT: movq %rax, %r11
-; CHECK-NEXT: vmovq %rcx, %xmm0
+; CHECK-NEXT: divq %rcx
+; CHECK-NEXT: movq %rax, %rcx
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm5[0],xmm0[0]
; CHECK-NEXT: vmovq %rsi, %xmm2
-; CHECK-NEXT: vmovq %rdi, %xmm4
-; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
-; CHECK-NEXT: vmovq %r8, %xmm2
-; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
+; CHECK-NEXT: vmovq %r8, %xmm4
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm4[0],xmm2[0]
+; CHECK-NEXT: vpextrq $1, %xmm1, %rax
; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm2, %ymm0
-; CHECK-NEXT: vmovq %r9, %xmm2
+; CHECK-NEXT: vpextrq $1, %xmm3, %rsi
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: divq %rsi
+; CHECK-NEXT: movq %rax, %rsi
+; CHECK-NEXT: vmovq %rdi, %xmm2
; CHECK-NEXT: vmovq %xmm1, %rax
-; CHECK-NEXT: vmovq %xmm3, %rcx
+; CHECK-NEXT: vmovq %xmm3, %rdi
; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divq %rcx
-; CHECK-NEXT: vmovq %r10, %xmm1
+; CHECK-NEXT: divq %rdi
+; CHECK-NEXT: vmovq %rcx, %xmm1
; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; CHECK-NEXT: vmovq %r11, %xmm2
+; CHECK-NEXT: vmovq %rsi, %xmm2
; CHECK-NEXT: vmovq %rax, %xmm3
; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
diff --git a/llvm/test/CodeGen/X86/rematerialize-sub-super-reg-dead-flags.mir b/llvm/test/CodeGen/X86/rematerialize-sub-super-reg-dead-flags.mir
new file mode 100644
index 000000000000000..4957e1231296901
--- /dev/null
+++ b/llvm/test/CodeGen/X86/rematerialize-sub-super-reg-dead-flags.mir
@@ -0,0 +1,84 @@
+# RUN: llc -mtriple=x86_64-- -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s
+
+# Checks are anchored with {{^}}, since an unanchored check also matches a line
+# with a spurious "dead".
+
+# Def and copy destination cover the same units.
+---
+name: remat_def_units_equal_copy_dst
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: remat_def_units_equal_copy_dst
+ ; CHECK: {{^}} $rax = MOV64ri32 -11, implicit-def $eax{{$}}
+ bb.0:
+ %t1:gr64 = MOV64ri32 -11
+ CMP64ri8 %t1, 1, implicit-def $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
+ JMP_1 %bb.1
+
+ bb.1:
+ %t2:gr64 = COPY %t1
+ $eax = COPY %t2.sub_32bit
+ CMP64ri8 %t2, 1, implicit-def $eflags
+ JCC_1 %bb.1, 4, implicit killed $eflags
+ RET 0, $eax
+
+ bb.2:
+ %t3:gr64 = COPY %t1
+ %t3:gr64 = ADD64ri8 %t3, 10, implicit-def $eflags
+
+ bb.3:
+ $rax = COPY %t3
+ RET 0, $rax
+
+...
+
+# Def covers fewer units than the copy destination.
+---
+name: remat_def_units_subset_of_copy_dst
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: remat_def_units_subset_of_copy_dst
+ ; CHECK: {{^}} $al = MOV8ri 11, implicit-def $rax{{$}}
+ bb.0:
+ undef %t1.sub_8bit:gr64_with_sub_8bit = MOV8ri 11
+ CMP64ri8 %t1, 1, implicit-def $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
+ JMP_1 %bb.1
+
+ bb.1:
+ %t2:gr64_with_sub_8bit = COPY %t1
+ $rax = COPY %t2
+ CMP64ri8 %t2, 1, implicit-def $eflags
+ JCC_1 %bb.1, 4, implicit killed $eflags
+ RET 0, $rax
+
+ bb.2:
+ %t3:gr64_with_sub_8bit = COPY %t1
+ %t3:gr64_with_sub_8bit = ADD64ri8 %t3, 10, implicit-def $eflags
+
+ bb.3:
+ $rax = COPY %t3
+ RET 0, $rax
+
+...
+
+# Def covers units the copy destination does not, and nothing uses them.
+---
+name: remat_def_units_superset_of_copy_dst
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: remat_def_units_superset_of_copy_dst
+ ; CHECK: {{^}} $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi{{$}}
+ ; CHECK-NEXT: {{^}} $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx{{$}}
+ ; CHECK: {{^}} dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def dead $rax, implicit-def $al{{$}}
+ bb.0:
+ undef %0.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def %0
+ $rsi = COPY %0
+ $rdx = COPY %0
+ CALL64pcrel32 &use64, csr_64, implicit $rsp, implicit $ssp, implicit $rsi, implicit $rdx, implicit-def $rsp, implicit-def $ssp
+ %1:gr8 = COPY killed %0.sub_8bit
+ $al = COPY killed %1
+ CALL64pcrel32 &use8, csr_64, implicit $rsp, implicit $ssp, implicit $al, implicit-def $rsp, implicit-def $ssp
+ RET 0
+...
diff --git a/llvm/test/CodeGen/X86/rematerialize-sub-super-reg.mir b/llvm/test/CodeGen/X86/rematerialize-sub-super-reg.mir
index 44a2aecdc367228..e03440e78fe00d0 100644
--- a/llvm/test/CodeGen/X86/rematerialize-sub-super-reg.mir
+++ b/llvm/test/CodeGen/X86/rematerialize-sub-super-reg.mir
@@ -24,7 +24,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead $rax = MOV64ri32 -11, implicit-def $eax
+ ; CHECK-NEXT: $rax = MOV64ri32 -11, implicit-def $eax
; CHECK-NEXT: CMP64ri8 %t3, 1, implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.1, 4, implicit killed $eflags
; CHECK-NEXT: RET 0, $eax
@@ -60,6 +60,61 @@ body: |
...
+# Test an undef subregister def of %t1 rematerializing into a physical
+# super register def, where the def covers strictly fewer register units
+# than the copy destination.
+---
+name: rematerialize_narrow_subregister_into_superreg_def
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: rematerialize_narrow_subregister_into_superreg_def
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: undef %t3.sub_8bit:gr64_with_sub_8bit = MOV8ri 11
+ ; CHECK-NEXT: CMP64ri8 %t3, 1, implicit-def $eflags
+ ; CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
+ ; CHECK-NEXT: JMP_1 %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $al = MOV8ri 11, implicit-def $rax
+ ; CHECK-NEXT: CMP64ri8 %t3, 1, implicit-def $eflags
+ ; CHECK-NEXT: JCC_1 %bb.1, 4, implicit killed $eflags
+ ; CHECK-NEXT: RET 0, $rax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %t3:gr64_with_sub_8bit = ADD64ri8 %t3, 10, implicit-def $eflags
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: $rax = COPY %t3
+ ; CHECK-NEXT: RET 0, $rax
+ bb.0:
+ undef %t1.sub_8bit:gr64_with_sub_8bit = MOV8ri 11
+ CMP64ri8 %t1, 1, implicit-def $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
+ JMP_1 %bb.1
+
+ bb.1:
+ %t2:gr64_with_sub_8bit = COPY %t1
+ $rax = COPY %t2
+ CMP64ri8 %t2, 1, implicit-def $eflags
+ JCC_1 %bb.1, 4, implicit killed $eflags
+ RET 0, $rax
+
+ bb.2:
+ %t3:gr64_with_sub_8bit = COPY %t1
+ %t3:gr64_with_sub_8bit = ADD64ri8 %t3, 10, implicit-def $eflags
+
+ bb.3:
+ $rax = COPY %t3
+ RET 0, $rax
+
+...
+
# Test an undef subregister def of %t1 rematerializing into a physical
# super register def
---
@@ -78,7 +133,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead $eax = MOV32ri -11, implicit-def $rax
+ ; CHECK-NEXT: $eax = MOV32ri -11, implicit-def $rax
; CHECK-NEXT: CMP64ri8 %t3, 1, implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.1, 4, implicit killed $eflags
; CHECK-NEXT: RET 0, $rax
@@ -132,7 +187,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead $eax = MOV32ri -11, implicit-def $rax
+ ; CHECK-NEXT: $eax = MOV32ri -11, implicit-def $rax
; CHECK-NEXT: CMP64ri8 %t3, 1, implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.1, 4, implicit killed $eflags
; CHECK-NEXT: RET 0, $rax
@@ -171,8 +226,8 @@ name: rematerialize_superregister_into_subregister_def_with_impdef_physreg
body: |
bb.0.entry:
; CHECK-LABEL: name: rematerialize_superregister_into_subregister_def_with_impdef_physreg
- ; CHECK: dead $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
- ; CHECK-NEXT: dead $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
+ ; CHECK: $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
+ ; CHECK-NEXT: $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
; CHECK-NEXT: FAKE_USE implicit killed $rsi, implicit killed $rdx
; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def dead $rax, implicit-def $al
; CHECK-NEXT: FAKE_USE implicit killed $al
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
index 8d38d687edaad74..61642a5e7498345 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
@@ -206,7 +206,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
- ; CHECK-NEXT: dead $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
+ ; CHECK-NEXT: $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
; CHECK-NEXT: STATEPOINT 2, 5, 2, undef %24:gr64, $rdi, undef $rsi, 2, 0, 2, 0, 2, 37, 2, 0, 2, 2, 2, 0, 2, 43, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 10, 2, 1, 2, 6, 2, 0, 2, 4, 2, 1, 2, 0, 2, 0, 2, 7, 2, 0, 2, 0, 2, 0, 2, 7, 2, 0, 2, 0, 2, 0, 2, 2, 2, 4, 2, 5, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 1, 2, 0, 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
index 05c7ceb914c9327..ba8df968e2b8dbc 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
@@ -324,7 +324,7 @@ body: |
; CHECK-NEXT: EH_LABEL <mcsymbol .Ltmp0>
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %stack.1)
- ; CHECK-NEXT: dead $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
+ ; CHECK-NEXT: $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
; CHECK-NEXT: $ecx = MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: dead [[MOV64rm1:%[0-9]+]]:gr64, dead [[DEF2:%[0-9]+]]:gr64_with_sub_8bit, dead [[DEF1:%[0-9]+]]:gr64, dead [[DEF:%[0-9]+]]:gr64 = STATEPOINT 1, 16, 5, undef %41:gr64, undef $edi, undef $rsi, $rdx, $ecx, undef $r8d, 2, 0, 2, 0, 2, 89, 2, 0, 2, 10, 2, 0, 2, 10, 2, 0, 2, 4, 2, 1, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, [[DEF2]], 2, 7, 2, 0, 2, 0, [[DEF2]], 2, 10, 2, 2, 2, 12, 2, 0, 2, 3, 2, 1, 2, 0, [[DEF2]], 2, 0, [[DEF2]], 2, 7, 2, 0, 2, 0, [[DEF2]], 2, 2, 2, 8, 2, 4, 2, 0, 2, 1, 2, 0, 2, 7, 2, 0, 2, 2, 2, 12, 2, 7, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 10, 2, 18, 2, 96, 2, 0, 2, 9, 2, 1, 2, 0, [[DEF1]], 2, 0, 2, 4278124286, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, [[DEF]], 2, 3, 1, 4, %stack.0, 0, 2, 3, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, [[DEF]], 2, 8, 2, 9, 2, 34, 2, 0, 2, 3, 2, 1, 2, 0, [[DEF1]], 2, 0, 2, 4278124286, 2, 7, 2, 0, 2, 0, 2, 4278124286, 2, 5, [[MOV64rm1]](tied-def 0), [[DEF2]](tied-def 1), [[DEF1]](tied-def 2), 2, 4278124286, [[DEF]](tied-def 3), 2, 0, 2, 5, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store (s32) on %stack.0)
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
@@ -518,7 +518,7 @@ body: |
EH_LABEL <mcsymbol .Ltmp0>
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
%32:gr64 = COPY %0
- dead $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
+ $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
$ecx = MOV32r0 implicit-def dead $eflags
dead %32:gr64, dead %3:gr64_with_sub_8bit, dead %2:gr64, dead %1:gr64 = STATEPOINT 1, 16, 5, undef %41:gr64, undef $edi, undef $rsi, $rdx, $ecx, undef $r8d, 2, 0, 2, 0, 2, 89, 2, 0, 2, 10, 2, 0, 2, 10, 2, 0, 2, 4, 2, 1, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, %3, 2, 7, 2, 0, 2, 0, %3, 2, 10, 2, 2, 2, 12, 2, 0, 2, 3, 2, 1, 2, 0, %3, 2, 0, %3, 2, 7, 2, 0, 2, 0, %3, 2, 2, 2, 8, 2, 4, 2, 0, 2, 1, 2, 0, 2, 7, 2, 0, 2, 2, 2, 12, 2, 7, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 10, 2, 18, 2, 96, 2, 0, 2, 9, 2, 1, 2, 0, %2, 2, 0, 2, 4278124286, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, %1, 2, 3, 1, 4, %stack.0, 0, 2, 3, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, %1, 2, 8, 2, 9, 2, 34, 2, 0, 2, 3, 2, 1, 2, 0, %2, 2, 0, 2, 4278124286, 2, 7, 2, 0, 2, 0, 2, 4278124286, 2, 5, %32(tied-def 0), %3(tied-def 1), %2(tied-def 2), 2, 4278124286, %1(tied-def 3), 2, 0, 2, 5, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store (s32) on %stack.0)
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
index 01e5966e8d6a373..aa1548bbd67ce76 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
@@ -31,7 +31,7 @@
# CHECK: EH_LABEL <mcsymbol .Ltmp0>
# CHECK: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
# CHECK: $edi = MOV32r0 implicit-def dead $eflags
-# CHECK: dead $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
+# CHECK: $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
# CHECK: $ecx = COPY %7
# CHECK: $r8d = MOV32r0 implicit-def dead $eflags
# CHECK: %37:gr64 = lr-split COPY %38
diff --git a/llvm/test/CodeGen/X86/statepoint-ra.ll b/llvm/test/CodeGen/X86/statepoint-ra.ll
index 5a4e04dd70553a6..8a3a9f2c4edbf38 100644
--- a/llvm/test/CodeGen/X86/statepoint-ra.ll
+++ b/llvm/test/CodeGen/X86/statepoint-ra.ll
@@ -100,7 +100,7 @@ declare token @llvm.experimental.gc.statepoint.p0(i64 , i32 , ptr, i32 , i32 , .
;CHECK: successors: %bb.3(0x80000000)
;CHECK: ADJCALLSTACKDOWN64 8, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
;CHECK: MOVSDmr $rsp, 1, $noreg, 0, $noreg, %14 :: (store (s64) into stack)
-;CHECK: dead $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
+;CHECK: $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
;CHECK: $xmm0 = COPY %68
;CHECK: $xmm1 = COPY %64
;CHECK: $xmm2 = COPY %6
diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-details.ll b/llvm/test/CodeGen/X86/statepoint-vreg-details.ll
index a7114b3d10434e1..7f2836b8c1340ed 100644
--- a/llvm/test/CodeGen/X86/statepoint-vreg-details.ll
+++ b/llvm/test/CodeGen/X86/statepoint-vreg-details.ll
@@ -64,9 +64,9 @@ define void @test_mixed(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(
; CHECK-PREG: renamable $r15 = COPY $rdi
; CHECK-PREG: renamable $rbx, renamable $r14, renamable $r15 = STATEPOINT 0, 0, 0, @func, 2, 0, 2, 0, 2, 0, 2, 4, killed renamable $rbx(tied-def 0), 2, 0, killed renamable $r14(tied-def 1), killed renamable $r15(tied-def 2), 2, 0, 2, 4, 0, 0, 1, 1, 2, 2, 3, 3, csr_64, implicit-def $rsp, implicit-def $ssp
; CHECK-PREG: $rdi = COPY killed renamable $r15
-; CHECK-PREG: dead $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
+; CHECK-PREG: $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
; CHECK-PREG: $rdx = COPY killed renamable $r14
-; CHECK-PREG: dead $ecx = MOV32r0 implicit-def dead $eflags, implicit-def $rcx
+; CHECK-PREG: $ecx = MOV32r0 implicit-def dead $eflags, implicit-def $rcx
; CHECK-PREG: $r8 = COPY killed renamable $rbx
; CHECK-PREG: CALL64pcrel32 @consume5, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit $r8, implicit-def $rsp, implicit-def $ssp
diff --git a/llvm/test/CodeGen/X86/udiv_fix.ll b/llvm/test/CodeGen/X86/udiv_fix.ll
index 8c3698c535b005d..b2ad846b1be7ecc 100644
--- a/llvm/test/CodeGen/X86/udiv_fix.ll
+++ b/llvm/test/CodeGen/X86/udiv_fix.ll
@@ -230,33 +230,31 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-LABEL: vec:
; X64: # %bb.0:
; X64-NEXT: pxor %xmm2, %xmm2
-; X64-NEXT: movdqa %xmm0, %xmm3
+; X64-NEXT: movdqa %xmm0, %xmm4
+; X64-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm2[2],xmm4[3],xmm2[3]
+; X64-NEXT: psllq $31, %xmm4
+; X64-NEXT: movq %xmm4, %rax
+; X64-NEXT: movdqa %xmm1, %xmm3
; X64-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm2[2],xmm3[3],xmm2[3]
-; X64-NEXT: psllq $31, %xmm3
-; X64-NEXT: movq %xmm3, %rax
+; X64-NEXT: movd %xmm3, %ecx
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: divq %rcx
+; X64-NEXT: movq %rax, %xmm3
+; X64-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,3,2,3]
+; X64-NEXT: movq %xmm4, %rax
; X64-NEXT: movdqa %xmm1, %xmm4
-; X64-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm2[2],xmm4[3],xmm2[3]
+; X64-NEXT: psrldq {{.*#+}} xmm4 = xmm4[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; X64-NEXT: movd %xmm4, %ecx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx
-; X64-NEXT: movq %rax, %rcx
-; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
-; X64-NEXT: movq %xmm3, %rax
-; X64-NEXT: movdqa %xmm1, %xmm3
-; X64-NEXT: psrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; X64-NEXT: movd %xmm3, %esi
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divq %rsi
-; X64-NEXT: movq %rax, %rsi
+; X64-NEXT: movq %rax, %xmm4
+; X64-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; X64-NEXT: psllq $31, %xmm0
; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: movd %xmm1, %edi
+; X64-NEXT: movd %xmm1, %ecx
; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divq %rdi
-; X64-NEXT: movq %rcx, %xmm3
-; X64-NEXT: movq %rsi, %xmm2
-; X64-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
+; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm2
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X64-NEXT: movq %xmm0, %rax
diff --git a/llvm/test/CodeGen/X86/udiv_fix_sat.ll b/llvm/test/CodeGen/X86/udiv_fix_sat.ll
index 659ab7e69e9aebe..565918e5b159b17 100644
--- a/llvm/test/CodeGen/X86/udiv_fix_sat.ll
+++ b/llvm/test/CodeGen/X86/udiv_fix_sat.ll
@@ -302,61 +302,59 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-NEXT: movd %xmm4, %ecx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx
-; X64-NEXT: movq %rax, %rcx
+; X64-NEXT: movq %rax, %xmm8
; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
; X64-NEXT: movq %xmm3, %rax
; X64-NEXT: movdqa %xmm1, %xmm3
; X64-NEXT: psrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; X64-NEXT: movd %xmm3, %esi
+; X64-NEXT: movd %xmm3, %ecx
; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divq %rsi
-; X64-NEXT: movq %rax, %rsi
-; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
-; X64-NEXT: movq %xmm2, %rax
-; X64-NEXT: movd %xmm1, %edi
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: divq %rdi
-; X64-NEXT: movq %rcx, %xmm7
-; X64-NEXT: movq %rsi, %xmm0
-; X64-NEXT: punpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm0[0]
-; X64-NEXT: movdqa {{.*#+}} xmm0 = [9223372039002259456,9223372039002259456]
-; X64-NEXT: movdqa %xmm7, %xmm3
-; X64-NEXT: pxor %xmm0, %xmm3
-; X64-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
-; X64-NEXT: movdqa {{.*#+}} xmm6 = [2147483649,2147483649,2147483649,2147483649]
-; X64-NEXT: pcmpeqd %xmm6, %xmm4
-; X64-NEXT: movdqa {{.*#+}} xmm5 = [9223372043297226751,9223372043297226751]
-; X64-NEXT: movdqa %xmm5, %xmm8
-; X64-NEXT: pcmpgtd %xmm3, %xmm8
-; X64-NEXT: pshufd {{.*#+}} xmm9 = xmm8[0,0,2,2]
-; X64-NEXT: pand %xmm4, %xmm9
-; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm8[1,1,3,3]
-; X64-NEXT: por %xmm9, %xmm3
-; X64-NEXT: pcmpeqd %xmm4, %xmm4
-; X64-NEXT: pand %xmm3, %xmm7
+; X64-NEXT: divq %rcx
+; X64-NEXT: movq %rax, %xmm3
+; X64-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm3[0]
+; X64-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456]
+; X64-NEXT: movdqa %xmm8, %xmm3
; X64-NEXT: pxor %xmm4, %xmm3
-; X64-NEXT: por %xmm7, %xmm3
+; X64-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,1,3,3]
+; X64-NEXT: movdqa {{.*#+}} xmm7 = [2147483649,2147483649,2147483649,2147483649]
+; X64-NEXT: pcmpeqd %xmm7, %xmm6
+; X64-NEXT: movdqa {{.*#+}} xmm5 = [9223372043297226751,9223372043297226751]
+; X64-NEXT: movdqa %xmm5, %xmm9
+; X64-NEXT: pcmpgtd %xmm3, %xmm9
+; X64-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
+; X64-NEXT: pand %xmm6, %xmm10
+; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm9[1,1,3,3]
+; X64-NEXT: por %xmm10, %xmm3
+; X64-NEXT: pcmpeqd %xmm6, %xmm6
+; X64-NEXT: pand %xmm3, %xmm8
+; X64-NEXT: pxor %xmm6, %xmm3
+; X64-NEXT: por %xmm8, %xmm3
; X64-NEXT: psrlq $1, %xmm3
-; X64-NEXT: movq %rax, %xmm7
-; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
+; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; X64-NEXT: movq %xmm2, %rax
+; X64-NEXT: movd %xmm1, %ecx
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: divq %rcx
+; X64-NEXT: movq %rax, %xmm8
+; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
+; X64-NEXT: movq %xmm0, %rax
; X64-NEXT: psrlq $32, %xmm1
; X64-NEXT: movd %xmm1, %ecx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx
-; X64-NEXT: movq %rax, %xmm1
-; X64-NEXT: punpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm1[0]
-; X64-NEXT: pxor %xmm7, %xmm0
-; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; X64-NEXT: pcmpeqd %xmm6, %xmm1
-; X64-NEXT: pcmpgtd %xmm0, %xmm5
-; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm5[0,0,2,2]
-; X64-NEXT: pand %xmm1, %xmm2
+; X64-NEXT: movq %rax, %xmm0
+; X64-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm0[0]
+; X64-NEXT: pxor %xmm8, %xmm4
+; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
+; X64-NEXT: pcmpeqd %xmm7, %xmm0
+; X64-NEXT: pcmpgtd %xmm4, %xmm5
+; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2]
+; X64-NEXT: pand %xmm0, %xmm1
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]
-; X64-NEXT: por %xmm2, %xmm0
-; X64-NEXT: pxor %xmm0, %xmm4
-; X64-NEXT: pand %xmm7, %xmm0
-; X64-NEXT: por %xmm4, %xmm0
+; X64-NEXT: por %xmm1, %xmm0
+; X64-NEXT: pxor %xmm0, %xmm6
+; X64-NEXT: pand %xmm8, %xmm0
+; X64-NEXT: por %xmm6, %xmm0
; X64-NEXT: psrlq $1, %xmm0
; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-idiv-strictfp.ll b/llvm/test/CodeGen/X86/vector-idiv-strictfp.ll
index 7e4fbaec1019e92..972e759d1763c0e 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-strictfp.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-strictfp.ll
@@ -293,50 +293,44 @@ define <8 x i64> @test_divv_8i64_strictfp(<8 x i64> %a, <8 x i64> %b) nounwind s
; NODQ-NEXT: vpextrq $1, %xmm3, %rcx
; NODQ-NEXT: xorl %edx, %edx
; NODQ-NEXT: divq %rcx
-; NODQ-NEXT: movq %rax, %rcx
+; NODQ-NEXT: vmovq %rax, %xmm4
; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %rsi
+; NODQ-NEXT: vmovq %xmm3, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %rsi
-; NODQ-NEXT: movq %rax, %rsi
-; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; NODQ-NEXT: vpextrq $1, %xmm2, %rax
-; NODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm3
-; NODQ-NEXT: vpextrq $1, %xmm3, %rdi
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm2
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
+; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm3
+; NODQ-NEXT: vpextrq $1, %xmm3, %rax
+; NODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm4
+; NODQ-NEXT: vpextrq $1, %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %rdi
-; NODQ-NEXT: movq %rax, %rdi
-; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %r8
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm5
+; NODQ-NEXT: vmovq %xmm3, %rax
+; NODQ-NEXT: vmovq %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r8
-; NODQ-NEXT: movq %rax, %r8
-; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm2
-; NODQ-NEXT: vpextrq $1, %xmm2, %rax
-; NODQ-NEXT: vextracti128 $1, %ymm1, %xmm3
-; NODQ-NEXT: vpextrq $1, %xmm3, %r9
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm3
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0]
+; NODQ-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2
+; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm3
+; NODQ-NEXT: vpextrq $1, %xmm3, %rax
+; NODQ-NEXT: vextracti128 $1, %ymm1, %xmm4
+; NODQ-NEXT: vpextrq $1, %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r9
-; NODQ-NEXT: movq %rax, %r9
-; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %r10
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm5
+; NODQ-NEXT: vmovq %xmm3, %rax
+; NODQ-NEXT: vmovq %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r10
-; NODQ-NEXT: movq %rax, %r10
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm3
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax
-; NODQ-NEXT: vpextrq $1, %xmm1, %r11
+; NODQ-NEXT: vpextrq $1, %xmm1, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r11
-; NODQ-NEXT: vmovq %rcx, %xmm2
-; NODQ-NEXT: vmovq %rsi, %xmm3
-; NODQ-NEXT: vmovq %rdi, %xmm4
-; NODQ-NEXT: vmovq %r8, %xmm5
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; NODQ-NEXT: vmovq %r9, %xmm3
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
-; NODQ-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2
-; NODQ-NEXT: vmovq %r10, %xmm4
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; NODQ-NEXT: divq %rcx
; NODQ-NEXT: vmovq %rax, %xmm4
; NODQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vmovq %xmm1, %rcx
@@ -382,50 +376,44 @@ define <8 x i64> @test_divv_8i64_narrow_strictfp(<8 x i64> %a, <8 x i64> %b) nou
; NODQ-NEXT: vpextrq $1, %xmm3, %rcx
; NODQ-NEXT: xorl %edx, %edx
; NODQ-NEXT: divq %rcx
-; NODQ-NEXT: movq %rax, %rcx
+; NODQ-NEXT: vmovq %rax, %xmm4
; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %rsi
+; NODQ-NEXT: vmovq %xmm3, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %rsi
-; NODQ-NEXT: movq %rax, %rsi
-; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; NODQ-NEXT: vpextrq $1, %xmm2, %rax
-; NODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm3
-; NODQ-NEXT: vpextrq $1, %xmm3, %rdi
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm2
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
+; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm3
+; NODQ-NEXT: vpextrq $1, %xmm3, %rax
+; NODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm4
+; NODQ-NEXT: vpextrq $1, %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %rdi
-; NODQ-NEXT: movq %rax, %rdi
-; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %r8
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm5
+; NODQ-NEXT: vmovq %xmm3, %rax
+; NODQ-NEXT: vmovq %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r8
-; NODQ-NEXT: movq %rax, %r8
-; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm2
-; NODQ-NEXT: vpextrq $1, %xmm2, %rax
-; NODQ-NEXT: vextracti128 $1, %ymm1, %xmm3
-; NODQ-NEXT: vpextrq $1, %xmm3, %r9
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm3
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0]
+; NODQ-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2
+; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm3
+; NODQ-NEXT: vpextrq $1, %xmm3, %rax
+; NODQ-NEXT: vextracti128 $1, %ymm1, %xmm4
+; NODQ-NEXT: vpextrq $1, %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r9
-; NODQ-NEXT: movq %rax, %r9
-; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %r10
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm5
+; NODQ-NEXT: vmovq %xmm3, %rax
+; NODQ-NEXT: vmovq %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r10
-; NODQ-NEXT: movq %rax, %r10
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm3
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax
-; NODQ-NEXT: vpextrq $1, %xmm1, %r11
+; NODQ-NEXT: vpextrq $1, %xmm1, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r11
-; NODQ-NEXT: vmovq %rcx, %xmm2
-; NODQ-NEXT: vmovq %rsi, %xmm3
-; NODQ-NEXT: vmovq %rdi, %xmm4
-; NODQ-NEXT: vmovq %r8, %xmm5
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; NODQ-NEXT: vmovq %r9, %xmm3
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
-; NODQ-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2
-; NODQ-NEXT: vmovq %r10, %xmm4
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; NODQ-NEXT: divq %rcx
; NODQ-NEXT: vmovq %rax, %xmm4
; NODQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vmovq %xmm1, %rcx
@@ -461,44 +449,39 @@ define void @test_divv_7i64_narrow_strictfp(<7 x i64> %a, <7 x i64> %b, ptr %p)
; NODQ-NEXT: vpextrq $1, %xmm0, %rcx
; NODQ-NEXT: xorl %edx, %edx
; NODQ-NEXT: divq %rcx
-; NODQ-NEXT: movq %rax, %rcx
+; NODQ-NEXT: vmovq %rax, %xmm1
; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm0, %rsi
+; NODQ-NEXT: vmovq %xmm0, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %rsi
-; NODQ-NEXT: movq %rax, %rsi
-; NODQ-NEXT: vextracti128 $1, %ymm2, %xmm1
-; NODQ-NEXT: vpextrq $1, %xmm1, %rax
-; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm3
-; NODQ-NEXT: vpextrq $1, %xmm3, %r8
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm3
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm1[0]
+; NODQ-NEXT: vextracti128 $1, %ymm2, %xmm3
+; NODQ-NEXT: vpextrq $1, %xmm3, %rax
+; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm4
+; NODQ-NEXT: vpextrq $1, %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r8
-; NODQ-NEXT: movq %rax, %r8
-; NODQ-NEXT: vmovq %xmm1, %rax
-; NODQ-NEXT: vmovq %xmm3, %r9
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm5
+; NODQ-NEXT: vmovq %xmm3, %rax
+; NODQ-NEXT: vmovq %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r9
-; NODQ-NEXT: movq %rax, %r9
-; NODQ-NEXT: vextracti32x4 $2, %zmm2, %xmm1
-; NODQ-NEXT: vpextrq $1, %xmm1, %rax
-; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm3
-; NODQ-NEXT: vpextrq $1, %xmm3, %r10
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm3
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0]
+; NODQ-NEXT: vextracti32x4 $2, %zmm2, %xmm4
+; NODQ-NEXT: vpextrq $1, %xmm4, %rax
+; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm5
+; NODQ-NEXT: vpextrq $1, %xmm5, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r10
-; NODQ-NEXT: movq %rax, %r10
-; NODQ-NEXT: vmovq %xmm1, %rax
-; NODQ-NEXT: vmovq %xmm3, %r11
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm6
+; NODQ-NEXT: vmovq %xmm4, %rax
+; NODQ-NEXT: vmovq %xmm5, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r11
-; NODQ-NEXT: vmovq %rcx, %xmm1
-; NODQ-NEXT: vmovq %rsi, %xmm3
-; NODQ-NEXT: vmovq %r8, %xmm4
-; NODQ-NEXT: vmovq %r9, %xmm5
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm1[0]
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm5[0],xmm4[0]
-; NODQ-NEXT: vmovq %r10, %xmm4
-; NODQ-NEXT: vmovq %rax, %xmm5
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm4
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm6[0]
; NODQ-NEXT: vextracti32x4 $3, %zmm2, %xmm2
; NODQ-NEXT: vmovq %xmm2, %rax
; NODQ-NEXT: vextracti32x4 $3, %zmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
index e3918f0bddf904c..5fde70d7b083eb4 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
@@ -253,50 +253,44 @@ define <8 x i64> @test_divv_8i64(<8 x i64> %a, <8 x i64> %b) nounwind {
; NODQ-NEXT: vpextrq $1, %xmm3, %rcx
; NODQ-NEXT: xorl %edx, %edx
; NODQ-NEXT: divq %rcx
-; NODQ-NEXT: movq %rax, %rcx
+; NODQ-NEXT: vmovq %rax, %xmm4
; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %rsi
+; NODQ-NEXT: vmovq %xmm3, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %rsi
-; NODQ-NEXT: movq %rax, %rsi
-; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; NODQ-NEXT: vpextrq $1, %xmm2, %rax
-; NODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm3
-; NODQ-NEXT: vpextrq $1, %xmm3, %rdi
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm2
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
+; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm3
+; NODQ-NEXT: vpextrq $1, %xmm3, %rax
+; NODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm4
+; NODQ-NEXT: vpextrq $1, %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %rdi
-; NODQ-NEXT: movq %rax, %rdi
-; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %r8
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm5
+; NODQ-NEXT: vmovq %xmm3, %rax
+; NODQ-NEXT: vmovq %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r8
-; NODQ-NEXT: movq %rax, %r8
-; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm2
-; NODQ-NEXT: vpextrq $1, %xmm2, %rax
-; NODQ-NEXT: vextracti128 $1, %ymm1, %xmm3
-; NODQ-NEXT: vpextrq $1, %xmm3, %r9
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm3
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0]
+; NODQ-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2
+; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm3
+; NODQ-NEXT: vpextrq $1, %xmm3, %rax
+; NODQ-NEXT: vextracti128 $1, %ymm1, %xmm4
+; NODQ-NEXT: vpextrq $1, %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r9
-; NODQ-NEXT: movq %rax, %r9
-; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %r10
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm5
+; NODQ-NEXT: vmovq %xmm3, %rax
+; NODQ-NEXT: vmovq %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r10
-; NODQ-NEXT: movq %rax, %r10
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm3
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax
-; NODQ-NEXT: vpextrq $1, %xmm1, %r11
+; NODQ-NEXT: vpextrq $1, %xmm1, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r11
-; NODQ-NEXT: vmovq %rcx, %xmm2
-; NODQ-NEXT: vmovq %rsi, %xmm3
-; NODQ-NEXT: vmovq %rdi, %xmm4
-; NODQ-NEXT: vmovq %r8, %xmm5
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; NODQ-NEXT: vmovq %r9, %xmm3
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
-; NODQ-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2
-; NODQ-NEXT: vmovq %r10, %xmm4
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; NODQ-NEXT: divq %rcx
; NODQ-NEXT: vmovq %rax, %xmm4
; NODQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vmovq %xmm1, %rcx
@@ -746,50 +740,44 @@ define <8 x i64> @test_divv_8i64_narrow(<8 x i64> %a, <8 x i64> %b) nounwind {
; NODQ-NEXT: vpextrq $1, %xmm3, %rcx
; NODQ-NEXT: xorl %edx, %edx
; NODQ-NEXT: divq %rcx
-; NODQ-NEXT: movq %rax, %rcx
+; NODQ-NEXT: vmovq %rax, %xmm4
; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %rsi
+; NODQ-NEXT: vmovq %xmm3, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %rsi
-; NODQ-NEXT: movq %rax, %rsi
-; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; NODQ-NEXT: vpextrq $1, %xmm2, %rax
-; NODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm3
-; NODQ-NEXT: vpextrq $1, %xmm3, %rdi
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm2
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
+; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm3
+; NODQ-NEXT: vpextrq $1, %xmm3, %rax
+; NODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm4
+; NODQ-NEXT: vpextrq $1, %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %rdi
-; NODQ-NEXT: movq %rax, %rdi
-; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %r8
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm5
+; NODQ-NEXT: vmovq %xmm3, %rax
+; NODQ-NEXT: vmovq %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r8
-; NODQ-NEXT: movq %rax, %r8
-; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm2
-; NODQ-NEXT: vpextrq $1, %xmm2, %rax
-; NODQ-NEXT: vextracti128 $1, %ymm1, %xmm3
-; NODQ-NEXT: vpextrq $1, %xmm3, %r9
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm3
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0]
+; NODQ-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2
+; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm3
+; NODQ-NEXT: vpextrq $1, %xmm3, %rax
+; NODQ-NEXT: vextracti128 $1, %ymm1, %xmm4
+; NODQ-NEXT: vpextrq $1, %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r9
-; NODQ-NEXT: movq %rax, %r9
-; NODQ-NEXT: vmovq %xmm2, %rax
-; NODQ-NEXT: vmovq %xmm3, %r10
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm5
+; NODQ-NEXT: vmovq %xmm3, %rax
+; NODQ-NEXT: vmovq %xmm4, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r10
-; NODQ-NEXT: movq %rax, %r10
+; NODQ-NEXT: divq %rcx
+; NODQ-NEXT: vmovq %rax, %xmm3
+; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax
-; NODQ-NEXT: vpextrq $1, %xmm1, %r11
+; NODQ-NEXT: vpextrq $1, %xmm1, %rcx
; NODQ-NEXT: xorl %edx, %edx
-; NODQ-NEXT: divq %r11
-; NODQ-NEXT: vmovq %rcx, %xmm2
-; NODQ-NEXT: vmovq %rsi, %xmm3
-; NODQ-NEXT: vmovq %rdi, %xmm4
-; NODQ-NEXT: vmovq %r8, %xmm5
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; NODQ-NEXT: vmovq %r9, %xmm3
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
-; NODQ-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2
-; NODQ-NEXT: vmovq %r10, %xmm4
-; NODQ-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; NODQ-NEXT: divq %rcx
; NODQ-NEXT: vmovq %rax, %xmm4
; NODQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vmovq %xmm1, %rcx
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