[llvm] [ARM] Add combine for vector_deinterleave load (PR #225747)

[David Green via llvm-commits]

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@@ -15446,6 +15446,169 @@ static SDValue PerformBUILD_VECTORCombine(SDNode *N,
   return DAG.getNode(ISD::BITCAST, dl, VT, BV);
 }
 
+static SDValue performLegalizedVECTOR_DEINTERLEAVECombine(
+    SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG,
+    const ARMSubtarget *Subtarget) {
+  // Type legalization splits a wide load into consecutive legal loads. Combine
+  // each group used by a legal VECTOR_DEINTERLEAVE into a structured load.
+  if (DCI.getDAGCombineLevel() < AfterLegalizeTypes)
+    return SDValue();
+
+  unsigned NumParts = N->getNumOperands();
+  if (NumParts < 2 || NumParts > 4)
+    return SDValue();
+
+  if (NumParts == 3 && !Subtarget->hasNEON())
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davemgreen wrote:

!Subtarget->hasNEON() -> Subtarget->hasMVE()
It might be worth having a (Subtarget->hasNEON() || Subtarget->hasMVE()) check at the start, even if I understand correctly the LegalType checks handle other types.

https://github.com/llvm/llvm-project/pull/225747