[llvm] [NFC][AMDGPU] Precommit test for byte lane extension after vector split (PR #228423)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 2 05:42:48 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Dmitry Sidorov (MrSidims)
<details>
<summary>Changes</summary>
<sub>Stack created with <a href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
---
Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/228423.diff
1 Files Affected:
- (added) llvm/test/CodeGen/AMDGPU/v4i8-byte-lane-ext.ll (+747)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/v4i8-byte-lane-ext.ll b/llvm/test/CodeGen/AMDGPU/v4i8-byte-lane-ext.ll
new file mode 100644
index 0000000000000..ec76be49050d7
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/v4i8-byte-lane-ext.ll
@@ -0,0 +1,747 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgpu10.30 < %s | FileCheck -check-prefixes=GFX10 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgpu12.50 < %s | FileCheck -check-prefixes=GFX1250 %s
+
+define void @uitofp_v4i8_to_v4f64(ptr addrspace(1) %p, ptr addrspace(1) %o) {
+; GFX9-LABEL: uitofp_v4i8_to_v4f64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: global_load_dword v0, v[0:1], off
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 24, v0
+; GFX9-NEXT: v_and_b32_e32 v4, 0xff, v0
+; GFX9-NEXT: v_lshrrev_b16_e32 v6, 8, v0
+; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX9-NEXT: v_cvt_f64_u32_e32 v[10:11], v1
+; GFX9-NEXT: v_cvt_f64_u32_e32 v[8:9], v0
+; GFX9-NEXT: v_cvt_f64_u32_e32 v[4:5], v4
+; GFX9-NEXT: v_cvt_f64_u32_e32 v[6:7], v6
+; GFX9-NEXT: global_store_dwordx4 v[2:3], v[8:11], off offset:16
+; GFX9-NEXT: global_store_dwordx4 v[2:3], v[4:7], off
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: uitofp_v4i8_to_v4f64:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-NEXT: v_mov_b32_e32 v1, 0xffff
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v6, 24, v0
+; GFX10-NEXT: v_bfe_u32 v7, v0, 16, 8
+; GFX10-NEXT: v_and_b32_e32 v4, 0xff, v0
+; GFX10-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX10-NEXT: v_cvt_f64_u32_e32 v[10:11], v6
+; GFX10-NEXT: v_cvt_f64_u32_e32 v[8:9], v7
+; GFX10-NEXT: v_cvt_f64_u32_e32 v[4:5], v4
+; GFX10-NEXT: v_cvt_f64_u32_e32 v[6:7], v0
+; GFX10-NEXT: global_store_dwordx4 v[2:3], v[8:11], off offset:16
+; GFX10-NEXT: global_store_dwordx4 v[2:3], v[4:7], off
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: uitofp_v4i8_to_v4f64:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v1.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xff, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f64_u32_e32 v[4:5], v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f64_u32_e32 v[10:11], v6
+; GFX11-TRUE16-NEXT: v_cvt_f64_u32_e32 v[8:9], v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f64_u32_e32 v[6:7], v0
+; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16
+; GFX11-TRUE16-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: uitofp_v4i8_to_v4f64:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b16 v1, 8, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 24, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_cvt_f64_u32_e32 v[4:5], v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f64_u32_e32 v[10:11], v6
+; GFX11-FAKE16-NEXT: v_cvt_f64_u32_e32 v[8:9], v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f64_u32_e32 v[6:7], v1
+; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16
+; GFX11-FAKE16-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: uitofp_v4i8_to_v4f64:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: global_load_b32 v1, v[0:1], off
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_lshrrev_b16 v0.l, 8, v1.l
+; GFX1250-NEXT: s_mov_b32 s0, 0xff
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_dual_lshrrev_b32 v6, 24, v1 :: v_dual_bitop2_b32 v4, s0, v1 bitop3:0x40
+; GFX1250-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX1250-NEXT: v_cvt_u32_u16_e32 v0, v0.l
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_cvt_f64_u32_e32 v[4:5], v4
+; GFX1250-NEXT: v_cvt_f64_u32_e32 v[10:11], v6
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_cvt_f64_u32_e32 v[8:9], v1
+; GFX1250-NEXT: v_cvt_f64_u32_e32 v[6:7], v0
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16
+; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ %v = load <4 x i8>, ptr addrspace(1) %p, align 4
+ %c = uitofp <4 x i8> %v to <4 x double>
+ store <4 x double> %c, ptr addrspace(1) %o
+ ret void
+}
+
+define void @sitofp_v4i8_to_v4f32(ptr addrspace(1) %p, ptr addrspace(1) %o) {
+; GFX9-LABEL: sitofp_v4i8_to_v4f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: global_load_dword v0, v[0:1], off
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_ashrrev_i16_e32 v1, 8, v0
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v7, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v6, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v4, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX9-NEXT: global_store_dwordx4 v[2:3], v[4:7], off
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: sitofp_v4i8_to_v4f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_ashrrev_i16 v1, 8, v0
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v7, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v6, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v4, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX10-NEXT: global_store_dwordx4 v[2:3], v[4:7], off
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: sitofp_v4i8_to_v4f32:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v1.l, 8, v0.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v4, 24, v0
+; GFX11-TRUE16-NEXT: v_bfe_i32 v5, v0, 16, 8
+; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v7, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v6, v5
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v4, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v5, v1
+; GFX11-TRUE16-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: sitofp_v4i8_to_v4f32:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_ashrrev_i16 v1, 8, v0
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v4, 24, v0
+; GFX11-FAKE16-NEXT: v_bfe_i32 v5, v0, 16, 8
+; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v7, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v6, v5
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v4, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v5, v1
+; GFX11-FAKE16-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: sitofp_v4i8_to_v4f32:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: global_load_b32 v0, v[0:1], off
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_ashrrev_i16 v1.l, 8, v0.l
+; GFX1250-NEXT: v_ashrrev_i32_e32 v4, 24, v0
+; GFX1250-NEXT: v_bfe_i32 v5, v0, 16, 8
+; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v7, v4
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v6, v5
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v4, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v5, v1
+; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ %v = load <4 x i8>, ptr addrspace(1) %p, align 4
+ %c = sitofp <4 x i8> %v to <4 x float>
+ store <4 x float> %c, ptr addrspace(1) %o
+ ret void
+}
+
+define void @sitofp_2x_v4i8_to_v4f32(ptr addrspace(1) noalias %p, ptr addrspace(1) noalias %o) {
+; GFX9-LABEL: sitofp_2x_v4i8_to_v4f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX9-NEXT: v_mov_b32_e32 v4, 8
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_ashrrev_i16_sdwa v7, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_ashrrev_i16_e32 v5, 8, v0
+; GFX9-NEXT: v_ashrrev_i16_sdwa v11, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_ashrrev_i16_e32 v9, 8, v1
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v6, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v4, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v5, sext(v5) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v7, sext(v7) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v10, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v8, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v9, sext(v9) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v11, sext(v11) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX9-NEXT: global_store_dwordx4 v[2:3], v[4:7], off
+; GFX9-NEXT: global_store_dwordx4 v[2:3], v[8:11], off offset:16
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: sitofp_2x_v4i8_to_v4f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX10-NEXT: v_ashrrev_i16 v7, 8, v0
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v6, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v4, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; GFX10-NEXT: v_ashrrev_i16 v0, 8, v5
+; GFX10-NEXT: v_ashrrev_i16 v9, 8, v1
+; GFX10-NEXT: v_ashrrev_i16 v11, 8, v8
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v5, sext(v7) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v10, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v7, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v8, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v9, sext(v9) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v11, sext(v11) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX10-NEXT: global_store_dwordx4 v[2:3], v[4:7], off
+; GFX10-NEXT: global_store_dwordx4 v[2:3], v[8:11], off offset:16
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: sitofp_2x_v4i8_to_v4f32:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v5.l, 8, v0.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v7.l, 8, v1.l
+; GFX11-TRUE16-NEXT: v_bfe_i32 v8, v0, 16, 8
+; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v11.l, 8, v4.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v12.l, 8, v6.l
+; GFX11-TRUE16-NEXT: v_bfe_i32 v9, v1, 16, 8
+; GFX11-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 16
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v4, v0
+; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v5, 0, 16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v11, v11, 0, 16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX11-TRUE16-NEXT: v_bfe_i32 v12, v12, 0, 16
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v6, v8
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v10, v9
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v5, v0
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v9, v7
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v7, v11
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v8, v1
+; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v11, v12
+; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX11-TRUE16-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: sitofp_2x_v4i8_to_v4f32:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT: v_ashrrev_i16 v5, 8, v0
+; GFX11-FAKE16-NEXT: v_ashrrev_i16 v7, 8, v1
+; GFX11-FAKE16-NEXT: v_bfe_i32 v8, v0, 16, 8
+; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-FAKE16-NEXT: v_ashrrev_i16 v11, 8, v4
+; GFX11-FAKE16-NEXT: v_ashrrev_i16 v12, 8, v6
+; GFX11-FAKE16-NEXT: v_bfe_i32 v9, v1, 16, 8
+; GFX11-FAKE16-NEXT: v_bfe_i32 v7, v7, 0, 16
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v4, v0
+; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v5, 0, 16
+; GFX11-FAKE16-NEXT: v_bfe_i32 v11, v11, 0, 16
+; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX11-FAKE16-NEXT: v_bfe_i32 v12, v12, 0, 16
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v6, v8
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v10, v9
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v5, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v9, v7
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v7, v11
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v8, v1
+; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v11, v12
+; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX11-FAKE16-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: sitofp_2x_v4i8_to_v4f32:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: v_dual_lshrrev_b32 v4, 16, v0 :: v_dual_lshrrev_b32 v6, 16, v1
+; GFX1250-NEXT: v_ashrrev_i16 v5.l, 8, v0.l
+; GFX1250-NEXT: v_ashrrev_i16 v7.l, 8, v1.l
+; GFX1250-NEXT: v_bfe_i32 v8, v0, 16, 8
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX1250-NEXT: v_ashrrev_i16 v11.l, 8, v4.l
+; GFX1250-NEXT: v_ashrrev_i16 v12.l, 8, v6.l
+; GFX1250-NEXT: v_bfe_i32 v9, v1, 16, 8
+; GFX1250-NEXT: v_bfe_i32 v7, v7, 0, 16
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v4, v0
+; GFX1250-NEXT: v_bfe_i32 v0, v5, 0, 16
+; GFX1250-NEXT: v_bfe_i32 v11, v11, 0, 16
+; GFX1250-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX1250-NEXT: v_bfe_i32 v12, v12, 0, 16
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v6, v8
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v10, v9
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v5, v0
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v9, v7
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v7, v11
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v8, v1
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v11, v12
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ %v0 = load <4 x i8>, ptr addrspace(1) %p, align 8
+ %c0 = sitofp <4 x i8> %v0 to <4 x float>
+ store <4 x float> %c0, ptr addrspace(1) %o
+ %p4 = getelementptr inbounds i8, ptr addrspace(1) %p, i64 4
+ %o4 = getelementptr inbounds float, ptr addrspace(1) %o, i64 4
+ %v1 = load <4 x i8>, ptr addrspace(1) %p4, align 4
+ %c1 = sitofp <4 x i8> %v1 to <4 x float>
+ store <4 x float> %c1, ptr addrspace(1) %o4
+ ret void
+}
+
+define void @uitofp_2x_v2i8_to_v2f16(ptr addrspace(1) noalias %p, ptr addrspace(1) noalias %o) {
+; GFX9-LABEL: uitofp_2x_v2i8_to_v2f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: global_load_dword v0, v[0:1], off
+; GFX9-NEXT: s_movk_i32 s4, 0xff
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX9-NEXT: v_and_b32_sdwa v4, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT: v_cvt_f16_u16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; GFX9-NEXT: v_cvt_f16_u16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+; GFX9-NEXT: v_cvt_f16_u16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; GFX9-NEXT: v_cvt_f16_u16_e32 v1, v4
+; GFX9-NEXT: v_pack_b32_f16 v1, v1, v0
+; GFX9-NEXT: v_pack_b32_f16 v0, v5, v6
+; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: uito...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/228423
More information about the llvm-commits
mailing list