[llvm] [VPlan] Constant-fold ActiveLaneMask intrinsics (PR #208852)

[Florian Hahn via llvm-commits]

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@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "active.lane.mask" --version 6
+; RUN: opt -mtriple=aarch64 -mcpu=neoverse-v1 -passes=loop-vectorize -force-vector-width="vscale x 4" -force-vector-interleave=1 -tail-folding-policy=prefer-fold-tail -disable-output -vplan-print-after=printFinalVPlan %s 2>&1 | FileCheck %s
+
+; We never emit scalable active.lane.masks foldable to false.
+define i32 @scalable_alm_liveins(ptr %A, ptr noalias %B) vscale_range(1, 16) {
+; CHECK-LABEL: VPlan for loop in 'scalable_alm_liveins'
+; CHECK:    EMIT vp<%active.lane.mask.next> = wide active lane mask vp<%index.next>, ir<1002>, ir<1>
+; CHECK:    EMIT vp<%extract.next.alm.part> = extract-vector-for-part vp<%active.lane.mask.next>, ir<0>
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %for = phi i16 [ 0, %entry ], [ %for.next, %loop ]
+  %sext = sext i16 %for to i32
+  %iv.next = add i64 %iv, 1
+  %gep.A = getelementptr i32, ptr %A, i64 %iv.next
+  %for.next = load i16, ptr %gep.A, align 2
+  %gep.B = getelementptr i32, ptr %B, i64 %iv.next
+  store i32 %sext, ptr %gep.B
+  %ec = icmp eq i64 %iv, 1001
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret i32 0
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fhahn wrote:

```suggestion
  ret void
```

https://github.com/llvm/llvm-project/pull/208852