[llvm] [GlobalISel] [AArch64] Extend SelectShiftMask to handle ADD/SUB mod patterns (PR #225842)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 2 05:35:53 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Deepak Shirke (deepakshirkem)
<details>
<summary>Changes</summary>
AArch64 shift instructions only use the low log2(ShiftWidth) bits of the shift amount, so shifting by X+N where N == 0 mod ShiftWidth is equivalent to shifting by X alone.
This extends both SelectionDAG (SelectShiftMask) and GlobalISel (selectShiftMask) implementations.
Part of the incremental work tracked in #<!-- -->224245 to replace tryShiftAmountMod with ComplexPattern-based isel.
Depends on #<!-- -->223136.
CC: @<!-- -->davemgreen @<!-- -->RKSimon @<!-- -->arsenm @<!-- -->topperc
---
Patch is 74.30 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/225842.diff
8 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+14)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp (+15)
- (modified) llvm/test/CodeGen/AArch64/and-mask-variable.ll (+6-8)
- (modified) llvm/test/CodeGen/AArch64/fcvt-i256.ll (+332-364)
- (modified) llvm/test/CodeGen/AArch64/fsh.ll (+280-304)
- (modified) llvm/test/CodeGen/AArch64/funnel-shift.ll (+26-28)
- (modified) llvm/test/CodeGen/AArch64/shift-mod.ll (+35-10)
- (modified) llvm/test/CodeGen/AArch64/shift.ll (+49-67)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 81aa12190d875..b3c8ca0532cc6 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -789,6 +789,20 @@ bool AArch64DAGToDAGISel::SelectShiftMask(SDValue N, SDValue &ShAmt) {
return true;
}
}
+ // If shifting by X+/-N where N == 0 mod ShiftWidth, then just shift by X
+ // to avoid the ADD/SUB. Only do this if the ADD/SUB has a single use, so
+ // we don't leave the ADD/SUB behind for other users.
+ if ((N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) &&
+ N.hasOneUse() &&
+ N.getValueType() == (ShiftWidth == 32 ? MVT::i32 : MVT::i64)) {
+ uint64_t Imm;
+ if (isIntImmediate(N.getOperand(1).getNode(), Imm) &&
+ (Imm % ShiftWidth == 0)) {
+ ShAmt = N.getOperand(0);
+ return true;
+ }
+ }
+
return false;
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 93fcebf2a6dc7..2196b119cc360 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -7336,6 +7336,21 @@ AArch64InstructionSelector::selectShiftMask(MachineOperand &Root) const {
ShAmtReg = AndSrcReg;
}
+ // If shifting by X+/-N where N == 0 mod ShiftWidth, then just shift by X
+ // to avoid the ADD/SUB. Only do this if the ADD/SUB has a single use, so
+ // we don't leave the ADD/SUB behind for other users.
+ Register AddSrcReg;
+ int64_t AddImm;
+ if (MRI.hasOneUse(ShAmtReg) &&
+ (mi_match(ShAmtReg, MRI,
+ m_GAdd(m_Reg(AddSrcReg), m_ICstOrSplat(AddImm))) ||
+ mi_match(ShAmtReg, MRI,
+ m_GSub(m_Reg(AddSrcReg), m_ICstOrSplat(AddImm)))) &&
+ (AddImm % ShiftWidth == 0)) {
+ ShAmtReg = AddSrcReg;
+ return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(ShAmtReg); }}};
+ }
+
// Only succeed if we changed the shift amount; otherwise let other
// patterns (e.g. zext GPR32 -> SUBREG_TO_REG) match instead.
if (ShAmtReg == Root.getReg())
diff --git a/llvm/test/CodeGen/AArch64/and-mask-variable.ll b/llvm/test/CodeGen/AArch64/and-mask-variable.ll
index f41cdc6dd241b..ea5079770b243 100644
--- a/llvm/test/CodeGen/AArch64/and-mask-variable.ll
+++ b/llvm/test/CodeGen/AArch64/and-mask-variable.ll
@@ -58,16 +58,14 @@ define i128 @mask_pair_128(i128 %x, i128 %y) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #64 // =0x40
; CHECK-GI-NEXT: mov x9, #-1 // =0xffffffffffffffff
-; CHECK-GI-NEXT: sub x10, x2, #64
-; CHECK-GI-NEXT: sub x8, x8, x2
-; CHECK-GI-NEXT: lsl x11, x9, x2
; CHECK-GI-NEXT: cmp x2, #64
+; CHECK-GI-NEXT: sub x8, x8, x2
+; CHECK-GI-NEXT: lsl x10, x9, x2
; CHECK-GI-NEXT: lsr x8, x9, x8
-; CHECK-GI-NEXT: lsl x9, x9, x10
-; CHECK-GI-NEXT: csel x10, x11, xzr, lo
-; CHECK-GI-NEXT: orr x8, x8, x11
-; CHECK-GI-NEXT: and x0, x10, x0
-; CHECK-GI-NEXT: csel x8, x8, x9, lo
+; CHECK-GI-NEXT: csel x9, x10, xzr, lo
+; CHECK-GI-NEXT: orr x8, x8, x10
+; CHECK-GI-NEXT: and x0, x9, x0
+; CHECK-GI-NEXT: csel x8, x8, x10, lo
; CHECK-GI-NEXT: cmp x2, #0
; CHECK-GI-NEXT: csinv x8, x8, xzr, ne
; CHECK-GI-NEXT: and x1, x8, x1
diff --git a/llvm/test/CodeGen/AArch64/fcvt-i256.ll b/llvm/test/CodeGen/AArch64/fcvt-i256.ll
index d7d9d04187506..1e4f9b1d250b8 100644
--- a/llvm/test/CodeGen/AArch64/fcvt-i256.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt-i256.ll
@@ -698,81 +698,77 @@ define i256 @f32_to_s256(float %val) {
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB4_3: // %fp-to-i-if-exp.large
; CHECK-GI-NEXT: sub w11, w11, #150
-; CHECK-GI-NEXT: mov w13, #64 // =0x40
-; CHECK-GI-NEXT: mov w12, #128 // =0x80
-; CHECK-GI-NEXT: sub x14, x11, #64
-; CHECK-GI-NEXT: sub x15, x13, x11
+; CHECK-GI-NEXT: mov w12, #64 // =0x40
+; CHECK-GI-NEXT: mov w13, #128 // =0x80
+; CHECK-GI-NEXT: sub x15, x12, x11
; CHECK-GI-NEXT: lsl x16, x10, x11
+; CHECK-GI-NEXT: sub x13, x13, x11
; CHECK-GI-NEXT: lsr x15, x10, x15
-; CHECK-GI-NEXT: lsl x14, x10, x14
-; CHECK-GI-NEXT: sub x12, x12, x11
; CHECK-GI-NEXT: cmp x11, #64
-; CHECK-GI-NEXT: sub x17, x11, #128
-; CHECK-GI-NEXT: lsr x18, x10, x12
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: csel x14, x15, x14, lo
+; CHECK-GI-NEXT: sub x14, x11, #128
+; CHECK-GI-NEXT: lsr x17, x10, x13
+; CHECK-GI-NEXT: csel x18, x16, xzr, lo
+; CHECK-GI-NEXT: sub x12, x12, x14
+; CHECK-GI-NEXT: csel x15, x15, x16, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: sub x15, x17, #64
-; CHECK-GI-NEXT: csel x14, xzr, x14, eq
-; CHECK-GI-NEXT: cmp x12, #64
-; CHECK-GI-NEXT: sub x13, x13, x17
-; CHECK-GI-NEXT: csel x18, x18, xzr, lo
-; CHECK-GI-NEXT: cmp x12, #0
-; CHECK-GI-NEXT: lsl x12, x10, x17
-; CHECK-GI-NEXT: lsr x13, x10, x13
-; CHECK-GI-NEXT: lsl x15, x10, x15
-; CHECK-GI-NEXT: csel x18, x10, x18, eq
-; CHECK-GI-NEXT: cmp x17, #64
-; CHECK-GI-NEXT: csel x12, x12, xzr, lo
-; CHECK-GI-NEXT: csel x10, x13, x15, lo
-; CHECK-GI-NEXT: cmp x17, #0
-; CHECK-GI-NEXT: csel x13, xzr, x10, eq
+; CHECK-GI-NEXT: lsl x16, x10, x14
+; CHECK-GI-NEXT: csel x15, xzr, x15, eq
+; CHECK-GI-NEXT: cmp x13, #64
+; CHECK-GI-NEXT: lsr x12, x10, x12
+; CHECK-GI-NEXT: csel x17, x17, xzr, lo
+; CHECK-GI-NEXT: cmp x13, #0
+; CHECK-GI-NEXT: csel x13, x10, x17, eq
+; CHECK-GI-NEXT: cmp x14, #64
+; CHECK-GI-NEXT: csel x17, x16, xzr, lo
+; CHECK-GI-NEXT: csel x10, x12, x16, lo
+; CHECK-GI-NEXT: cmp x14, #0
+; CHECK-GI-NEXT: csel x12, xzr, x10, eq
; CHECK-GI-NEXT: cmp x11, #128
-; CHECK-GI-NEXT: csel x10, x16, xzr, lo
-; CHECK-GI-NEXT: csel x14, x14, xzr, lo
-; CHECK-GI-NEXT: csel x12, x18, x12, lo
-; CHECK-GI-NEXT: csel x13, xzr, x13, lo
+; CHECK-GI-NEXT: csel x10, x18, xzr, lo
+; CHECK-GI-NEXT: csel x15, x15, xzr, lo
+; CHECK-GI-NEXT: csel x13, x13, x17, lo
+; CHECK-GI-NEXT: csel x12, xzr, x12, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: umulh x11, x10, x9
-; CHECK-GI-NEXT: csel x12, xzr, x12, eq
+; CHECK-GI-NEXT: umulh x18, x10, x9
; CHECK-GI-NEXT: csel x13, xzr, x13, eq
-; CHECK-GI-NEXT: umulh x18, x14, x9
-; CHECK-GI-NEXT: umulh x17, x12, x8
-; CHECK-GI-NEXT: umulh x15, x10, x8
-; CHECK-GI-NEXT: add x18, x18, x11
+; CHECK-GI-NEXT: csel x12, xzr, x12, eq
+; CHECK-GI-NEXT: umulh x11, x15, x9
+; CHECK-GI-NEXT: umulh x17, x13, x8
+; CHECK-GI-NEXT: umulh x14, x10, x8
+; CHECK-GI-NEXT: add x11, x11, x18
; CHECK-GI-NEXT: mul x16, x10, x9
-; CHECK-GI-NEXT: add x17, x17, x18
-; CHECK-GI-NEXT: mul x0, x14, x8
-; CHECK-GI-NEXT: madd x17, x10, x9, x17
-; CHECK-GI-NEXT: adds x15, x15, x16
-; CHECK-GI-NEXT: umulh x2, x14, x8
+; CHECK-GI-NEXT: add x11, x17, x11
+; CHECK-GI-NEXT: mul x0, x15, x8
+; CHECK-GI-NEXT: umulh x2, x15, x8
+; CHECK-GI-NEXT: adds x14, x14, x16
+; CHECK-GI-NEXT: madd x11, x10, x9, x11
; CHECK-GI-NEXT: cset w3, hs
-; CHECK-GI-NEXT: adds x1, x15, x0
-; CHECK-GI-NEXT: mul x18, x14, x9
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: madd x14, x14, x9, x17
-; CHECK-GI-NEXT: adds x11, x2, x11
-; CHECK-GI-NEXT: mul x17, x12, x8
+; CHECK-GI-NEXT: adds x1, x14, x0
+; CHECK-GI-NEXT: mul x17, x15, x9
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: adds x18, x2, x18
+; CHECK-GI-NEXT: madd x11, x15, x9, x11
; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: adds x11, x11, x16
-; CHECK-GI-NEXT: and x16, x0, #0x1
-; CHECK-GI-NEXT: madd x9, x12, x9, x14
-; CHECK-GI-NEXT: and x12, x3, #0x1
-; CHECK-GI-NEXT: and x14, x15, #0x1
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: adds x11, x11, x18
-; CHECK-GI-NEXT: and x15, x15, #0x1
+; CHECK-GI-NEXT: adds x16, x18, x16
+; CHECK-GI-NEXT: and x18, x0, #0x1
+; CHECK-GI-NEXT: mul x15, x13, x8
+; CHECK-GI-NEXT: madd x9, x13, x9, x11
+; CHECK-GI-NEXT: and x11, x3, #0x1
+; CHECK-GI-NEXT: and x13, x14, #0x1
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: and x14, x14, #0x1
; CHECK-GI-NEXT: mul x0, x10, x8
-; CHECK-GI-NEXT: add x10, x12, x14
+; CHECK-GI-NEXT: add x10, x11, x13
+; CHECK-GI-NEXT: adds x13, x16, x17
+; CHECK-GI-NEXT: add x11, x18, x14
; CHECK-GI-NEXT: cset w14, hs
-; CHECK-GI-NEXT: adds x11, x11, x17
-; CHECK-GI-NEXT: add x12, x16, x15
-; CHECK-GI-NEXT: madd x8, x13, x8, x9
+; CHECK-GI-NEXT: adds x13, x13, x15
+; CHECK-GI-NEXT: madd x8, x12, x8, x9
; CHECK-GI-NEXT: and x9, x14, #0x1
-; CHECK-GI-NEXT: cset w13, hs
-; CHECK-GI-NEXT: adds x2, x11, x10
-; CHECK-GI-NEXT: add x9, x12, x9
-; CHECK-GI-NEXT: and x10, x13, #0x1
+; CHECK-GI-NEXT: cset w12, hs
+; CHECK-GI-NEXT: adds x2, x13, x10
+; CHECK-GI-NEXT: add x9, x11, x9
+; CHECK-GI-NEXT: and x10, x12, #0x1
; CHECK-GI-NEXT: cset w11, hs
; CHECK-GI-NEXT: add x9, x9, x10
; CHECK-GI-NEXT: and x10, x11, #0x1
@@ -871,40 +867,36 @@ define i256 @f32_to_u256(float %val) {
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB5_3: // %fp-to-i-if-exp.large
; CHECK-GI-NEXT: sub w9, w9, #150
-; CHECK-GI-NEXT: mov w11, #64 // =0x40
-; CHECK-GI-NEXT: mov w10, #128 // =0x80
-; CHECK-GI-NEXT: sub x12, x9, #64
-; CHECK-GI-NEXT: sub x13, x11, x9
-; CHECK-GI-NEXT: lsl x14, x8, x9
-; CHECK-GI-NEXT: lsr x13, x8, x13
-; CHECK-GI-NEXT: lsl x12, x8, x12
-; CHECK-GI-NEXT: sub x10, x10, x9
+; CHECK-GI-NEXT: mov w10, #64 // =0x40
+; CHECK-GI-NEXT: mov w11, #128 // =0x80
+; CHECK-GI-NEXT: sub x12, x10, x9
+; CHECK-GI-NEXT: lsl x13, x8, x9
+; CHECK-GI-NEXT: sub x11, x11, x9
+; CHECK-GI-NEXT: lsr x12, x8, x12
; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: sub x15, x9, #128
-; CHECK-GI-NEXT: lsr x16, x8, x10
-; CHECK-GI-NEXT: csel x14, x14, xzr, lo
-; CHECK-GI-NEXT: csel x12, x13, x12, lo
+; CHECK-GI-NEXT: lsr x14, x8, x11
+; CHECK-GI-NEXT: csel x15, x13, xzr, lo
+; CHECK-GI-NEXT: csel x12, x12, x13, lo
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: sub x13, x15, #64
+; CHECK-GI-NEXT: sub x13, x9, #128
; CHECK-GI-NEXT: csel x12, xzr, x12, eq
-; CHECK-GI-NEXT: cmp x10, #64
-; CHECK-GI-NEXT: sub x11, x11, x15
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: cmp x10, #0
-; CHECK-GI-NEXT: lsl x10, x8, x15
-; CHECK-GI-NEXT: lsr x11, x8, x11
-; CHECK-GI-NEXT: lsl x13, x8, x13
-; CHECK-GI-NEXT: csel x8, x8, x16, eq
-; CHECK-GI-NEXT: cmp x15, #64
-; CHECK-GI-NEXT: csel x10, x10, xzr, lo
-; CHECK-GI-NEXT: csel x11, x11, x13, lo
-; CHECK-GI-NEXT: cmp x15, #0
-; CHECK-GI-NEXT: csel x11, xzr, x11, eq
+; CHECK-GI-NEXT: cmp x11, #64
+; CHECK-GI-NEXT: sub x10, x10, x13
+; CHECK-GI-NEXT: csel x14, x14, xzr, lo
+; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: lsl x11, x8, x13
+; CHECK-GI-NEXT: lsr x10, x8, x10
+; CHECK-GI-NEXT: csel x8, x8, x14, eq
+; CHECK-GI-NEXT: cmp x13, #64
+; CHECK-GI-NEXT: csel x14, x11, xzr, lo
+; CHECK-GI-NEXT: csel x10, x10, x11, lo
+; CHECK-GI-NEXT: cmp x13, #0
+; CHECK-GI-NEXT: csel x10, xzr, x10, eq
; CHECK-GI-NEXT: cmp x9, #128
-; CHECK-GI-NEXT: csel x0, x14, xzr, lo
+; CHECK-GI-NEXT: csel x0, x15, xzr, lo
; CHECK-GI-NEXT: csel x1, x12, xzr, lo
-; CHECK-GI-NEXT: csel x8, x8, x10, lo
-; CHECK-GI-NEXT: csel x10, xzr, x11, lo
+; CHECK-GI-NEXT: csel x8, x8, x14, lo
+; CHECK-GI-NEXT: csel x10, xzr, x10, lo
; CHECK-GI-NEXT: cmp x9, #0
; CHECK-GI-NEXT: csel x2, xzr, x8, eq
; CHECK-GI-NEXT: csel x3, xzr, x10, eq
@@ -1059,81 +1051,77 @@ define i256 @f64_to_s256(double %val) {
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB6_3: // %fp-to-i-if-exp.large
; CHECK-GI-NEXT: sub x11, x11, #1075
-; CHECK-GI-NEXT: mov w13, #64 // =0x40
-; CHECK-GI-NEXT: mov w12, #128 // =0x80
-; CHECK-GI-NEXT: sub x14, x11, #64
-; CHECK-GI-NEXT: sub x15, x13, x11
+; CHECK-GI-NEXT: mov w12, #64 // =0x40
+; CHECK-GI-NEXT: mov w13, #128 // =0x80
+; CHECK-GI-NEXT: sub x15, x12, x11
; CHECK-GI-NEXT: lsl x16, x10, x11
+; CHECK-GI-NEXT: sub x13, x13, x11
; CHECK-GI-NEXT: lsr x15, x10, x15
-; CHECK-GI-NEXT: lsl x14, x10, x14
-; CHECK-GI-NEXT: sub x12, x12, x11
; CHECK-GI-NEXT: cmp x11, #64
-; CHECK-GI-NEXT: sub x17, x11, #128
-; CHECK-GI-NEXT: lsr x18, x10, x12
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: csel x14, x15, x14, lo
+; CHECK-GI-NEXT: sub x14, x11, #128
+; CHECK-GI-NEXT: lsr x17, x10, x13
+; CHECK-GI-NEXT: csel x18, x16, xzr, lo
+; CHECK-GI-NEXT: sub x12, x12, x14
+; CHECK-GI-NEXT: csel x15, x15, x16, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: sub x15, x17, #64
-; CHECK-GI-NEXT: csel x14, xzr, x14, eq
-; CHECK-GI-NEXT: cmp x12, #64
-; CHECK-GI-NEXT: sub x13, x13, x17
-; CHECK-GI-NEXT: csel x18, x18, xzr, lo
-; CHECK-GI-NEXT: cmp x12, #0
-; CHECK-GI-NEXT: lsl x12, x10, x17
-; CHECK-GI-NEXT: lsr x13, x10, x13
-; CHECK-GI-NEXT: lsl x15, x10, x15
-; CHECK-GI-NEXT: csel x18, x10, x18, eq
-; CHECK-GI-NEXT: cmp x17, #64
-; CHECK-GI-NEXT: csel x12, x12, xzr, lo
-; CHECK-GI-NEXT: csel x10, x13, x15, lo
-; CHECK-GI-NEXT: cmp x17, #0
-; CHECK-GI-NEXT: csel x13, xzr, x10, eq
+; CHECK-GI-NEXT: lsl x16, x10, x14
+; CHECK-GI-NEXT: csel x15, xzr, x15, eq
+; CHECK-GI-NEXT: cmp x13, #64
+; CHECK-GI-NEXT: lsr x12, x10, x12
+; CHECK-GI-NEXT: csel x17, x17, xzr, lo
+; CHECK-GI-NEXT: cmp x13, #0
+; CHECK-GI-NEXT: csel x13, x10, x17, eq
+; CHECK-GI-NEXT: cmp x14, #64
+; CHECK-GI-NEXT: csel x17, x16, xzr, lo
+; CHECK-GI-NEXT: csel x10, x12, x16, lo
+; CHECK-GI-NEXT: cmp x14, #0
+; CHECK-GI-NEXT: csel x12, xzr, x10, eq
; CHECK-GI-NEXT: cmp x11, #128
-; CHECK-GI-NEXT: csel x10, x16, xzr, lo
-; CHECK-GI-NEXT: csel x14, x14, xzr, lo
-; CHECK-GI-NEXT: csel x12, x18, x12, lo
-; CHECK-GI-NEXT: csel x13, xzr, x13, lo
+; CHECK-GI-NEXT: csel x10, x18, xzr, lo
+; CHECK-GI-NEXT: csel x15, x15, xzr, lo
+; CHECK-GI-NEXT: csel x13, x13, x17, lo
+; CHECK-GI-NEXT: csel x12, xzr, x12, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: umulh x11, x10, x9
-; CHECK-GI-NEXT: csel x12, xzr, x12, eq
+; CHECK-GI-NEXT: umulh x18, x10, x9
; CHECK-GI-NEXT: csel x13, xzr, x13, eq
-; CHECK-GI-NEXT: umulh x18, x14, x9
-; CHECK-GI-NEXT: umulh x17, x12, x8
-; CHECK-GI-NEXT: umulh x15, x10, x8
-; CHECK-GI-NEXT: add x18, x18, x11
+; CHECK-GI-NEXT: csel x12, xzr, x12, eq
+; CHECK-GI-NEXT: umulh x11, x15, x9
+; CHECK-GI-NEXT: umulh x17, x13, x8
+; CHECK-GI-NEXT: umulh x14, x10, x8
+; CHECK-GI-NEXT: add x11, x11, x18
; CHECK-GI-NEXT: mul x16, x10, x9
-; CHECK-GI-NEXT: add x17, x17, x18
-; CHECK-GI-NEXT: mul x0, x14, x8
-; CHECK-GI-NEXT: madd x17, x10, x9, x17
-; CHECK-GI-NEXT: adds x15, x15, x16
-; CHECK-GI-NEXT: umulh x2, x14, x8
+; CHECK-GI-NEXT: add x11, x17, x11
+; CHECK-GI-NEXT: mul x0, x15, x8
+; CHECK-GI-NEXT: umulh x2, x15, x8
+; CHECK-GI-NEXT: adds x14, x14, x16
+; CHECK-GI-NEXT: madd x11, x10, x9, x11
; CHECK-GI-NEXT: cset w3, hs
-; CHECK-GI-NEXT: adds x1, x15, x0
-; CHECK-GI-NEXT: mul x18, x14, x9
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: madd x14, x14, x9, x17
-; CHECK-GI-NEXT: adds x11, x2, x11
-; CHECK-GI-NEXT: mul x17, x12, x8
+; CHECK-GI-NEXT: adds x1, x14, x0
+; CHECK-GI-NEXT: mul x17, x15, x9
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: adds x18, x2, x18
+; CHECK-GI-NEXT: madd x11, x15, x9, x11
; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: adds x11, x11, x16
-; CHECK-GI-NEXT: and x16, x0, #0x1
-; CHECK-GI-NEXT: madd x9, x12, x9, x14
-; CHECK-GI-NEXT: and x12, x3, #0x1
-; CHECK-GI-NEXT: and x14, x15, #0x1
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: adds x11, x11, x18
-; CHECK-GI-NEXT: and x15, x15, #0x1
+; CHECK-GI-NEXT: adds x16, x18, x16
+; CHECK-GI-NEXT: and x18, x0, #0x1
+; CHECK-GI-NEXT: mul x15, x13, x8
+; CHECK-GI-NEXT: madd x9, x13, x9, x11
+; CHECK-GI-NEXT: and x11, x3, #0x1
+; CHECK-GI-NEXT: and x13, x14, #0x1
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: and x14, x14, #0x1
; CHECK-GI-NEXT: mul x0, x10, x8
-; CHECK-GI-NEXT: add x10, x12, x14
+; CHECK-GI-NEXT: add x10, x11, x13
+; CHECK-GI-NEXT: adds x13, x16, x17
+; CHECK-GI-NEXT: add x11, x18, x14
; CHECK-GI-NEXT: cset w14, hs
-; CHECK-GI-NEXT: adds x11, x11, x17
-; CHECK-GI-NEXT: add x12, x16, x15
-; CHECK-GI-NEXT: madd x8, x13, x8, x9
+; CHECK-GI-NEXT: adds x13, x13, x15
+; CHECK-GI-NEXT: madd x8, x12, x8, x9
; CHECK-GI-NEXT: and x9, x14, #0x1
-; CHECK-GI-NEXT: cset w13, hs
-; CHECK-GI-NEXT: adds x2, x11, x10
-; CHECK-GI-NEXT: add x9, x12, x9
-; CHECK-GI-NEXT: and x10, x13, #0x1
+; CHECK-GI-NEXT: cset w12, hs
+; CHECK-GI-NEXT: adds x2, x13, x10
+; CHECK-GI-NEXT: add x9, x11, x9
+; CHECK-GI-NEXT: and x10, x12, #0x1
; CHECK-GI-NEXT: cset w11, hs
; CHECK-GI-NEXT: add x9, x9, x10
; CHECK-GI-NEXT: and x10, x11, #0x1
@@ -1232,40 +1220,36 @@ define i256 @f64_to_u256(double %val) {
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB7_3: // %fp-to-i-if-exp.large
; CHECK-GI-NEXT: sub x9, x9, #1075
-; CHECK-GI-NEXT: mov w11, #64 // =0x40
-; CHECK-GI-NEXT: mov w10, #128 // =0x80
-; CHECK-GI-NEXT: sub x12, x9, #64
-; CHECK-GI-NEXT: sub x13, x11, x9
-; CHECK-GI-NEXT: lsl x14, x8, x9
-; CHECK-GI-NEXT: lsr x13, x8, x13
-; CHECK-GI-NEXT: lsl x12, x8, x12
-; CHECK-GI-NEXT: sub x10, x10, x9
+; CHECK-GI-NEXT: mov w10, #64 // =0x40
+; CHECK-GI-NEXT: mov w11, #128 // =0x80
+; CHECK-GI-NEXT: sub x12, x10, x9
+; CHECK-GI-NEXT: lsl x13, x8, x9
+; CHECK-GI-NEXT: sub x11, x11, x9
+; CHECK-GI-NEXT: lsr x12, x8, x12
; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: sub x15, x9, #128
-; CHECK-GI-NEXT: lsr x16, x8, x10
-; CHECK-GI-NEXT: csel x14, x14, xzr, lo
-; CHECK-GI-NEXT: csel x12, x13, x12, lo
+; CHECK-GI-NEXT: lsr x14, x8, x11
+; CHECK-GI-NEXT: csel x15, x13, xzr, lo
+; CHECK-GI-NEXT: csel x12, x12, x13, lo
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: sub x13, x15, #64
+; CHECK-GI-NEXT: sub x13, x9, #128
; CHECK-GI-NEXT: csel x12, xzr, x12, eq
-; CHECK-GI-NEXT: cmp x10, #64
-; CHECK-GI-NEXT: sub x11, x11, x15
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: cmp x10, #0
-; CHECK-GI-NEXT: lsl x10, x8, x15
-; CHECK-GI-NEXT: lsr x11, x8, x11
-; CHECK-GI-NEXT: lsl x13, x8, x13
-; CHECK-GI-NEXT: csel x8, x8, x16, eq
-; CHECK-GI-NEXT: cmp x15, #64
-; CHECK-GI-NEXT: csel x10, x10, xzr, lo
-; CHECK-GI-NEXT: csel x11, x11, x13, lo
-; CHECK-GI-NEXT: cmp x15, #0
-; CHECK-GI-NEXT: csel x11, xzr, x11, eq
+; CHECK-GI-NEXT: cmp x11, #64
+; CHECK-GI-NEXT: sub x10, x10, x13
+; CHECK-GI-NEXT: csel x14, x14, xzr, lo
+; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: lsl x11, x8, x13
+; CHECK-GI-NEXT: lsr x10, x8, x10
+; CHECK-GI-NEXT: csel x8, x8, x14, eq
+; CHECK-GI-NEXT: cmp x13, #64
+; CHECK-GI-NEXT: csel x14, x11, xzr, lo
+; CHECK-GI-NEXT: csel x10, x10, x11, lo
+; CHECK-GI-NEXT: cmp x13, #0
+; CHECK-GI-NEXT: csel x10, xzr, x10, eq
; CHECK-GI-NEXT: cmp x9, #128
-; CHECK-GI-NEXT: csel x0, x14, xzr, lo
+; CHECK-GI-NEXT: csel x0, x15, xzr, lo
; CHECK-GI-NEXT: csel x1, x12, xzr, lo
-; CHECK-GI-NEXT: csel x8, x8, x10, lo
-; CHECK-GI-NEXT: csel x10, xzr, x11, lo
+; CHECK-GI-NEXT: csel x8, x8, x14, lo
+; CHECK-GI-NEXT: csel x10, xzr, x10, lo
; CHECK-GI-NEXT: cmp x9, #0
; CHECK-GI-NEXT: csel x2, xzr, x8, eq
; CHECK-GI-NEXT: csel x3, xzr, x10, eq
@@ -1448,81 +1432,77 @@ define i256 @f32_to_s256_sat(float %val) {
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB8_6: // %fp-to-i-if-exp.large
; CHECK-GI-NEXT: sub w11, w11, #150
-; CHECK-GI-NEXT: mov w13, #64 // =0x40
-; CHECK-GI-NEXT: mov w12, #128 // =0x80
-; CHECK-GI-NEXT: sub x14, x11, #64
-; CHECK-GI-NEXT: sub x15, x13, x11
+; CHECK-GI-NEXT: mov w12, #64 // =0x40
+; CHECK-GI-NEXT: mov w13, #128 // =0x80
+; CHECK-GI-NEXT: sub x15, x12, x11
; CHECK-GI-...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/225842
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