[llvm] [AArch64] Fold DUPLANE of 0 to zeroimm (PR #228415)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: David Green (davemgreen)

<details>
<summary>Changes</summary>

This folds away DUPLANE8/16/32/64 of zero into a zero vector, which should be simpler and possibly allow other folds.

---
Full diff: https://github.com/llvm/llvm-project/pull/228415.diff


3 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+10) 
- (modified) llvm/test/CodeGen/AArch64/arm64-rev.ll (-1) 
- (modified) llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll (+2-7) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 9885dfc854d11..f94368be0cb8f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -30418,6 +30418,16 @@ static SDValue performDUPCombine(SDNode *N,
     }
 
     return performPostLD1Combine(N, DCI, false);
+  } else { // AArch64ISD::DUPLANE8/16/32/64
+    SDValue SrcOp = N->getOperand(0);
+    APInt InDemandedElts =
+        APInt::getOneBitSet(SrcOp.getValueType().getVectorNumElements(),
+                            N->getConstantOperandVal(1));
+    KnownBits Known = DCI.DAG.computeKnownBits(SrcOp, InDemandedElts);
+    if (Known.isZero())
+      return DCI.DAG.getBitcast(
+          VT, DCI.DAG.getConstant(Known.getConstant(), DL,
+                                  VT.changeVectorElementTypeToInteger()));
   }
 
   return SDValue();
diff --git a/llvm/test/CodeGen/AArch64/arm64-rev.ll b/llvm/test/CodeGen/AArch64/arm64-rev.ll
index a3c727c64ec02..1c88859df83aa 100644
--- a/llvm/test/CodeGen/AArch64/arm64-rev.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-rev.ll
@@ -491,7 +491,6 @@ define void @float_vrev64(ptr nocapture %source, ptr nocapture %dest) nounwind n
 ; CHECK-SD:       // %bb.0: // %entry
 ; CHECK-SD-NEXT:    movi.2d v0, #0000000000000000
 ; CHECK-SD-NEXT:    add x8, x0, #12
-; CHECK-SD-NEXT:    dup.4s v0, v0[0]
 ; CHECK-SD-NEXT:    ld1.s { v0 }[1], [x8]
 ; CHECK-SD-NEXT:    str q0, [x1, #176]
 ; CHECK-SD-NEXT:    ret
diff --git a/llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll b/llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
index 599e626ddcae1..04872b503a146 100644
--- a/llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
+++ b/llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
@@ -53,7 +53,6 @@ define <4 x float> @testv4f32_1(<4 x float> noundef %vec) {
 ; CHECK-SD-LABEL: testv4f32_1:
 ; CHECK-SD:       // %bb.0: // %entry
 ; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
-; CHECK-SD-NEXT:    dup v1.4s, v1.s[0]
 ; CHECK-SD-NEXT:    mov v1.s[0], v0.s[0]
 ; CHECK-SD-NEXT:    mov v0.16b, v1.16b
 ; CHECK-SD-NEXT:    ret
@@ -166,9 +165,8 @@ entry:
 define <4 x half> @testv4f16_1(<4 x half> noundef %vec) {
 ; CHECK-SD-LABEL: testv4f16_1:
 ; CHECK-SD:       // %bb.0: // %entry
-; CHECK-SD-NEXT:    movi d1, #0000000000000000
+; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT:    dup v1.4h, v1.h[0]
 ; CHECK-SD-NEXT:    mov v1.h[0], v0.h[0]
 ; CHECK-SD-NEXT:    fmov d0, d1
 ; CHECK-SD-NEXT:    ret
@@ -245,9 +243,8 @@ entry:
 define <4 x bfloat> @testv4bf16_1(<4 x bfloat> noundef %vec) {
 ; CHECK-SD-LABEL: testv4bf16_1:
 ; CHECK-SD:       // %bb.0: // %entry
-; CHECK-SD-NEXT:    movi d1, #0000000000000000
+; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT:    dup v1.4h, v1.h[0]
 ; CHECK-SD-NEXT:    mov v1.h[0], v0.h[0]
 ; CHECK-SD-NEXT:    fmov d0, d1
 ; CHECK-SD-NEXT:    ret
@@ -317,7 +314,6 @@ define <4 x i32> @testv4i32_1(<4 x i32> noundef %vec) {
 ; CHECK-SD-LABEL: testv4i32_1:
 ; CHECK-SD:       // %bb.0: // %entry
 ; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
-; CHECK-SD-NEXT:    dup v1.4s, v1.s[0]
 ; CHECK-SD-NEXT:    mov v1.s[0], v0.s[0]
 ; CHECK-SD-NEXT:    mov v0.16b, v1.16b
 ; CHECK-SD-NEXT:    ret
@@ -412,7 +408,6 @@ define <4 x i16> @testv4i16_1(<4 x i16> noundef %vec) {
 ; CHECK-SD:       // %bb.0: // %entry
 ; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT:    dup v1.4h, v1.h[0]
 ; CHECK-SD-NEXT:    mov v1.h[0], v0.h[0]
 ; CHECK-SD-NEXT:    fmov d0, d1
 ; CHECK-SD-NEXT:    ret

``````````

</details>


https://github.com/llvm/llvm-project/pull/228415